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RAM2GS
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This commit is contained in:
Zane Kaminski 2023-11-03 04:26:41 -04:00
parent c103137bfc
commit 5452b30f1d
189 changed files with 447488 additions and 950513 deletions
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1
CPLD/LCMXO2-1200HC/RAM2GS-LCMXO2.ccl Normal file
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@ -0,0 +1 @@
VERSION=20110520

5
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt
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@ -1,6 +1,6 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Thu Sep 21 05:40:22 2023 *
NOTE DATE CREATED: Thu Oct 19 23:51:27 2023 *
NOTE DESIGN NAME: RAM2GS *
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *
@ -13,6 +13,7 @@ NOTE PINS nRCAS : 52 : out *
NOTE PINS nRRAS : 54 : out *
NOTE PINS nRWE : 49 : out *
NOTE PINS RCKE : 53 : out *
NOTE PINS RCLKout : 62 : out *
NOTE PINS RCLK : 63 : in *
NOTE PINS nRCS : 57 : out *
NOTE PINS RD[7] : 43 : inout *
@ -24,7 +25,7 @@ NOTE PINS RD[2] : 38 : inout *
NOTE PINS RD[1] : 37 : inout *
NOTE PINS RA[11] : 59 : out *
NOTE PINS RA[10] : 64 : out *
NOTE PINS RA[9] : 62 : out *
NOTE PINS RA[9] : 47 : out *
NOTE PINS RA[8] : 65 : out *
NOTE PINS RA[7] : 75 : out *
NOTE PINS RA[6] : 68 : out *

18
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.areasrr
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@ -1,9 +1,9 @@
----------------------------------------------------------------------
Report for cell RAM2GS.verilog
Register bits: 109 of 1280 (9%)
Register bits: 110 of 1280 (9%)
PIC Latch: 0
I/O cells: 63
I/O cells: 64
Cell usage:
cell count Res Usage(%)
BB 8 100.0
@ -11,33 +11,33 @@ I/O cells: 63
EFB 1 100.0
FD1P3AX 25 100.0
FD1P3IX 2 100.0
FD1S3AX 53 100.0
FD1S3AX 54 100.0
FD1S3IX 4 100.0
GSR 1 100.0
IB 25 100.0
IFS1P3DX 9 100.0
INV 7 100.0
OB 30 100.0
OB 31 100.0
ODDRXE 1 100.0
OFS1P3BX 4 100.0
OFS1P3DX 11 100.0
OFS1P3JX 1 100.0
ORCALUT4 213 100.0
PFUMX 1 100.0
ORCALUT4 203 100.0
PUR 1 100.0
VHI 2 100.0
VLO 2 100.0
SUB MODULES
REFB 1 100.0
TOTAL 411
TOTAL 403
----------------------------------------------------------------------
Report for cell REFB.netlist
Instance path: ufmefb
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
ORCALUT4 2 0.9
ORCALUT4 1 0.5
VHI 1 50.0
VLO 1 50.0
TOTAL 5
TOTAL 4

4
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn
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@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Sep 21 05:40:18 2023
Thu Oct 19 23:51:23 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
@ -83,4 +83,4 @@ Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Peak Memory Usage: 274 MB
Peak Memory Usage: 275 MB

BIN
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bit
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CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi
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1079
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
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186
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
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@ -15,24 +15,36 @@ Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 09/21/23 05:39:45
Mapped on: 10/19/23 23:50:56
Design Summary
--------------
Number of registers: 109 out of 1520 (7%)
PFU registers: 84 out of 1280 (7%)
Number of registers: 110 out of 1520 (7%)
PFU registers: 85 out of 1280 (7%)
PIO registers: 25 out of 240 (10%)
Number of SLICEs: 120 out of 640 (19%)
SLICEs as Logic/ROM: 120 out of 640 (19%)
Number of SLICEs: 115 out of 640 (18%)
SLICEs as Logic/ROM: 115 out of 640 (18%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 10 out of 640 (2%)
Number of LUT4s: 237 out of 1280 (19%)
Number used as logic LUTs: 217
Number of LUT4s: 229 out of 1280 (18%)
Number used as logic LUTs: 209
Number used as distributed RAM: 0
Number used as ripple logic: 20
Number used as shift registers: 0
Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
Number of PIO sites used: 64 + 4(JTAG) out of 80 (85%)
Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
Number of IDDR cells: 0
Number of ODDR cells: 1
Number of TDDR cells: 0
Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
Number of PIO using IDDR only: 0 (0 differential)
Number of PIO using ODDR only: 1 (0 differential)
Number of PIO using TDDR only: 0 (0 differential)
Number of PIO using IDDR/ODDR: 0 (0 differential)
Number of PIO using IDDR/TDDR: 0 (0 differential)
Number of PIO using ODDR/TDDR: 0 (0 differential)
Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
@ -48,6 +60,16 @@ Design Summary
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Page 1
Design: RAM2GS Date: 10/19/23 23:50:56
Design Summary (cont)
---------------------
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
@ -59,24 +81,14 @@ Design Summary
ripple logic.
Number of clocks: 4
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
Page 1
Design: RAM2GS Date: 09/21/23 05:39:45
Design Summary (cont)
---------------------
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK )
Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
Number of Clock Enables: 5
Net N_178: 1 loads, 1 LSLICEs
Net N_103: 1 loads, 1 LSLICEs
Net XOR8MEG18: 5 loads, 5 LSLICEs
Net N_360_i: 2 loads, 2 LSLICEs
Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs
Net N_122: 9 loads, 9 LSLICEs
Net N_244_i: 2 loads, 2 LSLICEs
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
Number of LSRs: 5
Net RA10s_i: 1 loads, 0 LSLICEs
@ -86,16 +98,16 @@ Design Summary (cont)
Net RASr2: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net InitReady: 41 loads
Net FS[11]: 23 loads
Net FS[13]: 22 loads
Net FS[10]: 21 loads
Net FS[12]: 21 loads
Net FS[9]: 20 loads
Net InitReady: 31 loads
Net FS[12]: 23 loads
Net FS[13]: 23 loads
Net FS[11]: 21 loads
Net N_132: 20 loads
Net FS[14]: 18 loads
Net CO0: 15 loads
Net FS[10]: 16 loads
Net FS[9]: 14 loads
Net Ready: 14 loads
Net Ready_fast: 14 loads
Net N_214: 13 loads
@ -114,6 +126,14 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
Page 2
Design: RAM2GS Date: 10/19/23 23:50:56
IO (PIO) Attributes
-------------------
@ -126,16 +146,6 @@ IO (PIO) Attributes
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI2 | INPUT | LVCMOS33 | IN |
Page 2
Design: RAM2GS Date: 09/21/23 05:39:45
IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+
| RDQML | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@ -149,6 +159,8 @@ IO (PIO) Attributes (cont)
+---------------------+-----------+-----------+------------+
| RCKE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RCLKout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RCLK | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRCS | OUTPUT | LVCMOS33 | OUT |
@ -180,6 +192,16 @@ IO (PIO) Attributes (cont)
| RA[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[5] | OUTPUT | LVCMOS33 | |
Page 3
Design: RAM2GS Date: 10/19/23 23:50:56
IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+
| RA[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@ -192,16 +214,6 @@ IO (PIO) Attributes (cont)
| RA[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
Page 3
Design: RAM2GS Date: 09/21/23 05:39:45
IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
@ -246,6 +258,16 @@ IO (PIO) Attributes (cont)
| CROW[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CROW[0] | INPUT | LVCMOS33 | |
Page 4
Design: RAM2GS Date: 10/19/23 23:50:56
IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+
| MAin[9] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@ -258,16 +280,6 @@ IO (PIO) Attributes (cont)
| MAin[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[4] | INPUT | LVCMOS33 | |
Page 4
Design: RAM2GS Date: 09/21/23 05:39:45
IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+
| MAin[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@ -285,7 +297,6 @@ Block GSR_INST undriven or does not drive anything - clipped.
Signal nCRAS_c_i was merged into signal nCRAS_c
Signal RASr2_i was merged into signal RASr2
Signal XOR8MEG.CN was merged into signal PHI2_c
Signal GND undriven or does not drive anything - clipped.
Signal ufmefb/VCC undriven or does not drive anything - clipped.
Signal ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
@ -313,6 +324,16 @@ Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Page 5
Design: RAM2GS Date: 10/19/23 23:50:56
Removed logic (cont)
--------------------
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
@ -324,16 +345,6 @@ Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Page 5
Design: RAM2GS Date: 09/21/23 05:39:45
Removed logic (cont)
--------------------
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
@ -360,7 +371,6 @@ Signal N_1 undriven or does not drive anything - clipped.
Block nCRAS_pad_RNIBPVB was optimized away.
Block RASr2_RNIAFR1 was optimized away.
Block XOR8MEG.CN was optimized away.
Block GND was optimized away.
Block ufmefb/VCC was optimized away.
Block ufmefb/GND was optimized away.
@ -380,6 +390,16 @@ Embedded Functional Block Connection Summary
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
Page 6
Design: RAM2GS Date: 10/19/23 23:50:56
Embedded Functional Block Connection Summary (cont)
---------------------------------------------------
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
@ -390,16 +410,6 @@ Embedded Functional Block Connection Summary
Timer/Counter Function Summary:
------------------------------
None
Page 6
Design: RAM2GS Date: 09/21/23 05:39:45
Embedded Functional Block Connection Summary (cont)
---------------------------------------------------
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
@ -436,16 +446,6 @@ Run Time and Memory Usage

14
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad
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@ -6,7 +6,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.44
Thu Sep 21 05:39:56 2023
Thu Oct 19 23:51:05 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@ -53,11 +53,12 @@ Pinout by Port Name:
| RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
| RA[9] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| RBA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
| RCLKout | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:FAST |
| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
@ -134,7 +135,7 @@ Pinout by Pin Number:
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
| 47/2 | RA[9] | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
@ -146,7 +147,7 @@ Pinout by Pin Number:
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
| 62/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
@ -264,11 +265,12 @@ LOCATE COMP "RA[5]" SITE "70";
LOCATE COMP "RA[6]" SITE "68";
LOCATE COMP "RA[7]" SITE "75";
LOCATE COMP "RA[8]" SITE "65";
LOCATE COMP "RA[9]" SITE "62";
LOCATE COMP "RA[9]" SITE "47";
LOCATE COMP "RBA[0]" SITE "58";
LOCATE COMP "RBA[1]" SITE "60";
LOCATE COMP "RCKE" SITE "53";
LOCATE COMP "RCLK" SITE "63";
LOCATE COMP "RCLKout" SITE "62";
LOCATE COMP "RDQMH" SITE "51";
LOCATE COMP "RDQML" SITE "48";
LOCATE COMP "RD[0]" SITE "36";
@ -297,5 +299,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Sep 21 05:39:59 2023
Thu Oct 19 23:51:08 2023

6
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
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@ -1,5 +1,5 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:39:45 2023
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Oct 19 23:50:57 2023
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;
@ -11,6 +11,7 @@ LOCATE COMP "nRCAS" SITE "52" ;
LOCATE COMP "nRRAS" SITE "54" ;
LOCATE COMP "nRWE" SITE "49" ;
LOCATE COMP "RCKE" SITE "53" ;
LOCATE COMP "RCLKout" SITE "62" ;
LOCATE COMP "RCLK" SITE "63" ;
LOCATE COMP "nRCS" SITE "57" ;
LOCATE COMP "RD[7]" SITE "43" ;
@ -22,7 +23,7 @@ LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "RA[11]" SITE "59" ;
LOCATE COMP "RA[10]" SITE "64" ;
LOCATE COMP "RA[9]" SITE "62" ;
LOCATE COMP "RA[9]" SITE "47" ;
LOCATE COMP "RA[8]" SITE "65" ;
LOCATE COMP "RA[7]" SITE "75" ;
LOCATE COMP "RA[6]" SITE "68" ;
@ -110,4 +111,5 @@ OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
OUTPUT PORT "RCLKout" LOAD 5.000000 pF ;
COMMERCIAL ;

501
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr
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@ -3,7 +3,7 @@
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Sep 21 05:39:34 2023
# Thu Oct 19 23:50:47 2023
#Implementation: impl1
@ -51,10 +51,16 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\REFB.v" (library work)
Verilog syntax check successful!
Compiler output is up to date. No re-compile necessary
Selecting top level module RAM2GS
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
Running optimization stage 1 on ODDRXE .......
Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@ -65,6 +71,9 @@ Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current:
Running optimization stage 1 on REFB .......
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:6:46:6|Port-width mismatch for port D0. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:14:46:14|Port-width mismatch for port D1. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":47:7:47:7|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
Running optimization stage 1 on RAM2GS .......
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2GS .......
@ -77,13 +86,15 @@ Running optimization stage 2 on VLO .......
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VHI .......
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on ODDRXE .......
Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:39:35 2023
# Thu Oct 19 23:50:47 2023
###########################################################]
###########################################################[
@ -110,7 +121,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:39:35 2023
# Thu Oct 19 23:50:48 2023
###########################################################]
@ -125,7 +136,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:39:35 2023
# Thu Oct 19 23:50:48 2023
###########################################################]
###########################################################[
@ -146,18 +157,17 @@ Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:39:36 2023
# Thu Oct 19 23:50:49 2023
###########################################################]
Premap Report
# Thu Sep 21 05:39:37 2023
# Thu Oct 19 23:50:49 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -179,7 +189,7 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
@ -223,17 +233,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2GS
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@ -317,12 +327,10 @@ Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Sep 21 05:39:38 2023
# Thu Oct 19 23:50:50 2023
###########################################################]
Map & Optimize Report
# Thu Sep 21 05:39:39 2023
# Thu Oct 19 23:50:50 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -341,42 +349,42 @@ Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":150:4:150:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":156:4:156:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
@N: FX493 |Applying initial value "0" on instance IS[0].
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: FX493 |Applying initial value "0" on instance IS[1].
@N: FX493 |Applying initial value "0" on instance IS[2].
@N: FX493 |Applying initial value "0" on instance IS[3].
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
Available hyper_sources - for debug and ip models
@ -398,50 +406,63 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s -2.98ns 201 / 106
2 0h:00m:01s -2.98ns 217 / 106
3 0h:00m:01s -2.76ns 215 / 106
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":121:4:121:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":304:4:304:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 11 loads 1 time to improve timing.
1 0h:00m:01s -2.76ns 193 / 106
2 0h:00m:01s -2.76ns 209 / 106
3 0h:00m:01s -2.76ns 208 / 106
4 0h:00m:01s -2.76ns 206 / 106
5 0h:00m:01s -2.76ns 206 / 106
6 0h:00m:01s -2.76ns 205 / 106
7 0h:00m:01s -2.76ns 205 / 106
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":310:4:310:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
Timing driven replication report
Added 3 Registers via timing driven replication
Added 1 LUTs via timing driven replication
Added 4 Registers via timing driven replication
Added 2 LUTs via timing driven replication
4 0h:00m:02s -1.97ns 220 / 109
8 0h:00m:01s -1.83ns 209 / 110
9 0h:00m:01s -1.83ns 209 / 110
10 0h:00m:01s -1.83ns 209 / 110
11 0h:00m:01s -1.83ns 209 / 110
12 0h:00m:01s -1.83ns 209 / 110
5 0h:00m:02s -1.97ns 220 / 109
13 0h:00m:01s -1.83ns 208 / 110
14 0h:00m:01s -1.83ns 209 / 110
15 0h:00m:01s -1.83ns 209 / 110
16 0h:00m:01s -1.83ns 209 / 110
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB)
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 196MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 198MB peak: 198MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 201MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 202MB)
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:8:43:10|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock RCLK with period 16.00ns
@N: MT615 |Found clock PHI2 with period 350.00ns
@ -450,7 +471,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0
##### START OF TIMING REPORT #####[
# Timing report written on Thu Sep 21 05:39:43 2023
# Timing report written on Thu Oct 19 23:50:54 2023
#
@ -470,15 +491,15 @@ Performance Summary
*******************
Worst slack in design: -2.605
Worst slack in design: -1.828
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------
PHI2 2.9 MHz 1.0 MHz 350.000 989.870 -1.828 declared default_clkgroup
RCLK 62.5 MHz 17.3 MHz 16.000 57.686 -0.784 declared default_clkgroup
RCLK 62.5 MHz 22.1 MHz 16.000 45.251 -0.784 declared default_clkgroup
nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup
nCRAS 2.9 MHz 0.8 MHz 350.000 1261.890 -2.605 declared default_clkgroup
nCRAS 2.9 MHz 1.1 MHz 350.000 942.410 -1.693 declared default_clkgroup
System 100.0 MHz NA 10.000 NA 12.918 system system_clkgroup
===================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@ -501,12 +522,12 @@ Starting Ending | constraint slack | constraint slack | constraint
---------------------------------------------------------------------------------------------------------------
System RCLK | 16.000 12.918 | No paths - | No paths - | No paths -
RCLK System | 16.000 14.956 | No paths - | No paths - | No paths -
RCLK RCLK | 16.000 9.040 | No paths - | No paths - | No paths -
RCLK RCLK | 16.000 9.100 | No paths - | No paths - | No paths -
RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths -
RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths -
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828
PHI2 PHI2 | No paths - | 350.000 346.603 | 175.000 169.081 | 175.000 173.428
nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -2.605
PHI2 PHI2 | No paths - | 350.000 347.156 | 175.000 169.041 | 175.000 173.428
nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.693
===============================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
@ -540,30 +561,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589
CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572
CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.081
Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.041
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.041
Bank_0io[4] PHI2 IFS1P3DX Q Bank[4] 0.972 169.041
==========================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------
wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
=========================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------
wb_adr[0] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[1] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[2] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[3] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[4] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[5] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[6] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[7] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_dati[0] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_dati[1] PHI2 FD1P3AX SP N_122 0.528 -1.828
==============================================================================
@ -579,7 +600,7 @@ Path information for path number 1:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.828
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@ -594,7 +615,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i_0 Net - - - - 17
N_122 Net - - - - 17
wb_adr[0] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@ -607,7 +628,7 @@ Path information for path number 2:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.828
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@ -622,7 +643,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i_0 Net - - - - 17
N_122 Net - - - - 17
wb_adr[7] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@ -635,7 +656,7 @@ Path information for path number 3:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.828
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@ -650,7 +671,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i_0 Net - - - - 17
N_122 Net - - - - 17
wb_adr[6] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@ -663,7 +684,7 @@ Path information for path number 4:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.828
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@ -678,7 +699,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i_0 Net - - - - 17
N_122 Net - - - - 17
wb_adr[5] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@ -691,7 +712,7 @@ Path information for path number 5:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.828
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@ -706,7 +727,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i_0 Net - - - - 17
N_122 Net - - - - 17
wb_adr[4] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@ -729,13 +750,13 @@ Instance Reference Type Pin Net Time Slac
Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784
LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676
n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636
IS[1] RCLK FD1P3AX Q IS[1] 1.204 9.040
IS[2] RCLK FD1P3AX Q IS[2] 1.188 9.056
IS[3] RCLK FD1P3AX Q IS[3] 1.148 9.096
InitReady RCLK FD1S3AX Q InitReady 1.339 9.228
FS[15] RCLK FD1S3AX Q FS[15] 1.228 9.339
FS[16] RCLK FD1S3AX Q FS[16] 1.188 9.379
FS[17] RCLK FD1S3AX Q FS[17] 1.188 9.379
FS[12] RCLK FD1S3AX Q FS[12] 1.288 9.100
FS[11] RCLK FD1S3AX Q FS[11] 1.280 9.108
FS[9] RCLK FD1S3AX Q FS[9] 1.256 9.132
InitReady RCLK FD1S3AX Q InitReady 1.317 9.708
FS[16] RCLK FD1S3AX Q FS[16] 1.180 9.845
FS[17] RCLK FD1S3AX Q FS[17] 1.180 9.845
FS[15] RCLK FD1S3AX Q FS[15] 1.148 9.877
==================================================================================
@ -832,7 +853,7 @@ Path information for path number 3:
Number of logic level(s): 1
Starting point: Ready_fast / Q
Ending point: RowA[0] / D
Ending point: RowA[1] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@ -841,10 +862,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
RowAd[0] ORCALUT4 B In 0.000 1.256 r -
RowAd[0] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[0] Net - - - - 1
RowA[0] FD1S3AX D In 0.000 1.873 r -
RowAd[1] ORCALUT4 B In 0.000 1.256 r -
RowAd[1] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[1] Net - - - - 1
RowA[1] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@ -860,7 +881,7 @@ Path information for path number 4:
Number of logic level(s): 1
Starting point: Ready_fast / Q
Ending point: RowA[5] / D
Ending point: RowA[4] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@ -869,10 +890,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
RowAd[5] ORCALUT4 B In 0.000 1.256 r -
RowAd[5] ORCALUT4 Z Out 0.617 1.873 f -
RowAd_0[5] Net - - - - 1
RowA[5] FD1S3AX D In 0.000 1.873 f -
RowAd[4] ORCALUT4 B In 0.000 1.256 r -
RowAd[4] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[4] Net - - - - 1
RowA[4] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@ -888,7 +909,7 @@ Path information for path number 5:
Number of logic level(s): 1
Starting point: Ready_fast / Q
Ending point: RowA[8] / D
Ending point: RowA[2] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@ -897,10 +918,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
RowAd[8] ORCALUT4 B In 0.000 1.256 r -
RowAd[8] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[8] Net - - - - 1
RowA[8] FD1S3AX D In 0.000 1.873 r -
RowAd[2] ORCALUT4 B In 0.000 1.256 r -
RowAd[2] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[2] Net - - - - 1
RowA[2] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@ -915,29 +936,30 @@ Detailed Report for Clock: nCRAS
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------
CBR_fast nCRAS FD1S3AX Q CBR_fast 0.972 -2.605
CBR nCRAS FD1S3AX Q CBR 1.180 -1.797
FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797
==============================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
CBR nCRAS FD1S3AX Q CBR 1.148 -1.693
FWEr nCRAS FD1S3AX Q FWEr 1.148 -1.693
CBR_fast nCRAS FD1S3AX Q CBR_fast 1.044 -1.661
FWEr_fast nCRAS FD1S3AX Q FWEr_fast 0.972 -1.589
================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------
nRCAS_0io nCRAS OFS1P3BX D N_248_i 1.089 -2.605
nRCS_0io nCRAS OFS1P3BX D N_247_i 1.089 -1.797
nRWE_0io nCRAS OFS1P3BX D N_49_i 1.089 -1.797
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0_0 1.089 -1.797
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
==========================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.693
nRCAS_0io nCRAS OFS1P3BX D N_242_i 1.089 -1.693
nRCS_0io nCRAS OFS1P3BX D N_28_i 1.089 -1.693
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.693
nRWE_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.661
========================================================================================
@ -951,32 +973,29 @@ Path information for path number 1:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 3.694
- Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -2.605
= Slack (non-critical) : -1.693
Number of logic level(s): 3
Starting point: CBR_fast / Q
Number of logic level(s): 2
Starting point: CBR / Q
Ending point: nRCAS_0io / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------
CBR_fast FD1S3AX Q Out 0.972 0.972 r -
CBR_fast Net - - - - 1
CBR_fast_RNIQ31K1 ORCALUT4 A In 0.000 0.972 r -
CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r -
nRCAS_0_sqmuxa_1 Net - - - - 2
nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r -
nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r -
N_248_i_sx Net - - - - 1
nRCAS_0io_RNO ORCALUT4 D In 0.000 3.077 r -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f -
N_248_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 3.694 f -
====================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
CBR FD1S3AX Q Out 1.148 1.148 r -
CBR Net - - - - 4
nRCAS_0io_RNO_0 ORCALUT4 A In 0.000 1.148 r -
nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f -
N_242_i_1 Net - - - - 1
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 f -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r -
N_242_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 2.781 r -
==================================================================================
Path information for path number 2:
@ -985,29 +1004,29 @@ Path information for path number 2:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 2.885
- Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.797
= Slack (non-critical) : -1.693
Number of logic level(s): 2
Starting point: CBR / Q
Ending point: nRCS_0io / D
Starting point: FWEr / Q
Ending point: RCKEEN / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------
CBR FD1S3AX Q Out 1.180 1.180 r -
CBR Net - - - - 5
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
N_590 Net - - - - 2
nRCS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
N_247_i Net - - - - 1
nRCS_0io OFS1P3BX D In 0.000 2.885 r -
======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
FWEr FD1S3AX Q Out 1.148 1.148 r -
FWEr Net - - - - 4
RCKEEN_8_u_1_0 ORCALUT4 C In 0.000 1.148 r -
RCKEEN_8_u_1_0 ORCALUT4 Z Out 1.017 2.165 r -
RCKEEN_8_u_1 Net - - - - 1
RCKEEN_8_u ORCALUT4 C In 0.000 2.165 r -
RCKEEN_8_u ORCALUT4 Z Out 0.617 2.781 r -
RCKEEN_8 Net - - - - 1
RCKEEN FD1S3AX D In 0.000 2.781 r -
=================================================================================
Path information for path number 3:
@ -1016,29 +1035,29 @@ Path information for path number 3:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 2.885
- Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.797
= Slack (non-critical) : -1.693
Number of logic level(s): 2
Starting point: FWEr / Q
Ending point: nRCAS_0io / D
Starting point: CBR / Q
Ending point: nRowColSel / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
FWEr FD1S3AX Q Out 1.180 1.180 r -
FWEr Net - - - - 5
nRCAS_r_i_0_a2 ORCALUT4 B In 0.000 1.180 r -
nRCAS_r_i_0_a2 ORCALUT4 Z Out 1.089 2.269 f -
N_248_i_1_0 Net - - - - 2
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
N_248_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
=================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------
CBR FD1S3AX Q Out 1.148 1.148 r -
CBR Net - - - - 4
nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.148 r -
nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.017 2.165 f -
N_255 Net - - - - 1
nRowColSel_0_0 ORCALUT4 B In 0.000 2.165 f -
nRowColSel_0_0 ORCALUT4 Z Out 0.617 2.781 f -
nRowColSel_0_0 Net - - - - 1
nRowColSel FD1S3IX D In 0.000 2.781 f -
======================================================================================
Path information for path number 4:
@ -1047,29 +1066,29 @@ Path information for path number 4:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 2.885
- Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.797
= Slack (non-critical) : -1.693
Number of logic level(s): 2
Starting point: CBR / Q
Ending point: nRWE_0io / D
Starting point: FWEr / Q
Ending point: nRCS_0io / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------
CBR FD1S3AX Q Out 1.180 1.180 r -
CBR Net - - - - 5
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
N_590 Net - - - - 2
nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
N_49_i Net - - - - 1
nRWE_0io OFS1P3BX D In 0.000 2.885 r -
======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
FWEr FD1S3AX Q Out 1.148 1.148 r -
FWEr Net - - - - 4
nRCS_0io_RNO_0 ORCALUT4 B In 0.000 1.148 r -
nRCS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f -
nRCS_0io_RNO_0 Net - - - - 1
nRCS_0io_RNO ORCALUT4 B In 0.000 2.165 f -
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r -
N_28_i Net - - - - 1
nRCS_0io OFS1P3BX D In 0.000 2.781 r -
=================================================================================
Path information for path number 5:
@ -1078,9 +1097,9 @@ Path information for path number 5:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 2.885
- Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.797
= Slack (non-critical) : -1.693
Number of logic level(s): 2
Starting point: FWEr / Q
@ -1088,19 +1107,19 @@ Path information for path number 5:
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------
FWEr FD1S3AX Q Out 1.180 1.180 r -
FWEr Net - - - - 5
nRowColSel_0_0_0_a2 ORCALUT4 B In 0.000 1.180 r -
nRowColSel_0_0_0_a2 ORCALUT4 Z Out 1.089 2.269 r -
N_248_i_1_1 Net - - - - 2
nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f -
N_248_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 2.885 f -
======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
FWEr FD1S3AX Q Out 1.148 1.148 r -
FWEr Net - - - - 4
nRCAS_0io_RNO_0 ORCALUT4 C In 0.000 1.148 r -
nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 r -
N_242_i_1 Net - - - - 1
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 r -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 f -
N_242_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 2.781 f -
==================================================================================
@ -1133,7 +1152,7 @@ Instance Reference Type Pin Net Time Sla
-----------------------------------------------------------------------------------
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
wb_cyc_stb System FD1P3IX SP N_178 15.528 14.912
wb_cyc_stb System FD1P3IX SP N_103 15.528 14.912
===================================================================================
@ -1159,25 +1178,25 @@ Path information for path number 1:
The start point is clocked by System [rising]
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
wb_ack Net - - - - 2
ufmefb.EFBInst_0_RNISGNB ORCALUT4 D In 0.000 0.000 r -
ufmefb.EFBInst_0_RNISGNB ORCALUT4 Z Out 1.017 1.017 r -
g0_0_a3_2 Net - - - - 1
ufmefb.EFBInst_0_RNISI191 ORCALUT4 C In 0.000 1.017 r -
ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r -
N_4 Net - - - - 1
CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r -
CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r -
CmdValid_RNIOOBE2 Net - - - - 2
LEDENe ORCALUT4 B In 0.000 2.554 r -
LEDENe ORCALUT4 Z Out 0.617 3.171 r -
LEDENe_0 Net - - - - 1
LEDEN FD1S3AX D In 0.000 3.171 r -
==============================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
wb_ack Net - - - - 2
ufmefb.EFBInst_0_RNI8K48 ORCALUT4 C In 0.000 0.000 r -
ufmefb.EFBInst_0_RNI8K48 ORCALUT4 Z Out 0.449 0.449 r -
g0_0_a3_1 Net - - - - 1
wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 D In 0.000 0.449 r -
wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 Z Out 1.017 1.466 r -
N_4 Net - - - - 1
CmdValid_RNITBH02 ORCALUT4 C In 0.000 1.466 r -
CmdValid_RNITBH02 ORCALUT4 Z Out 1.089 2.554 r -
CmdValid_RNITBH02 Net - - - - 2
LEDENe ORCALUT4 B In 0.000 2.554 r -
LEDENe ORCALUT4 Z Out 0.617 3.171 r -
LEDENe_0 Net - - - - 1
LEDEN FD1S3AX D In 0.000 3.171 r -
=====================================================================================================
@ -1185,18 +1204,18 @@ LEDEN FD1S3AX D In 0.000 3.171 r
Timing exceptions that could not be applied
Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB)
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 109 of 1280 (9%)
Register bits: 110 of 1280 (9%)
PIC Latch: 0
I/O cells: 63
I/O cells: 64
Details:
@ -1205,26 +1224,26 @@ CCU2D: 10
EFB: 1
FD1P3AX: 25
FD1P3IX: 2
FD1S3AX: 53
FD1S3AX: 54
FD1S3IX: 4
GSR: 1
IB: 25
IFS1P3DX: 9
INV: 7
OB: 30
OB: 31
ODDRXE: 1
OFS1P3BX: 4
OFS1P3DX: 11
OFS1P3JX: 1
ORCALUT4: 213
PFUMX: 1
ORCALUT4: 203
PUR: 1
VHI: 2
VLO: 2
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB)
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 202MB)
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Thu Sep 21 05:39:43 2023
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Thu Oct 19 23:50:54 2023
###########################################################]

110
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1
View File

@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Sep 21 05:39:46 2023
Thu Oct 19 23:50:57 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -42,42 +42,42 @@ Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
Passed: The following path meets requirements by 163.779ns (weighted slack = 327.558ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
Delay: 8.469ns (36.0% logic, 64.0% route), 6 logic levels.
Constraint Details:
9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
8.469ns physical path delay Din[0]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.779ns
Physical Path Details:
Data path Din[0]_MGIOL to SLICE_17:
Data path Din[0]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0]
CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93
ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84
ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3
CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
ROUTE 1 e 1.234 SLICE_33.F0 to SLICE_17.D0 CmdEnable_0_sqmuxa
CTOF_DEL --- 0.495 SLICE_17.D0 to SLICE_17.F0 SLICE_17
ROUTE 1 e 0.001 SLICE_17.F0 to SLICE_17.DI0 CmdEnable_s (to PHI2_c)
ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_89.A0 Bank[0]
CTOF_DEL --- 0.495 SLICE_89.A0 to SLICE_89.F0 SLICE_89
ROUTE 1 e 1.234 SLICE_89.F0 to SLICE_75.C1 un1_ADWR_i_o2_10
CTOF_DEL --- 0.495 SLICE_75.C1 to SLICE_75.F1 SLICE_75
ROUTE 8 e 0.480 SLICE_75.F1 to SLICE_75.B0 N_294
CTOF_DEL --- 0.495 SLICE_75.B0 to SLICE_75.F0 SLICE_75
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_73.C0 N_382
CTOF_DEL --- 0.495 SLICE_73.C0 to SLICE_73.F0 SLICE_73
ROUTE 2 e 1.234 SLICE_73.F0 to SLICE_10.C0 CmdEnable17
CTOF_DEL --- 0.495 SLICE_10.C0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
9.223 (33.1% logic, 66.9% route), 6 logic levels.
8.469 (36.0% logic, 64.0% route), 6 logic levels.
Report: 53.254MHz is the maximum frequency for this preference.
Report: 57.904MHz is the maximum frequency for this preference.
================================================================================
@ -118,48 +118,48 @@ Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
878 items scored, 0 timing errors detected.
868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.049ns
Passed: The following path meets requirements by 5.761ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS[1] (from RCLK_c +)
Destination: FF Data in nRCAS_0io (to RCLK_c +)
Source: FF Q FS[11] (from RCLK_c +)
Destination: FF Data in wb_adr[0] (to RCLK_c +)
Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels.
Delay: 10.073ns (34.0% logic, 66.0% route), 7 logic levels.
Constraint Details:
9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
10.073ns physical path delay SLICE_4 to SLICE_48 meets
16.000ns delay constraint less
0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns
0.166ns DIN_SET requirement (totaling 15.834ns) by 5.761ns
Physical Path Details:
Data path SLICE_27 to nRCAS_MGIOL:
Data path SLICE_4 to SLICE_48:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c)
ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1]
CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74
ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74
ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408
CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61
ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61
ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1
CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94
ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
REG_DEL --- 0.452 SLICE_4.CLK to SLICE_4.Q0 SLICE_4 (from RCLK_c)
ROUTE 21 e 1.234 SLICE_4.Q0 to SLICE_66.B1 FS[11]
CTOF_DEL --- 0.495 SLICE_66.B1 to SLICE_66.F1 SLICE_66
ROUTE 1 e 0.480 SLICE_66.F1 to SLICE_66.D0 wb_adr_5_i_i_a2_3_0[0]
CTOF_DEL --- 0.495 SLICE_66.D0 to SLICE_66.F0 SLICE_66
ROUTE 1 e 1.234 SLICE_66.F0 to SLICE_86.D0 wb_adr_5_i_i_1_0_tz_0[0]
CTOF_DEL --- 0.495 SLICE_86.D0 to SLICE_86.F0 SLICE_86
ROUTE 1 e 1.234 SLICE_86.F0 to SLICE_85.C0 wb_adr_5_i_i_1_0[0]
CTOF_DEL --- 0.495 SLICE_85.C0 to SLICE_85.F0 SLICE_85
ROUTE 1 e 1.234 SLICE_85.F0 to SLICE_77.D0 wb_adr_5_i_i_1[0]
CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_48.D0 wb_adr_5_i_i_5[0]
CTOF_DEL --- 0.495 SLICE_48.D0 to SLICE_48.F0 SLICE_48
ROUTE 1 e 0.001 SLICE_48.F0 to SLICE_48.DI0 N_283 (to RCLK_c)
--------
9.798 (34.9% logic, 65.1% route), 7 logic levels.
10.073 (34.0% logic, 66.0% route), 7 logic levels.
Report: 100.492MHz is the maximum frequency for this preference.
Report: 97.666MHz is the maximum frequency for this preference.
Report Summary
--------------
@ -167,13 +167,13 @@ Report Summary
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 57.904 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 97.666 MHz| 7
| | |
----------------------------------------------------------------------------
@ -186,7 +186,7 @@ Clock Domains Analysis
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@ -198,7 +198,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@ -228,11 +228,11 @@ Timing summary (Setup):
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu Sep 21 05:39:46 2023
Thu Oct 19 23:50:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -284,7 +284,7 @@ Passed: The following path meets requirements by 0.447ns
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to PHI2_c)
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
@ -303,7 +303,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
================================================================================
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
878 items scored, 0 timing errors detected.
868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
@ -357,7 +357,7 @@ Clock Domains Analysis
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@ -369,7 +369,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@ -399,7 +399,7 @@ Timing summary (Hold):
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage)

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@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Sep 21 05:40:13 2023
Thu Oct 19 23:51:23 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
Design name: RAM2GS
@ -80,10 +80,20 @@ Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.bit".
Total CPU Time: 4 secs
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 511 Pages (128*511 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Peak Memory Usage: 274 MB
Peak Memory Usage: 275 MB

3
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_cck.rpt
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@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Thu Sep 21 05:39:38 2023
# Written on Thu Oct 19 23:50:50 2023
##### DESIGN INFO #######################################################
@ -103,6 +103,7 @@ p:RA[11]
p:RBA[0]
p:RBA[1]
p:RCKE
p:RCLKout
p:RDQMH
p:RDQML
p:RD[0] (bidir end point)

171
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html
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@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4.
// Package: TQFP100
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
// Written on Thu Sep 21 05:40:06 2023
// Written on Thu Oct 19 23:51:14 2023
// M: Minimum Performance Grade
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
@ -50,96 +50,99 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
----------------------------------------------------------------------
CROW[0] nCRAS F 2.913 4 -0.274 M
CROW[1] nCRAS F 2.475 4 -0.161 M
Din[0] PHI2 F 5.366 4 4.293 4
Din[0] nCCAS F 1.448 4 -0.034 M
Din[1] PHI2 F 4.971 4 4.173 4
Din[1] nCCAS F 0.519 4 0.708 4
Din[2] PHI2 F 5.192 4 4.173 4
Din[2] nCCAS F 1.948 4 -0.142 M
Din[3] PHI2 F 5.298 4 4.173 4
Din[3] nCCAS F 1.974 4 -0.157 M
Din[4] PHI2 F 4.281 4 4.173 4
Din[4] nCCAS F 1.060 4 0.217 4
Din[5] PHI2 F 5.059 4 4.173 4
Din[5] nCCAS F 1.956 4 -0.150 M
Din[6] PHI2 F 4.644 4 4.293 4
Din[6] nCCAS F 2.886 4 -0.382 M
Din[7] PHI2 F 5.316 4 4.293 4
Din[7] nCCAS F 2.381 4 -0.244 M
MAin[0] PHI2 F 4.362 4 1.145 4
MAin[0] nCRAS F 1.189 4 0.362 4
MAin[1] PHI2 F 4.386 4 0.999 4
MAin[1] nCRAS F 1.884 4 -0.024 M
MAin[2] PHI2 F 9.426 4 -0.750 M
MAin[2] nCRAS F 1.136 4 0.453 4
MAin[3] PHI2 F 10.458 4 -0.997 M
MAin[3] nCRAS F 1.564 4 0.067 4
MAin[4] PHI2 F 11.109 4 -1.209 M
MAin[4] nCRAS F 1.390 4 0.207 4
MAin[5] PHI2 F 9.884 4 -0.896 M
MAin[5] nCRAS F 1.269 4 0.218 4
MAin[6] PHI2 F 9.859 4 -0.845 M
MAin[6] nCRAS F 0.889 4 0.653 4
MAin[7] PHI2 F 10.678 4 -1.070 M
MAin[7] nCRAS F 1.186 4 0.309 4
MAin[8] nCRAS F 1.639 4 0.014 M
MAin[9] nCRAS F 1.097 4 0.457 4
CROW[0] nCRAS F 1.569 4 0.268 6
CROW[1] nCRAS F 1.013 4 0.820 4
Din[0] PHI2 F 5.478 4 4.293 4
Din[0] nCCAS F 2.010 4 -0.119 M
Din[1] PHI2 F 4.088 4 4.173 4
Din[1] nCCAS F 0.601 4 0.796 4
Din[2] PHI2 F 4.967 4 4.173 4
Din[2] nCCAS F 0.811 4 0.583 4
Din[3] PHI2 F 3.810 4 4.173 4
Din[3] nCCAS F 1.136 4 0.322 4
Din[4] PHI2 F 4.400 4 4.173 4
Din[4] nCCAS F 0.762 4 0.590 4
Din[5] PHI2 F 5.595 4 4.173 4
Din[5] nCCAS F 0.779 4 0.576 4
Din[6] PHI2 F 5.120 4 4.293 4
Din[6] nCCAS F 2.036 4 -0.117 M
Din[7] PHI2 F 5.630 4 4.293 4
Din[7] nCCAS F 2.301 4 -0.192 M
MAin[0] PHI2 F 4.196 4 1.086 4
MAin[0] nCRAS F 0.152 6 1.567 4
MAin[1] PHI2 F 3.875 4 1.164 4
MAin[1] nCRAS F -0.177 M 2.102 4
MAin[2] PHI2 F 8.381 4 -0.693 M
MAin[2] nCRAS F -0.315 M 2.358 4
MAin[3] PHI2 F 7.199 4 -0.405 M
MAin[3] nCRAS F -0.173 M 1.962 4
MAin[4] PHI2 F 8.710 4 -0.769 M
MAin[4] nCRAS F 0.292 4 1.419 4
MAin[5] PHI2 F 8.562 4 -0.730 M
MAin[5] nCRAS F -0.055 M 1.752 4
MAin[6] PHI2 F 7.862 4 -0.604 M
MAin[6] nCRAS F -0.126 M 1.965 4
MAin[7] PHI2 F 8.829 4 -0.836 M
MAin[7] nCRAS F -0.122 M 1.960 4
MAin[8] nCRAS F -0.288 M 2.424 4
MAin[9] nCRAS F -0.212 M 2.196 4
PHI2 RCLK R -0.133 M 2.360 4
nCCAS RCLK R 2.943 4 -0.337 M
nCCAS nCRAS F 2.967 4 -0.214 M
nCRAS RCLK R 3.047 4 -0.402 M
nFWE PHI2 F 11.116 4 -1.189 M
nFWE nCRAS F 1.394 4 0.225 4
nCCAS RCLK R 3.627 4 -0.577 M
nCCAS nCRAS F 3.154 4 -0.145 M
nCRAS RCLK R 1.461 4 -0.017 M
nFWE PHI2 F 6.933 4 -0.318 M
nFWE nCRAS F 0.403 4 1.860 4
// Clock to Output Delay
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
------------------------------------------------------------------------
LED RCLK R 11.046 4 3.298 M
LED nCRAS F 11.710 4 3.359 M
RA[0] RCLK R 11.397 4 3.516 M
RA[0] nCRAS F 11.476 4 3.432 M
RA[10] RCLK R 7.888 4 2.711 M
RA[11] PHI2 R 9.755 4 3.200 M
RA[1] RCLK R 11.272 4 3.469 M
RA[1] nCRAS F 11.238 4 3.348 M
RA[2] RCLK R 11.235 4 3.468 M
RA[2] nCRAS F 11.665 4 3.453 M
RA[3] RCLK R 11.390 4 3.512 M
RA[3] nCRAS F 11.922 4 3.539 M
RA[4] RCLK R 11.662 4 3.573 M
RA[4] nCRAS F 11.818 4 3.505 M
RA[5] RCLK R 11.744 4 3.584 M
RA[5] nCRAS F 11.779 4 3.513 M
RA[6] RCLK R 11.738 4 3.607 M
RA[6] nCRAS F 11.836 4 3.531 M
RA[7] RCLK R 12.475 4 3.797 M
RA[7] nCRAS F 11.420 4 3.426 M
RA[8] RCLK R 11.122 4 3.431 M
RA[8] nCRAS F 11.667 4 3.471 M
RA[9] RCLK R 11.935 4 3.649 M
RA[9] nCRAS F 11.401 4 3.424 M
RBA[0] nCRAS F 8.903 4 2.891 M
RBA[1] nCRAS F 8.903 4 2.891 M
RCKE RCLK R 10.011 4 3.215 M
RDQMH RCLK R 10.790 4 3.354 M
RDQML RCLK R 11.053 4 3.450 M
RD[0] nCCAS F 8.977 4 3.012 M
RD[1] nCCAS F 8.977 4 3.012 M
RD[2] nCCAS F 8.977 4 3.012 M
RD[3] nCCAS F 8.977 4 3.012 M
RD[4] nCCAS F 8.977 4 3.012 M
RD[5] nCCAS F 8.977 4 3.012 M
RD[6] nCCAS F 8.977 4 3.012 M
RD[7] nCCAS F 8.977 4 3.012 M
nRCAS RCLK R 7.822 4 2.706 M
nRCS RCLK R 7.822 4 2.706 M
nRRAS RCLK R 7.822 4 2.706 M
nRWE RCLK R 7.803 4 2.713 M
LED RCLK R 10.948 4 3.270 M
LED nCRAS F 12.507 4 3.690 M
RA[0] RCLK R 13.208 4 4.000 M
RA[0] nCRAS F 13.040 4 3.935 M
RA[10] RCLK R 7.888 4 2.711 M
RA[11] PHI2 R 9.755 4 3.200 M
RA[1] RCLK R 13.332 4 4.024 M
RA[1] nCRAS F 12.944 4 3.885 M
RA[2] RCLK R 13.624 4 4.099 M
RA[2] nCRAS F 13.220 4 3.993 M
RA[3] RCLK R 13.506 4 4.055 M
RA[3] nCRAS F 13.322 4 4.022 M
RA[4] RCLK R 12.512 4 3.834 M
RA[4] nCRAS F 14.534 4 4.331 M
RA[5] RCLK R 13.530 4 4.069 M
RA[5] nCRAS F 13.126 4 3.963 M
RA[6] RCLK R 14.238 4 4.245 M
RA[6] nCRAS F 13.589 4 4.077 M
RA[7] RCLK R 13.759 4 4.129 M
RA[7] nCRAS F 13.371 4 3.990 M
RA[8] RCLK R 11.858 4 3.632 M
RA[8] nCRAS F 13.338 4 4.026 M
RA[9] RCLK R 11.007 4 3.423 M
RA[9] nCRAS F 12.651 4 3.856 M
RBA[0] nCRAS F 10.201 4 3.325 M
RBA[1] nCRAS F 10.201 4 3.325 M
RCKE RCLK R 9.754 4 3.167 M
RCLKout RCLK R 7.971 4 2.504 M
RDQMH RCLK R 11.153 4 3.458 M
RDQML RCLK R 11.133 4 3.466 M
RD[0] nCCAS F 9.354 4 3.132 M
RD[1] nCCAS F 9.354 4 3.132 M
RD[2] nCCAS F 9.354 4 3.132 M
RD[3] nCCAS F 9.354 4 3.132 M
RD[4] nCCAS F 9.354 4 3.132 M
RD[5] nCCAS F 9.354 4 3.132 M
RD[6] nCCAS F 9.354 4 3.132 M
RD[7] nCCAS F 9.354 4 3.132 M
nRCAS RCLK R 7.822 4 2.706 M
nRCS RCLK R 7.822 4 2.706 M
nRRAS RCLK R 7.822 4 2.706 M
nRWE RCLK R 7.803 4 2.713 M
WARNING: you must also run trce with hold speed: 4
WARNING: you must also run trce with setup speed: 6
WARNING: you must also run trce with hold speed: 6
WARNING: you must also run trce with setup speed: M

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@ -23,23 +23,35 @@ Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 09/21/23 05:39:45
Mapped on: 10/19/23 23:50:56
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 109 out of 1520 (7%)
PFU registers: 84 out of 1280 (7%)
Number of registers: 110 out of 1520 (7%)
PFU registers: 85 out of 1280 (7%)
PIO registers: 25 out of 240 (10%)
Number of SLICEs: 120 out of 640 (19%)
SLICEs as Logic/ROM: 120 out of 640 (19%)
Number of SLICEs: 115 out of 640 (18%)
SLICEs as Logic/ROM: 115 out of 640 (18%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 10 out of 640 (2%)
Number of LUT4s: 237 out of 1280 (19%)
Number used as logic LUTs: 217
Number of LUT4s: 229 out of 1280 (18%)
Number used as logic LUTs: 209
Number used as distributed RAM: 0
Number used as ripple logic: 20
Number used as shift registers: 0
Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
Number of PIO sites used: 64 + 4(JTAG) out of 80 (85%)
Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
Number of IDDR cells: 0
Number of ODDR cells: 1
Number of TDDR cells: 0
Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
Number of PIO using IDDR only: 0 (0 differential)
Number of PIO using ODDR only: 1 (0 differential)
Number of PIO using TDDR only: 0 (0 differential)
Number of PIO using IDDR/ODDR: 0 (0 differential)
Number of PIO using IDDR/TDDR: 0 (0 differential)
Number of PIO using ODDR/TDDR: 0 (0 differential)
Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
@ -55,6 +67,7 @@ Mapped on: 09/21/23 05:39:45
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
@ -66,15 +79,14 @@ Mapped on: 09/21/23 05:39:45
ripple logic.
Number of clocks: 4
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK )
Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
Number of Clock Enables: 5
Net N_178: 1 loads, 1 LSLICEs
Net N_103: 1 loads, 1 LSLICEs
Net XOR8MEG18: 5 loads, 5 LSLICEs
Net N_360_i: 2 loads, 2 LSLICEs
Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs
Net N_122: 9 loads, 9 LSLICEs
Net N_244_i: 2 loads, 2 LSLICEs
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
Number of LSRs: 5
Net RA10s_i: 1 loads, 0 LSLICEs
@ -84,16 +96,16 @@ Mapped on: 09/21/23 05:39:45
Net RASr2: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net InitReady: 41 loads
Net FS[11]: 23 loads
Net FS[13]: 22 loads
Net FS[10]: 21 loads
Net FS[12]: 21 loads
Net FS[9]: 20 loads
Net InitReady: 31 loads
Net FS[12]: 23 loads
Net FS[13]: 23 loads
Net FS[11]: 21 loads
Net N_132: 20 loads
Net FS[14]: 18 loads
Net CO0: 15 loads
Net FS[10]: 16 loads
Net FS[9]: 14 loads
Net Ready: 14 loads
Net Ready_fast: 14 loads
Net N_214: 13 loads
@ -116,6 +128,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+---------------------+-----------+-----------+------------+
@ -127,7 +140,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI2 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
| RDQML | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@ -141,6 +153,8 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+---------------------+-----------+-----------+------------+
| RCKE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RCLKout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RCLK | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nRCS | OUTPUT | LVCMOS33 | OUT |
@ -172,6 +186,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
| RA[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@ -184,7 +199,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
| RA[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
@ -229,6 +243,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
| CROW[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CROW[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[9] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@ -241,7 +256,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
| MAin[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MAin[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@ -260,7 +274,6 @@ Block GSR_INST undriven or does not drive anything - clipped.
Signal nCRAS_c_i was merged into signal nCRAS_c
Signal RASr2_i was merged into signal RASr2
Signal XOR8MEG.CN was merged into signal PHI2_c
Signal GND undriven or does not drive anything - clipped.
Signal ufmefb/VCC undriven or does not drive anything - clipped.
Signal ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
@ -288,6 +301,7 @@ Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
@ -299,7 +313,6 @@ Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
@ -326,7 +339,6 @@ Signal N_1 undriven or does not drive anything - clipped.
Block nCRAS_pad_RNIBPVB was optimized away.
Block RASr2_RNIAFR1 was optimized away.
Block XOR8MEG.CN was optimized away.
Block GND was optimized away.
Block ufmefb/VCC was optimized away.
Block ufmefb/GND was optimized away.
@ -347,6 +359,7 @@ Block ufmefb/GND was optimized away.
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
@ -357,7 +370,6 @@ Block ufmefb/GND was optimized away.
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
@ -400,16 +412,6 @@ Instance Name: ufmefb/EFBInst_0

14
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html
View File

@ -14,7 +14,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.44
Thu Sep 21 05:39:56 2023
Thu Oct 19 23:51:05 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@ -61,11 +61,12 @@ Pinout by Port Name:
| RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
| RA[9] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| RBA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
| RCLKout | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:FAST |
| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
@ -143,7 +144,7 @@ Vccio by Bank:
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
| 47/2 | RA[9] | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
@ -155,7 +156,7 @@ Vccio by Bank:
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
| 62/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
@ -273,11 +274,12 @@ LOCATE COMP "RA[5]" SITE "70";
LOCATE COMP "RA[6]" SITE "68";
LOCATE COMP "RA[7]" SITE "75";
LOCATE COMP "RA[8]" SITE "65";
LOCATE COMP "RA[9]" SITE "62";
LOCATE COMP "RA[9]" SITE "47";
LOCATE COMP "RBA[0]" SITE "58";
LOCATE COMP "RBA[1]" SITE "60";
LOCATE COMP "RCKE" SITE "53";
LOCATE COMP "RCLK" SITE "63";
LOCATE COMP "RCLKout" SITE "62";
LOCATE COMP "RDQMH" SITE "51";
LOCATE COMP "RDQML" SITE "48";
LOCATE COMP "RD[0]" SITE "36";
@ -306,7 +308,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Sep 21 05:39:59 2023
Thu Oct 19 23:51:08 2023

130
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html
View File

@ -12,7 +12,7 @@ Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Sep 21 05:39:49 2023
Thu Oct 19 23:50:59 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 5.578 0 0.304 0 13 Completed
5_1 * 0 5.798 0 0.304 0 12 Completed
* : Design saved.
Total (real) run time for 1-seed: 13 secs
Total (real) run time for 1-seed: 12 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Lattice Place and Route Report for Design &quot;RAM2GS_LCMXO2_1200HC_impl1_map.ncd&quot;
Thu Sep 21 05:39:49 2023
Thu Oct 19 23:50:59 2023
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
@ -63,47 +63,47 @@ Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 63+4(JTAG)/108 62% used
63+4(JTAG)/80 84% bonded
IOLOGIC 25/108 23% used
PIO (prelim) 64+4(JTAG)/108 63% used
64+4(JTAG)/80 85% bonded
IOLOGIC 26/108 24% used
SLICE 120/640 18% used
SLICE 115/640 17% used
EFB 1/1 100% used
Number of Signals: 388
Number of Connections: 1017
Number of Signals: 383
Number of Connections: 993
Pin Constraint Summary:
63 out of 63 pins locked (100% locked).
64 out of 64 pins locked (100% locked).
The following 2 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 47)
The following 3 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 48)
PHI2_c (driver: PHI2, clk load #: 20)
nCRAS_c (driver: nCRAS, clk load #: 10)
WARNING - par: Signal &quot;PHI2_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;PHI2&quot; is located at &quot;8&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal &quot;nCRAS_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;nCRAS&quot; is located at &quot;17&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 2 signals are selected to use the secondary clock routing resources:
nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0)
The following 1 signal is selected to use the secondary clock routing resources:
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
WARNING - par: Signal &quot;nCRAS_c&quot; is selected to use Secondary clock resources. However, its driver comp &quot;nCRAS&quot; is located at &quot;17&quot;, which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal &quot;nCCAS_c&quot; is selected to use Secondary clock resources. However, its driver comp &quot;nCCAS&quot; is located at &quot;9&quot;, which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0. REAL time: 0 secs
........
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
Placer score = 68062.
Finished Placer Phase 1. REAL time: 7 secs
.....................
Placer score = 66969.
Finished Placer Phase 1. REAL time: 6 secs
Starting Placer Phase 2.
.
Placer score = 67096
Finished Placer Phase 2. REAL time: 7 secs
Placer score = 66494
Finished Placer Phase 2. REAL time: 6 secs
@ -117,13 +117,13 @@ Global Clock Resources:
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on CLK_PIN site &quot;63 (PR5C)&quot;, clk load = 47
PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on CLK_PIN site &quot;63 (PR5C)&quot;, clk load = 48
PRIMARY &quot;PHI2_c&quot; from comp &quot;PHI2&quot; on PIO site &quot;8 (PL3D)&quot;, clk load = 20
SECONDARY &quot;nCRAS_c&quot; from comp &quot;nCRAS&quot; on PIO site &quot;17 (PL8B)&quot;, clk load = 9, ce load = 0, sr load = 0
PRIMARY &quot;nCRAS_c&quot; from comp &quot;nCRAS&quot; on PIO site &quot;17 (PL8B)&quot;, clk load = 10
SECONDARY &quot;nCCAS_c&quot; from comp &quot;nCCAS&quot; on PIO site &quot;9 (PL4A)&quot;, clk load = 8, ce load = 0, sr load = 0
PRIMARY : 2 out of 8 (25%)
SECONDARY: 2 out of 8 (25%)
PRIMARY : 3 out of 8 (37%)
SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
@ -132,9 +132,9 @@ Edge Clocks:
I/O Usage Summary (final):
63 + 4(JTAG) out of 108 (62.0%) PIO sites used.
63 + 4(JTAG) out of 80 (83.8%) bonded PIO sites used.
Number of PIO comps: 63; differential: 0.
64 + 4(JTAG) out of 108 (63.0%) PIO sites used.
64 + 4(JTAG) out of 80 (85.0%) bonded PIO sites used.
Number of PIO comps: 64; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
@ -143,20 +143,21 @@ I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
| 1 | 20 / 21 ( 95%) | 3.3V | - |
| 2 | 12 / 20 ( 60%) | 3.3V | - |
| 2 | 13 / 20 ( 65%) | 3.3V | - |
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 6 secs
Total placer CPU time: 5 secs
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
0 connections routed; 1017 unrouted.
0 connections routed; 993 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 11 secs
Completed router resource preassignment. Real time: 10 secs
Start NBR router at 05:40:00 09/21/23
Start NBR router at 23:51:09 10/19/23
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
@ -171,41 +172,50 @@ Note: NBR uses a different method to calculate timing slacks. The
your design.
*****************************************************************
Start NBR special constraint process at 05:40:00 09/21/23
Start NBR special constraint process at 23:51:09 10/19/23
Start NBR section for initial routing at 05:40:01 09/21/23
Start NBR section for initial routing at 23:51:09 10/19/23
Level 1, iteration 1
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.089ns/0.000ns; real time: 12 secs
0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.138ns/0.000ns; real time: 10 secs
Level 2, iteration 1
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.089ns/0.000ns; real time: 12 secs
0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.138ns/0.000ns; real time: 10 secs
Level 3, iteration 1
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.089ns/0.000ns; real time: 12 secs
0(0.00%) conflict; 795(80.06%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 6.138ns/0.000ns; real time: 10 secs
Level 4, iteration 1
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.578ns/0.000ns; real time: 12 secs
17(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.804ns/0.000ns; real time: 11 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 05:40:01 09/21/23
Start NBR section for normal routing at 23:51:10 10/19/23
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.578ns/0.000ns; real time: 12 secs
11(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
Level 4, iteration 2
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
Level 4, iteration 3
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
Level 4, iteration 4
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
Level 4, iteration 5
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.578ns/0.000ns; real time: 12 secs
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 05:40:01 09/21/23
Start NBR section for setup/hold timing optimization with effort level 3 at 23:51:10 10/19/23
Start NBR section for re-routing at 05:40:01 09/21/23
Start NBR section for re-routing at 23:51:10 10/19/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 5.578ns/0.000ns; real time: 12 secs
Estimated worst slack/total negative slack&lt;setup&gt;: 5.798ns/0.000ns; real time: 11 secs
Start NBR section for post-routing at 05:40:01 09/21/23
Start NBR section for post-routing at 23:51:10 10/19/23
End NBR router with 0 unrouted connection
@ -213,17 +223,17 @@ NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack&lt;setup&gt; : 5.578ns
Estimated worst slack&lt;setup&gt; : 5.798ns
Timing score&lt;setup&gt; : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 12 secs
Total REAL time: 13 secs
Total CPU time 11 secs
Total REAL time: 12 secs
Completely routed.
End of route. 1017 routed (100.00%); 0 unrouted.
End of route. 993 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
@ -237,14 +247,14 @@ All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 5.578
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 5.798
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.304
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 13 secs
Total REAL time to completion: 13 secs
Total CPU time to completion: 11 secs
Total REAL time to completion: 12 secs
par done!

2
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
View File

@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Thu Sep 21 05:39:37 2023
# Written on Thu Oct 19 23:50:49 2023
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"

2
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html
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@ -62,7 +62,7 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:40:22</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/10/20 00:05:05</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>

501
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_synplify.html
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@ -12,7 +12,7 @@
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Sep 21 05:39:34 2023
# Thu Oct 19 23:50:47 2023
#Implementation: impl1
@ -60,10 +60,16 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\REFB.v" (library work)
Verilog syntax check successful!
Compiler output is up to date. No re-compile necessary
Selecting top level module RAM2GS
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
Running optimization stage 1 on ODDRXE .......
Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@ -74,6 +80,9 @@ Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current:
Running optimization stage 1 on REFB .......
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":1:7:1:12|Synthesizing module RAM2GS in library work.
@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:6:46:6|Port-width mismatch for port D0. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":46:14:46:14|Port-width mismatch for port D1. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v":47:7:47:7|Port-width mismatch for port RST. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
Running optimization stage 1 on RAM2GS .......
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2GS .......
@ -86,13 +95,15 @@ Running optimization stage 2 on VLO .......
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VHI .......
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on ODDRXE .......
Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:39:35 2023
# Thu Oct 19 23:50:47 2023
###########################################################]
###########################################################[
@ -119,7 +130,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:39:35 2023
# Thu Oct 19 23:50:48 2023
###########################################################]
@ -134,7 +145,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:39:35 2023
# Thu Oct 19 23:50:48 2023
###########################################################]
###########################################################[
@ -155,18 +166,17 @@ Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:39:36 2023
# Thu Oct 19 23:50:49 2023
###########################################################]
Premap Report
# Thu Sep 21 05:39:37 2023
# Thu Oct 19 23:50:49 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -188,7 +198,7 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
@ -232,17 +242,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2GS
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@ -326,12 +336,10 @@ Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Sep 21 05:39:38 2023
# Thu Oct 19 23:50:50 2023
###########################################################]
Map & Optimize Report
# Thu Sep 21 05:39:39 2023
# Thu Oct 19 23:50:50 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -350,42 +358,42 @@ Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":150:4:150:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":156:4:156:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
@N: FX493 |Applying initial value "0" on instance IS[0].
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: FX493 |Applying initial value "0" on instance IS[1].
@N: FX493 |Applying initial value "0" on instance IS[2].
@N: FX493 |Applying initial value "0" on instance IS[3].
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
Available hyper_sources - for debug and ip models
@ -407,50 +415,63 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s -2.98ns 201 / 106
2 0h:00m:01s -2.98ns 217 / 106
3 0h:00m:01s -2.76ns 215 / 106
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":121:4:121:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":304:4:304:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 11 loads 1 time to improve timing.
1 0h:00m:01s -2.76ns 193 / 106
2 0h:00m:01s -2.76ns 209 / 106
3 0h:00m:01s -2.76ns 208 / 106
4 0h:00m:01s -2.76ns 206 / 106
5 0h:00m:01s -2.76ns 206 / 106
6 0h:00m:01s -2.76ns 205 / 106
7 0h:00m:01s -2.76ns 205 / 106
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":310:4:310:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":169:4:169:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":127:4:127:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
Timing driven replication report
Added 3 Registers via timing driven replication
Added 1 LUTs via timing driven replication
Added 4 Registers via timing driven replication
Added 2 LUTs via timing driven replication
4 0h:00m:02s -1.97ns 220 / 109
8 0h:00m:01s -1.83ns 209 / 110
9 0h:00m:01s -1.83ns 209 / 110
10 0h:00m:01s -1.83ns 209 / 110
11 0h:00m:01s -1.83ns 209 / 110
12 0h:00m:01s -1.83ns 209 / 110
5 0h:00m:02s -1.97ns 220 / 109
13 0h:00m:01s -1.83ns 208 / 110
14 0h:00m:01s -1.83ns 209 / 110
15 0h:00m:01s -1.83ns 209 / 110
16 0h:00m:01s -1.83ns 209 / 110
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 196MB peak: 196MB)
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB)
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 196MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 198MB peak: 198MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 201MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 202MB)
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:8:43:10|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock RCLK with period 16.00ns
@N: MT615 |Found clock PHI2 with period 350.00ns
@ -459,7 +480,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0
##### START OF TIMING REPORT #####[
# Timing report written on Thu Sep 21 05:39:43 2023
# Timing report written on Thu Oct 19 23:50:54 2023
#
@ -479,15 +500,15 @@ Performance Summary
*******************
Worst slack in design: -2.605
Worst slack in design: -1.828
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------
PHI2 2.9 MHz 1.0 MHz 350.000 989.870 -1.828 declared default_clkgroup
RCLK 62.5 MHz 17.3 MHz 16.000 57.686 -0.784 declared default_clkgroup
RCLK 62.5 MHz 22.1 MHz 16.000 45.251 -0.784 declared default_clkgroup
nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup
nCRAS 2.9 MHz 0.8 MHz 350.000 1261.890 -2.605 declared default_clkgroup
nCRAS 2.9 MHz 1.1 MHz 350.000 942.410 -1.693 declared default_clkgroup
System 100.0 MHz NA 10.000 NA 12.918 system system_clkgroup
===================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@ -510,12 +531,12 @@ Starting Ending | constraint slack | constraint slack | constraint
---------------------------------------------------------------------------------------------------------------
System RCLK | 16.000 12.918 | No paths - | No paths - | No paths -
RCLK System | 16.000 14.956 | No paths - | No paths - | No paths -
RCLK RCLK | 16.000 9.040 | No paths - | No paths - | No paths -
RCLK RCLK | 16.000 9.100 | No paths - | No paths - | No paths -
RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths -
RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths -
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828
PHI2 PHI2 | No paths - | 350.000 346.603 | 175.000 169.081 | 175.000 173.428
nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -2.605
PHI2 PHI2 | No paths - | 350.000 347.156 | 175.000 169.041 | 175.000 173.428
nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -1.693
===============================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
@ -549,30 +570,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589
CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572
CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.081
Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.041
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.041
Bank_0io[4] PHI2 IFS1P3DX Q Bank[4] 0.972 169.041
==========================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------
wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
=========================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------
wb_adr[0] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[1] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[2] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[3] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[4] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[5] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[6] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_adr[7] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_dati[0] PHI2 FD1P3AX SP N_122 0.528 -1.828
wb_dati[1] PHI2 FD1P3AX SP N_122 0.528 -1.828
==============================================================================
@ -588,7 +609,7 @@ Path information for path number 1:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.828
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@ -603,7 +624,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i_0 Net - - - - 17
N_122 Net - - - - 17
wb_adr[0] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@ -616,7 +637,7 @@ Path information for path number 2:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.828
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@ -631,7 +652,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i_0 Net - - - - 17
N_122 Net - - - - 17
wb_adr[7] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@ -644,7 +665,7 @@ Path information for path number 3:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.828
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@ -659,7 +680,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i_0 Net - - - - 17
N_122 Net - - - - 17
wb_adr[6] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@ -672,7 +693,7 @@ Path information for path number 4:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.828
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@ -687,7 +708,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i_0 Net - - - - 17
N_122 Net - - - - 17
wb_adr[5] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@ -700,7 +721,7 @@ Path information for path number 5:
- Propagation time: 2.357
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.828
= Slack (critical) : -1.828
Number of logic level(s): 1
Starting point: CmdUFMShift / Q
@ -715,7 +736,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
CmdUFMShift Net - - - - 2
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
un1_wb_rst14_i_0 Net - - - - 17
N_122 Net - - - - 17
wb_adr[4] FD1P3AX SP In 0.000 2.357 r -
=========================================================================================
@ -738,13 +759,13 @@ Instance Reference Type Pin Net Time Slac
Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784
LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676
n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636
IS[1] RCLK FD1P3AX Q IS[1] 1.204 9.040
IS[2] RCLK FD1P3AX Q IS[2] 1.188 9.056
IS[3] RCLK FD1P3AX Q IS[3] 1.148 9.096
InitReady RCLK FD1S3AX Q InitReady 1.339 9.228
FS[15] RCLK FD1S3AX Q FS[15] 1.228 9.339
FS[16] RCLK FD1S3AX Q FS[16] 1.188 9.379
FS[17] RCLK FD1S3AX Q FS[17] 1.188 9.379
FS[12] RCLK FD1S3AX Q FS[12] 1.288 9.100
FS[11] RCLK FD1S3AX Q FS[11] 1.280 9.108
FS[9] RCLK FD1S3AX Q FS[9] 1.256 9.132
InitReady RCLK FD1S3AX Q InitReady 1.317 9.708
FS[16] RCLK FD1S3AX Q FS[16] 1.180 9.845
FS[17] RCLK FD1S3AX Q FS[17] 1.180 9.845
FS[15] RCLK FD1S3AX Q FS[15] 1.148 9.877
==================================================================================
@ -841,7 +862,7 @@ Path information for path number 3:
Number of logic level(s): 1
Starting point: Ready_fast / Q
Ending point: RowA[0] / D
Ending point: RowA[1] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@ -850,10 +871,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
RowAd[0] ORCALUT4 B In 0.000 1.256 r -
RowAd[0] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[0] Net - - - - 1
RowA[0] FD1S3AX D In 0.000 1.873 r -
RowAd[1] ORCALUT4 B In 0.000 1.256 r -
RowAd[1] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[1] Net - - - - 1
RowA[1] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@ -869,7 +890,7 @@ Path information for path number 4:
Number of logic level(s): 1
Starting point: Ready_fast / Q
Ending point: RowA[5] / D
Ending point: RowA[4] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@ -878,10 +899,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
RowAd[5] ORCALUT4 B In 0.000 1.256 r -
RowAd[5] ORCALUT4 Z Out 0.617 1.873 f -
RowAd_0[5] Net - - - - 1
RowA[5] FD1S3AX D In 0.000 1.873 f -
RowAd[4] ORCALUT4 B In 0.000 1.256 r -
RowAd[4] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[4] Net - - - - 1
RowA[4] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@ -897,7 +918,7 @@ Path information for path number 5:
Number of logic level(s): 1
Starting point: Ready_fast / Q
Ending point: RowA[8] / D
Ending point: RowA[2] / D
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
@ -906,10 +927,10 @@ Name Type Name Dir Delay Time Fan Out(s
---------------------------------------------------------------------------------
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
Ready_fast Net - - - - 14
RowAd[8] ORCALUT4 B In 0.000 1.256 r -
RowAd[8] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[8] Net - - - - 1
RowA[8] FD1S3AX D In 0.000 1.873 r -
RowAd[2] ORCALUT4 B In 0.000 1.256 r -
RowAd[2] ORCALUT4 Z Out 0.617 1.873 r -
RowAd_0[2] Net - - - - 1
RowA[2] FD1S3AX D In 0.000 1.873 r -
=================================================================================
@ -924,29 +945,30 @@ Detailed Report for Clock: nCRAS
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------
CBR_fast nCRAS FD1S3AX Q CBR_fast 0.972 -2.605
CBR nCRAS FD1S3AX Q CBR 1.180 -1.797
FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797
==============================================================================
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
CBR nCRAS FD1S3AX Q CBR 1.148 -1.693
FWEr nCRAS FD1S3AX Q FWEr 1.148 -1.693
CBR_fast nCRAS FD1S3AX Q CBR_fast 1.044 -1.661
FWEr_fast nCRAS FD1S3AX Q FWEr_fast 0.972 -1.589
================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------
nRCAS_0io nCRAS OFS1P3BX D N_248_i 1.089 -2.605
nRCS_0io nCRAS OFS1P3BX D N_247_i 1.089 -1.797
nRWE_0io nCRAS OFS1P3BX D N_49_i 1.089 -1.797
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0_0 1.089 -1.797
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
==========================================================================================
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.693
nRCAS_0io nCRAS OFS1P3BX D N_242_i 1.089 -1.693
nRCS_0io nCRAS OFS1P3BX D N_28_i 1.089 -1.693
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.693
nRWE_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.661
========================================================================================
@ -960,32 +982,29 @@ Path information for path number 1:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 3.694
- Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : -2.605
= Slack (non-critical) : -1.693
Number of logic level(s): 3
Starting point: CBR_fast / Q
Number of logic level(s): 2
Starting point: CBR / Q
Ending point: nRCAS_0io / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------
CBR_fast FD1S3AX Q Out 0.972 0.972 r -
CBR_fast Net - - - - 1
CBR_fast_RNIQ31K1 ORCALUT4 A In 0.000 0.972 r -
CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r -
nRCAS_0_sqmuxa_1 Net - - - - 2
nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r -
nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r -
N_248_i_sx Net - - - - 1
nRCAS_0io_RNO ORCALUT4 D In 0.000 3.077 r -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f -
N_248_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 3.694 f -
====================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
CBR FD1S3AX Q Out 1.148 1.148 r -
CBR Net - - - - 4
nRCAS_0io_RNO_0 ORCALUT4 A In 0.000 1.148 r -
nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f -
N_242_i_1 Net - - - - 1
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 f -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r -
N_242_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 2.781 r -
==================================================================================
Path information for path number 2:
@ -994,29 +1013,29 @@ Path information for path number 2:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 2.885
- Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.797
= Slack (non-critical) : -1.693
Number of logic level(s): 2
Starting point: CBR / Q
Ending point: nRCS_0io / D
Starting point: FWEr / Q
Ending point: RCKEEN / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------
CBR FD1S3AX Q Out 1.180 1.180 r -
CBR Net - - - - 5
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
N_590 Net - - - - 2
nRCS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
N_247_i Net - - - - 1
nRCS_0io OFS1P3BX D In 0.000 2.885 r -
======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
FWEr FD1S3AX Q Out 1.148 1.148 r -
FWEr Net - - - - 4
RCKEEN_8_u_1_0 ORCALUT4 C In 0.000 1.148 r -
RCKEEN_8_u_1_0 ORCALUT4 Z Out 1.017 2.165 r -
RCKEEN_8_u_1 Net - - - - 1
RCKEEN_8_u ORCALUT4 C In 0.000 2.165 r -
RCKEEN_8_u ORCALUT4 Z Out 0.617 2.781 r -
RCKEEN_8 Net - - - - 1
RCKEEN FD1S3AX D In 0.000 2.781 r -
=================================================================================
Path information for path number 3:
@ -1025,29 +1044,29 @@ Path information for path number 3:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 2.885
- Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.797
= Slack (non-critical) : -1.693
Number of logic level(s): 2
Starting point: FWEr / Q
Ending point: nRCAS_0io / D
Starting point: CBR / Q
Ending point: nRowColSel / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
FWEr FD1S3AX Q Out 1.180 1.180 r -
FWEr Net - - - - 5
nRCAS_r_i_0_a2 ORCALUT4 B In 0.000 1.180 r -
nRCAS_r_i_0_a2 ORCALUT4 Z Out 1.089 2.269 f -
N_248_i_1_0 Net - - - - 2
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
N_248_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
=================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------
CBR FD1S3AX Q Out 1.148 1.148 r -
CBR Net - - - - 4
nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.148 r -
nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.017 2.165 f -
N_255 Net - - - - 1
nRowColSel_0_0 ORCALUT4 B In 0.000 2.165 f -
nRowColSel_0_0 ORCALUT4 Z Out 0.617 2.781 f -
nRowColSel_0_0 Net - - - - 1
nRowColSel FD1S3IX D In 0.000 2.781 f -
======================================================================================
Path information for path number 4:
@ -1056,29 +1075,29 @@ Path information for path number 4:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 2.885
- Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.797
= Slack (non-critical) : -1.693
Number of logic level(s): 2
Starting point: CBR / Q
Ending point: nRWE_0io / D
Starting point: FWEr / Q
Ending point: nRCS_0io / D
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------
CBR FD1S3AX Q Out 1.180 1.180 r -
CBR Net - - - - 5
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
N_590 Net - - - - 2
nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
N_49_i Net - - - - 1
nRWE_0io OFS1P3BX D In 0.000 2.885 r -
======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
FWEr FD1S3AX Q Out 1.148 1.148 r -
FWEr Net - - - - 4
nRCS_0io_RNO_0 ORCALUT4 B In 0.000 1.148 r -
nRCS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 f -
nRCS_0io_RNO_0 Net - - - - 1
nRCS_0io_RNO ORCALUT4 B In 0.000 2.165 f -
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.781 r -
N_28_i Net - - - - 1
nRCS_0io OFS1P3BX D In 0.000 2.781 r -
=================================================================================
Path information for path number 5:
@ -1087,9 +1106,9 @@ Path information for path number 5:
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 1.089
- Propagation time: 2.885
- Propagation time: 2.781
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : -1.797
= Slack (non-critical) : -1.693
Number of logic level(s): 2
Starting point: FWEr / Q
@ -1097,19 +1116,19 @@ Path information for path number 5:
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------
FWEr FD1S3AX Q Out 1.180 1.180 r -
FWEr Net - - - - 5
nRowColSel_0_0_0_a2 ORCALUT4 B In 0.000 1.180 r -
nRowColSel_0_0_0_a2 ORCALUT4 Z Out 1.089 2.269 r -
N_248_i_1_1 Net - - - - 2
nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f -
N_248_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 2.885 f -
======================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
FWEr FD1S3AX Q Out 1.148 1.148 r -
FWEr Net - - - - 4
nRCAS_0io_RNO_0 ORCALUT4 C In 0.000 1.148 r -
nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 2.165 r -
N_242_i_1 Net - - - - 1
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.165 r -
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.781 f -
N_242_i Net - - - - 1
nRCAS_0io OFS1P3BX D In 0.000 2.781 f -
==================================================================================
@ -1142,7 +1161,7 @@ Instance Reference Type Pin Net Time Sla
-----------------------------------------------------------------------------------
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
wb_cyc_stb System FD1P3IX SP N_178 15.528 14.912
wb_cyc_stb System FD1P3IX SP N_103 15.528 14.912
===================================================================================
@ -1168,25 +1187,25 @@ Path information for path number 1:
The start point is clocked by System [rising]
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
wb_ack Net - - - - 2
ufmefb.EFBInst_0_RNISGNB ORCALUT4 D In 0.000 0.000 r -
ufmefb.EFBInst_0_RNISGNB ORCALUT4 Z Out 1.017 1.017 r -
g0_0_a3_2 Net - - - - 1
ufmefb.EFBInst_0_RNISI191 ORCALUT4 C In 0.000 1.017 r -
ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r -
N_4 Net - - - - 1
CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r -
CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r -
CmdValid_RNIOOBE2 Net - - - - 2
LEDENe ORCALUT4 B In 0.000 2.554 r -
LEDENe ORCALUT4 Z Out 0.617 3.171 r -
LEDENe_0 Net - - - - 1
LEDEN FD1S3AX D In 0.000 3.171 r -
==============================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
wb_ack Net - - - - 2
ufmefb.EFBInst_0_RNI8K48 ORCALUT4 C In 0.000 0.000 r -
ufmefb.EFBInst_0_RNI8K48 ORCALUT4 Z Out 0.449 0.449 r -
g0_0_a3_1 Net - - - - 1
wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 D In 0.000 0.449 r -
wb_cyc_stb_2_sqmuxa_i_o2_RNI167R ORCALUT4 Z Out 1.017 1.466 r -
N_4 Net - - - - 1
CmdValid_RNITBH02 ORCALUT4 C In 0.000 1.466 r -
CmdValid_RNITBH02 ORCALUT4 Z Out 1.089 2.554 r -
CmdValid_RNITBH02 Net - - - - 2
LEDENe ORCALUT4 B In 0.000 2.554 r -
LEDENe ORCALUT4 Z Out 0.617 3.171 r -
LEDENe_0 Net - - - - 1
LEDEN FD1S3AX D In 0.000 3.171 r -
=====================================================================================================
@ -1194,18 +1213,18 @@ LEDEN FD1S3AX D In 0.000 3.171 r
Timing exceptions that could not be applied
Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB)
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 202MB peak: 203MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 202MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 109 of 1280 (9%)
Register bits: 110 of 1280 (9%)
PIC Latch: 0
I/O cells: 63
I/O cells: 64
Details:
@ -1214,27 +1233,27 @@ CCU2D: 10
EFB: 1
FD1P3AX: 25
FD1P3IX: 2
FD1S3AX: 53
FD1S3AX: 54
FD1S3IX: 4
GSR: 1
IB: 25
IFS1P3DX: 9
INV: 7
OB: 30
OB: 31
ODDRXE: 1
OFS1P3BX: 4
OFS1P3DX: 11
OFS1P3JX: 1
ORCALUT4: 213
PFUMX: 1
ORCALUT4: 203
PUR: 1
VHI: 2
VLO: 2
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB)
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 202MB)
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Thu Sep 21 05:39:43 2023
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Thu Oct 19 23:50:54 2023
###########################################################]

118
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html
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@ -22,7 +22,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Thu Sep 21 05:39:46 2023
Thu Oct 19 23:50:57 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -42,7 +42,7 @@ Report level: verbose report, limited to 1 item per preference
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 147 items scored, 0 timing errors detected.
Report: 53.254MHz is the maximum frequency for this preference.
Report: 57.904MHz is the maximum frequency for this preference.
<LI><A href='#map_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
@ -50,8 +50,8 @@ Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 878 items scored, 0 timing errors detected.
Report: 100.492MHz is the maximum frequency for this preference.
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 868 items scored, 0 timing errors detected.
Report: 97.666MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
@ -65,42 +65,42 @@ BLOCK RESETPATHS
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
Passed: The following path meets requirements by 163.779ns (weighted slack = 327.558ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
Delay: 8.469ns (36.0% logic, 64.0% route), 6 logic levels.
Constraint Details:
9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
8.469ns physical path delay Din[0]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.779ns
Physical Path Details:
Data path Din[0]_MGIOL to SLICE_17:
Data path Din[0]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0]
CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93
ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84
ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3
CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
ROUTE 1 e 1.234 SLICE_33.F0 to SLICE_17.D0 CmdEnable_0_sqmuxa
CTOF_DEL --- 0.495 SLICE_17.D0 to SLICE_17.F0 SLICE_17
ROUTE 1 e 0.001 SLICE_17.F0 to SLICE_17.DI0 CmdEnable_s (to PHI2_c)
ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_89.A0 Bank[0]
CTOF_DEL --- 0.495 SLICE_89.A0 to SLICE_89.F0 SLICE_89
ROUTE 1 e 1.234 SLICE_89.F0 to SLICE_75.C1 un1_ADWR_i_o2_10
CTOF_DEL --- 0.495 SLICE_75.C1 to SLICE_75.F1 SLICE_75
ROUTE 8 e 0.480 SLICE_75.F1 to SLICE_75.B0 N_294
CTOF_DEL --- 0.495 SLICE_75.B0 to SLICE_75.F0 SLICE_75
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_73.C0 N_382
CTOF_DEL --- 0.495 SLICE_73.C0 to SLICE_73.F0 SLICE_73
ROUTE 2 e 1.234 SLICE_73.F0 to SLICE_10.C0 CmdEnable17
CTOF_DEL --- 0.495 SLICE_10.C0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
9.223 (33.1% logic, 66.9% route), 6 logic levels.
8.469 (36.0% logic, 64.0% route), 6 logic levels.
Report: 53.254MHz is the maximum frequency for this preference.
Report: 57.904MHz is the maximum frequency for this preference.
================================================================================
@ -141,48 +141,48 @@ Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
878 items scored, 0 timing errors detected.
868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.049ns
Passed: The following path meets requirements by 5.761ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q IS[1] (from RCLK_c +)
Destination: FF Data in nRCAS_0io (to RCLK_c +)
Source: FF Q FS[11] (from RCLK_c +)
Destination: FF Data in wb_adr[0] (to RCLK_c +)
Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels.
Delay: 10.073ns (34.0% logic, 66.0% route), 7 logic levels.
Constraint Details:
9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
10.073ns physical path delay SLICE_4 to SLICE_48 meets
16.000ns delay constraint less
0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns
0.166ns DIN_SET requirement (totaling 15.834ns) by 5.761ns
Physical Path Details:
Data path SLICE_27 to nRCAS_MGIOL:
Data path SLICE_4 to SLICE_48:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c)
ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1]
CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74
ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74
ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408
CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61
ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61
ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1
CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94
ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
REG_DEL --- 0.452 SLICE_4.CLK to SLICE_4.Q0 SLICE_4 (from RCLK_c)
ROUTE 21 e 1.234 SLICE_4.Q0 to SLICE_66.B1 FS[11]
CTOF_DEL --- 0.495 SLICE_66.B1 to SLICE_66.F1 SLICE_66
ROUTE 1 e 0.480 SLICE_66.F1 to SLICE_66.D0 wb_adr_5_i_i_a2_3_0[0]
CTOF_DEL --- 0.495 SLICE_66.D0 to SLICE_66.F0 SLICE_66
ROUTE 1 e 1.234 SLICE_66.F0 to SLICE_86.D0 wb_adr_5_i_i_1_0_tz_0[0]
CTOF_DEL --- 0.495 SLICE_86.D0 to SLICE_86.F0 SLICE_86
ROUTE 1 e 1.234 SLICE_86.F0 to SLICE_85.C0 wb_adr_5_i_i_1_0[0]
CTOF_DEL --- 0.495 SLICE_85.C0 to SLICE_85.F0 SLICE_85
ROUTE 1 e 1.234 SLICE_85.F0 to SLICE_77.D0 wb_adr_5_i_i_1[0]
CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_48.D0 wb_adr_5_i_i_5[0]
CTOF_DEL --- 0.495 SLICE_48.D0 to SLICE_48.F0 SLICE_48
ROUTE 1 e 0.001 SLICE_48.F0 to SLICE_48.DI0 N_283 (to RCLK_c)
--------
9.798 (34.9% logic, 65.1% route), 7 logic levels.
10.073 (34.0% logic, 66.0% route), 7 logic levels.
Report: 100.492MHz is the maximum frequency for this preference.
Report: 97.666MHz is the maximum frequency for this preference.
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
@ -190,13 +190,13 @@ Report: 100.492MHz is the maximum frequency for this preference.
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 57.904 MHz| 6
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 97.666 MHz| 7
| | |
----------------------------------------------------------------------------
@ -209,7 +209,7 @@ All preferences were met.
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@ -221,7 +221,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@ -251,11 +251,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage)
--------------------------------------------------------------------------------
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Thu Sep 21 05:39:46 2023
Thu Oct 19 23:50:58 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -280,7 +280,7 @@ Report level: verbose report, limited to 1 item per preference
<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 878 items scored, 0 timing errors detected.
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 868 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
@ -317,7 +317,7 @@ Passed: The following path meets requirements by 0.447ns
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to PHI2_c)
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0 (to PHI2_c)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
@ -336,7 +336,7 @@ ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to
================================================================================
<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
878 items scored, 0 timing errors detected.
868 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
@ -390,7 +390,7 @@ All preferences were met.
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
@ -402,7 +402,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
@ -432,7 +432,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
Constraints cover 1015 paths, 4 nets, and 706 connections (71.10% coverage)

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CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html
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2523
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.sdf
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3587
CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_vo.vo
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8
CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
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@ -4,11 +4,15 @@ Starting: parse design source files
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v'
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/REFB.v'
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-615,10) (VERI-9000) elaborating module 'RAM2GS'
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-621,10) (VERI-9000) elaborating module 'RAM2GS'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1601,1-1606,10) (VERI-9000) elaborating module 'ODDRXE_uniq_1'
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
Done: design load finished with (0) errors, and (0) warnings
WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(46,7-46,8) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'D0'
WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(46,15-46,16) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'D1'
WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(47,8-47,9) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port 'RST'
Done: design load finished with (0) errors, and (3) warnings
</PRE></BODY></HTML>

171
CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior
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@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4.
// Package: TQFP100
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
// Written on Thu Sep 21 05:40:06 2023
// Written on Thu Oct 19 23:51:14 2023
// M: Minimum Performance Grade
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
@ -41,94 +41,97 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
----------------------------------------------------------------------
CROW[0] nCRAS F 2.913 4 -0.274 M
CROW[1] nCRAS F 2.475 4 -0.161 M
Din[0] PHI2 F 5.366 4 4.293 4
Din[0] nCCAS F 1.448 4 -0.034 M
Din[1] PHI2 F 4.971 4 4.173 4
Din[1] nCCAS F 0.519 4 0.708 4
Din[2] PHI2 F 5.192 4 4.173 4
Din[2] nCCAS F 1.948 4 -0.142 M
Din[3] PHI2 F 5.298 4 4.173 4
Din[3] nCCAS F 1.974 4 -0.157 M
Din[4] PHI2 F 4.281 4 4.173 4
Din[4] nCCAS F 1.060 4 0.217 4
Din[5] PHI2 F 5.059 4 4.173 4
Din[5] nCCAS F 1.956 4 -0.150 M
Din[6] PHI2 F 4.644 4 4.293 4
Din[6] nCCAS F 2.886 4 -0.382 M
Din[7] PHI2 F 5.316 4 4.293 4
Din[7] nCCAS F 2.381 4 -0.244 M
MAin[0] PHI2 F 4.362 4 1.145 4
MAin[0] nCRAS F 1.189 4 0.362 4
MAin[1] PHI2 F 4.386 4 0.999 4
MAin[1] nCRAS F 1.884 4 -0.024 M
MAin[2] PHI2 F 9.426 4 -0.750 M
MAin[2] nCRAS F 1.136 4 0.453 4
MAin[3] PHI2 F 10.458 4 -0.997 M
MAin[3] nCRAS F 1.564 4 0.067 4
MAin[4] PHI2 F 11.109 4 -1.209 M
MAin[4] nCRAS F 1.390 4 0.207 4
MAin[5] PHI2 F 9.884 4 -0.896 M
MAin[5] nCRAS F 1.269 4 0.218 4
MAin[6] PHI2 F 9.859 4 -0.845 M
MAin[6] nCRAS F 0.889 4 0.653 4
MAin[7] PHI2 F 10.678 4 -1.070 M
MAin[7] nCRAS F 1.186 4 0.309 4
MAin[8] nCRAS F 1.639 4 0.014 M
MAin[9] nCRAS F 1.097 4 0.457 4
CROW[0] nCRAS F 1.569 4 0.268 6
CROW[1] nCRAS F 1.013 4 0.820 4
Din[0] PHI2 F 5.478 4 4.293 4
Din[0] nCCAS F 2.010 4 -0.119 M
Din[1] PHI2 F 4.088 4 4.173 4
Din[1] nCCAS F 0.601 4 0.796 4
Din[2] PHI2 F 4.967 4 4.173 4
Din[2] nCCAS F 0.811 4 0.583 4
Din[3] PHI2 F 3.810 4 4.173 4
Din[3] nCCAS F 1.136 4 0.322 4
Din[4] PHI2 F 4.400 4 4.173 4
Din[4] nCCAS F 0.762 4 0.590 4
Din[5] PHI2 F 5.595 4 4.173 4
Din[5] nCCAS F 0.779 4 0.576 4
Din[6] PHI2 F 5.120 4 4.293 4
Din[6] nCCAS F 2.036 4 -0.117 M
Din[7] PHI2 F 5.630 4 4.293 4
Din[7] nCCAS F 2.301 4 -0.192 M
MAin[0] PHI2 F 4.196 4 1.086 4
MAin[0] nCRAS F 0.152 6 1.567 4
MAin[1] PHI2 F 3.875 4 1.164 4
MAin[1] nCRAS F -0.177 M 2.102 4
MAin[2] PHI2 F 8.381 4 -0.693 M
MAin[2] nCRAS F -0.315 M 2.358 4
MAin[3] PHI2 F 7.199 4 -0.405 M
MAin[3] nCRAS F -0.173 M 1.962 4
MAin[4] PHI2 F 8.710 4 -0.769 M
MAin[4] nCRAS F 0.292 4 1.419 4
MAin[5] PHI2 F 8.562 4 -0.730 M
MAin[5] nCRAS F -0.055 M 1.752 4
MAin[6] PHI2 F 7.862 4 -0.604 M
MAin[6] nCRAS F -0.126 M 1.965 4
MAin[7] PHI2 F 8.829 4 -0.836 M
MAin[7] nCRAS F -0.122 M 1.960 4
MAin[8] nCRAS F -0.288 M 2.424 4
MAin[9] nCRAS F -0.212 M 2.196 4
PHI2 RCLK R -0.133 M 2.360 4
nCCAS RCLK R 2.943 4 -0.337 M
nCCAS nCRAS F 2.967 4 -0.214 M
nCRAS RCLK R 3.047 4 -0.402 M
nFWE PHI2 F 11.116 4 -1.189 M
nFWE nCRAS F 1.394 4 0.225 4
nCCAS RCLK R 3.627 4 -0.577 M
nCCAS nCRAS F 3.154 4 -0.145 M
nCRAS RCLK R 1.461 4 -0.017 M
nFWE PHI2 F 6.933 4 -0.318 M
nFWE nCRAS F 0.403 4 1.860 4
// Clock to Output Delay
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
------------------------------------------------------------------------
LED RCLK R 11.046 4 3.298 M
LED nCRAS F 11.710 4 3.359 M
RA[0] RCLK R 11.397 4 3.516 M
RA[0] nCRAS F 11.476 4 3.432 M
RA[10] RCLK R 7.888 4 2.711 M
RA[11] PHI2 R 9.755 4 3.200 M
RA[1] RCLK R 11.272 4 3.469 M
RA[1] nCRAS F 11.238 4 3.348 M
RA[2] RCLK R 11.235 4 3.468 M
RA[2] nCRAS F 11.665 4 3.453 M
RA[3] RCLK R 11.390 4 3.512 M
RA[3] nCRAS F 11.922 4 3.539 M
RA[4] RCLK R 11.662 4 3.573 M
RA[4] nCRAS F 11.818 4 3.505 M
RA[5] RCLK R 11.744 4 3.584 M
RA[5] nCRAS F 11.779 4 3.513 M
RA[6] RCLK R 11.738 4 3.607 M
RA[6] nCRAS F 11.836 4 3.531 M
RA[7] RCLK R 12.475 4 3.797 M
RA[7] nCRAS F 11.420 4 3.426 M
RA[8] RCLK R 11.122 4 3.431 M
RA[8] nCRAS F 11.667 4 3.471 M
RA[9] RCLK R 11.935 4 3.649 M
RA[9] nCRAS F 11.401 4 3.424 M
RBA[0] nCRAS F 8.903 4 2.891 M
RBA[1] nCRAS F 8.903 4 2.891 M
RCKE RCLK R 10.011 4 3.215 M
RDQMH RCLK R 10.790 4 3.354 M
RDQML RCLK R 11.053 4 3.450 M
RD[0] nCCAS F 8.977 4 3.012 M
RD[1] nCCAS F 8.977 4 3.012 M
RD[2] nCCAS F 8.977 4 3.012 M
RD[3] nCCAS F 8.977 4 3.012 M
RD[4] nCCAS F 8.977 4 3.012 M
RD[5] nCCAS F 8.977 4 3.012 M
RD[6] nCCAS F 8.977 4 3.012 M
RD[7] nCCAS F 8.977 4 3.012 M
nRCAS RCLK R 7.822 4 2.706 M
nRCS RCLK R 7.822 4 2.706 M
nRRAS RCLK R 7.822 4 2.706 M
nRWE RCLK R 7.803 4 2.713 M
LED RCLK R 10.948 4 3.270 M
LED nCRAS F 12.507 4 3.690 M
RA[0] RCLK R 13.208 4 4.000 M
RA[0] nCRAS F 13.040 4 3.935 M
RA[10] RCLK R 7.888 4 2.711 M
RA[11] PHI2 R 9.755 4 3.200 M
RA[1] RCLK R 13.332 4 4.024 M
RA[1] nCRAS F 12.944 4 3.885 M
RA[2] RCLK R 13.624 4 4.099 M
RA[2] nCRAS F 13.220 4 3.993 M
RA[3] RCLK R 13.506 4 4.055 M
RA[3] nCRAS F 13.322 4 4.022 M
RA[4] RCLK R 12.512 4 3.834 M
RA[4] nCRAS F 14.534 4 4.331 M
RA[5] RCLK R 13.530 4 4.069 M
RA[5] nCRAS F 13.126 4 3.963 M
RA[6] RCLK R 14.238 4 4.245 M
RA[6] nCRAS F 13.589 4 4.077 M
RA[7] RCLK R 13.759 4 4.129 M
RA[7] nCRAS F 13.371 4 3.990 M
RA[8] RCLK R 11.858 4 3.632 M
RA[8] nCRAS F 13.338 4 4.026 M
RA[9] RCLK R 11.007 4 3.423 M
RA[9] nCRAS F 12.651 4 3.856 M
RBA[0] nCRAS F 10.201 4 3.325 M
RBA[1] nCRAS F 10.201 4 3.325 M
RCKE RCLK R 9.754 4 3.167 M
RCLKout RCLK R 7.971 4 2.504 M
RDQMH RCLK R 11.153 4 3.458 M
RDQML RCLK R 11.133 4 3.466 M
RD[0] nCCAS F 9.354 4 3.132 M
RD[1] nCCAS F 9.354 4 3.132 M
RD[2] nCCAS F 9.354 4 3.132 M
RD[3] nCCAS F 9.354 4 3.132 M
RD[4] nCCAS F 9.354 4 3.132 M
RD[5] nCCAS F 9.354 4 3.132 M
RD[6] nCCAS F 9.354 4 3.132 M
RD[7] nCCAS F 9.354 4 3.132 M
nRCAS RCLK R 7.822 4 2.706 M
nRCS RCLK R 7.822 4 2.706 M
nRRAS RCLK R 7.822 4 2.706 M
nRWE RCLK R 7.803 4 2.713 M
WARNING: you must also run trce with hold speed: 4
WARNING: you must also run trce with setup speed: 6
WARNING: you must also run trce with hold speed: 6
WARNING: you must also run trce with setup speed: M

5
CPLD/RAM2GS-LCMXO2.lpf
View File

@ -42,7 +42,7 @@ LOCATE COMP "RA[5]" SITE "70" ;
LOCATE COMP "RA[6]" SITE "68" ;
LOCATE COMP "RA[7]" SITE "75" ;
LOCATE COMP "RA[8]" SITE "65" ;
LOCATE COMP "RA[9]" SITE "62" ;
LOCATE COMP "RA[9]" SITE "47" ;
LOCATE COMP "RA[10]" SITE "64" ;
LOCATE COMP "RA[11]" SITE "59" ;
LOCATE COMP "RBA[0]" SITE "58" ;
@ -164,3 +164,6 @@ OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
LOCATE COMP "RCLK" SITE "63" ;
LOCATE COMP "RCLKout" SITE "62" ;
IOBUF PORT "RCLKout" IO_TYPE=LVCMOS33 PULLMODE=NONE SLEWRATE=FAST DRIVE=24 ;
OUTPUT PORT "RCLKout" LOAD 5.000000 pF ;

12
CPLD/RAM2GS-LCMXO2.v
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@ -1,6 +1,6 @@
module RAM2GS(PHI2, MAin, CROW, Din, Dout,
nCCAS, nCRAS, nFWE, LED,
RBA, RA, RD, nRCS, RCLK, RCKE,
RBA, RA, RD, nRCS, RCLK, RCLKout, RCKE,
nRWE, nRRAS, nRCAS, RDQMH, RDQML);
@ -37,8 +37,14 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
reg n8MEGEN = 0;
reg XOR8MEG = 0;
/* SDRAM Clock */
input RCLK;
/* SDRAM Clock in/out */
input RCLK;
output RCLKout;
ODDRXE rck(
.SCLK(RCLK),
.Q(RCLKout),
.D0(0), .D1(1),
.RST(0));
/* SDRAM */
reg RCKEEN;

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592
Hardware/LCMXO/RAM2GS-cache.lib
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@ -1,592 +0,0 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x05_Odd_Even
#
DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 300 50 H V C CNN
F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 150 -250 1 1 10 f
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_10 10 300 -200 150 L 50 50 1 1 P
X Pin_2 2 300 200 150 L 50 50 1 1 P
X Pin_3 3 -200 100 150 R 50 50 1 1 P
X Pin_4 4 300 100 150 L 50 50 1 1 P
X Pin_5 5 -200 0 150 R 50 50 1 1 P
X Pin_6 6 300 0 150 L 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 300 -100 150 L 50 50 1 1 P
X Pin_9 9 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x22_Counter_Clockwise
#
DEF Connector_Generic_Conn_02x22_Counter_Clockwise J 0 40 Y N 1 F N
F0 "J" 50 1100 50 H V C CNN
F1 "Connector_Generic_Conn_02x22_Counter_Clockwise" 50 -1200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1050 150 -1150 1 1 10 f
S 150 -1095 100 -1105 1 1 6 N
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 905 100 895 1 1 6 N
S 150 1005 100 995 1 1 6 N
X Pin_1 1 -200 1000 150 R 50 50 1 1 P
X Pin_10 10 -200 100 150 R 50 50 1 1 P
X Pin_11 11 -200 0 150 R 50 50 1 1 P
X Pin_12 12 -200 -100 150 R 50 50 1 1 P
X Pin_13 13 -200 -200 150 R 50 50 1 1 P
X Pin_14 14 -200 -300 150 R 50 50 1 1 P
X Pin_15 15 -200 -400 150 R 50 50 1 1 P
X Pin_16 16 -200 -500 150 R 50 50 1 1 P
X Pin_17 17 -200 -600 150 R 50 50 1 1 P
X Pin_18 18 -200 -700 150 R 50 50 1 1 P
X Pin_19 19 -200 -800 150 R 50 50 1 1 P
X Pin_2 2 -200 900 150 R 50 50 1 1 P
X Pin_20 20 -200 -900 150 R 50 50 1 1 P
X Pin_21 21 -200 -1000 150 R 50 50 1 1 P
X Pin_22 22 -200 -1100 150 R 50 50 1 1 P
X Pin_23 23 300 -1100 150 L 50 50 1 1 P
X Pin_24 24 300 -1000 150 L 50 50 1 1 P
X Pin_25 25 300 -900 150 L 50 50 1 1 P
X Pin_26 26 300 -800 150 L 50 50 1 1 P
X Pin_27 27 300 -700 150 L 50 50 1 1 P
X Pin_28 28 300 -600 150 L 50 50 1 1 P
X Pin_29 29 300 -500 150 L 50 50 1 1 P
X Pin_3 3 -200 800 150 R 50 50 1 1 P
X Pin_30 30 300 -400 150 L 50 50 1 1 P
X Pin_31 31 300 -300 150 L 50 50 1 1 P
X Pin_32 32 300 -200 150 L 50 50 1 1 P
X Pin_33 33 300 -100 150 L 50 50 1 1 P
X Pin_34 34 300 0 150 L 50 50 1 1 P
X Pin_35 35 300 100 150 L 50 50 1 1 P
X Pin_36 36 300 200 150 L 50 50 1 1 P
X Pin_37 37 300 300 150 L 50 50 1 1 P
X Pin_38 38 300 400 150 L 50 50 1 1 P
X Pin_39 39 300 500 150 L 50 50 1 1 P
X Pin_4 4 -200 700 150 R 50 50 1 1 P
X Pin_40 40 300 600 150 L 50 50 1 1 P
X Pin_41 41 300 700 150 L 50 50 1 1 P
X Pin_42 42 300 800 150 L 50 50 1 1 P
X Pin_43 43 300 900 150 L 50 50 1 1 P
X Pin_44 44 300 1000 150 L 50 50 1 1 P
X Pin_5 5 -200 600 150 R 50 50 1 1 P
X Pin_6 6 -200 500 150 R 50 50 1 1 P
X Pin_7 7 -200 400 150 R 50 50 1 1 P
X Pin_8 8 -200 300 150 R 50 50 1 1 P
X Pin_9 9 -200 200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED_Small_ALT
#
DEF Device_LED_Small_ALT D 0 10 N N 1 F N
F0 "D" -50 125 50 H V L CNN
F1 "Device_LED_Small_ALT" -175 -100 50 H V L CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 10 -30 -40 -30 40 N
P 2 0 1 0 40 0 -30 0 N
P 4 0 1 10 30 -40 -30 0 30 40 30 -40 F
P 5 0 1 0 0 30 -20 50 -10 50 -20 50 -20 40 N
P 5 0 1 0 20 50 0 70 10 70 0 70 0 60 N
X K 1 -100 0 70 R 50 50 1 1 P
X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_Logic_741G04GW
#
DEF GW_Logic_741G04GW U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Logic_741G04GW" 0 -250 50 H V C CNN
F2 "stdpads:SOT-353" 0 -300 50 H I C TNN
F3 "" 0 -200 60 H I C CNN
DRAW
S 200 -200 -200 200 0 1 10 f
X NC 1 -350 100 150 R 50 50 1 1 N
X A 2 -400 0 200 R 50 50 1 1 I
X GND 3 -400 -100 200 R 50 50 1 1 W
X Y 4 400 -100 200 L 50 50 1 1 O
X Vcc 5 400 100 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_Logic_74245
#
DEF GW_Logic_74245 U 0 40 Y Y 1 F N
F0 "U" 0 600 50 H V C CNN
F1 "GW_Logic_74245" 0 -600 50 H V C CNN
F2 "" 0 -650 50 H I C TNN
F3 "" 0 100 60 H I C CNN
DRAW
S -200 550 200 -550 0 1 10 f
X AtoB 1 -400 450 200 R 50 50 1 1 I
X GND 10 -400 -450 200 R 50 50 1 1 W
X B7 11 400 -450 200 L 50 50 1 1 B
X B6 12 400 -350 200 L 50 50 1 1 B
X B5 13 400 -250 200 L 50 50 1 1 B
X B4 14 400 -150 200 L 50 50 1 1 B
X B3 15 400 -50 200 L 50 50 1 1 B
X B2 16 400 50 200 L 50 50 1 1 B
X B1 17 400 150 200 L 50 50 1 1 B
X B0 18 400 250 200 L 50 50 1 1 B
X ~OE~ 19 400 350 200 L 50 50 1 1 I
X A0 2 -400 350 200 R 50 50 1 1 B
X Vcc 20 400 450 200 L 50 50 1 1 W
X A1 3 -400 250 200 R 50 50 1 1 B
X A2 4 -400 150 200 R 50 50 1 1 B
X A3 5 -400 50 200 R 50 50 1 1 B
X A4 6 -400 -50 200 R 50 50 1 1 B
X A5 7 -400 -150 200 R 50 50 1 1 B
X A6 8 -400 -250 200 R 50 50 1 1 B
X A7 9 -400 -350 200 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# GW_Logic_Oscillator_4P
#
DEF GW_Logic_Oscillator_4P U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Logic_Oscillator_4P" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -250 200 250 -100 0 1 10 f
X EN 1 -350 100 100 R 50 50 1 1 I
X GND 2 -350 0 100 R 50 50 1 1 W
X Output 3 350 0 100 L 50 50 1 1 O
X Vdd 4 350 100 100 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_PLD_LCMXO640-TQFP-100
#
DEF GW_PLD_LCMXO640-TQFP-100 U 0 40 Y Y 1 F N
F0 "U" 0 50 50 H V C CNN
F1 "GW_PLD_LCMXO640-TQFP-100" 0 0 40 H V C TNN
F2 "stdpads:TQFP-100" 0 -100 40 H I C CNN
F3 "" 0 100 50 H I C CNN
DRAW
S -850 2200 850 -2200 0 1 10 f
X PL2A 1 -1050 2100 200 R 50 50 1 1 B
X VccIO3 10 100 2400 200 D 50 50 1 1 W
X PT2A 100 1050 2000 200 L 50 50 1 1 B
X PL4C 11 -1050 1200 200 R 50 50 1 1 B
X GNDIO3 12 100 -2400 200 U 50 50 1 1 W
X PL4D 13 -1050 1100 200 R 50 50 1 1 B
X PL5B/~GSRN~ 14 -1050 1000 200 R 50 50 1 1 B
X PL7B 15 -1050 900 200 R 50 50 1 1 B
X PL8C/TSALL 16 -1050 800 200 R 50 50 1 1 B
X PL8D 17 -1050 700 200 R 50 50 1 1 B
X PL9A 18 -1050 600 200 R 50 50 1 1 B
X PL9C 19 -1050 500 200 R 50 50 1 1 B
X PL2C 2 -1050 2000 200 R 50 50 1 1 B
X PL10A 20 -1050 400 200 R 50 50 1 1 B
X PL10C 21 -1050 300 200 R 50 50 1 1 B
X PL11A 22 -1050 200 200 R 50 50 1 1 B
X PL11C 23 -1050 100 200 R 50 50 1 1 B
X VccIO3 24 200 2400 200 D 50 50 1 1 W
X GNDIO3 25 200 -2400 200 U 50 50 1 1 W
X TMS 26 -1050 -2100 200 R 50 50 1 1 I
X PL2C 27 -1050 -100 200 R 50 50 1 1 B
X TCK 28 -1050 -1800 200 R 50 50 1 1 I
X VccIO2 29 -100 2400 200 D 50 50 1 1 W
X PL2B 3 -1050 1900 200 R 50 50 1 1 B
X GNDIO2 30 -100 -2400 200 U 50 50 1 1 W
X TDO 31 -1050 -1900 200 R 50 50 1 1 O
X PB4C 32 -1050 -400 200 R 50 50 1 1 B
X TDI 33 -1050 -2000 200 R 50 50 1 1 I
X PB4E 34 -1050 -500 200 R 50 50 1 1 B
X Vcc 35 400 2400 200 D 50 50 1 1 W
X PB5B/PCLK2_1 36 -1050 -600 200 R 50 50 1 1 B
X PB5D 37 -1050 -700 200 R 50 50 1 1 B
X PB6B/PCLK2_0 38 -1050 -800 200 R 50 50 1 1 B
X PB6C 39 -1050 -900 200 R 50 50 1 1 B
X PL2D 4 -1050 1800 200 R 50 50 1 1 B
X GND 40 300 -2400 200 U 50 50 1 1 W
X VccIO2 41 0 2400 200 D 50 50 1 1 W
X GNDIO2 42 0 -2400 200 U 50 50 1 1 W
X PB8B 43 -1050 -1000 200 R 50 50 1 1 B
X PB8C 44 -1050 -1100 200 R 50 50 1 1 B
X PB8D 45 -1050 -1200 200 R 50 50 1 1 B
X PB9A 46 -1050 -1300 200 R 50 50 1 1 B
X PB9C 47 -1050 -1400 200 R 50 50 1 1 B
X ~SLEEP~ 48 1050 2100 200 L 50 50 1 1 I
X PB9D 49 -1050 -1500 200 R 50 50 1 1 B
X PL3A 5 -1050 1700 200 R 50 50 1 1 B
X PB9F 50 -1050 -1600 200 R 50 50 1 1 B
X PR11D 51 1050 -2100 200 L 50 50 1 1 B
X PR11B 52 1050 -2000 200 L 50 50 1 1 B
X PR11C 53 1050 -1900 200 L 50 50 1 1 B
X PR11A 54 1050 -1800 200 L 50 50 1 1 B
X PR10D 55 1050 -1700 200 L 50 50 1 1 B
X PR10C 56 1050 -1600 200 L 50 50 1 1 B
X PR10B 57 1050 -1500 200 L 50 50 1 1 B
X PR10A 58 1050 -1400 200 L 50 50 1 1 B
X PR9D 59 1050 -1300 200 L 50 50 1 1 B
X PL3B 6 -1050 1600 200 R 50 50 1 1 B
X VccIO1 60 -300 2400 200 D 50 50 1 1 W
X PR9B 61 1050 -1200 200 L 50 50 1 1 B
X GNDIO1 62 -300 -2400 200 U 50 50 1 1 W
X PR7B 63 1050 -1100 200 L 50 50 1 1 B
X PR6C 64 1050 -1000 200 L 50 50 1 1 B
X PR6B 65 1050 -900 200 L 50 50 1 1 B
X PR5D 66 1050 -800 200 L 50 50 1 1 B
X PR5B 67 1050 -700 200 L 50 50 1 1 B
X PR4D 68 1050 -600 200 L 50 50 1 1 B
X PR4B 69 1050 -500 200 L 50 50 1 1 B
X PL3C 7 -1050 1500 200 R 50 50 1 1 B
X PR3D 70 1050 -400 200 L 50 50 1 1 B
X PR3B 71 1050 -300 200 L 50 50 1 1 B
X PR2D 72 1050 -200 200 L 50 50 1 1 B
X PR2B 73 1050 -100 200 L 50 50 1 1 B
X VccIO1 74 -200 2400 200 D 50 50 1 1 W
X GNDIO1 75 -200 -2400 200 U 50 50 1 1 W
X PR9F 76 1050 100 200 L 50 50 1 1 B
X PT9E 77 1050 200 200 L 50 50 1 1 B
X PT9C 78 1050 300 200 L 50 50 1 1 B
X PT9A 79 1050 400 200 L 50 50 1 1 B
X PL3D 8 -1050 1400 200 R 50 50 1 1 B
X VccIO0 80 -500 2400 200 D 50 50 1 1 W
X GNDIO0 81 -500 -2400 200 U 50 50 1 1 W
X PT7E 82 1050 700 200 L 50 50 1 1 B
X PT7A 83 1050 800 200 L 50 50 1 1 B
X GND 84 400 -2400 200 U 50 50 1 1 W
X PT6B/PCLK0_1 85 1050 900 200 L 50 50 1 1 B
X PT5B/PCLK0_0 86 1050 1000 200 L 50 50 1 1 B
X PT5A 87 1050 1100 200 L 50 50 1 1 B
X VccAUX 88 300 2400 200 D 50 50 1 1 W
X PT4F 89 1050 1200 200 L 50 50 1 1 B
X PL4A 9 -1050 1300 200 R 50 50 1 1 B
X Vcc 90 500 2400 200 D 50 50 1 1 W
X PT3F 91 1050 1300 200 L 50 50 1 1 B
X VccIO0 92 -400 2400 200 D 50 50 1 1 W
X GNDIO0 93 -400 -2400 200 U 50 50 1 1 W
X PT3B 94 1050 1400 200 L 50 50 1 1 B
X PT3A 95 1050 1500 200 L 50 50 1 1 B
X PT2F 96 1050 1600 200 L 50 50 1 1 B
X PT2E 97 1050 1700 200 L 50 50 1 1 B
X PT2B 98 1050 1800 200 L 50 50 1 1 B
X PT2C 99 1050 1900 200 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# GW_RAM_SDRAM-16Mx16-TSOP2-54
#
DEF GW_RAM_SDRAM-16Mx16-TSOP2-54 U 0 40 Y Y 1 F N
F0 "U" 0 1150 50 H V C CNN
F1 "GW_RAM_SDRAM-16Mx16-TSOP2-54" 0 0 50 V V C CNN
F2 "stdpads:Winbond_TSOPII-54" 0 -1650 50 H I C CIN
F3 "" 0 -250 50 H I C CNN
DRAW
S -300 1100 300 -1400 0 1 10 f
X VDD 1 -500 1000 200 R 50 50 1 1 W
X DQ5 10 500 500 200 L 50 50 1 1 B
X DQ6 11 500 400 200 L 50 50 1 1 B
X VSSQ 12 -500 -1300 200 R 50 50 1 1 W N
X DQ7 13 500 300 200 L 50 50 1 1 B
X VDD 14 -500 1000 200 R 50 50 1 1 W N
X DQML 15 500 -600 200 L 50 50 1 1 I
X ~WE~ 16 500 -1100 200 L 50 50 1 1 I
X ~CAS~ 17 500 -1200 200 L 50 50 1 1 I
X ~RAS~ 18 500 -1300 200 L 50 50 1 1 I
X ~CS~ 19 500 -1000 200 L 50 50 1 1 I
X DQ0 2 500 1000 200 L 50 50 1 1 B
X BA0 20 -500 -600 200 R 50 50 1 1 I
X BA1 21 -500 -700 200 R 50 50 1 1 I
X A10 22 -500 -300 200 R 50 50 1 1 I
X A0 23 -500 700 200 R 50 50 1 1 I
X A1 24 -500 600 200 R 50 50 1 1 I
X A2 25 -500 500 200 R 50 50 1 1 I
X A3 26 -500 400 200 R 50 50 1 1 I
X VDD 27 -500 1000 200 R 50 50 1 1 W N
X VSS 28 -500 -1200 200 R 50 50 1 1 W
X A4 29 -500 300 200 R 50 50 1 1 I
X VDDQ 3 -500 900 200 R 50 50 1 1 W
X A5 30 -500 200 200 R 50 50 1 1 I
X A6 31 -500 100 200 R 50 50 1 1 I
X A7 32 -500 0 200 R 50 50 1 1 I
X A8 33 -500 -100 200 R 50 50 1 1 I
X A9 34 -500 -200 200 R 50 50 1 1 I
X A11 35 -500 -400 200 R 50 50 1 1 I
X A12 36 -500 -500 200 R 50 50 1 1 I
X CKE 37 -500 -900 200 R 50 50 1 1 I
X CLK 38 -500 -1000 200 R 50 50 1 1 I
X DQMH 39 500 -700 200 L 50 50 1 1 I
X DQ1 4 500 900 200 L 50 50 1 1 B
X VSS 41 -500 -1200 200 R 50 50 1 1 W N
X DQ8 42 500 200 200 L 50 50 1 1 B
X VDDQ 43 -500 900 200 R 50 50 1 1 W N
X DQ9 44 500 100 200 L 50 50 1 1 B
X DQ10 45 500 0 200 L 50 50 1 1 B
X VSSQ 46 -500 -1300 200 R 50 50 1 1 W N
X DQ11 47 500 -100 200 L 50 50 1 1 B
X DQ12 48 500 -200 200 L 50 50 1 1 B
X VDDQ 49 -500 900 200 R 50 50 1 1 W N
X DQ2 5 500 800 200 L 50 50 1 1 B
X DQ13 50 500 -300 200 L 50 50 1 1 B
X DQ14 51 500 -400 200 L 50 50 1 1 B
X VSSQ 52 -500 -1300 200 R 50 50 1 1 W N
X DQ15 53 500 -500 200 L 50 50 1 1 B
X VSS 54 -500 -1200 200 R 50 50 1 1 W N
X VSSQ 6 -500 -1300 200 R 50 50 1 1 W
X DQ3 7 500 700 200 L 50 50 1 1 B
X DQ4 8 500 600 200 L 50 50 1 1 B
X VDDQ 9 -500 900 200 R 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# GW_RAM_SPIFlash-SO-8
#
DEF GW_RAM_SPIFlash-SO-8 U 0 40 Y Y 1 F N
F0 "U" 0 350 50 H V C CNN
F1 "GW_RAM_SPIFlash-SO-8" 0 -250 50 H V C CNN
F2 "stdpads:stdpads:SOIC-8_5.3mm" 0 -300 50 H I C TNN
F3 "" 0 0 50 H I C TNN
DRAW
S -350 300 350 -200 0 1 10 f
X ~CS~ 1 -550 200 200 R 50 50 1 1 I
X DO/IO1 2 -550 100 200 R 50 50 1 1 B
X ~WP~/IO2 3 -550 0 200 R 50 50 1 1 B
X GND 4 -550 -100 200 R 50 50 1 1 W
X DI/IO0 5 550 -100 200 L 50 50 1 1 B
X CLK 6 550 0 200 L 50 50 1 1 I
X ~HLD~/IO3 7 550 100 200 L 50 50 1 1 B
X Vcc 8 550 200 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole
#
DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
F0 "H" 0 200 50 H V C CNN
F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*
$ENDFPLIST
DRAW
C 0 0 50 0 1 50 N
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole_Pad
#
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
F0 "H" 0 250 50 H V C CNN
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*Pad*
$ENDFPLIST
DRAW
C 0 50 50 0 1 50 N
X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Regulator_Linear_AP2127K-1.2
#
DEF Regulator_Linear_AP2127K-1.2 U 0 10 Y Y 1 F N
F0 "U" -200 225 50 H V L CNN
F1 "Regulator_Linear_AP2127K-1.2" 0 225 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23-5" 0 325 50 H I C CNN
F3 "" 0 100 50 H I C CNN
ALIAS AP2204K-1.8 AP2204K-2.5 AP2204K-2.8 AP2204K-3.0 AP2204K-3.3 AP2204K-5.0 AP2127K-1.0 AP2127K-1.2 AP2127K-1.5 AP2127K-1.8 AP2127K-2.5 AP2127K-2.8 AP2127K-3.0 AP2127K-3.3 AP2127K-4.2 AP2127K-4.75 AP2112K-1.2 AP2112K-1.8 AP2112K-2.5 AP2112K-2.6 AP2112K-3.3
$FPLIST
SOT?23?5*
$ENDFPLIST
DRAW
S -200 175 200 -200 0 1 10 f
X VIN 1 -300 100 100 R 50 50 1 1 W
X GND 2 0 -300 100 U 50 50 1 1 W
X EN 3 -300 0 100 R 50 50 1 1 I
X NC 4 200 0 100 L 50 50 1 1 N N
X VOUT 5 300 100 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# Regulator_Linear_LD1117S33TR_SOT223
#
DEF Regulator_Linear_LD1117S33TR_SOT223 U 0 10 Y Y 1 F N
F0 "U" -150 125 50 H V C CNN
F1 "Regulator_Linear_LD1117S33TR_SOT223" 0 125 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 200 50 H I C CNN
F3 "" 100 -250 50 H I C CNN
ALIAS AP1117-18 AP1117-25 AP1117-33 AP1117-50 LD1117S33TR_SOT223 LD1117S12TR_SOT223 LD1117S18TR_SOT223 LD1117S25TR_SOT223 LD1117S50TR_SOT223 NCP1117-12_SOT223 NCP1117-1.5_SOT223 NCP1117-1.8_SOT223 NCP1117-2.0_SOT223 NCP1117-2.5_SOT223 NCP1117-2.85_SOT223 NCP1117-3.3_SOT223 NCP1117-5.0_SOT223 AMS1117-1.5 AMS1117-1.8 AMS1117-2.5 AMS1117-2.85 AMS1117-3.3 AMS1117-5.0
$FPLIST
SOT?223*TabPin2*
$ENDFPLIST
DRAW
S -200 -200 200 75 0 1 10 f
X GND 1 0 -300 100 U 50 50 1 1 W
X VO 2 300 0 100 L 50 50 1 1 w
X VI 3 -300 0 100 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# power_+1V2
#
DEF power_+1V2 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+1V2" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +1V2 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3V3
#
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

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}

7573
Hardware/LCMXO/RAM2GS.kicad_sch Normal file
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275
Hardware/LCMXO/RAM2GS.pro
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@ -1,275 +0,0 @@
update=Monday, May 31, 2021 at 06:10:59 PM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=RAM2GS.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.15
MinViaDiameter=0.5
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.15
TrackWidth2=0.2
TrackWidth3=0.254
TrackWidth4=0.3
TrackWidth5=0.4
TrackWidth6=0.45
TrackWidth7=0.5
TrackWidth8=0.508
TrackWidth9=0.6
TrackWidth10=0.762
TrackWidth11=0.8
TrackWidth12=0.85
TrackWidth13=0.895
TrackWidth14=0.9
TrackWidth15=1
TrackWidth16=1.2
TrackWidth17=1.27
TrackWidth18=1.524
ViaDiameter1=0.5
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.762
ViaDrill3=0.381
ViaDiameter4=0.8
ViaDrill4=0.4
ViaDiameter5=1
ViaDrill5=0.5
ViaDiameter6=1.524
ViaDrill6=0.762
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.075
SolderMaskMinWidth=0.09999999999999999
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=1
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.15
TrackWidth=0.15
ViaDiameter=0.5
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
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LabSize=50
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2345
Hardware/LCMXO/RAM2GS.sch
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24434
Hardware/LCMXO/gerber/RAM2GS-B_Cu.gbl
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617
Hardware/LCMXO/gerber/RAM2GS-B_Mask.gbs
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@ -1,21 +1,40 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.10-1-10_14)*
G04 #@! TF.CreationDate,2021-05-31T18:25:56-04:00*
G04 #@! TF.ProjectId,RAM2GS,52414d32-4753-42e6-9b69-6361645f7063,2.0*
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-11-03T04:24:25-04:00*
G04 #@! TF.ProjectId,RAM2GS,52414d32-4753-42e6-9b69-6361645f7063,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Soldermask,Bot*
G04 #@! TF.FilePolarity,Negative*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-11-03 04:24:25*
%MOMM*%
%LPD*%
G01*
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%ADD11C,1.448000*%
%ADD12C,2.524900*%
%ADD13C,1.140600*%
%ADD14C,2.150000*%
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%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10C,0.000000*%
%ADD11RoundRect,0.457200X-0.381000X-3.289000X0.381000X-3.289000X0.381000X3.289000X-0.381000X3.289000X0*%
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%ADD13C,2.527300*%
%ADD14C,1.143000*%
%ADD15C,1.448000*%
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D10*
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M02*

472
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@ -0,0 +1,472 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-11-03T04:24:25-04:00*
G04 #@! TF.ProjectId,RAM2GS,52414d32-4753-42e6-9b69-6361645f7063,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Legend,Bot*
G04 #@! TF.FilePolarity,Positive*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-11-03 04:24:25*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 Aperture macros list*
%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10C,0.200000*%
%ADD11C,0.203200*%
%ADD12C,0.190500*%
%ADD13C,0.000000*%
%ADD14RoundRect,0.457200X-0.381000X-3.289000X0.381000X-3.289000X0.381000X3.289000X-0.381000X3.289000X0*%
%ADD15C,2.152400*%
%ADD16C,2.527300*%
%ADD17C,1.143000*%
%ADD18C,1.448000*%
G04 APERTURE END LIST*
D10*
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D13*
G36*
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G01*
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G37*
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68
Hardware/LCMXO/gerber/RAM2GS-Edge_Cuts.gm1
View File

@ -1,11 +1,11 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.10-1-10_14)*
G04 #@! TF.CreationDate,2021-05-31T18:25:56-04:00*
G04 #@! TF.ProjectId,RAM2GS,52414d32-4753-42e6-9b69-6361645f7063,2.0*
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-11-03T04:24:25-04:00*
G04 #@! TF.ProjectId,RAM2GS,52414d32-4753-42e6-9b69-6361645f7063,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.10-1-10_14)) date 2021-05-31 18:25:56*
G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-11-03 04:24:25*
%MOMM*%
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G01*
@ -15,48 +15,48 @@ G04 #@! TA.AperFunction,Profile*
G04 #@! TD*
G04 APERTURE END LIST*
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61820
Hardware/LCMXO/gerber/RAM2GS-F_Cu.gtl
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5064
Hardware/LCMXO/gerber/RAM2GS-F_Fab.gbr
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9304
Hardware/LCMXO/gerber/RAM2GS-F_Mask.gts
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8675
Hardware/LCMXO/gerber/RAM2GS-F_Paste.gtp
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9911
Hardware/LCMXO/gerber/RAM2GS-F_SilkS.gto
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8444
Hardware/LCMXO/gerber/RAM2GS-F_Silkscreen.gto Normal file
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57268
Hardware/LCMXO/gerber/RAM2GS-In1_Cu.g2
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66741
Hardware/LCMXO/gerber/RAM2GS-In2_Cu.g3
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1
Hardware/LCMXO/gerber/RAM2GS-bottom-pos.csv
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@ -1 +0,0 @@
Ref,Val,Package,MidX,MidY,Rot,Side
1 Ref Val Package MidX MidY Rot Side

6
Hardware/LCMXO/gerber/RAM2GS-bottom.pos
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@ -1,6 +0,0 @@
### Module positions - created on Monday, May 31, 2021 at 06:26:03 PM ###
### Printed by Pcbnew version kicad (5.1.10-1-10_14)
## Unit = mm, Angle = deg.
## Side : bottom
# Ref Val Package PosX PosY Rot Side
## End

7961
Hardware/LCMXO/gerber/RAM2GS-drl_map.ps
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164
Hardware/LCMXO/gerber/RAM2GS-job.gbrjob Normal file
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@ -0,0 +1,164 @@
{
"Header": {
"GenerationSoftware": {
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "7.0.1-0"
},
"CreationDate": "2023-11-03T04:24:25-04:00"
},
"GeneralSpecs": {
"ProjectId": {
"Name": "RAM2GS",
"GUID": "52414d32-4753-42e6-9b69-6361645f7063",
"Revision": "2.1"
},
"Size": {
"X": 67.46,
"Y": 48.664
},
"LayerNumber": 4,
"BoardThickness": 1.6108,
"Finish": "None"
},
"DesignRules": [
{
"Layers": "Outer",
"PadToPad": 0.15,
"PadToTrack": 0.15,
"TrackToTrack": 0.15,
"MinLineWidth": 0.15,
"TrackToRegion": 0.15,
"RegionToRegion": 0.15
},
{
"Layers": "Inner",
"PadToPad": 0.15,
"PadToTrack": 0.15,
"TrackToTrack": 0.15,
"TrackToRegion": 0.15,
"RegionToRegion": 0.15
}
],
"FilesAttributes": [
{
"Path": "RAM2GS-F_Cu.gtl",
"FileFunction": "Copper,L1,Top",
"FilePolarity": "Positive"
},
{
"Path": "RAM2GS-In1_Cu.g2",
"FileFunction": "Copper,L2,Inr",
"FilePolarity": "Positive"
},
{
"Path": "RAM2GS-In2_Cu.g3",
"FileFunction": "Copper,L3,Inr",
"FilePolarity": "Positive"
},
{
"Path": "RAM2GS-B_Cu.gbl",
"FileFunction": "Copper,L4,Bot",
"FilePolarity": "Positive"
},
{
"Path": "RAM2GS-F_Paste.gtp",
"FileFunction": "SolderPaste,Top",
"FilePolarity": "Positive"
},
{
"Path": "RAM2GS-F_Silkscreen.gto",
"FileFunction": "Legend,Top",
"FilePolarity": "Positive"
},
{
"Path": "RAM2GS-B_Silkscreen.gbo",
"FileFunction": "Legend,Bot",
"FilePolarity": "Positive"
},
{
"Path": "RAM2GS-F_Mask.gts",
"FileFunction": "SolderMask,Top",
"FilePolarity": "Negative"
},
{
"Path": "RAM2GS-B_Mask.gbs",
"FileFunction": "SolderMask,Bot",
"FilePolarity": "Negative"
},
{
"Path": "RAM2GS-Edge_Cuts.gm1",
"FileFunction": "Profile",
"FilePolarity": "Positive"
}
],
"MaterialStackup": [
{
"Type": "Legend",
"Name": "Top Silk Screen"
},
{
"Type": "SolderPaste",
"Name": "Top Solder Paste"
},
{
"Type": "SolderMask",
"Thickness": 0.01,
"Name": "Top Solder Mask"
},
{
"Type": "Copper",
"Thickness": 0.035,
"Name": "F.Cu"
},
{
"Type": "Dielectric",
"Thickness": 0.2104,
"Material": "FR4",
"Name": "F.Cu/In1.Cu",
"Notes": "Type: dielectric layer 1 (from F.Cu to In1.Cu)"
},
{
"Type": "Copper",
"Thickness": 0.0175,
"Name": "In1.Cu"
},
{
"Type": "Dielectric",
"Thickness": 1.065,
"Material": "FR4",
"Name": "In1.Cu/In2.Cu",
"Notes": "Type: dielectric layer 2 (from In1.Cu to In2.Cu)"
},
{
"Type": "Copper",
"Thickness": 0.0175,
"Name": "In2.Cu"
},
{
"Type": "Dielectric",
"Thickness": 0.2104,
"Material": "FR4",
"Name": "In2.Cu/B.Cu",
"Notes": "Type: dielectric layer 3 (from In2.Cu to B.Cu)"
},
{
"Type": "Copper",
"Thickness": 0.035,
"Name": "B.Cu"
},
{
"Type": "SolderMask",
"Thickness": 0.01,
"Name": "Bottom Solder Mask"
},
{
"Type": "SolderPaste",
"Name": "Bottom Solder Paste"
},
{
"Type": "Legend",
"Name": "Bottom Silk Screen"
}
]
}

55
Hardware/LCMXO/gerber/RAM2GS-top-pos.JUMPER.csv Normal file
View File

@ -0,0 +1,55 @@
Ref,Val,Package,MidX,MidY,Rotation,Side
"C1","10u","C_0805",58.928000,-128.778000,180.000000,top
"C2","10u","C_0805",109.982000,-127.889000,0.000000,top
"C3","10u","C_0805",109.500000,-105.550000,0.000000,top
"C4","10u","C_0805",107.700000,-116.150000,0.000000,top
"C5","2u2","C_0603",72.600000,-123.250000,-90.000000,top
"C6","2u2","C_0603",81.800000,-123.250000,-90.000000,top
"C7","2u2","C_0603",91.000000,-123.250000,-90.000000,top
"C8","2u2","C_0603",100.200000,-123.250000,-90.000000,top
"C9","2u2","C_0603",84.400000,-118.200000,0.000000,top
"C10","2u2","C_0603",69.500000,-110.400000,90.000000,top
"C11","2u2","C_0603",75.700000,-107.550000,90.000000,top
"C12","2u2","C_0603",79.150000,-98.900000,180.000000,top
"C13","2u2","C_0603",86.400000,-98.900000,180.000000,top
"C14","2u2","C_0603",95.050000,-110.800000,-90.000000,top
"C15","2u2","C_0603",75.700000,-110.350000,-90.000000,top
"C16","2u2","C_0603",95.050000,-107.300000,-90.000000,top
"C17","2u2","C_0603",54.150000,-99.350000,0.000000,top
"C18","2u2","C_0603",51.350000,-102.100000,90.000000,top
"C19","2u2","C_0603",51.350000,-106.900000,90.000000,top
"C20","2u2","C_0603",51.350000,-110.900000,90.000000,top
"C21","2u2","C_0603",54.150000,-123.950000,0.000000,top
"C22","2u2","C_0603",64.150000,-123.950000,0.000000,top
"C23","2u2","C_0603",66.950000,-110.800000,-90.000000,top
"C24","2u2","C_0603",66.950000,-106.000000,-90.000000,top
"C25","2u2","C_0603",64.150000,-99.350000,0.000000,top
"C26","10u","C_0805",59.150000,-124.250000,0.000000,top
"C27","2u2","C_0603",70.000000,-121.050000,180.000000,top
"C28","2u2","C_0603",109.150000,-120.500000,90.000000,top
"C29","2u2","C_0603",91.650000,-118.200000,0.000000,top
"C30","15p","C_0603",95.050000,-99.500000,45.000000,top
"D1","Amber","LED_0805",71.300000,-102.650000,180.000000,top
"FID1","Fiducial","Fiducial",51.054000,-93.726000,0.000000,top
"FID2","Fiducial","Fiducial",100.330000,-93.726000,0.000000,top
"FID3","Fiducial","Fiducial",110.236000,-117.983000,0.000000,top
"FID4","Fiducial","Fiducial",48.514000,-123.952000,0.000000,top
"R1","22k","R_0805",96.300000,-101.700000,-45.000000,top
"R2","22k","R_0805",98.750000,-104.150000,135.000000,top
"R3","47","R_0603",96.750000,-115.850000,-90.000000,top
"R4","0","R_0805",100.000000,-120.500000,180.000000,top
"R5","47","R_0603",97.800000,-98.200000,45.000000,top
"R6","47","R_0603",70.450000,-107.950000,180.000000,top
"R7","47","R_0603",73.250000,-107.950000,0.000000,top
"R8","220","R_0805",71.300000,-104.600000,0.000000,top
"U1","LCMXO256-TN100","TQFP-100_14x14mm_P0.5mm",85.400000,-108.550000,0.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",59.150000,-111.650000,-90.000000,top
"U3","60M","Crystal_SMD_7050-4Pin_7.0x5.0mm_SiTime",72.100000,-115.300000,0.000000,top
"U4","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",77.025000,-125.450000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",86.225000,-125.450000,0.000000,top
"U6","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",95.425000,-125.450000,0.000000,top
"U7","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",104.625000,-125.450000,0.000000,top
"U8","AZ1117CH-3.3TRG1","SOT-223",105.387000,-111.150000,0.000000,top
"U9","74LVC1G04GW","SOT-353",69.900000,-123.150000,-90.000000,top
"U10","74LVC1G04GW","SOT-353",72.100000,-110.500000,90.000000,top
"U12","25F010","SOIC-8_3.9mm",53.086000,-127.635000,-90.000000,top
1 Ref Val Package MidX MidY Rotation Side
2 C1 10u C_0805 58.928000 -128.778000 180.000000 top
3 C2 10u C_0805 109.982000 -127.889000 0.000000 top
4 C3 10u C_0805 109.500000 -105.550000 0.000000 top
5 C4 10u C_0805 107.700000 -116.150000 0.000000 top
6 C5 2u2 C_0603 72.600000 -123.250000 -90.000000 top
7 C6 2u2 C_0603 81.800000 -123.250000 -90.000000 top
8 C7 2u2 C_0603 91.000000 -123.250000 -90.000000 top
9 C8 2u2 C_0603 100.200000 -123.250000 -90.000000 top
10 C9 2u2 C_0603 84.400000 -118.200000 0.000000 top
11 C10 2u2 C_0603 69.500000 -110.400000 90.000000 top
12 C11 2u2 C_0603 75.700000 -107.550000 90.000000 top
13 C12 2u2 C_0603 79.150000 -98.900000 180.000000 top
14 C13 2u2 C_0603 86.400000 -98.900000 180.000000 top
15 C14 2u2 C_0603 95.050000 -110.800000 -90.000000 top
16 C15 2u2 C_0603 75.700000 -110.350000 -90.000000 top
17 C16 2u2 C_0603 95.050000 -107.300000 -90.000000 top
18 C17 2u2 C_0603 54.150000 -99.350000 0.000000 top
19 C18 2u2 C_0603 51.350000 -102.100000 90.000000 top
20 C19 2u2 C_0603 51.350000 -106.900000 90.000000 top
21 C20 2u2 C_0603 51.350000 -110.900000 90.000000 top
22 C21 2u2 C_0603 54.150000 -123.950000 0.000000 top
23 C22 2u2 C_0603 64.150000 -123.950000 0.000000 top
24 C23 2u2 C_0603 66.950000 -110.800000 -90.000000 top
25 C24 2u2 C_0603 66.950000 -106.000000 -90.000000 top
26 C25 2u2 C_0603 64.150000 -99.350000 0.000000 top
27 C26 10u C_0805 59.150000 -124.250000 0.000000 top
28 C27 2u2 C_0603 70.000000 -121.050000 180.000000 top
29 C28 2u2 C_0603 109.150000 -120.500000 90.000000 top
30 C29 2u2 C_0603 91.650000 -118.200000 0.000000 top
31 C30 15p C_0603 95.050000 -99.500000 45.000000 top
32 D1 Amber LED_0805 71.300000 -102.650000 180.000000 top
33 FID1 Fiducial Fiducial 51.054000 -93.726000 0.000000 top
34 FID2 Fiducial Fiducial 100.330000 -93.726000 0.000000 top
35 FID3 Fiducial Fiducial 110.236000 -117.983000 0.000000 top
36 FID4 Fiducial Fiducial 48.514000 -123.952000 0.000000 top
37 R1 22k R_0805 96.300000 -101.700000 -45.000000 top
38 R2 22k R_0805 98.750000 -104.150000 135.000000 top
39 R3 47 R_0603 96.750000 -115.850000 -90.000000 top
40 R4 0 R_0805 100.000000 -120.500000 180.000000 top
41 R5 47 R_0603 97.800000 -98.200000 45.000000 top
42 R6 47 R_0603 70.450000 -107.950000 180.000000 top
43 R7 47 R_0603 73.250000 -107.950000 0.000000 top
44 R8 220 R_0805 71.300000 -104.600000 0.000000 top
45 U1 LCMXO256-TN100 TQFP-100_14x14mm_P0.5mm 85.400000 -108.550000 0.000000 top
46 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 59.150000 -111.650000 -90.000000 top
47 U3 60M Crystal_SMD_7050-4Pin_7.0x5.0mm_SiTime 72.100000 -115.300000 0.000000 top
48 U4 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 77.025000 -125.450000 0.000000 top
49 U5 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 86.225000 -125.450000 0.000000 top
50 U6 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 95.425000 -125.450000 0.000000 top
51 U7 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 104.625000 -125.450000 0.000000 top
52 U8 AZ1117CH-3.3TRG1 SOT-223 105.387000 -111.150000 0.000000 top
53 U9 74LVC1G04GW SOT-353 69.900000 -123.150000 -90.000000 top
54 U10 74LVC1G04GW SOT-353 72.100000 -110.500000 90.000000 top
55 U12 25F010 SOIC-8_3.9mm 53.086000 -127.635000 -90.000000 top

55
Hardware/LCMXO/gerber/RAM2GS-top-pos.VCORE.csv Normal file
View File

@ -0,0 +1,55 @@
Ref,Val,Package,MidX,MidY,Rotation,Side
"C1","10u","C_0805",58.928000,-128.778000,180.000000,top
"C2","10u","C_0805",109.982000,-127.889000,0.000000,top
"C3","10u","C_0805",109.500000,-105.550000,0.000000,top
"C4","10u","C_0805",107.700000,-116.150000,0.000000,top
"C5","2u2","C_0603",72.600000,-123.250000,-90.000000,top
"C6","2u2","C_0603",81.800000,-123.250000,-90.000000,top
"C7","2u2","C_0603",91.000000,-123.250000,-90.000000,top
"C8","2u2","C_0603",100.200000,-123.250000,-90.000000,top
"C9","2u2","C_0603",84.400000,-118.200000,0.000000,top
"C10","2u2","C_0603",69.500000,-110.400000,90.000000,top
"C11","2u2","C_0603",75.700000,-107.550000,90.000000,top
"C12","2u2","C_0603",79.150000,-98.900000,180.000000,top
"C13","2u2","C_0603",86.400000,-98.900000,180.000000,top
"C14","2u2","C_0603",95.050000,-110.800000,-90.000000,top
"C15","2u2","C_0603",75.700000,-110.350000,-90.000000,top
"C16","2u2","C_0603",95.050000,-107.300000,-90.000000,top
"C17","2u2","C_0603",54.150000,-99.350000,0.000000,top
"C18","2u2","C_0603",51.350000,-102.100000,90.000000,top
"C19","2u2","C_0603",51.350000,-106.900000,90.000000,top
"C20","2u2","C_0603",51.350000,-110.900000,90.000000,top
"C21","2u2","C_0603",54.150000,-123.950000,0.000000,top
"C22","2u2","C_0603",64.150000,-123.950000,0.000000,top
"C23","2u2","C_0603",66.950000,-110.800000,-90.000000,top
"C24","2u2","C_0603",66.950000,-106.000000,-90.000000,top
"C25","2u2","C_0603",64.150000,-99.350000,0.000000,top
"C26","10u","C_0805",59.150000,-124.250000,0.000000,top
"C27","2u2","C_0603",70.000000,-121.050000,180.000000,top
"C28","2u2","C_0603",109.150000,-120.500000,90.000000,top
"C29","2u2","C_0603",91.650000,-118.200000,0.000000,top
"C30","15p","C_0603",95.050000,-99.500000,45.000000,top
"D1","Amber","LED_0805",71.300000,-102.650000,180.000000,top
"FID1","Fiducial","Fiducial",51.054000,-93.726000,0.000000,top
"FID2","Fiducial","Fiducial",100.330000,-93.726000,0.000000,top
"FID3","Fiducial","Fiducial",110.236000,-117.983000,0.000000,top
"FID4","Fiducial","Fiducial",48.514000,-123.952000,0.000000,top
"R1","22k","R_0805",96.300000,-101.700000,-45.000000,top
"R2","22k","R_0805",98.750000,-104.150000,135.000000,top
"R3","47","R_0603",96.750000,-115.850000,-90.000000,top
"R5","47","R_0603",97.800000,-98.200000,45.000000,top
"R6","47","R_0603",70.450000,-107.950000,180.000000,top
"R7","47","R_0603",73.250000,-107.950000,0.000000,top
"R8","220","R_0805",71.300000,-104.600000,0.000000,top
"U1","LCMXO256-TN100","TQFP-100_14x14mm_P0.5mm",85.400000,-108.550000,0.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",59.150000,-111.650000,-90.000000,top
"U3","60M","Crystal_SMD_7050-4Pin_7.0x5.0mm_SiTime",72.100000,-115.300000,0.000000,top
"U4","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",77.025000,-125.450000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",86.225000,-125.450000,0.000000,top
"U6","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",95.425000,-125.450000,0.000000,top
"U7","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",104.625000,-125.450000,0.000000,top
"U8","AZ1117CH-3.3TRG1","SOT-223",105.387000,-111.150000,0.000000,top
"U9","74LVC1G04GW","SOT-353",69.900000,-123.150000,-90.000000,top
"U10","74LVC1G04GW","SOT-353",72.100000,-110.500000,90.000000,top
"U11","AP2127K-1.2TRG1","SOT-23-5",110.100000,-124.250000,0.000000,top
"U12","25F010","SOIC-8_3.9mm",53.086000,-127.635000,-90.000000,top
1 Ref Val Package MidX MidY Rotation Side
2 C1 10u C_0805 58.928000 -128.778000 180.000000 top
3 C2 10u C_0805 109.982000 -127.889000 0.000000 top
4 C3 10u C_0805 109.500000 -105.550000 0.000000 top
5 C4 10u C_0805 107.700000 -116.150000 0.000000 top
6 C5 2u2 C_0603 72.600000 -123.250000 -90.000000 top
7 C6 2u2 C_0603 81.800000 -123.250000 -90.000000 top
8 C7 2u2 C_0603 91.000000 -123.250000 -90.000000 top
9 C8 2u2 C_0603 100.200000 -123.250000 -90.000000 top
10 C9 2u2 C_0603 84.400000 -118.200000 0.000000 top
11 C10 2u2 C_0603 69.500000 -110.400000 90.000000 top
12 C11 2u2 C_0603 75.700000 -107.550000 90.000000 top
13 C12 2u2 C_0603 79.150000 -98.900000 180.000000 top
14 C13 2u2 C_0603 86.400000 -98.900000 180.000000 top
15 C14 2u2 C_0603 95.050000 -110.800000 -90.000000 top
16 C15 2u2 C_0603 75.700000 -110.350000 -90.000000 top
17 C16 2u2 C_0603 95.050000 -107.300000 -90.000000 top
18 C17 2u2 C_0603 54.150000 -99.350000 0.000000 top
19 C18 2u2 C_0603 51.350000 -102.100000 90.000000 top
20 C19 2u2 C_0603 51.350000 -106.900000 90.000000 top
21 C20 2u2 C_0603 51.350000 -110.900000 90.000000 top
22 C21 2u2 C_0603 54.150000 -123.950000 0.000000 top
23 C22 2u2 C_0603 64.150000 -123.950000 0.000000 top
24 C23 2u2 C_0603 66.950000 -110.800000 -90.000000 top
25 C24 2u2 C_0603 66.950000 -106.000000 -90.000000 top
26 C25 2u2 C_0603 64.150000 -99.350000 0.000000 top
27 C26 10u C_0805 59.150000 -124.250000 0.000000 top
28 C27 2u2 C_0603 70.000000 -121.050000 180.000000 top
29 C28 2u2 C_0603 109.150000 -120.500000 90.000000 top
30 C29 2u2 C_0603 91.650000 -118.200000 0.000000 top
31 C30 15p C_0603 95.050000 -99.500000 45.000000 top
32 D1 Amber LED_0805 71.300000 -102.650000 180.000000 top
33 FID1 Fiducial Fiducial 51.054000 -93.726000 0.000000 top
34 FID2 Fiducial Fiducial 100.330000 -93.726000 0.000000 top
35 FID3 Fiducial Fiducial 110.236000 -117.983000 0.000000 top
36 FID4 Fiducial Fiducial 48.514000 -123.952000 0.000000 top
37 R1 22k R_0805 96.300000 -101.700000 -45.000000 top
38 R2 22k R_0805 98.750000 -104.150000 135.000000 top
39 R3 47 R_0603 96.750000 -115.850000 -90.000000 top
40 R5 47 R_0603 97.800000 -98.200000 45.000000 top
41 R6 47 R_0603 70.450000 -107.950000 180.000000 top
42 R7 47 R_0603 73.250000 -107.950000 0.000000 top
43 R8 220 R_0805 71.300000 -104.600000 0.000000 top
44 U1 LCMXO256-TN100 TQFP-100_14x14mm_P0.5mm 85.400000 -108.550000 0.000000 top
45 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 59.150000 -111.650000 -90.000000 top
46 U3 60M Crystal_SMD_7050-4Pin_7.0x5.0mm_SiTime 72.100000 -115.300000 0.000000 top
47 U4 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 77.025000 -125.450000 0.000000 top
48 U5 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 86.225000 -125.450000 0.000000 top
49 U6 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 95.425000 -125.450000 0.000000 top
50 U7 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 104.625000 -125.450000 0.000000 top
51 U8 AZ1117CH-3.3TRG1 SOT-223 105.387000 -111.150000 0.000000 top
52 U9 74LVC1G04GW SOT-353 69.900000 -123.150000 -90.000000 top
53 U10 74LVC1G04GW SOT-353 72.100000 -110.500000 90.000000 top
54 U11 AP2127K-1.2TRG1 SOT-23-5 110.100000 -124.250000 0.000000 top
55 U12 25F010 SOIC-8_3.9mm 53.086000 -127.635000 -90.000000 top

38
Hardware/LCMXO/gerber/RAM2GS-top-pos.csv
View File

@ -1,56 +1,56 @@
Ref,Val,Package,MidX,MidY,Rot,Side
Ref,Val,Package,MidX,MidY,Rotation,Side
"C1","10u","C_0805",58.928000,-128.778000,180.000000,top
"C2","10u","C_0805",109.982000,-127.889000,0.000000,top
"C3","10u","C_0805",109.500000,-105.550000,0.000000,top
"C4","10u","C_0805",107.700000,-116.150000,0.000000,top
"C5","2u2","C_0603",72.600000,-123.250000,270.000000,top
"C6","2u2","C_0603",81.800000,-123.250000,270.000000,top
"C7","2u2","C_0603",91.000000,-123.250000,270.000000,top
"C8","2u2","C_0603",100.200000,-123.250000,270.000000,top
"C5","2u2","C_0603",72.600000,-123.250000,-90.000000,top
"C6","2u2","C_0603",81.800000,-123.250000,-90.000000,top
"C7","2u2","C_0603",91.000000,-123.250000,-90.000000,top
"C8","2u2","C_0603",100.200000,-123.250000,-90.000000,top
"C9","2u2","C_0603",84.400000,-118.200000,0.000000,top
"C10","2u2","C_0603",69.500000,-110.400000,90.000000,top
"C11","2u2","C_0603",75.700000,-107.550000,90.000000,top
"C12","2u2","C_0603",79.150000,-98.900000,180.000000,top
"C13","2u2","C_0603",86.400000,-98.900000,180.000000,top
"C14","2u2","C_0603",95.050000,-110.800000,270.000000,top
"C15","2u2","C_0603",75.700000,-110.350000,270.000000,top
"C16","2u2","C_0603",95.050000,-107.300000,270.000000,top
"C14","2u2","C_0603",95.050000,-110.800000,-90.000000,top
"C15","2u2","C_0603",75.700000,-110.350000,-90.000000,top
"C16","2u2","C_0603",95.050000,-107.300000,-90.000000,top
"C17","2u2","C_0603",54.150000,-99.350000,0.000000,top
"C18","2u2","C_0603",51.350000,-102.100000,90.000000,top
"C19","2u2","C_0603",51.350000,-106.900000,90.000000,top
"C20","2u2","C_0603",51.350000,-110.900000,90.000000,top
"C21","2u2","C_0603",54.150000,-123.950000,0.000000,top
"C22","2u2","C_0603",64.150000,-123.950000,0.000000,top
"C23","2u2","C_0603",66.950000,-110.800000,270.000000,top
"C24","2u2","C_0603",66.950000,-106.000000,270.000000,top
"C23","2u2","C_0603",66.950000,-110.800000,-90.000000,top
"C24","2u2","C_0603",66.950000,-106.000000,-90.000000,top
"C25","2u2","C_0603",64.150000,-99.350000,0.000000,top
"C26","10u","C_0805",59.150000,-124.250000,0.000000,top
"C27","2u2","C_0603",70.000000,-121.050000,180.000000,top
"C28","2u2","C_0603",109.150000,-120.500000,90.000000,top
"C29","2u2","C_0603",91.650000,-118.200000,0.000000,top
"C30","15p","C_0603",95.050000,-99.500000,45.000000,top
"D1","White","LED_0805",71.300000,-102.650000,180.000000,top
"D1","Amber","LED_0805",71.300000,-102.650000,180.000000,top
"FID1","Fiducial","Fiducial",51.054000,-93.726000,0.000000,top
"FID2","Fiducial","Fiducial",100.330000,-93.726000,0.000000,top
"FID3","Fiducial","Fiducial",110.236000,-117.983000,0.000000,top
"FID4","Fiducial","Fiducial",48.514000,-123.952000,0.000000,top
"R1","22k","R_0805",96.300000,-101.700000,315.000000,top
"R1","22k","R_0805",96.300000,-101.700000,-45.000000,top
"R2","22k","R_0805",98.750000,-104.150000,135.000000,top
"R3","47","R_0603",96.750000,-115.850000,270.000000,top
"R3","47","R_0603",96.750000,-115.850000,-90.000000,top
"R4","0","R_0805",100.000000,-120.500000,180.000000,top
"R5","47","R_0603",97.800000,-98.200000,45.000000,top
"R6","47","R_0603",70.450000,-107.950000,180.000000,top
"R7","47","R_0603",73.250000,-107.950000,0.000000,top
"R8","180","R_0805",71.300000,-104.600000,0.000000,top
"R8","220","R_0805",71.300000,-104.600000,0.000000,top
"U1","LCMXO256-TN100","TQFP-100_14x14mm_P0.5mm",85.400000,-108.550000,0.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",59.150000,-111.650000,0.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",59.150000,-111.650000,-90.000000,top
"U3","60M","Crystal_SMD_7050-4Pin_7.0x5.0mm_SiTime",72.100000,-115.300000,0.000000,top
"U4","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",77.025000,-125.450000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",86.225000,-125.450000,0.000000,top
"U6","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",95.425000,-125.450000,0.000000,top
"U7","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",104.625000,-125.450000,0.000000,top
"U8","AZ1117CH-3.3TRG1","SOT-223",105.387000,-111.150000,0.000000,top
"U9","74LVC1G04GW","SOT-353",69.900000,-123.150000,180.000000,top
"U10","74LVC1G04GW","SOT-353",72.100000,-110.500000,0.000000,top
"U11","AP2127K-1.2TRG1","SOT-23-5",110.100000,-124.250000,270.000000,top
"U12","25F010","SOIC-8_3.9mm",53.086000,-127.635000,270.000000,top
"U9","74LVC1G04GW","SOT-353",69.900000,-123.150000,-90.000000,top
"U10","74LVC1G04GW","SOT-353",72.100000,-110.500000,90.000000,top
"U11","AP2127K-1.2TRG1","SOT-23-5",110.100000,-124.250000,0.000000,top
"U12","25F010","SOIC-8_3.9mm",53.086000,-127.635000,-90.000000,top

1 Ref Val Package MidX MidY Rot Rotation Side
2 C1 10u C_0805 58.928000 -128.778000 180.000000 180.000000 top
3 C2 10u C_0805 109.982000 -127.889000 0.000000 0.000000 top
4 C3 10u C_0805 109.500000 -105.550000 0.000000 0.000000 top
5 C4 10u C_0805 107.700000 -116.150000 0.000000 0.000000 top
6 C5 2u2 C_0603 72.600000 -123.250000 270.000000 -90.000000 top
7 C6 2u2 C_0603 81.800000 -123.250000 270.000000 -90.000000 top
8 C7 2u2 C_0603 91.000000 -123.250000 270.000000 -90.000000 top
9 C8 2u2 C_0603 100.200000 -123.250000 270.000000 -90.000000 top
10 C9 2u2 C_0603 84.400000 -118.200000 0.000000 0.000000 top
11 C10 2u2 C_0603 69.500000 -110.400000 90.000000 90.000000 top
12 C11 2u2 C_0603 75.700000 -107.550000 90.000000 90.000000 top
13 C12 2u2 C_0603 79.150000 -98.900000 180.000000 180.000000 top
14 C13 2u2 C_0603 86.400000 -98.900000 180.000000 180.000000 top
15 C14 2u2 C_0603 95.050000 -110.800000 270.000000 -90.000000 top
16 C15 2u2 C_0603 75.700000 -110.350000 270.000000 -90.000000 top
17 C16 2u2 C_0603 95.050000 -107.300000 270.000000 -90.000000 top
18 C17 2u2 C_0603 54.150000 -99.350000 0.000000 0.000000 top
19 C18 2u2 C_0603 51.350000 -102.100000 90.000000 90.000000 top
20 C19 2u2 C_0603 51.350000 -106.900000 90.000000 90.000000 top
21 C20 2u2 C_0603 51.350000 -110.900000 90.000000 90.000000 top
22 C21 2u2 C_0603 54.150000 -123.950000 0.000000 0.000000 top
23 C22 2u2 C_0603 64.150000 -123.950000 0.000000 0.000000 top
24 C23 2u2 C_0603 66.950000 -110.800000 270.000000 -90.000000 top
25 C24 2u2 C_0603 66.950000 -106.000000 270.000000 -90.000000 top
26 C25 2u2 C_0603 64.150000 -99.350000 0.000000 0.000000 top
27 C26 10u C_0805 59.150000 -124.250000 0.000000 0.000000 top
28 C27 2u2 C_0603 70.000000 -121.050000 180.000000 180.000000 top
29 C28 2u2 C_0603 109.150000 -120.500000 90.000000 90.000000 top
30 C29 2u2 C_0603 91.650000 -118.200000 0.000000 0.000000 top
31 C30 15p C_0603 95.050000 -99.500000 45.000000 45.000000 top
32 D1 White Amber LED_0805 71.300000 -102.650000 180.000000 180.000000 top
33 FID1 Fiducial Fiducial 51.054000 -93.726000 0.000000 0.000000 top
34 FID2 Fiducial Fiducial 100.330000 -93.726000 0.000000 0.000000 top
35 FID3 Fiducial Fiducial 110.236000 -117.983000 0.000000 0.000000 top
36 FID4 Fiducial Fiducial 48.514000 -123.952000 0.000000 0.000000 top
37 R1 22k R_0805 96.300000 -101.700000 315.000000 -45.000000 top
38 R2 22k R_0805 98.750000 -104.150000 135.000000 135.000000 top
39 R3 47 R_0603 96.750000 -115.850000 270.000000 -90.000000 top
40 R4 0 R_0805 100.000000 -120.500000 180.000000 180.000000 top
41 R5 47 R_0603 97.800000 -98.200000 45.000000 45.000000 top
42 R6 47 R_0603 70.450000 -107.950000 180.000000 180.000000 top
43 R7 47 R_0603 73.250000 -107.950000 0.000000 0.000000 top
44 R8 180 220 R_0805 71.300000 -104.600000 0.000000 0.000000 top
45 U1 LCMXO256-TN100 TQFP-100_14x14mm_P0.5mm 85.400000 -108.550000 0.000000 0.000000 top
46 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 59.150000 -111.650000 0.000000 -90.000000 top
47 U3 60M Crystal_SMD_7050-4Pin_7.0x5.0mm_SiTime 72.100000 -115.300000 0.000000 0.000000 top
48 U4 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 77.025000 -125.450000 0.000000 0.000000 top
49 U5 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 86.225000 -125.450000 0.000000 0.000000 top
50 U6 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 95.425000 -125.450000 0.000000 0.000000 top
51 U7 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 104.625000 -125.450000 0.000000 0.000000 top
52 U8 AZ1117CH-3.3TRG1 SOT-223 105.387000 -111.150000 0.000000 0.000000 top
53 U9 74LVC1G04GW SOT-353 69.900000 -123.150000 180.000000 -90.000000 top
54 U10 74LVC1G04GW SOT-353 72.100000 -110.500000 0.000000 90.000000 top
55 U11 AP2127K-1.2TRG1 SOT-23-5 110.100000 -124.250000 270.000000 0.000000 top
56 U12 25F010 SOIC-8_3.9mm 53.086000 -127.635000 270.000000 -90.000000 top

61
Hardware/LCMXO/gerber/RAM2GS-top.pos
View File

@ -1,61 +0,0 @@
### Module positions - created on Monday, May 31, 2021 at 06:26:03 PM ###
### Printed by Pcbnew version kicad (5.1.10-1-10_14)
## Unit = mm, Angle = deg.
## Side : top
# Ref Val Package PosX PosY Rot Side
C1 10u C_0805 58.9280 -128.7780 180.0000 top
C2 10u C_0805 109.9820 -127.8890 0.0000 top
C3 10u C_0805 109.5000 -105.5500 0.0000 top
C4 10u C_0805 107.7000 -116.1500 0.0000 top
C5 2u2 C_0603 72.6000 -123.2500 270.0000 top
C6 2u2 C_0603 81.8000 -123.2500 270.0000 top
C7 2u2 C_0603 91.0000 -123.2500 270.0000 top
C8 2u2 C_0603 100.2000 -123.2500 270.0000 top
C9 2u2 C_0603 84.4000 -118.2000 0.0000 top
C10 2u2 C_0603 69.5000 -110.4000 90.0000 top
C11 2u2 C_0603 75.7000 -107.5500 90.0000 top
C12 2u2 C_0603 79.1500 -98.9000 180.0000 top
C13 2u2 C_0603 86.4000 -98.9000 180.0000 top
C14 2u2 C_0603 95.0500 -110.8000 270.0000 top
C15 2u2 C_0603 75.7000 -110.3500 270.0000 top
C16 2u2 C_0603 95.0500 -107.3000 270.0000 top
C17 2u2 C_0603 54.1500 -99.3500 0.0000 top
C18 2u2 C_0603 51.3500 -102.1000 90.0000 top
C19 2u2 C_0603 51.3500 -106.9000 90.0000 top
C20 2u2 C_0603 51.3500 -110.9000 90.0000 top
C21 2u2 C_0603 54.1500 -123.9500 0.0000 top
C22 2u2 C_0603 64.1500 -123.9500 0.0000 top
C23 2u2 C_0603 66.9500 -110.8000 270.0000 top
C24 2u2 C_0603 66.9500 -106.0000 270.0000 top
C25 2u2 C_0603 64.1500 -99.3500 0.0000 top
C26 10u C_0805 59.1500 -124.2500 0.0000 top
C27 2u2 C_0603 70.0000 -121.0500 180.0000 top
C28 2u2 C_0603 109.1500 -120.5000 90.0000 top
C29 2u2 C_0603 91.6500 -118.2000 0.0000 top
C30 15p C_0603 95.0500 -99.5000 45.0000 top
D1 White LED_0805 71.3000 -102.6500 180.0000 top
FID1 Fiducial Fiducial 51.0540 -93.7260 0.0000 top
FID2 Fiducial Fiducial 100.3300 -93.7260 0.0000 top
FID3 Fiducial Fiducial 110.2360 -117.9830 0.0000 top
FID4 Fiducial Fiducial 48.5140 -123.9520 0.0000 top
R1 22k R_0805 96.3000 -101.7000 315.0000 top
R2 22k R_0805 98.7500 -104.1500 135.0000 top
R3 47 R_0603 96.7500 -115.8500 270.0000 top
R4 0 R_0805 100.0000 -120.5000 180.0000 top
R5 47 R_0603 97.8000 -98.2000 45.0000 top
R6 47 R_0603 70.4500 -107.9500 180.0000 top
R7 47 R_0603 73.2500 -107.9500 0.0000 top
R8 180 R_0805 71.3000 -104.6000 0.0000 top
U1 LCMXO256-TN100 TQFP-100_14x14mm_P0.5mm 85.4000 -108.5500 0.0000 top
U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 59.1500 -111.6500 0.0000 top
U3 60M Crystal_SMD_7050-4Pin_7.0x5.0mm_SiTime 72.1000 -115.3000 0.0000 top
U4 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 77.0250 -125.4500 0.0000 top
U5 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 86.2250 -125.4500 0.0000 top
U6 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 95.4250 -125.4500 0.0000 top
U7 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 104.6250 -125.4500 0.0000 top
U8 AZ1117CH-3.3TRG1 SOT-223 105.3870 -111.1500 0.0000 top
U9 74LVC1G04GW SOT-353 69.9000 -123.1500 180.0000 top
U10 74LVC1G04GW SOT-353 72.1000 -110.5000 0.0000 top
U11 AP2127K-1.2TRG1 SOT-23-5 110.1000 -124.2500 270.0000 top
U12 25F010 SOIC-8_3.9mm 53.0860 -127.6350 270.0000 top
## End

BIN
Hardware/LCMXO/gerber/RAM2GS.4201D.LCMXO-gerber.zip Normal file
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185
Hardware/LCMXO/gerber/RAM2GS.drl
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@ -1,20 +1,27 @@
M48
; DRILL file {KiCad (5.1.10-1-10_14)} date Monday, May 31, 2021 at 06:25:57 PM
; DRILL file {KiCad 7.0.1-0} date 2023 November 03, Friday 04:24:26
; FORMAT={-:-/ absolute / inch / decimal}
; #@! TF.CreationDate,2021-05-31T18:25:57-04:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.10-1-10_14)
; #@! TF.CreationDate,2023-11-03T04:24:26-04:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,7.0.1-0
; #@! TF.FileFunction,MixedPlating,1,4
FMAT,2
INCH
T1C0.0079
T2C0.0118
T3C0.0150
T4C0.0157
T5C0.0197
T6C0.0300
T7C0.0433
T8C0.0390
T9C0.0454
T10C0.0935
; #@! TA.AperFunction,Plated,PTH,ViaDrill
T1C0.0118
; #@! TA.AperFunction,Plated,PTH,ViaDrill
T2C0.0157
; #@! TA.AperFunction,Plated,PTH,ViaDrill
T3C0.0197
; #@! TA.AperFunction,Plated,PTH,ViaDrill
T4C0.0300
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T5C0.0433
; #@! TA.AperFunction,NonPlated,NPTH,ComponentDrill
T6C0.0390
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T7C0.0454
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T8C0.0935
%
G90
G05
@ -30,19 +37,35 @@ X1.935Y-4.95
X1.935Y-5.0
X1.935Y-5.05
X1.965Y-5.16
X1.97Y-3.74
X1.97Y-3.93
X1.97Y-4.545
X1.97Y-4.745
X1.9823Y-3.9902
X1.9823Y-4.0492
X1.9823Y-4.1791
X1.9823Y-4.2382
X1.9823Y-4.3366
X1.9823Y-4.3957
X2.0025Y-5.1325
X2.0217Y-3.9528
X2.0217Y-4.0866
X2.0217Y-4.1417
X2.0217Y-4.2717
X2.0217Y-4.3031
X2.0217Y-4.4331
X2.05Y-5.1
X2.0571Y-4.0492
X2.0571Y-4.2382
X2.0571Y-4.3327
X2.0571Y-4.3957
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X2.065Y-3.63
X2.065Y-3.83
X2.0689Y-3.9114
X2.0689Y-4.8799
X2.1024Y-3.876
X2.1024Y-3.9606
X2.1024Y-4.8307
X2.1024Y-4.9154
X2.13Y-4.955
X2.13Y-5.05
X2.13Y-5.1
@ -58,7 +81,11 @@ X2.1516Y-4.5531
X2.1516Y-4.6161
X2.1516Y-4.6791
X2.1516Y-4.7421
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X2.1575Y-3.74
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X2.1693Y-4.4272
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@ -74,11 +101,18 @@ X2.1752Y-4.2657
X2.1752Y-4.3051
X2.1752Y-4.3642
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X2.1949Y-3.9114
X2.1949Y-4.8799
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@ -87,11 +121,16 @@ X2.3287Y-4.1909
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X2.3287Y-4.3327
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X2.3646Y-3.9291
X2.376Y-4.3957
X2.3839Y-4.8051
X2.4035Y-4.8917
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X2.4823Y-4.0177
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@ -101,6 +140,9 @@ X2.4823Y-4.2106
X2.4823Y-4.2657
X2.4823Y-4.3051
X2.4823Y-4.3642
X2.4961Y-3.876
X2.4961Y-3.9469
X2.4961Y-4.8425
X2.4961Y-4.9134
X2.5098Y-3.9862
X2.5098Y-4.0492
@ -110,8 +152,13 @@ X2.5098Y-4.3327
X2.5098Y-4.3957
X2.5098Y-4.8051
X2.52Y-5.155
X2.5551Y-3.876
X2.5551Y-3.9606
X2.5551Y-4.8307
X2.5551Y-4.9134
X2.57Y-5.12
X2.5886Y-3.9114
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X2.6004Y-3.9862
X2.6004Y-4.0492
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@ -129,7 +176,9 @@ X2.626Y-4.6476
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X2.626Y-4.7736
X2.6358Y-4.2362
X2.6358Y-4.2953
X2.6358Y-4.4252
X2.6417Y-4.1063
X2.6575Y-4.939
X2.665Y-3.63
X2.6693Y-4.3366
@ -154,26 +203,30 @@ X2.8169Y-4.7657
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X2.8248Y-4.8819
X2.8268Y-5.0276
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X2.8583Y-4.7894
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X2.8927Y-4.8228
X2.8937Y-4.8819
X2.9075Y-4.3248
X2.9075Y-4.3957
X2.9094Y-4.7402
X2.9173Y-4.7795
X2.9173Y-5.0098
X2.92Y-5.155
X2.9331Y-5.1102
X2.939Y-4.6752
X2.9469Y-4.2106
X2.9469Y-4.2677
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X2.9823Y-4.4055
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X3.002Y-4.6142
X3.0098Y-4.9646
X3.0157Y-4.0374
X3.0157Y-4.0768
@ -222,6 +275,7 @@ X3.1634Y-4.3583
X3.1654Y-4.0512
X3.1732Y-5.0551
X3.185Y-4.0157
X3.185Y-4.8819
X3.187Y-4.8228
X3.2047Y-3.9272
X3.2087Y-5.0098
@ -249,6 +303,7 @@ X3.3071Y-4.8661
X3.32Y-5.155
X3.3228Y-3.9272
X3.3307Y-5.0098
X3.3406Y-3.8445
X3.3406Y-3.8878
X3.3425Y-4.0157
X3.3425Y-4.5315
@ -270,7 +325,7 @@ X3.4488Y-4.4705
X3.4606Y-4.0157
X3.465Y-3.63
X3.47Y-5.12
X3.4843Y-3.83
X3.4843Y-3.8878
X3.4882Y-4.4134
X3.5Y-3.9272
X3.5Y-4.372
@ -281,7 +336,8 @@ X3.5098Y-5.1004
X3.5197Y-4.0157
X3.52Y-5.155
X3.5354Y-5.0551
X3.5394Y-3.83
X3.5394Y-3.8878
X3.5472Y-4.8819
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@ -311,7 +367,6 @@ X3.6319Y-4.687
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X3.6654Y-5.0098
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@ -340,26 +395,31 @@ X3.7756Y-4.3386
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X3.7874Y-3.9213
X3.7953Y-4.9803
X3.8189Y-3.9528
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X3.9094Y-4.8819
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X3.9783Y-4.8819
X3.9783Y-5.0551
X3.9793Y-4.8228
X3.9975Y-3.9975
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@ -374,88 +434,31 @@ X4.128Y-3.9272
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T2
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X2.1024Y-3.9606
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X2.8937Y-4.8819
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X3.185Y-4.8819
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X3.9094Y-4.8819
X3.9449Y-4.9154
X3.9975Y-3.9975
X4.0256Y-4.0453
X4.1673Y-4.5728
X4.1978Y-4.1171
X4.2618Y-4.7205
X4.2972Y-4.8071
X4.3327Y-4.7205
X4.3327Y-4.7677
X4.3346Y-4.9764
T3
X1.9823Y-4.3366
X1.9823Y-4.3957
X2.0217Y-4.1417
X2.0217Y-4.4331
X2.2972Y-5.0217
X2.6358Y-4.2953
T4
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X2.2539Y-4.8917
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X2.3622Y-4.8445
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X2.6417Y-4.1063
X2.939Y-4.6752
X3.002Y-4.6142
X4.2067Y-4.5236
X4.3445Y-4.2047
T5
T3
X3.9488Y-4.1791
X3.9488Y-4.2776
X3.9488Y-4.3366
@ -470,7 +473,7 @@ X4.2776Y-4.1024
X4.3346Y-4.5728
X4.3445Y-4.1024
X4.3917Y-4.1555
T6
T4
X2.27Y-5.14
X2.37Y-5.14
X4.0276Y-4.2579
@ -484,18 +487,18 @@ X4.2776Y-4.2185
X4.3484Y-4.2854
X4.3484Y-4.4665
X4.3563Y-4.376
T7
T5
X4.37Y-5.125
T8
T6
X3.9677Y-3.8867
X4.1516Y-4.1271
X4.2081Y-4.0705
T9
T7
X1.91Y-3.69
X1.91Y-5.1
X4.05Y-3.69
X4.39Y-4.535
T10
T8
X3.897Y-3.9574
X4.0384Y-3.8159
X4.0561Y-4.1165

7
Hardware/LCMXO/sym-lib-table
View File

@ -1,5 +1,6 @@
(sym_lib_table
(lib (name GW_Logic)(type Legacy)(uri "$(KIPRJMOD)/../../../GW_Parts/GW_Logic.lib")(options "")(descr ""))
(lib (name GW_PLD)(type Legacy)(uri "$(KIPRJMOD)/../../../GW_Parts/GW_PLD.lib")(options "")(descr ""))
(lib (name GW_RAM)(type Legacy)(uri "$(KIPRJMOD)/../../../GW_Parts/GW_RAM.lib")(options "")(descr ""))
(version 7)
(lib (name "GW_Logic")(type "KiCad")(uri "$(KIPRJMOD)/../../../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
(lib (name "GW_PLD")(type "KiCad")(uri "$(KIPRJMOD)/../../../GW_Parts/GW_PLD.kicad_sym")(options "")(descr ""))
(lib (name "GW_RAM")(type "KiCad")(uri "$(KIPRJMOD)/../../../GW_Parts/GW_RAM.kicad_sym")(options "")(descr ""))
)

0
Hardware/LCMXO2/gerber/RAM2GS-BOM. LCMXO2ZE.csv → Hardware/LCMXO2/BOM/RAM2GS-BOM. LCMXO2ZE.csv
View File

2
Hardware/LCMXO2/gerber/RAM2GS-BOM.LCMXO2HC.csv → Hardware/LCMXO2/BOM/RAM2GS-BOM.LCMXO2HC.csv
View File

@ -9,7 +9,7 @@ H3 ,1, ,stdpads:PasteHole_1.1mm_PTH,,DNP - mounting hole,,
J1 ,1,Memory Expansion,stdpads:AppleIIgsMemoryExpansion_Edge,,DNP - edge connector,,
J2 ,1,JTAG,Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical,,DNP - test pad connector,,
R1 R7 R8 R9 R10 ,5,10k,stdpads:R_0603,,Any manufacturer's part is acceptable.,C25804,Uniroyal 0603WAF1002T5E
R2 R3 R5 R11 ,4,47,stdpads:R_0603,,Any manufacturer's part is acceptable.,C23182,Uniroyal 0603WAF470JT5E
R2 R3 R5 R11 R12 R13 ,4,47,stdpads:R_0603,,Any manufacturer's part is acceptable.,C23182,Uniroyal 0603WAF470JT5E
R4 ,1,0,stdpads:R_0805,,Any manufacturer's part is acceptable.,C17477,Uniroyal 0805W8F0000T5E
R6 ,1,180,stdpads:R_0805,,Any manufacturer's part is acceptable.,C25270,Uniroyal 0805W8F1800T5E
U1 ,1,LCMXO2HC-TG100,stdpads:TQFP-100_14x14mm_P0.5mm,,,C1519051,"Lattice LCMXO2-640HC-4TG100C, Lattice LCMXO2-640HC-5TG100C, Lattice LCMXO2-640HC-6TG100C, Lattice LCMXO2-640HC-4TG100I, Lattice LCMXO2-640HC-5TG100I, Lattice LCMXO2-640HC-6TG100I, Lattice LCMXO2-1200HC-4TG100C, Lattice LCMXO2-1200HC-5TG100C, Lattice LCMXO2-1200HC-6TG100C, Lattice LCMXO2-1200HC-4TG100I, Lattice LCMXO2-1200HC-5TG100I, Lattice LCMXO2-1200HC-6TG100I"
1 Reference Quantity Value Footprint Datasheet Notes LCSC Part Mfg. Part Numbers
9 J1 1 Memory Expansion stdpads:AppleIIgsMemoryExpansion_Edge DNP - edge connector
10 J2 1 JTAG Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical DNP - test pad connector
11 R1 R7 R8 R9 R10 5 10k stdpads:R_0603 Any manufacturer's part is acceptable. C25804 Uniroyal 0603WAF1002T5E
12 R2 R3 R5 R11 R2 R3 R5 R11 R12 R13 4 47 stdpads:R_0603 Any manufacturer's part is acceptable. C23182 Uniroyal 0603WAF470JT5E
13 R4 1 0 stdpads:R_0805 Any manufacturer's part is acceptable. C17477 Uniroyal 0805W8F0000T5E
14 R6 1 180 stdpads:R_0805 Any manufacturer's part is acceptable. C25270 Uniroyal 0805W8F1800T5E
15 U1 1 LCMXO2HC-TG100 stdpads:TQFP-100_14x14mm_P0.5mm C1519051 Lattice LCMXO2-640HC-4TG100C, Lattice LCMXO2-640HC-5TG100C, Lattice LCMXO2-640HC-6TG100C, Lattice LCMXO2-640HC-4TG100I, Lattice LCMXO2-640HC-5TG100I, Lattice LCMXO2-640HC-6TG100I, Lattice LCMXO2-1200HC-4TG100C, Lattice LCMXO2-1200HC-5TG100C, Lattice LCMXO2-1200HC-6TG100C, Lattice LCMXO2-1200HC-4TG100I, Lattice LCMXO2-1200HC-5TG100I, Lattice LCMXO2-1200HC-6TG100I

9197
Hardware/LCMXO2/Docs.kicad_sch Normal file
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4548
Hardware/LCMXO2/Docs.sch
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BIN
Hardware/LCMXO2/Documentation/RAM2GS.4201D.LCMXO2-Placement.pdf Normal file
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Hardware/LCMXO2/Documentation/RAM2GS.4201D.LCMXO2-Schematic.pdf Normal file
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569
Hardware/LCMXO2/RAM2GS-cache.lib
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@ -1,569 +0,0 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x05_Odd_Even
#
DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 300 50 H V C CNN
F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 150 -250 1 1 10 f
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_10 10 300 -200 150 L 50 50 1 1 P
X Pin_2 2 300 200 150 L 50 50 1 1 P
X Pin_3 3 -200 100 150 R 50 50 1 1 P
X Pin_4 4 300 100 150 L 50 50 1 1 P
X Pin_5 5 -200 0 150 R 50 50 1 1 P
X Pin_6 6 300 0 150 L 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 300 -100 150 L 50 50 1 1 P
X Pin_9 9 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x22_Counter_Clockwise
#
DEF Connector_Generic_Conn_02x22_Counter_Clockwise J 0 40 Y N 1 F N
F0 "J" 50 1100 50 H V C CNN
F1 "Connector_Generic_Conn_02x22_Counter_Clockwise" 50 -1200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1050 150 -1150 1 1 10 f
S 150 -1095 100 -1105 1 1 6 N
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 905 100 895 1 1 6 N
S 150 1005 100 995 1 1 6 N
X Pin_1 1 -200 1000 150 R 50 50 1 1 P
X Pin_10 10 -200 100 150 R 50 50 1 1 P
X Pin_11 11 -200 0 150 R 50 50 1 1 P
X Pin_12 12 -200 -100 150 R 50 50 1 1 P
X Pin_13 13 -200 -200 150 R 50 50 1 1 P
X Pin_14 14 -200 -300 150 R 50 50 1 1 P
X Pin_15 15 -200 -400 150 R 50 50 1 1 P
X Pin_16 16 -200 -500 150 R 50 50 1 1 P
X Pin_17 17 -200 -600 150 R 50 50 1 1 P
X Pin_18 18 -200 -700 150 R 50 50 1 1 P
X Pin_19 19 -200 -800 150 R 50 50 1 1 P
X Pin_2 2 -200 900 150 R 50 50 1 1 P
X Pin_20 20 -200 -900 150 R 50 50 1 1 P
X Pin_21 21 -200 -1000 150 R 50 50 1 1 P
X Pin_22 22 -200 -1100 150 R 50 50 1 1 P
X Pin_23 23 300 -1100 150 L 50 50 1 1 P
X Pin_24 24 300 -1000 150 L 50 50 1 1 P
X Pin_25 25 300 -900 150 L 50 50 1 1 P
X Pin_26 26 300 -800 150 L 50 50 1 1 P
X Pin_27 27 300 -700 150 L 50 50 1 1 P
X Pin_28 28 300 -600 150 L 50 50 1 1 P
X Pin_29 29 300 -500 150 L 50 50 1 1 P
X Pin_3 3 -200 800 150 R 50 50 1 1 P
X Pin_30 30 300 -400 150 L 50 50 1 1 P
X Pin_31 31 300 -300 150 L 50 50 1 1 P
X Pin_32 32 300 -200 150 L 50 50 1 1 P
X Pin_33 33 300 -100 150 L 50 50 1 1 P
X Pin_34 34 300 0 150 L 50 50 1 1 P
X Pin_35 35 300 100 150 L 50 50 1 1 P
X Pin_36 36 300 200 150 L 50 50 1 1 P
X Pin_37 37 300 300 150 L 50 50 1 1 P
X Pin_38 38 300 400 150 L 50 50 1 1 P
X Pin_39 39 300 500 150 L 50 50 1 1 P
X Pin_4 4 -200 700 150 R 50 50 1 1 P
X Pin_40 40 300 600 150 L 50 50 1 1 P
X Pin_41 41 300 700 150 L 50 50 1 1 P
X Pin_42 42 300 800 150 L 50 50 1 1 P
X Pin_43 43 300 900 150 L 50 50 1 1 P
X Pin_44 44 300 1000 150 L 50 50 1 1 P
X Pin_5 5 -200 600 150 R 50 50 1 1 P
X Pin_6 6 -200 500 150 R 50 50 1 1 P
X Pin_7 7 -200 400 150 R 50 50 1 1 P
X Pin_8 8 -200 300 150 R 50 50 1 1 P
X Pin_9 9 -200 200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED_Small_ALT
#
DEF Device_LED_Small_ALT D 0 10 N N 1 F N
F0 "D" -50 125 50 H V L CNN
F1 "Device_LED_Small_ALT" -175 -100 50 H V L CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 10 -30 -40 -30 40 N
P 2 0 1 0 40 0 -30 0 N
P 4 0 1 10 30 -40 -30 0 30 40 30 -40 F
P 5 0 1 0 0 30 -20 50 -10 50 -20 50 -20 40 N
P 5 0 1 0 20 50 0 70 10 70 0 70 0 60 N
X K 1 -100 0 70 R 50 50 1 1 P
X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_Logic_741G04GW
#
DEF GW_Logic_741G04GW U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Logic_741G04GW" 0 -250 50 H V C CNN
F2 "stdpads:SOT-353" 0 -300 50 H I C TNN
F3 "" 0 -200 60 H I C CNN
DRAW
S 200 -200 -200 200 0 1 10 f
X NC 1 -350 100 150 R 50 50 1 1 N
X A 2 -400 0 200 R 50 50 1 1 I
X GND 3 -400 -100 200 R 50 50 1 1 W
X Y 4 400 -100 200 L 50 50 1 1 O
X Vcc 5 400 100 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_Logic_74245
#
DEF GW_Logic_74245 U 0 40 Y Y 1 F N
F0 "U" 0 600 50 H V C CNN
F1 "GW_Logic_74245" 0 -600 50 H V C CNN
F2 "" 0 -650 50 H I C TNN
F3 "" 0 100 60 H I C CNN
DRAW
S -200 550 200 -550 0 1 10 f
X AtoB 1 -400 450 200 R 50 50 1 1 I
X GND 10 -400 -450 200 R 50 50 1 1 W
X B7 11 400 -450 200 L 50 50 1 1 B
X B6 12 400 -350 200 L 50 50 1 1 B
X B5 13 400 -250 200 L 50 50 1 1 B
X B4 14 400 -150 200 L 50 50 1 1 B
X B3 15 400 -50 200 L 50 50 1 1 B
X B2 16 400 50 200 L 50 50 1 1 B
X B1 17 400 150 200 L 50 50 1 1 B
X B0 18 400 250 200 L 50 50 1 1 B
X ~OE~ 19 400 350 200 L 50 50 1 1 I
X A0 2 -400 350 200 R 50 50 1 1 B
X Vcc 20 400 450 200 L 50 50 1 1 W
X A1 3 -400 250 200 R 50 50 1 1 B
X A2 4 -400 150 200 R 50 50 1 1 B
X A3 5 -400 50 200 R 50 50 1 1 B
X A4 6 -400 -50 200 R 50 50 1 1 B
X A5 7 -400 -150 200 R 50 50 1 1 B
X A6 8 -400 -250 200 R 50 50 1 1 B
X A7 9 -400 -350 200 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# GW_Logic_Oscillator_4P
#
DEF GW_Logic_Oscillator_4P U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Logic_Oscillator_4P" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -250 200 250 -100 0 1 10 f
X EN 1 -350 100 100 R 50 50 1 1 I
X GND 2 -350 0 100 R 50 50 1 1 W
X Output 3 350 0 100 L 50 50 1 1 O
X Vdd 4 350 100 100 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_PLD_LCMXO2-640-TG100
#
DEF GW_PLD_LCMXO2-640-TG100 U 0 40 Y Y 1 F N
F0 "U" 0 50 50 H V C CNN
F1 "GW_PLD_LCMXO2-640-TG100" 0 0 40 H V C TNN
F2 "stdpads:TQFP-100" 0 -200 40 H I C CNN
F3 "" 0 100 50 H I C CNN
DRAW
S -750 2200 750 -2200 1 1 10 f
X PL2A 1 -950 2000 200 R 50 50 1 1 B
X PL3D 10 -950 1300 200 R 50 50 1 1 B
X Vcc 100 500 2400 200 D 50 50 1 1 W
X PL5A/PCLKT3_1 12 -950 1200 200 R 50 50 1 1 B
X PL5B/PCLKC3_1 13 -950 1100 200 R 50 50 1 1 B
X PL5C 14 -950 1000 200 R 50 50 1 1 B
X PL5D 15 -950 900 200 R 50 50 1 1 B
X PL6A 16 -950 800 200 R 50 50 1 1 B
X PL6B 17 -950 700 200 R 50 50 1 1 B
X PL6C 18 -950 600 200 R 50 50 1 1 B
X PL6D 19 -950 500 200 R 50 50 1 1 B
X PL2B 2 -950 1900 200 R 50 50 1 1 B
X PL7A/PCLKT3_0 20 -950 400 200 R 50 50 1 1 B
X PL7B/PCLKC3_0 21 -950 300 200 R 50 50 1 1 B
X GND 22 -100 -2400 200 U 50 30 1 1 W
X VccIO3 23 -300 2400 200 D 50 50 1 1 W
X PL7C 24 -950 200 200 R 50 50 1 1 B
X PL7D 25 -950 100 200 R 50 50 1 1 B
X VccIO2 26 -200 2400 200 D 50 50 1 1 W
X PB4A/CSSPIN 27 -950 -100 200 R 50 50 1 1 B
X PB4B 28 -950 -200 200 R 50 50 1 1 B
X PB4C 29 -950 -300 200 R 50 50 1 1 B
X PL2C/PCLKT3_2 3 -950 1800 200 R 50 50 1 1 B
X PB4D 30 -950 -400 200 R 50 50 1 1 B
X PB6A/MCLK/CCLK 31 -950 -500 200 R 50 50 1 1 B
X PB6B/SO/SPISO 32 -950 -600 200 R 50 50 1 1 B
X GND 33 0 -2400 200 U 50 50 1 1 W
X PB6C/PCLKT2_0 34 -950 -700 200 R 50 50 1 1 B
X PB6D/PCLKC_0 35 -950 -800 200 R 50 50 1 1 B
X PB10A 36 -950 -900 200 R 50 50 1 1 B
X PB10B 37 -950 -1000 200 R 50 50 1 1 B
X PB10C/PCLKT2_1 38 -950 -1100 200 R 50 50 1 1 B
X PB10D/PCLKC2_1 39 -950 -1200 200 R 50 50 1 1 B
X PL2D/PCLKC3_2 4 -950 1700 200 R 50 50 1 1 B
X PB12A 40 -950 -1300 200 R 50 50 1 1 B
X PB12B 41 -950 -1400 200 R 50 50 1 1 B
X PB12C 42 -950 -1500 200 R 50 50 1 1 B
X PB12D 43 -950 -1600 200 R 50 50 1 1 B
X GND 44 100 -2400 200 U 50 50 1 1 W
X PB14A 45 -950 -1700 200 R 50 50 1 1 B
X VccIO2 46 -100 2400 200 D 50 50 1 1 W
X PB14 47 -950 -1800 200 R 50 50 1 1 B
X PB14C/SN 48 -950 -1900 200 R 50 50 1 1 B
X PB14D/SI/SISPI 49 -950 -2000 200 R 50 50 1 1 B
X VccIO3 5 -400 2400 200 D 50 50 1 1 W
X Vcc 50 400 2400 200 D 50 50 1 1 W
X PR7D 51 950 -2000 200 L 50 50 1 1 B
X PR7C 52 950 -1900 200 L 50 50 1 1 B
X PR7B 53 950 -1800 200 L 50 50 1 1 B
X PR7A 54 950 -1700 200 L 50 50 1 1 B
X VccIO1 55 0 2400 200 D 50 50 1 1 W
X GNDIO1 56 200 -2400 200 U 50 50 1 1 W
X PR6D 57 950 -1600 200 L 50 50 1 1 B
X PR6C 58 950 -1500 200 L 50 50 1 1 B
X PR6B 59 950 -1400 200 L 50 50 1 1 B
X GND 6 -200 -2400 200 U 50 30 1 1 W
X PR6A 60 950 -1300 200 L 50 50 1 1 B
X PCLKC1_0/PR5D 62 950 -1200 200 L 50 50 1 1 B
X PCLKT1_0/PR5C 63 950 -1100 200 L 50 50 1 1 B
X PR5B 64 950 -1000 200 L 50 50 1 1 B
X PR5A 65 950 -900 200 L 50 50 1 1 B
X PR3D 66 950 -800 200 L 50 50 1 1 B
X PR3C 67 950 -700 200 L 50 50 1 1 B
X PR3B 68 950 -600 200 L 50 50 1 1 B
X PR3A 69 950 -500 200 L 50 50 1 1 B
X PL3A 7 -950 1600 200 R 50 50 1 1 B
X PR2D 70 950 -400 200 L 50 50 1 1 B
X PR2C 71 950 -300 200 L 50 50 1 1 B
X GNDIO1 72 300 -2400 200 U 50 50 1 1 W
X VccIO1 73 100 2400 200 D 50 50 1 1 W
X PR2B 74 950 -200 200 L 50 50 1 1 B
X PR2A 75 950 -100 200 L 50 50 1 1 B
X DONE/PT11D 76 950 100 200 L 50 50 1 1 B
X ~INIT~/PT11C 77 950 200 200 L 50 50 1 1 B
X PT11A 78 950 300 200 L 50 50 1 1 B
X GND 79 400 -2400 200 U 50 50 1 1 W
X PL3B 8 -950 1500 200 R 50 50 1 1 B
X VccIO0 80 200 2400 200 D 50 50 1 1 W
X ~PROGRAM~/PT10D 81 950 400 200 L 50 50 1 1 B
X ~JTAGEN~/PT10C 82 950 500 200 L 50 50 1 1 B
X PT10B 83 950 600 200 L 50 50 1 1 B
X PT10A 84 950 700 200 L 50 50 1 1 B
X SDA/PCLKC0_0/PT9D 85 950 800 200 L 50 50 1 1 B
X SCL/PCLKT0_0/PT9C 86 950 900 200 L 50 50 1 1 B
X PT9B/PCLKC0_1 87 950 1000 200 L 50 50 1 1 B
X PT9A/PCLKT0_1 88 950 1100 200 L 50 50 1 1 B
X PL3C 9 -950 1400 200 R 50 50 1 1 B
X TMS/PT7D 90 950 1200 200 L 50 50 1 1 B
X TCK/PT7C 91 950 1300 200 L 50 50 1 1 B
X GND 92 500 -2400 200 U 50 30 1 1 W
X VccIO0 93 300 2400 200 D 50 50 1 1 W
X TDI/PT7B 94 950 1400 200 L 50 50 1 1 B
X TDO/PT7A 95 950 1500 200 L 50 50 1 1 B
X PT6D 96 950 1600 200 L 50 50 1 1 B
X PT6C 97 950 1700 200 L 50 50 1 1 B
X PT6B 98 950 1800 200 L 50 50 1 1 B
X PT6A 99 950 1900 200 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# GW_RAM_SDRAM-16Mx16-TSOP2-54
#
DEF GW_RAM_SDRAM-16Mx16-TSOP2-54 U 0 40 Y Y 1 F N
F0 "U" 0 1150 50 H V C CNN
F1 "GW_RAM_SDRAM-16Mx16-TSOP2-54" 0 0 50 V V C CNN
F2 "stdpads:Winbond_TSOPII-54" 0 -1650 50 H I C CIN
F3 "" 0 -250 50 H I C CNN
DRAW
S -300 1100 300 -1400 0 1 10 f
X VDD 1 -500 1000 200 R 50 50 1 1 W
X DQ5 10 500 500 200 L 50 50 1 1 B
X DQ6 11 500 400 200 L 50 50 1 1 B
X VSSQ 12 -500 -1300 200 R 50 50 1 1 W N
X DQ7 13 500 300 200 L 50 50 1 1 B
X VDD 14 -500 1000 200 R 50 50 1 1 W N
X DQML 15 500 -600 200 L 50 50 1 1 I
X ~WE~ 16 500 -1100 200 L 50 50 1 1 I
X ~CAS~ 17 500 -1200 200 L 50 50 1 1 I
X ~RAS~ 18 500 -1300 200 L 50 50 1 1 I
X ~CS~ 19 500 -1000 200 L 50 50 1 1 I
X DQ0 2 500 1000 200 L 50 50 1 1 B
X BA0 20 -500 -600 200 R 50 50 1 1 I
X BA1 21 -500 -700 200 R 50 50 1 1 I
X A10 22 -500 -300 200 R 50 50 1 1 I
X A0 23 -500 700 200 R 50 50 1 1 I
X A1 24 -500 600 200 R 50 50 1 1 I
X A2 25 -500 500 200 R 50 50 1 1 I
X A3 26 -500 400 200 R 50 50 1 1 I
X VDD 27 -500 1000 200 R 50 50 1 1 W N
X VSS 28 -500 -1200 200 R 50 50 1 1 W
X A4 29 -500 300 200 R 50 50 1 1 I
X VDDQ 3 -500 900 200 R 50 50 1 1 W
X A5 30 -500 200 200 R 50 50 1 1 I
X A6 31 -500 100 200 R 50 50 1 1 I
X A7 32 -500 0 200 R 50 50 1 1 I
X A8 33 -500 -100 200 R 50 50 1 1 I
X A9 34 -500 -200 200 R 50 50 1 1 I
X A11 35 -500 -400 200 R 50 50 1 1 I
X A12 36 -500 -500 200 R 50 50 1 1 I
X CKE 37 -500 -900 200 R 50 50 1 1 I
X CLK 38 -500 -1000 200 R 50 50 1 1 I
X DQMH 39 500 -700 200 L 50 50 1 1 I
X DQ1 4 500 900 200 L 50 50 1 1 B
X VSS 41 -500 -1200 200 R 50 50 1 1 W N
X DQ8 42 500 200 200 L 50 50 1 1 B
X VDDQ 43 -500 900 200 R 50 50 1 1 W N
X DQ9 44 500 100 200 L 50 50 1 1 B
X DQ10 45 500 0 200 L 50 50 1 1 B
X VSSQ 46 -500 -1300 200 R 50 50 1 1 W N
X DQ11 47 500 -100 200 L 50 50 1 1 B
X DQ12 48 500 -200 200 L 50 50 1 1 B
X VDDQ 49 -500 900 200 R 50 50 1 1 W N
X DQ2 5 500 800 200 L 50 50 1 1 B
X DQ13 50 500 -300 200 L 50 50 1 1 B
X DQ14 51 500 -400 200 L 50 50 1 1 B
X VSSQ 52 -500 -1300 200 R 50 50 1 1 W N
X DQ15 53 500 -500 200 L 50 50 1 1 B
X VSS 54 -500 -1200 200 R 50 50 1 1 W N
X VSSQ 6 -500 -1300 200 R 50 50 1 1 W
X DQ3 7 500 700 200 L 50 50 1 1 B
X DQ4 8 500 600 200 L 50 50 1 1 B
X VDDQ 9 -500 900 200 R 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole
#
DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
F0 "H" 0 200 50 H V C CNN
F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*
$ENDFPLIST
DRAW
C 0 0 50 0 1 50 N
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole_Pad
#
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
F0 "H" 0 250 50 H V C CNN
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*Pad*
$ENDFPLIST
DRAW
C 0 50 50 0 1 50 N
X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Regulator_Linear_AP2127K-1.2
#
DEF Regulator_Linear_AP2127K-1.2 U 0 10 Y Y 1 F N
F0 "U" -200 225 50 H V L CNN
F1 "Regulator_Linear_AP2127K-1.2" 0 225 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23-5" 0 325 50 H I C CNN
F3 "" 0 100 50 H I C CNN
ALIAS AP2204K-1.8 AP2204K-2.5 AP2204K-2.8 AP2204K-3.0 AP2204K-3.3 AP2204K-5.0 AP2127K-1.0 AP2127K-1.2 AP2127K-1.5 AP2127K-1.8 AP2127K-2.5 AP2127K-2.8 AP2127K-3.0 AP2127K-3.3 AP2127K-4.2 AP2127K-4.75 AP2112K-1.2 AP2112K-1.8 AP2112K-2.5 AP2112K-2.6 AP2112K-3.3
$FPLIST
SOT?23?5*
$ENDFPLIST
DRAW
S -200 175 200 -200 0 1 10 f
X VIN 1 -300 100 100 R 50 50 1 1 W
X GND 2 0 -300 100 U 50 50 1 1 W
X EN 3 -300 0 100 R 50 50 1 1 I
X NC 4 200 0 100 L 50 50 1 1 N N
X VOUT 5 300 100 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# Regulator_Linear_LD1117S33TR_SOT223
#
DEF Regulator_Linear_LD1117S33TR_SOT223 U 0 10 Y Y 1 F N
F0 "U" -150 125 50 H V C CNN
F1 "Regulator_Linear_LD1117S33TR_SOT223" 0 125 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 200 50 H I C CNN
F3 "" 100 -250 50 H I C CNN
ALIAS AP1117-18 AP1117-25 AP1117-33 AP1117-50 LD1117S33TR_SOT223 LD1117S12TR_SOT223 LD1117S18TR_SOT223 LD1117S25TR_SOT223 LD1117S50TR_SOT223 NCP1117-12_SOT223 NCP1117-1.5_SOT223 NCP1117-1.8_SOT223 NCP1117-2.0_SOT223 NCP1117-2.5_SOT223 NCP1117-2.85_SOT223 NCP1117-3.3_SOT223 NCP1117-5.0_SOT223 AMS1117-1.5 AMS1117-1.8 AMS1117-2.5 AMS1117-2.85 AMS1117-3.3 AMS1117-5.0
$FPLIST
SOT?223*TabPin2*
$ENDFPLIST
DRAW
S -200 -200 200 75 0 1 10 f
X GND 1 0 -300 100 U 50 50 1 1 W
X VO 2 300 0 100 L 50 50 1 1 w
X VI 3 -300 0 100 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# power_+1V2
#
DEF power_+1V2 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+1V2" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +1V2 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3V3
#
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

BIN
Hardware/LCMXO2/RAM2GS.4201D.LCMXO2-gerber.zip
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BIN
Hardware/LCMXO2/RAM2GS.4201D.LCMXO2-stencil.zip
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90651
Hardware/LCMXO2/RAM2GS.kicad_pcb
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2
Hardware/LCMXO2/RAM2GS.kicad_prl
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@ -61,7 +61,7 @@
34,
35,
36,
39,
37,
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],
"visible_layers": "fffffff_ffffffff",

200
Hardware/LCMXO2/RAM2GS.kicad_pro
View File

@ -4,83 +4,203 @@
"design_settings": {
"defaults": {
"board_outline_line_width": 0.15,
"copper_line_width": 0.2,
"copper_line_width": 0.15239999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": true,
"courtyard_line_width": 0.05,
"other_line_width": 0.15,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": true,
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 0.95,
"width": 0.7
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": true
"silk_text_upright": false,
"zones": {
"min_clearance": 0.15239999999999998
}
},
"diff_pair_dimensions": [
{
"gap": 0.25,
"via_gap": 0.25,
"width": 0.2
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "error",
"courtyards_overlap": "warning",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "error",
"extra_footprint": "error",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "ignore",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "error",
"net_conflict": "error",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "warning",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"max_error": 0.005,
"min_clearance": 0.15,
"min_connection": 0.12,
"min_copper_edge_clearance": 0.4064,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.254,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_through_hole_diameter": 0.2,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.15,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.5,
"solder_mask_clearance": 0.075,
"solder_mask_min_width": 0.09999999999999999,
"solder_paste_clearance": -0.03809999999999999,
"solder_paste_margin_ratio": 0.0
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.15,
0.2,
0.254,
0.25,
0.3,
0.35,
0.4,
0.45,
0.5,
0.508,
0.6,
0.762,
0.8,
0.85,
0.895,
0.9,
1.0,
1.2,
1.27,
1.524
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.5,
"drill": 0.2
"drill": 0.3
},
{
"diameter": 0.6,
"drill": 0.3
},
{
"diameter": 0.762,
"drill": 0.381
},
{
"diameter": 0.8,
"drill": 0.4
@ -93,7 +213,8 @@
"diameter": 1.524,
"drill": 0.762
}
]
],
"zones_allow_external_fillets": false
},
"layer_presets": [],
"viewports": []
@ -325,7 +446,7 @@
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
@ -335,8 +456,8 @@
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"track_width": 0.15,
"via_diameter": 0.5,
"via_drill": 0.3,
"wire_width": 6
}
@ -394,6 +515,15 @@
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [],
"sheets": [
[
"0fd24f5c-4245-40b1-8698-6faceb999cd9",
""
],
[
"00000000-0000-0000-0000-00005ee767bf",
"Docs"
]
],
"text_variables": {}
}

7579
Hardware/LCMXO2/RAM2GS.kicad_sch Normal file
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275
Hardware/LCMXO2/RAM2GS.pro
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@ -1,275 +0,0 @@
update=Saturday, August 21, 2021 at 01:52:48 AM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=RAM2GS.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.15
MinViaDiameter=0.5
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.15
TrackWidth2=0.2
TrackWidth3=0.254
TrackWidth4=0.3
TrackWidth5=0.4
TrackWidth6=0.45
TrackWidth7=0.5
TrackWidth8=0.508
TrackWidth9=0.6
TrackWidth10=0.762
TrackWidth11=0.8
TrackWidth12=0.85
TrackWidth13=0.895
TrackWidth14=0.9
TrackWidth15=1
TrackWidth16=1.2
TrackWidth17=1.27
TrackWidth18=1.524
ViaDiameter1=0.5
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.762
ViaDrill3=0.381
ViaDiameter4=0.8
ViaDrill4=0.4
ViaDiameter5=1
ViaDrill5=0.5
ViaDiameter6=1.524
ViaDrill6=0.762
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.075
SolderMaskMinWidth=0.09999999999999999
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=1
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.15
TrackWidth=0.15
ViaDiameter=0.5
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

2357
Hardware/LCMXO2/RAM2GS.sch
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22
Hardware/LCMXO2/gerber/RAM2GS-BOM. LCMXO2HE.csv
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@ -1,22 +0,0 @@
Reference, Quantity, Value, Footprint, Datasheet, Notes, LCSC Part, Mfg. Part Numbers
C30 ,1,15p,stdpads:C_0603,,"10V or higher. Any manufacturer's part is acceptable but Samsung, Murata, Yageo preferred.",C1644,Samsung CL10C150JB8NNNC
C1 C2 C3 C4 C26 ,5,10u,stdpads:C_0805,,"10V or higher. Any manufacturer's part is acceptable but Samsung, Murata, Yageo preferred.",C15850,Samsung CL21A106KAYNNNE
C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C27 C28 C29 ,24,2u2,stdpads:C_0603,,"10V or higher. Any manufacturer's part is acceptable but Samsung, Murata, Yageo preferred.",C23630,Samsung CL10A225KO8NNNC
D1 ,1,White,stdpads:LED_0805,,Any manufacturer's part is acceptable.,C34499,Hubei Kento C34499
FID1 FID2 FID3 FID4 ,4,Fiducial,stdpads:Fiducial,,DNP - SMT vision system fiducial,,
H1 H2 H4 H5 ,4, ,stdpads:PasteHole_1.152mm_NPTH,,DNP - mounting hole for solder paste printing,,
H3 ,1, ,stdpads:PasteHole_1.1mm_PTH,,DNP - mounting hole,,
J1 ,1,Memory Expansion,stdpads:AppleIIgsMemoryExpansion_Edge,,DNP - edge connector,,
J2 ,1,JTAG,Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical,,DNP - test pad connector,,
R1 R7 R8 R9 R10 ,5,10k,stdpads:R_0603,,Any manufacturer's part is acceptable.,C25804,Uniroyal 0603WAF1002T5E
R2 R3 R5 R11 ,4,47,stdpads:R_0603,,Any manufacturer's part is acceptable.,C23182,Uniroyal 0603WAF470JT5E
R4 ,1,DNP,stdpads:R_0805,,,,
R6 ,1,180,stdpads:R_0805,,Any manufacturer's part is acceptable.,C25270,Uniroyal 0805W8F1800T5E
U1 ,1,LCMXO2HE-TG100,stdpads:TQFP-100_14x14mm_P0.5mm,,,C1519051,"Lattice LCMXO2-640HE-4TG100C, Lattice LCMXO2-640HE-5TG100C, Lattice LCMXO2-640HE-6TG100C, Lattice LCMXO2-640HE-4TG100I, Lattice LCMXO2-640HE-5TG100I, Lattice LCMXO2-640HE-6TG100I, Lattice LCMXO2-1200HE-4TG100C, Lattice LCMXO2-1200HE-5TG100C, Lattice LCMXO2-1200HE-6TG100C, Lattice LCMXO2-1200HE-4TG100I, Lattice LCMXO2-1200HE-5TG100I, Lattice LCMXO2-1200HE-6TG100I"
U9 U10 ,2,74LVC1G04GW,stdpads:SOT-353,,Most 74LVC1G04 or 74AHC1G04 in SOT-353 package is acceptable.,C10237,"NXP 74LVC1G04GW, TI SN74LVC1G04DCK"
U11 ,1,AP2127K-1.2TRG1,stdpads:SOT-23-5,,Most 1.2V regulator in SOT-23-5 package is acceptable.,C151376,"Diodes AP2127K-1.2TRG1, Torex XC6228D122VR"
U2 ,1,W9812G6KH-6,stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm,,Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.,C62379,"Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G"
U3 ,1,60M,stdpads:Crystal_SMD_7050-4Pin_7.0x5.0mm_SiTime,,Most 60-62.5 MHz 3.3V crystal oscillator or silicon oscillator is acceptable. Do not use crystal resonator or ceramic resonator.,C26255,"SiTime SIT1602AI-82-33E-60.000000Y, Shenzhen SCTF S7D60.000000B20F30T, Taiten OCETGLJTNF-60MHZ"
U4 ,1,74AHCT245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,Most 74AHCT245 in TSSOP-20 package is acceptable.,C173388,"NXP 74AHCT245PW, TI SN74AHCT245PW"
U5 U6 U7 ,3,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.,C6082,"NXP 74LVC245APW, TI SN74LVC245APW"
U8 ,1,AZ1117CH-3.3TRG1,stdpads:SOT-223,,Most 1117-type 3.3V regulator in SOT-223 package is acceptable.,C92102,"Diodes AZ1117CH-3.3TRG1, Diodes AZ1117EH-3.3TRG1"
1 Reference Quantity Value Footprint Datasheet Notes LCSC Part Mfg. Part Numbers
2 C30 1 15p stdpads:C_0603 10V or higher. Any manufacturer's part is acceptable but Samsung, Murata, Yageo preferred. C1644 Samsung CL10C150JB8NNNC
3 C1 C2 C3 C4 C26 5 10u stdpads:C_0805 10V or higher. Any manufacturer's part is acceptable but Samsung, Murata, Yageo preferred. C15850 Samsung CL21A106KAYNNNE
4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C27 C28 C29 24 2u2 stdpads:C_0603 10V or higher. Any manufacturer's part is acceptable but Samsung, Murata, Yageo preferred. C23630 Samsung CL10A225KO8NNNC
5 D1 1 White stdpads:LED_0805 Any manufacturer's part is acceptable. C34499 Hubei Kento C34499
6 FID1 FID2 FID3 FID4 4 Fiducial stdpads:Fiducial DNP - SMT vision system fiducial
7 H1 H2 H4 H5 4 stdpads:PasteHole_1.152mm_NPTH DNP - mounting hole for solder paste printing
8 H3 1 stdpads:PasteHole_1.1mm_PTH DNP - mounting hole
9 J1 1 Memory Expansion stdpads:AppleIIgsMemoryExpansion_Edge DNP - edge connector
10 J2 1 JTAG Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical DNP - test pad connector
11 R1 R7 R8 R9 R10 5 10k stdpads:R_0603 Any manufacturer's part is acceptable. C25804 Uniroyal 0603WAF1002T5E
12 R2 R3 R5 R11 4 47 stdpads:R_0603 Any manufacturer's part is acceptable. C23182 Uniroyal 0603WAF470JT5E
13 R4 1 DNP stdpads:R_0805
14 R6 1 180 stdpads:R_0805 Any manufacturer's part is acceptable. C25270 Uniroyal 0805W8F1800T5E
15 U1 1 LCMXO2HE-TG100 stdpads:TQFP-100_14x14mm_P0.5mm C1519051 Lattice LCMXO2-640HE-4TG100C, Lattice LCMXO2-640HE-5TG100C, Lattice LCMXO2-640HE-6TG100C, Lattice LCMXO2-640HE-4TG100I, Lattice LCMXO2-640HE-5TG100I, Lattice LCMXO2-640HE-6TG100I, Lattice LCMXO2-1200HE-4TG100C, Lattice LCMXO2-1200HE-5TG100C, Lattice LCMXO2-1200HE-6TG100C, Lattice LCMXO2-1200HE-4TG100I, Lattice LCMXO2-1200HE-5TG100I, Lattice LCMXO2-1200HE-6TG100I
16 U9 U10 2 74LVC1G04GW stdpads:SOT-353 Most 74LVC1G04 or 74AHC1G04 in SOT-353 package is acceptable. C10237 NXP 74LVC1G04GW, TI SN74LVC1G04DCK
17 U11 1 AP2127K-1.2TRG1 stdpads:SOT-23-5 Most 1.2V regulator in SOT-23-5 package is acceptable. C151376 Diodes AP2127K-1.2TRG1, Torex XC6228D122VR
18 U2 1 W9812G6KH-6 stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable. C62379 Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G
19 U3 1 60M stdpads:Crystal_SMD_7050-4Pin_7.0x5.0mm_SiTime Most 60-62.5 MHz 3.3V crystal oscillator or silicon oscillator is acceptable. Do not use crystal resonator or ceramic resonator. C26255 SiTime SIT1602AI-82-33E-60.000000Y, Shenzhen SCTF S7D60.000000B20F30T, Taiten OCETGLJTNF-60MHZ
20 U4 1 74AHCT245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm Most 74AHCT245 in TSSOP-20 package is acceptable. C173388 NXP 74AHCT245PW, TI SN74AHCT245PW
21 U5 U6 U7 3 74LVC245APW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable. C6082 NXP 74LVC245APW, TI SN74LVC245APW
22 U8 1 AZ1117CH-3.3TRG1 stdpads:SOT-223 Most 1117-type 3.3V regulator in SOT-223 package is acceptable. C92102 Diodes AZ1117CH-3.3TRG1, Diodes AZ1117EH-3.3TRG1

24541
Hardware/LCMXO2/gerber/RAM2GS-B_Cu.gbl
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822
Hardware/LCMXO2/gerber/RAM2GS-B_SilkS.gbo
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@ -1,822 +0,0 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.10-1-10_14)*
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G01*
X65696500Y-131537000D01*
G75*
G02*
X66115000Y-131955500I0J-418500D01*
G01*
X66115000Y-138608500D01*
G75*
G02*
X65696500Y-139027000I-418500J0D01*
G01*
X64859500Y-139027000D01*
G75*
G02*
X64441000Y-138608500I0J418500D01*
G01*
G37*
G36*
G01*
X61901000Y-138608500D02*
X61901000Y-131955500D01*
G75*
G02*
X62319500Y-131537000I418500J0D01*
G01*
X63156500Y-131537000D01*
G75*
G02*
X63575000Y-131955500I0J-418500D01*
G01*
X63575000Y-138608500D01*
G75*
G02*
X63156500Y-139027000I-418500J0D01*
G01*
X62319500Y-139027000D01*
G75*
G02*
X61901000Y-138608500I0J418500D01*
G01*
G37*
G36*
G01*
X59361000Y-138608500D02*
X59361000Y-131955500D01*
G75*
G02*
X59779500Y-131537000I418500J0D01*
G01*
X60616500Y-131537000D01*
G75*
G02*
X61035000Y-131955500I0J-418500D01*
G01*
X61035000Y-138608500D01*
G75*
G02*
X60616500Y-139027000I-418500J0D01*
G01*
X59779500Y-139027000D01*
G75*
G02*
X59361000Y-138608500I0J418500D01*
G01*
G37*
G36*
G01*
X56821000Y-138608500D02*
X56821000Y-131955500D01*
G75*
G02*
X57239500Y-131537000I418500J0D01*
G01*
X58076500Y-131537000D01*
G75*
G02*
X58495000Y-131955500I0J-418500D01*
G01*
X58495000Y-138608500D01*
G75*
G02*
X58076500Y-139027000I-418500J0D01*
G01*
X57239500Y-139027000D01*
G75*
G02*
X56821000Y-138608500I0J418500D01*
G01*
G37*
D15*
X106617090Y-100965987D03*
X103024987Y-104558090D03*
X98983872Y-100516974D03*
X102575974Y-96924872D03*
D16*
X100779923Y-98720923D03*
X105449656Y-104827497D03*
X106886497Y-103390656D03*
D17*
X110998000Y-130175000D03*
D14*
X48514000Y-93726000D03*
X102870000Y-93726000D03*
X111506000Y-115189000D03*
M02*

466
Hardware/LCMXO2/gerber/RAM2GS-B_Silkscreen.gbo Normal file
View File

@ -0,0 +1,466 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-11-03T04:24:27-04:00*
G04 #@! TF.ProjectId,RAM2GS,52414d32-4753-42e6-9b69-6361645f7063,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Legend,Bot*
G04 #@! TF.FilePolarity,Positive*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-11-03 04:24:27*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 Aperture macros list*
%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10C,0.200000*%
%ADD11C,0.203200*%
%ADD12C,0.190500*%
%ADD13C,0.000000*%
%ADD14RoundRect,0.457200X-0.381000X-3.289000X0.381000X-3.289000X0.381000X3.289000X-0.381000X3.289000X0*%
%ADD15C,2.152400*%
%ADD16C,2.527300*%
%ADD17C,1.143000*%
%ADD18C,1.448000*%
G04 APERTURE END LIST*
D10*
X48895000Y-119634000D02*
X47625000Y-119634000D01*
X47625000Y-119634000D02*
X48006000Y-120015000D01*
X47625000Y-119634000D02*
X48006000Y-119253000D01*
X47625000Y-105537000D02*
X48006000Y-105918000D01*
X47625000Y-105537000D02*
X48006000Y-105156000D01*
X48895000Y-105537000D02*
X47625000Y-105537000D01*
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X49276000Y-102171500D01*
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X47371000Y-103251000D01*
X49276000Y-102171500D02*
X49276000Y-104330500D01*
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X47704526Y-107236381D01*
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X48732621Y-107962095D01*
X48732621Y-107962095D02*
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X48248811Y-108022571D02*
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X48732621Y-108627333D02*
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D11*
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D12*
X48876107Y-103250999D02*
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X48914812Y-103289704D02*
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X48179421Y-103289704D02*
X48643878Y-103250999D01*
X48643878Y-103250999D02*
X48140716Y-103250999D01*
%LPC*%
D13*
G36*
X113538000Y-139446000D02*
G01*
X113030000Y-139954000D01*
X55626000Y-139954000D01*
X55118000Y-139446000D01*
X55118000Y-132080000D01*
X113538000Y-132080000D01*
X113538000Y-139446000D01*
G37*
D14*
X110998000Y-135282000D03*
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X65278000Y-135282000D03*
X62738000Y-135282000D03*
X60198000Y-135282000D03*
X57658000Y-135282000D03*
D15*
X110998000Y-130175000D03*
D16*
X102575974Y-96924872D03*
D17*
X100779923Y-98720923D03*
D16*
X98983872Y-100516974D03*
X106617090Y-100965987D03*
X103024987Y-104558090D03*
D17*
X106886497Y-103390656D03*
X105449656Y-104827497D03*
D18*
X48514000Y-93726000D03*
X102870000Y-93726000D03*
X48514000Y-129540000D03*
X111506000Y-115189000D03*
M02*

70
Hardware/LCMXO2/gerber/RAM2GS-Edge_Cuts.gm1
View File

@ -1,11 +1,11 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.10-1-10_14)*
G04 #@! TF.CreationDate,2021-10-29T05:10:38-04:00*
G04 #@! TF.ProjectId,RAM2GS,52414d32-4753-42e6-9b69-6361645f7063,2.0*
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-11-03T04:24:27-04:00*
G04 #@! TF.ProjectId,RAM2GS,52414d32-4753-42e6-9b69-6361645f7063,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.10-1-10_14)) date 2021-10-29 05:10:38*
G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-11-03 04:24:27*
%MOMM*%
%LPD*%
G01*
@ -15,48 +15,48 @@ G04 #@! TA.AperFunction,Profile*
G04 #@! TD*
G04 APERTURE END LIST*
D10*
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G75*
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G03*
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G01*
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G75*
G02*
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G03*
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G01*
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G75*
G03*
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G01*
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G75*
G02*
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G03*
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G01*
X113284000Y-139192000D02*
X113284000Y-101346000D01*
X55372000Y-139192000D02*
G75*
G03*
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G01*
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X104648000Y-91694000D01*
X104648000Y-91694000D02*
G75*
G03*
X103124000Y-91186000I-1524000J-2032000D01*
G01*
X112776000Y-99822000D02*
X104648000Y-91694000D01*
X112776000Y-99822000D02*
G75*
G02*
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G01*
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X113284000Y-101346000D01*
X48514000Y-132080000D02*
G75*
G02*
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G01*
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X55372000Y-139192000D02*
X55372000Y-132080000D01*
X112776000Y-139700000D02*
X55880000Y-139700000D01*
M02*

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