Documentation update

Docs.sch

@@ -4,10 +4,10 @@ EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
 Sheet 2 2
-Title ""
-Date ""
-Rev ""
-Comp ""
+Title "GW4201D (RAM2GS II)"
+Date "2020-08-02"
+Rev "1.0"
+Comp "Garrett's Workshop"
 Comment1 ""
 Comment2 ""
 Comment3 ""

Documentation/Description.txt

@@ -1,63 +0,0 @@
-RAM2GS II (GW4201D) expands the Apple IIgs's 
-fast memory to 8 MB. 
-
-
-Low-Power, SDRAM-Based Design
-----------------------------------------
-Thanks to a modern, low-power design, 
-RAM2GS II uses a maximum of 0.15 watts when idle
-(30 mA @ 5V) and 0.3W in active use (60 mA @ 5V). 
-Unlike other IIgs expansion RAM cards, which are 
-built with vintage asynchronous DRAM chips, 
-RAM2GS II uses modern SDRAM. This design allows for 
-low power consumption and improved reliability 
-over other memory cards using 15+ year old chips. 
-
-
-Small Size, Low-Profile
-----------------------------------------
-RAM2GS II features a small board outline and is the 
-thinnest Apple IIgs expansion memory card ever produced, 
-at under 4mm thin. Small and thin dimensions improve 
-the mechanical compatibility between RAM2GS II and 
-peripheral cards installed into the IIgs's Slot 7.
-
-
-Adjustable Capacity, Highly Compatible
-----------------------------------------
-The Apple IIgs can utilize up to 8 MB of fast memory, 
-but due to limitations of the Apple IIgs hardware, 
-not all 8 MB is considered "DMA-compatible."
-Only 4 MB of the 8 MB provided by an expansion RAM 
-card such as the RAM2GS II is DMA-compatible, 
-and peripheral cards which use DMA are 
-not able to access expansion memory beyond 4 MB. 
-RAM2GS II implements an adjustable capacity 
-feature, allowing the user to select between 
-fully DMA-compatible 4 MB capacity, or
-partially DMA-compatible 8MB capacity.
-Capacity settings can be set temporarily 
-or saved in nonvolatile memory. 
-The capacity adjustment utility is available on 
-_RAM2GS II's support page_.
-
-
-Ecologically Friendly, Gold-Plated PCB
-----------------------------------------
-RAM2GS II features a lead-free, ENIG gold-plated,
-4-layer PCB and is fully EU RoHS-compliant. 
-All units are tested extensively before shipment. 
-Only new parts are used to build RAM2GS II, 
-and all RAM2GS II cards are manufactured in our 
-semi-automated facility in Columbus, Ohio, 
-in the United States. 
-
-
-Open-Source Design
-----------------------------------------
-RAM2GS II's design is fully open-source. 
-The schematics, board layouts, CPLD firmware, 
-and utility software are all freely available 
-for commercial and noncommercial use. 
-To download the design files, visit the 
-_Garrett's Workshop GitHub page_. 

RAM2GS.kicad_pcb

@@ -10,6 +10,13 @@
   )
 
   (page A4)
+  (title_block
+    (title "GW4203D (RAM2GS II)")
+    (date 2020-08-02)
+    (rev 1.0)
+    (company "Garrett's Workshop")
+  )
+
   (layers
     (0 F.Cu signal)
     (1 In1.Cu power)
@@ -437,7 +444,7 @@
     (fp_text reference U9 (at 0 0 90) (layer F.Fab)
       (effects (font (size 0.254 0.254) (thickness 0.0635)))
     )
-    (fp_text value 74LVC1G04GW (at 0.35 0 90) (layer F.Fab)
+    (fp_text value 74LVC1G04 (at 0.35 0 90) (layer F.Fab)
       (effects (font (size 0.1905 0.1905) (thickness 0.047625)))
     )
     (fp_line (start 1.6 1.3) (end -1.6 1.3) (layer F.CrtYd) (width 0.05))
@@ -478,7 +485,7 @@
     (fp_text reference U10 (at 0 0 90) (layer F.Fab)
       (effects (font (size 0.254 0.254) (thickness 0.0635)))
     )
-    (fp_text value 74LVC1G04GW (at 0.35 0 90) (layer F.Fab)
+    (fp_text value 74LVC1G04 (at 0.35 0 90) (layer F.Fab)
       (effects (font (size 0.1905 0.1905) (thickness 0.047625)))
     )
     (fp_line (start 1.6 1.3) (end -1.6 1.3) (layer F.CrtYd) (width 0.05))
@@ -568,7 +575,7 @@
     (fp_text reference RN2 (at 0 0 90) (layer F.Fab)
       (effects (font (size 0.254 0.254) (thickness 0.0635)))
     )
-    (fp_text value 4x47 (at 0.3 0 90) (layer F.Fab)
+    (fp_text value 4x30 (at 0.3 0 90) (layer F.Fab)
       (effects (font (size 0.1905 0.1905) (thickness 0.047625)))
     )
     (fp_text user %R (at 0 0 270) (layer F.SilkS) hide
@@ -617,7 +624,7 @@
     (fp_text reference RN3 (at 0 0 90) (layer F.Fab)
       (effects (font (size 0.254 0.254) (thickness 0.0635)))
     )
-    (fp_text value 4x47 (at 0.3 0 90) (layer F.Fab)
+    (fp_text value 4x30 (at 0.3 0 90) (layer F.Fab)
       (effects (font (size 0.1905 0.1905) (thickness 0.047625)))
     )
     (fp_text user %R (at 0 0 270) (layer F.SilkS) hide
@@ -666,7 +673,7 @@
     (fp_text reference RN4 (at 0 0) (layer F.Fab)
       (effects (font (size 0.254 0.254) (thickness 0.0635)))
     )
-    (fp_text value 4x47 (at 0.3 0) (layer F.Fab)
+    (fp_text value 4x30 (at 0.3 0) (layer F.Fab)
       (effects (font (size 0.1905 0.1905) (thickness 0.047625)))
     )
     (fp_text user %R (at 0 0 180) (layer F.SilkS) hide
@@ -715,7 +722,7 @@
     (fp_text reference RN5 (at 0 0) (layer F.Fab)
       (effects (font (size 0.254 0.254) (thickness 0.0635)))
     )
-    (fp_text value 4x47 (at 0.3 0) (layer F.Fab)
+    (fp_text value 4x30 (at 0.3 0) (layer F.Fab)
       (effects (font (size 0.1905 0.1905) (thickness 0.047625)))
     )
     (fp_text user %R (at 0 0 180) (layer F.SilkS) hide
@@ -2367,7 +2374,7 @@
     )
   )
 
-  (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5EE296B4) (tstamp 5E96A451)
+  (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5EE296B4) (tstamp 5F273F52)
     (at 77.025 125.45 90)
     (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)")
     (tags "SSOP 0.65")
@@ -2896,7 +2903,7 @@
   (module stdpads:R_0805 (layer F.Cu) (tedit 5F027DD1) (tstamp 5EED1618)
     (at 71.7 125.65)
     (tags resistor)
-    (path /5EED7F16)
+    (path /5F2CC469)
     (solder_mask_margin 0.05)
     (solder_paste_margin -0.025)
     (attr smd)

RAM2GS.pro

@@ -1,4 +1,4 @@
-update=Sunday, July 05, 2020 at 10:26:01 PM
+update=Sunday, August 02, 2020 at 06:25:20 PM
 version=1
 last_client=kicad
 [general]
@@ -12,16 +12,6 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=Pcbnew
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1
 [pcbnew]
 version=1
 PageLayoutDescrFile=
@@ -272,3 +262,13 @@ uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1