RAM2GS/CPLD/MAXV/output_files
Zane Kaminski c103137bfc RC2
2023-09-30 04:50:51 -04:00
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RAM2GS.asm.rpt RC2 2023-09-30 04:50:51 -04:00
RAM2GS.done RC2 2023-09-30 04:50:51 -04:00
RAM2GS.fit.rpt RC2 2023-09-30 04:50:51 -04:00
RAM2GS.fit.smsg MAX, MachXO, MachXO2 working 2023-08-20 07:10:11 -04:00
RAM2GS.fit.summary RC2 2023-09-30 04:50:51 -04:00
RAM2GS.flow.rpt RC2 2023-09-30 04:50:51 -04:00
RAM2GS.jdi RC2 2023-09-30 04:50:51 -04:00
RAM2GS.map.rpt RC2 2023-09-30 04:50:51 -04:00
RAM2GS.map.smsg RC2 2023-09-30 04:50:51 -04:00
RAM2GS.map.summary RC2 2023-09-30 04:50:51 -04:00
RAM2GS.pin Gate LED with Ready signal 2023-09-29 15:18:46 -04:00
RAM2GS.pof Gate LED with Ready signal 2023-09-29 15:18:46 -04:00
RAM2GS.sld MAX, MachXO, MachXO2 working 2023-08-20 07:10:11 -04:00
RAM2GS.sta.rpt RC2 2023-09-30 04:50:51 -04:00
RAM2GS.sta.summary Gate LED with Ready signal 2023-09-29 15:18:46 -04:00