Merge pull request #1 from a2-4am/patch-1

fix register confusion if interleave=0
2023-08-30 16:39:27 -07:00 · 2023-08-30 16:39:27 -07:00 · b751af7746
parent 017a7b214b a41a656906
commit b751af7746
1 changed files with 2 additions and 0 deletions
--- a/0BOOT.S
+++ b/0BOOT.S
@ -225,6 +225,8 @@ read
 !if interleave=1 {
        tax
        ldy     $100, x
+} else {
+        tay
 }
        sty     <(sector+1)     ;store index for later
        ldx     <addrtbl, y     ;fetch corresponding address