A2osX/DRV/LANCEGS.DRV.S.txt

561 lines
10 KiB
Plaintext
Raw Normal View History

2017-12-22 21:24:30 +00:00
NEW
2019-05-02 09:52:32 +00:00
AUTO 3,1
2016-01-10 22:16:07 +00:00
.LIST OFF
.OP 65C02
.OR $2000
2020-05-14 11:47:46 +00:00
.TF drv/lancegs.drv
2016-01-10 22:16:07 +00:00
*--------------------------------------
2018-07-23 15:28:42 +00:00
.INB INC/MACROS.I
.INB INC/A2OSX.I
2018-10-02 15:52:30 +00:00
.INB INC/MLI.E.I
2018-07-23 15:28:42 +00:00
.INB INC/NIC.I
.INB INC/NIC.91C96.I
2018-08-27 05:39:42 +00:00
.INB INC/ETH.I
2016-01-10 22:16:07 +00:00
*--------------------------------------
2019-09-07 06:41:17 +00:00
ZPArgPtr .EQ ZPBIN
DEVSLOT0x .EQ ZPBIN+2
2016-01-10 22:16:07 +00:00
*--------------------------------------
* File Header (16 Bytes)
*--------------------------------------
CS.START cld
jmp Dev.Detect cld,jmp abs=DRV
.DA #$61 6502,Level 1 (65c02)
.DA #1 DRV Layout Version 1
.DA 0
.DA CS.END-CS.START Code Length
2018-08-27 05:39:42 +00:00
.DA 0
.DA 0
.DA 0
2016-01-10 22:16:07 +00:00
*--------------------------------------
* Relocation Table
*--------------------------------------
L.MSG.DETECT .DA MSG.DETECT
L.MSG.DETECT.OK .DA MSG.DETECT.OK
L.MSG.DETECT.KO .DA MSG.DETECT.KO
2018-08-27 05:39:42 +00:00
L.DRV.CS.START .DA DRV.CS.START
L.FD.DEV .DA FD.DEV
L.FD.DEV.NAME .DA FD.DEV.NAME
L.SSCANF.MAC .DA SSCANF.MAC
L.MAC0 .DA DCB+S.DCB.NIC.MAC
L.MAC1 .DA DCB+S.DCB.NIC.MAC+1
L.MAC2 .DA DCB+S.DCB.NIC.MAC+2
L.MAC3 .DA DCB+S.DCB.NIC.MAC+3
L.MAC4 .DA DCB+S.DCB.NIC.MAC+4
L.MAC5 .DA DCB+S.DCB.NIC.MAC+5
2016-01-10 22:16:07 +00:00
.DA 0 End Of Reloc Table
*--------------------------------------
2018-08-27 05:39:42 +00:00
Dev.Detect >STYA ARGS
2016-01-10 22:16:07 +00:00
>LDYA L.MSG.DETECT
2020-02-28 07:21:46 +00:00
>SYSCALL PutS
ldx #$70
ldy #7
2019-10-06 20:57:41 +00:00
.1 lda A2osX.S,y IO based detection, avoid scanning in Disk Controller IO!!!!
bne .2
2019-10-06 20:57:41 +00:00
lda L91C96.BSR+1,x
2016-01-10 22:16:07 +00:00
cmp #DEVID
2016-03-30 15:54:47 +00:00
beq .3
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
.2 dec FD.DEV.NAME+3
2016-01-10 22:16:07 +00:00
txa
sec
sbc #$10
2016-01-10 22:16:07 +00:00
tax
dey
bne .1
2019-10-06 20:57:41 +00:00
2016-01-10 22:16:07 +00:00
>LDYA L.MSG.DETECT.KO
2020-02-28 07:21:46 +00:00
>SYSCALL PutS
2016-01-10 22:16:07 +00:00
lda #MLI.E.NODEV
2016-01-10 22:16:07 +00:00
sec
rts
2019-10-06 20:57:41 +00:00
2016-01-10 22:16:07 +00:00
.3 stx DEVSLOTx0
2019-09-07 06:41:17 +00:00
sty DEVSLOT0x
2018-08-27 05:39:42 +00:00
jsr Dev.ParseArgs
2020-02-14 16:32:52 +00:00
bcs .99
2019-10-06 20:57:41 +00:00
2020-02-14 07:21:56 +00:00
.8 >PUSHW L.MSG.DETECT.OK
>PUSHW L.FD.DEV.NAME
2018-08-27 05:39:42 +00:00
>PUSHBI 2
2020-02-28 07:21:46 +00:00
>SYSCALL PrintF
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
>PUSHWI DRV.END
2019-07-22 06:31:01 +00:00
>PUSHWI DRV.CS.END-DRV.CS.START
2018-08-27 05:39:42 +00:00
>PUSHWI DRV.CS.START
>LDYA L.DRV.CS.START
>SYSCALL InsDrv
2020-02-14 16:32:52 +00:00
.99 bcs .9
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
>STYA FD.DEV+S.FD.DEV.DRVPTR
2020-03-16 06:50:15 +00:00
>PUSHW L.FD.DEV
2018-12-11 16:41:25 +00:00
>PUSHW L.FD.DEV.NAME
2018-08-27 05:39:42 +00:00
>SYSCALL MKDEV
2019-09-07 06:41:17 +00:00
bcs .9
2019-10-06 20:57:41 +00:00
2019-09-07 06:41:17 +00:00
ldx DEVSLOT0x
lda #A2osX.S.NIC
sta A2osX.S,x
* clc
2018-08-27 05:39:42 +00:00
.9 rts
*--------------------------------------
Dev.ParseArgs >LDYA ARGS
>STYA ZPArgPTR
lda (ZPArgPTR)
2019-10-28 06:32:12 +00:00
bne .1
2019-10-07 15:49:03 +00:00
2019-10-28 06:32:12 +00:00
lda A2osX.RANDOM16
eor A2osX.TIMER16
sta DCB+S.DCB.NIC.MAC+3
eor A2osX.RANDOM16+1
sta DCB+S.DCB.NIC.MAC+4
eor A2osX.TIMER16+1
sta DCB+S.DCB.NIC.MAC+5
clc
rts
2020-02-14 16:32:52 +00:00
.1 >PUSHW ZPArgPtr
>PUSHW L.SSCANF.MAC
2020-04-13 17:04:02 +00:00
ldx #0
2019-10-07 15:49:03 +00:00
2019-10-23 15:12:58 +00:00
.2 >PUSHW L.MAC0,x
2020-04-13 17:04:02 +00:00
inx
inx
cpx #12
bne .2
2019-10-28 06:32:12 +00:00
2018-08-27 05:39:42 +00:00
>PUSHBI 12 6 x byte PTRs
>SYSCALL sscanf
2019-10-28 06:32:12 +00:00
bcc .8
2019-10-07 15:49:03 +00:00
2019-10-28 06:32:12 +00:00
lda #E.SYN
2018-08-27 05:39:42 +00:00
sec
2019-10-28 06:32:12 +00:00
.8 rts
2016-01-10 22:16:07 +00:00
*--------------------------------------
CS.END
2018-08-27 05:39:42 +00:00
ARGS .BS 2
MSG.DETECT .AZ "LanCeGS/SMSC91C96 Driver."
2019-10-06 20:57:41 +00:00
MSG.DETECT.OK .AZ "LanCeGS/SMSC91C96 Installed As Device : %s\r\n"
2018-08-27 05:39:42 +00:00
MSG.DETECT.KO .AZ "Hardware Not Found."
SSCANF.MAC .AZ "%h:%h:%h:%h:%h:%h"
2016-01-10 22:16:07 +00:00
*--------------------------------------
2018-08-27 05:39:42 +00:00
FD.DEV .DA #S.FD.T.CDEV
.DA #0 HANDLER
.DA #0 BUSID
.DA #0 DEVID
.DA 0 BUSPTR
.BS 2 DRVPTR
2018-12-13 16:39:24 +00:00
.DA 0 DCBPTR
2018-12-11 16:41:25 +00:00
.DA 0 BUFPTR
2019-12-03 15:42:17 +00:00
FD.DEV.NAME .AZ "eth7"
2016-01-10 22:16:07 +00:00
*--------------------------------------
* Driver Code
*--------------------------------------
2018-08-27 05:39:42 +00:00
ZPIOCTL .EQ ZPDRV
ZPBufPtr .EQ ZPDRV+2
Size .EQ ZPDRV+4
Counter .EQ ZPDRV+6
*--------------------------------------
DRV.CS.START cld
jmp (.1,x)
.1 .DA STATUS
.DA A2osX.BADCALL
.DA A2osX.BADCALL
.DA A2osX.BADCALL
.DA A2osX.BADCALL
.DA A2osX.BADCALL
2018-08-27 05:39:42 +00:00
.DA OPEN
.DA CLOSE
.DA READ
.DA WRITE
2016-01-10 22:16:07 +00:00
.DA 0 end or relocation
*--------------------------------------
2018-08-27 05:39:42 +00:00
STATUS >STYA ZPIOCTL
ldy #S.IOCTL.STATCODE
lda (ZPIOCTL),y
beq .1
cmp #S.IOCTL.STATCODE.GETDIB
bne STATUS.DCB
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
ldx #S.DIB-1
.HS 2C bit abs
.1 ldx #3
ldy #S.IOCTL.BUFPTR
lda (ZPIOCTL),y
sta .3+1
iny
lda (ZPIOCTL),y
sta .3+2
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
.2 lda DIB,x
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
.3 sta $ffff,x SELF MODIFIED
dex
bpl .2
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
clc
rts
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
STATUS.DCB cmp #S.IOCTL.STATCODE.GETDCB
bne STATUS.9
stz DCB+S.DCB.NIC.LINK
2016-03-13 22:07:01 +00:00
ldx DEVSLOTx0
2016-03-13 22:07:01 +00:00
stz L91C96.BSR,x
lda L91C96.0.EPHSR,x
lda L91C96.0.EPHSR+1,x
and /L91C96.0.EPHSR.LINK
beq .1
2018-08-27 05:39:42 +00:00
lda #S.DCB.NIC.LINK.OK
tsb DCB+S.DCB.NIC.LINK
2016-03-13 22:07:01 +00:00
2018-08-27 05:39:42 +00:00
lda L91C96.0.TCR,x
lda L91C96.0.TCR+1,x
and /L91C96.0.TCR.FDSE
2018-08-27 05:39:42 +00:00
beq .1
lda #S.DCB.NIC.LINK.FD
tsb DCB+S.DCB.NIC.LINK
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
.1 ldy #S.IOCTL.BUFPTR
lda (ZPIOCTL),y
sta .4+1
iny
lda (ZPIOCTL),y
sta .4+2
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
ldx #S.DCB.NIC-1
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
.3 lda DCB,x
.4 sta $ffff,x SELF MODIFIED
dex
bpl .3
clc
rts
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
STATUS.9 lda #MLI.E.BADCTL
sec
2019-10-03 06:25:27 +00:00
rts
2018-08-27 05:39:42 +00:00
*--------------------------------------
2019-05-02 09:52:32 +00:00
OPEN lda #S.DIB.S.OPENED
bit DIB+S.DIB.S
bne .9
2019-10-06 20:57:41 +00:00
2019-05-02 09:52:32 +00:00
jsr CLOSE
2018-08-27 05:39:42 +00:00
* ldx DEVSLOTx0 Done by CLOSE
lda #L91C96.0.TCR.FDSE+L91C96.0.TCR.FUDPLX+L91C96.0.TCR.PADEN+L91C96.0.TCR.TXENA
sta L91C96.0.TCR,x
lda /L91C96.0.TCR.FDSE+L91C96.0.TCR.FUDPLX+L91C96.0.TCR.PADEN+L91C96.0.TCR.TXENA
sta L91C96.0.TCR+1,x
lda #L91C96.0.RCR.NOCRC+L91C96.0.RCR.RXENA+L91C96.0.RCR.ALLMUL
sta L91C96.0.RCR,x
lda /L91C96.0.RCR.NOCRC+L91C96.0.RCR.RXENA+L91C96.0.RCR.ALLMUL
sta L91C96.0.RCR+1,x
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
lda #1
sta L91C96.BSR,x
2019-10-14 05:23:09 +00:00
2018-08-27 05:39:42 +00:00
lda #L91C96.1.CR.NOWAIT
sta L91C96.1.CR,x
lda /L91C96.1.CR.NOWAIT
sta L91C96.1.CR+1,x
ldy #0
2019-10-22 14:28:54 +00:00
.2 lda DCB+S.DCB.NIC.MAC,y
2018-08-27 05:39:42 +00:00
sta L91C96.1.IAR,x
inx
iny
cpy #6
2016-03-13 22:07:01 +00:00
bne .2
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
.3 ldx DEVSLOTx0
2019-10-07 15:49:03 +00:00
2018-08-27 05:39:42 +00:00
lda #L91C96.1.CTR.DEFAULT+L91C96.1.CTR.AUTOREL
sta L91C96.1.CTR,x
lda /L91C96.1.CTR.DEFAULT+L91C96.1.CTR.AUTOREL
sta L91C96.1.CTR+1,x
clc
rts
2019-05-02 09:52:32 +00:00
.9 lda #MLI.E.OPEN
sec
2019-10-03 06:25:27 +00:00
rts
2018-08-27 05:39:42 +00:00
*--------------------------------------
CLOSE ldx DEVSLOTx0
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
stz L91C96.BSR,x
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
lda #L91C96.0.RCR.RESET
sta L91C96.0.RCR,x
lda /L91C96.0.RCR.RESET
sta L91C96.0.RCR+1,x
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
lda $C019 we can use VBL as we are not on //c
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
.1 eor $C019
bpl .1
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
.2 eor $C019
bpl .2
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
stz L91C96.0.RCR,x
stz L91C96.0.RCR+1,x
2016-01-10 22:16:07 +00:00
clc
rts
*--------------------------------------
2018-08-27 05:39:42 +00:00
READ php
sei
>STYA ZPIOCTL
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
ldx DEVSLOTx0
2019-10-06 20:57:41 +00:00
2016-03-13 22:07:01 +00:00
lda #2
sta L91C96.BSR,x
lda L91C96.2.IST,x
and #L91C96.2.IST.RCV
2019-10-06 20:57:41 +00:00
beq READWRITE.9
2018-08-27 05:39:42 +00:00
.1 lda #L91C96.2.PTR.RCVD+L91C96.2.PTR.AUTOI+L91C96.2.PTR.READ
2016-03-13 22:07:01 +00:00
sta L91C96.2.PTR,x
lda /L91C96.2.PTR.RCVD+L91C96.2.PTR.AUTOI+L91C96.2.PTR.READ
sta L91C96.2.PTR+1,x
2016-03-30 15:54:47 +00:00
lda L91C96.2.DATA,x Get Frame Status Word (lo)
lda L91C96.2.DATA,x Get Frame Status Word (HI)
asl
2016-03-30 15:54:47 +00:00
asl
asl #$10 = odd?
asl if odd, CS
lda L91C96.2.DATA,x get lo byte count
sbc #5 compute Size
2018-08-27 05:39:42 +00:00
pha
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
ldy #S.IOCTL.BYTECNT
sta (ZPIOCTL),y
eor #$ff
sta Counter
2019-10-06 20:57:41 +00:00
2016-03-30 15:54:47 +00:00
lda L91C96.2.DATA,x get hi byte count
sbc #0
2018-08-27 05:39:42 +00:00
iny
sta (ZPIOCTL),y
eor #$ff
sta Counter+1
eor #$ff
2019-10-06 20:57:41 +00:00
ply Y,A = Size
2019-05-12 20:45:11 +00:00
>SYSCALL2 getmem
2019-10-06 20:57:41 +00:00
bcs READWRITE.99
2018-08-27 05:39:42 +00:00
>STYA ZPBufPtr
2019-10-06 20:57:41 +00:00
2019-05-12 20:45:11 +00:00
phx
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
phy
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
ldy #S.IOCTL.BUFPTR+1
sta (ZPIOCTL),y
dey
pla
sta (ZPIOCTL),y
2016-03-13 22:07:01 +00:00
ldx DEVSLOTx0
2018-08-27 05:39:42 +00:00
ldy #0
2019-10-06 20:57:41 +00:00
.2 inc Counter
2016-03-13 22:07:01 +00:00
bne .3
inc Counter+1
beq .4
2019-10-06 20:57:41 +00:00
2019-10-07 15:49:03 +00:00
.3 lda L91C96.2.DATA,x
2018-08-27 05:39:42 +00:00
sta (ZPBufPtr),y
2016-03-13 22:07:01 +00:00
iny
bne .2
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
inc ZPBufPtr+1
2016-03-13 22:07:01 +00:00
bra .2
.4 lda #L91C96.2.MMUCR.REMREL
2016-03-13 22:07:01 +00:00
sta L91C96.2.MMUCR,x
2019-10-06 20:57:41 +00:00
2019-05-12 20:45:11 +00:00
.8 pla hMem
2018-08-27 05:39:42 +00:00
plp
2016-01-10 22:16:07 +00:00
clc
2018-08-27 05:39:42 +00:00
rts
2019-10-03 06:25:27 +00:00
*--------------------------------------
2019-10-06 20:57:41 +00:00
READWRITE.9 lda #E.NODATA
READWRITE.99 plp
sec
rts
*--------------------------------------
2018-08-27 05:39:42 +00:00
WRITE php
sei
>STYA ZPIOCTL
2016-03-13 22:07:01 +00:00
ldx DEVSLOTx0
2019-10-06 20:57:41 +00:00
2016-03-13 22:07:01 +00:00
lda #2
sta L91C96.BSR,x
2018-08-27 05:39:42 +00:00
ldy #S.IOCTL.BYTECNT
lda (ZPIOCTL),y
sta Size
eor #$ff
sta Counter
eor #$ff
2016-01-10 22:16:07 +00:00
clc
2016-03-13 22:07:01 +00:00
adc #6 3 WORDs more Status, len & Control
2016-03-31 20:07:47 +00:00
bne .10
2019-10-06 20:57:41 +00:00
2016-03-31 20:07:47 +00:00
clc LO byte is 0, no need for an extra empty page
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
.10 iny
lda (ZPIOCTL),y
sta Size+1
eor #$ff
sta Counter+1
eor #$ff
2019-10-06 20:57:41 +00:00
2016-03-13 22:07:01 +00:00
adc #0
2019-10-13 08:35:31 +00:00
2016-03-13 22:07:01 +00:00
.1 ora #L91C96.2.MMUCR.ALLOC
sta L91C96.2.MMUCR,x
ldy #0
2019-10-06 20:57:41 +00:00
2016-03-13 22:07:01 +00:00
.2 lda L91C96.2.IST,x
and #L91C96.2.IST.ALLOC
bne .3
2019-10-06 20:57:41 +00:00
2016-03-13 22:07:01 +00:00
dey
bne .2
2019-10-06 20:57:41 +00:00
bra READWRITE.9
2019-10-03 06:25:27 +00:00
2016-03-13 22:07:01 +00:00
.3 lda L91C96.2.AAR,x
sta L91C96.2.PNR,x
2016-03-30 06:30:41 +00:00
lda #L91C96.2.PTR.AUTOI
2016-03-13 22:07:01 +00:00
sta L91C96.2.PTR,x
2016-03-30 06:30:41 +00:00
lda /L91C96.2.PTR.AUTOI
2016-03-13 22:07:01 +00:00
sta L91C96.2.PTR+1,x
2018-08-27 05:39:42 +00:00
ldy #S.IOCTL.BUFPTR
lda (ZPIOCTL),y
sta ZPBufPtr
iny
lda (ZPIOCTL),y
sta ZPBufPtr+1
2019-10-06 20:57:41 +00:00
2019-10-14 05:23:09 +00:00
ldy #S.ETH.SRCMAC+5 Add Src MAC Address
ldx #5
2019-10-06 20:57:41 +00:00
2019-10-22 14:28:54 +00:00
.4 lda DCB+S.DCB.NIC.MAC,x
2019-10-14 05:23:09 +00:00
sta (ZPBufPtr),y
dey
dex
bpl .4
2019-10-07 15:49:03 +00:00
2019-10-14 05:23:09 +00:00
ldx DEVSLOTx0
2016-03-13 22:07:01 +00:00
2016-03-30 15:54:47 +00:00
stz L91C96.2.DATA,x write fake status word
2016-03-30 06:30:41 +00:00
stz L91C96.2.DATA,x
2019-10-06 20:57:41 +00:00
lda Size
2016-03-13 22:07:01 +00:00
pha
2016-03-30 15:54:47 +00:00
eor #$01
2016-03-13 22:07:01 +00:00
lsr
pla
2019-10-06 20:57:41 +00:00
2016-03-30 15:54:47 +00:00
adc #$05 add 5 if odd, 6 if even
2016-03-13 22:07:01 +00:00
sta L91C96.2.DATA,x
2019-10-06 20:57:41 +00:00
lda Size+1
2016-03-30 15:54:47 +00:00
adc #$00
2016-03-30 06:30:41 +00:00
sta L91C96.2.DATA,x
2019-10-06 20:57:41 +00:00
2019-10-13 08:35:31 +00:00
ldy #0
2019-10-06 20:57:41 +00:00
.5 inc Counter
bne .51
inc Counter+1
2016-03-13 22:07:01 +00:00
beq .70
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
.51 lda (ZPBufPtr),y
2016-03-13 22:07:01 +00:00
iny
bne .6
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
inc ZPBufPtr+1
2019-10-06 20:57:41 +00:00
.6 inc Counter
bne .61
2019-10-06 20:57:41 +00:00
inc Counter+1
2016-03-13 22:07:01 +00:00
beq .71
2019-10-06 20:57:41 +00:00
.61 sta L91C96.2.DATA,x
2018-08-27 05:39:42 +00:00
lda (ZPBufPtr),y
2016-03-30 06:30:41 +00:00
sta L91C96.2.DATA,x
2016-03-13 22:07:01 +00:00
iny
bne .5
2019-10-13 08:35:31 +00:00
2018-08-27 05:39:42 +00:00
inc ZPBufPtr+1
2016-03-13 22:07:01 +00:00
bra .5
2019-10-06 20:57:41 +00:00
2016-03-13 22:07:01 +00:00
.70 lda #0
sta L91C96.2.DATA,x
2016-03-30 06:30:41 +00:00
sta L91C96.2.DATA,x
2016-03-13 22:07:01 +00:00
bra .8
2019-10-06 20:57:41 +00:00
.71 sta L91C96.2.DATA,x
2016-03-30 15:54:47 +00:00
lda #%00100000 signal an extra (odd) byte
2016-03-30 06:30:41 +00:00
sta L91C96.2.DATA,x
2019-10-06 20:57:41 +00:00
2016-03-13 22:07:01 +00:00
.8 lda #L91C96.2.MMUCR.NQPKT
2018-08-27 05:39:42 +00:00
sta L91C96.2.MMUCR,x
2019-10-06 20:57:41 +00:00
2018-08-27 05:39:42 +00:00
plp
clc
2016-01-10 22:16:07 +00:00
rts
*--------------------------------------
DRV.CS.END
DEVSLOTx0 .BS 1
*--------------------------------------
2018-08-27 05:39:42 +00:00
DIB .DA #0
.DA #0,#0,#0 size
>PSTR "LanCEGS/L91C96"
2020-05-14 11:47:46 +00:00
.BS 2
2018-08-27 05:39:42 +00:00
.DA #S.DIB.T.NIC
.BS 1 Subtype
.BS 2 Version
2016-01-10 22:16:07 +00:00
*--------------------------------------
2018-08-27 05:39:42 +00:00
DCB .DA #S.DCB.T.NIC
.BS 1 FLAGS
.BS 1 LINK
.DA #S.DCB.NIC.SPEED.10
.HS 000E3A123456 MAC
.BS 12 IP/MASK/GW
*--------------------------------------
DRV.END
2016-01-10 22:16:07 +00:00
MAN
2018-12-11 16:41:25 +00:00
SAVE USR/SRC/DRV/LANCEGS.DRV.S
2016-01-10 22:16:07 +00:00
ASM