68030tk/Logic/68030_tk.crf

// Signal Name Cross Reference File
// ispLEVER Classic 2.0.00.17.20.15

// Design '68030_tk' created Fri Aug 19 00:39:35 2016


// LEGEND:  '>'  Functional Block Port Separator
//          '/'  Hierarchy Path Separator
//          '@'  Automatically Generated Node


// Hierarchical Name                    Short Name

// *** Shortened names not required for this design. ***
Initial push First VErsion after I decided to use version controll ;) 2014-05-15 19:16:29 +00:00			`// Signal Name Cross Reference File`
Clean up 2016-08-18 05:48:07 +00:00			`// ispLEVER Classic 2.0.00.17.20.15`
Initial push First VErsion after I decided to use version controll ;) 2014-05-15 19:16:29 +00:00
Horray! No Sync of Pos and Neg edges needed anymore! 2016-08-18 22:42:01 +00:00			`// Design '68030_tk' created Fri Aug 19 00:39:35 2016`
Initial push First VErsion after I decided to use version controll ;) 2014-05-15 19:16:29 +00:00

			`// LEGEND: '>' Functional Block Port Separator`
			`// '/' Hierarchy Path Separator`
			`// '@' Automatically Generated Node`


			`// Hierarchical Name Short Name`
Reset-Problem solved The AMiga was not able to recover from a reste, because the e-clock was not generated properly during reste. 2015-03-15 12:50:46 +00:00
			`// * Shortened names not required for this design. *`