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68030tk
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Clean up

This commit is contained in:
MHeinrichs 2016-08-18 07:48:07 +02:00
parent 4fb647308c
commit 0c2122cd7f
57 changed files with 9288 additions and 2722 deletions
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45
Logic/68030-68000-bus.vhd
View File

@ -126,11 +126,7 @@ signal CLK_OUT_PRE_D: STD_LOGIC := '1';
signal CLK_OUT_INT: STD_LOGIC := '1';
signal CLK_OUT_EXP_INT: STD_LOGIC := '1';
signal CLK_030_H: STD_LOGIC := '1';
signal CLK_000_D0: STD_LOGIC := '1';
signal CLK_000_D1: STD_LOGIC := '1';
signal CLK_000_D2: STD_LOGIC := '1';
signal CLK_000_D3: STD_LOGIC := '1';
signal CLK_000_D4: STD_LOGIC := '1';
signal CLK_000_D: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000";
signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
signal CLK_000_PE: STD_LOGIC := '0';
@ -169,28 +165,26 @@ begin
CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
CLK_OUT_EXP_INT <= CLK_OUT_PRE_50;
--delayed Clocks and signals for edge detection
CLK_000_D0 <= CLK_000;
CLK_000_D1 <= CLK_000_D0;
CLK_000_D2 <= CLK_000_D1;
CLK_000_D3 <= CLK_000_D2;
CLK_000_D4 <= CLK_000_D3;
CLK_000_D(0) <= CLK_000;
CLK_000_D(7 downto 1) <= CLK_000_D(6 downto 0);
--shift registers for edge detection
CLK_000_P_SYNC( 12 downto 1 ) <= CLK_000_P_SYNC( 11 downto 0 );
CLK_000_P_SYNC(0) <= CLK_000_D0 AND NOT CLK_000_D1;
CLK_000_P_SYNC(0) <= CLK_000_D(0) AND NOT CLK_000_D(1);
CLK_000_N_SYNC( 12 downto 1 ) <= CLK_000_N_SYNC( 11 downto 0 );
CLK_000_N_SYNC(0) <= NOT CLK_000_D0 AND CLK_000_D1;
CLK_000_N_SYNC(0) <= NOT CLK_000_D(0) AND CLK_000_D(1);
-- values are determined empiracally for 7.09 MHz Clock
-- since the clock is not symmetrically these values differ!
CLK_000_PE <= CLK_000_P_SYNC(9);
CLK_000_NE <= CLK_000_N_SYNC(11);
--CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1) AND NOT CLK_000_D(2);
--CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1) AND CLK_000_D(2);
CLK_000_NE_D0 <= CLK_000_NE;
-- e-clock is changed on the FALLING edge!
if(CLK_000_NE_D0 = '1' ) then
--if(CLK_000_D0='0' AND CLK_000_D1='1') then
case (cpu_est) is
when E1 => cpu_est <= E2 ;
when E2 => cpu_est <= E3 ;
@ -279,7 +273,6 @@ begin
elsif ( BGACK_000='1'
AND CLK_000_PE='1'
AND AS_000 = '1' --the amiga AS can be still active while bgack is deasserted, so wait for this signal too!
--AND CLK_000_D0='1' and CLK_000_D1='0'
) then -- BGACK_000 is high here!
BGACK_030_INT_PRE<= '1';
BGACK_030_INT <= BGACK_030_INT_PRE; --hold this signal high until 7m clock goes low
@ -293,8 +286,7 @@ begin
BG_000 <= '1';
elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
and nEXP_SPACE_D0 = '1' and AS_030_D0='1'
and CLK_000_D0='1'
--and CLK_000_D0='1' AND CLK_000_D1='0'
and CLK_000_D(0)='1'
) then --bus granted no local access and no AS_030 running!
BG_000 <= '0';
end if;
@ -302,7 +294,6 @@ begin
--interrupt buffering to avoid ghost interrupts
--if(CLK_000_NE='1')then
--if(CLK_000_D0='0' and CLK_000_D1='1')then
IPL_D0<=IPL;
if(IPL = IPL_D0)then
IPL_030<=IPL;
@ -332,7 +323,6 @@ begin
-- VMA generation
if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
--if(CLK_000_D0='0' AND CLK_000_D1='1' AND VPA_D='0' AND cpu_est = E4)then --assert
VMA_INT <= '0';
elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert
VMA_INT <= '1';
@ -362,14 +352,13 @@ begin
case (SM_AMIGA) is
when IDLE_P => --68000:S0 wait for a falling edge
RW_000_INT <= '1';
AMIGA_BUS_ENABLE_INT <= CLK_000_D1;
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
AMIGA_BUS_ENABLE_INT <= CLK_000_D(1);
if( CLK_000_D(0)='0' and CLK_000_D(1)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
SM_AMIGA<=IDLE_N; --go to s1
end if;
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
if(CLK_000_PE='1')then --go to s2
--if(CLK_000_D0='1')then --go to s2
SM_AMIGA <= AS_SET_P; --as for amiga set!
end if;
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
@ -379,13 +368,11 @@ begin
DS_000_ENABLE <= '1';
end if;
if(CLK_000_NE='1')then --go to s3
--if(CLK_000_D0='0')then --go to s3
SM_AMIGA<=AS_SET_N;
end if;
when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
if(CLK_000_PE='1')then --go to s4
--if(CLK_000_D0='1')then --go to s4
-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
SM_AMIGA <= SAMPLE_DTACK_P;
@ -393,7 +380,6 @@ begin
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
DS_000_ENABLE <= '1';
if( CLK_000_NE_D0='1' and --falling edge
--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
)then --go to s5
@ -402,7 +388,6 @@ begin
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
DS_000_ENABLE <= '1';
if(CLK_000_PE = '1')then --go to s6
--if(CLK_000_D0='1')then --go to s6
SM_AMIGA<=DATA_FETCH_P;
end if;
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
@ -411,17 +396,11 @@ begin
(CLK_000_N_SYNC(10)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
DSACK1_INT <='0';
end if;
--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
-- DSACK1_INT <='0';
--end if;
if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
--if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
--DSACK1_INT <='0';
SM_AMIGA<=END_CYCLE_N;
end if;
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
if(CLK_000_PE='1')then --go to s0
--if(CLK_000_D0='1')then --go to s0
SM_AMIGA<=IDLE_P;
RW_000_INT <= '1';
--AMIGA_BUS_ENABLE_INT <= '1';
@ -462,7 +441,7 @@ begin
if(BGACK_030_INT='0' and AS_000='0')then
-- an 68000-memory cycle is three positive edges long!
if(CLK_000_P_SYNC(10)='1')then
if(CLK_000_PE='1')then
CYCLE_DMA <= CYCLE_DMA+1;
end if;
else
@ -609,4 +588,4 @@ begin
'0' when DSACK1_INT ='0' else
'1';
end Behavioral;
end Behavioral;

3519
Logic/68030_TK.tcl
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File diff suppressed because it is too large Load Diff

216
Logic/68030_tk.bl2
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@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
#$ DATE Wed Jan 27 21:56:48 2016
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 17 17:45:46 2016
#$ MODULE 68030_tk
#$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ \
# IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 \
@ -37,17 +37,17 @@
# lds_000_int_0_un0_n inst_CLK_OUT_PRE_D sm_amiga_i_3__n N_350_i rw_000_dma_0_un3_n \
# inst_DTACK_D0 cpu_est_i_0__n N_188_0 rw_000_dma_0_un1_n inst_RESET_OUT \
# cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n inst_CLK_OUT_PRE_50 cpu_est_i_2__n \
# N_185_i a_15__n inst_CLK_000_D1 cpu_est_i_1__n N_182_i inst_CLK_000_D0 VPA_D_i \
# N_181_i a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ \
# N_185_i a_15__n CLK_000_D_1_ cpu_est_i_1__n N_182_i CLK_000_D_0_ VPA_D_i N_181_i \
# a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ \
# sm_amiga_i_1__n N_175_0 a_13__n inst_CLK_000_NE rst_dly_i_2__n N_168_i \
# CLK_000_N_SYNC_11_ CLK_030_i AS_030_000_SYNC_i a_12__n IPL_D0_0_ rst_dly_i_0__n \
# N_158_i IPL_D0_1_ rst_dly_i_1__n CLK_000_D0_i a_11__n IPL_D0_2_ CLK_000_D1_i N_148_i \
# inst_CLK_000_NE_D0 DTACK_D0_i N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i \
# SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH \
# N_158_i IPL_D0_1_ rst_dly_i_1__n clk_000_d_i_0__n a_11__n IPL_D0_2_ clk_000_d_i_1__n \
# N_148_i inst_CLK_000_NE_D0 DTACK_D0_i N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i \
# N_344_i SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH \
# sm_amiga_i_6__n N_138_0 inst_DSACK1_INTreg sm_amiga_i_2__n a_8__n AS_000_i N_342_i \
# pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n SM_AMIGA_4_ A1_i N_124_0 \
# inst_DS_000_ENABLE a_i_31__n N_341_i a_6__n RST_DLY_0_ a_i_29__n N_119_0 RST_DLY_1_ \
# a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un8_bg_030_n a_i_28__n \
# a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un9_bg_030_n a_i_28__n \
# cpu_est_2_0_2__n a_4__n CLK_000_P_SYNC_0_ a_i_25__n N_338_i CLK_000_P_SYNC_1_ \
# a_i_26__n N_339_i a_3__n CLK_000_P_SYNC_2_ N_213_i cpu_est_2_0_1__n \
# CLK_000_P_SYNC_3_ N_214_i N_332_i a_2__n CLK_000_P_SYNC_4_ N_215_i N_336_i \
@ -69,7 +69,7 @@
# N_17_i N_42_0 a_c_23__n N_19_i N_40_0 SM_AMIGA_i_7_ a_c_24__n N_20_i N_123 N_39_0 \
# cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i G_134 \
# N_37_0 G_135 a_c_27__n N_25_i G_136 N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \
# BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un8_bg_030_0_n N_80 \
# BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \
# N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \
# pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 N_138 \
# nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 N_137_i_2 N_175 \
@ -94,7 +94,7 @@
# as_030_000_sync_0_un3_n N_347 N_272_i as_030_000_sync_0_un1_n N_350 N_271_i \
# as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 \
# ds_000_enable_0_un1_n N_361 N_281_0 ds_000_enable_0_un0_n \
# pos_clk_un24_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n \
# pos_clk_un23_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n \
# pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n \
# cpu_est_0_0_x2_0_ N_299_i as_000_int_0_un0_n pos_clk_CYCLE_DMA_5_1_i_x2 \
# pos_clk_size_dma_6_0_1__n dsack1_int_0_un3_n un22_berr_1 un1_as_000_i \
@ -164,14 +164,14 @@ sm_amiga_i_3__n.BLIF N_350_i.BLIF rw_000_dma_0_un3_n.BLIF inst_DTACK_D0.BLIF \
cpu_est_i_0__n.BLIF N_188_0.BLIF rw_000_dma_0_un1_n.BLIF inst_RESET_OUT.BLIF \
cpu_est_i_3__n.BLIF N_187_i.BLIF rw_000_dma_0_un0_n.BLIF \
inst_CLK_OUT_PRE_50.BLIF cpu_est_i_2__n.BLIF N_185_i.BLIF a_15__n.BLIF \
inst_CLK_000_D1.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF inst_CLK_000_D0.BLIF \
CLK_000_D_1_.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF CLK_000_D_0_.BLIF \
VPA_D_i.BLIF N_181_i.BLIF a_14__n.BLIF inst_CLK_000_PE.BLIF CLK_000_NE_i.BLIF \
CLK_OUT_PRE_D_i.BLIF CLK_000_P_SYNC_9_.BLIF sm_amiga_i_1__n.BLIF N_175_0.BLIF \
a_13__n.BLIF inst_CLK_000_NE.BLIF rst_dly_i_2__n.BLIF N_168_i.BLIF \
CLK_000_N_SYNC_11_.BLIF CLK_030_i.BLIF AS_030_000_SYNC_i.BLIF a_12__n.BLIF \
IPL_D0_0_.BLIF rst_dly_i_0__n.BLIF N_158_i.BLIF IPL_D0_1_.BLIF \
rst_dly_i_1__n.BLIF CLK_000_D0_i.BLIF a_11__n.BLIF IPL_D0_2_.BLIF \
CLK_000_D1_i.BLIF N_148_i.BLIF inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF \
rst_dly_i_1__n.BLIF clk_000_d_i_0__n.BLIF a_11__n.BLIF IPL_D0_2_.BLIF \
clk_000_d_i_1__n.BLIF N_148_i.BLIF inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF \
N_345_i.BLIF a_10__n.BLIF pos_clk_un6_bg_030_n.BLIF RW_000_i.BLIF N_344_i.BLIF \
SM_AMIGA_0_.BLIF CLK_030_H_i.BLIF N_144_0.BLIF a_9__n.BLIF \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF sm_amiga_i_6__n.BLIF N_138_0.BLIF \
@ -180,7 +180,7 @@ N_342_i.BLIF pos_clk_ipl_n.BLIF sm_amiga_i_0__n.BLIF N_343_i.BLIF a_7__n.BLIF \
SM_AMIGA_4_.BLIF A1_i.BLIF N_124_0.BLIF inst_DS_000_ENABLE.BLIF a_i_31__n.BLIF \
N_341_i.BLIF a_6__n.BLIF RST_DLY_0_.BLIF a_i_29__n.BLIF N_119_0.BLIF \
RST_DLY_1_.BLIF a_i_30__n.BLIF N_340_i.BLIF a_5__n.BLIF RST_DLY_2_.BLIF \
a_i_27__n.BLIF N_361_i.BLIF pos_clk_un8_bg_030_n.BLIF a_i_28__n.BLIF \
a_i_27__n.BLIF N_361_i.BLIF pos_clk_un9_bg_030_n.BLIF a_i_28__n.BLIF \
cpu_est_2_0_2__n.BLIF a_4__n.BLIF CLK_000_P_SYNC_0_.BLIF a_i_25__n.BLIF \
N_338_i.BLIF CLK_000_P_SYNC_1_.BLIF a_i_26__n.BLIF N_339_i.BLIF a_3__n.BLIF \
CLK_000_P_SYNC_2_.BLIF N_213_i.BLIF cpu_est_2_0_1__n.BLIF \
@ -216,7 +216,7 @@ cpu_est_2_1__n.BLIF a_c_25__n.BLIF N_21_i.BLIF cpu_est_2_2__n.BLIF N_38_0.BLIF \
N_209.BLIF a_c_26__n.BLIF N_22_i.BLIF G_134.BLIF N_37_0.BLIF G_135.BLIF \
a_c_27__n.BLIF N_25_i.BLIF G_136.BLIF N_34_0.BLIF N_217.BLIF a_c_28__n.BLIF \
N_26_i.BLIF N_33_0.BLIF N_61.BLIF a_c_29__n.BLIF BG_030_c_i.BLIF N_127.BLIF \
pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un8_bg_030_0_n.BLIF \
pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un9_bg_030_0_n.BLIF \
N_80.BLIF N_289_0_1.BLIF a_c_31__n.BLIF un1_SM_AMIGA_5_i_1.BLIF N_90.BLIF \
un1_SM_AMIGA_5_i_2.BLIF N_96.BLIF A0_c.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF \
N_99.BLIF N_351_1.BLIF N_119.BLIF A1_c.BLIF N_351_2.BLIF N_124.BLIF \
@ -259,7 +259,7 @@ as_030_000_sync_0_un1_n.BLIF N_350.BLIF N_271_i.BLIF \
as_030_000_sync_0_un0_n.BLIF N_351.BLIF N_279_0.BLIF \
ds_000_enable_0_un3_n.BLIF N_353.BLIF N_280_0.BLIF ds_000_enable_0_un1_n.BLIF \
N_361.BLIF N_281_0.BLIF ds_000_enable_0_un0_n.BLIF \
pos_clk_un24_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF \
pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF \
as_000_int_0_un3_n.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF \
pos_clk_size_dma_6_0_0__n.BLIF as_000_int_0_un1_n.BLIF cpu_est_0_0_x2_0_.BLIF \
N_299_i.BLIF as_000_int_0_un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF \
@ -286,18 +286,17 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \
A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C \
SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \
SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \
IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \
IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \
IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C \
SM_AMIGA_6_.D SM_AMIGA_6_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C \
CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \
CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \
CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \
cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \
SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \
SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \
IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \
IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \
IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \
SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \
CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \
CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \
cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \
CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \
CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \
CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \
@ -306,33 +305,34 @@ CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \
CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \
CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \
CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D \
RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \
CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \
CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \
CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \
CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \
CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \
CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_DMA.D \
inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \
inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \
inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \
inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \
BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D \
inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \
inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \
inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \
inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \
inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \
BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \
inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \
inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D \
inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \
inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D \
inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C \
inst_CLK_000_NE.D inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 \
LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 N_289_0 \
cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 cpu_est_0_2__un0_n \
N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 N_246_i \
cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i \
inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 RW_000 \
UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 \
N_289_0 cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 \
cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 \
N_246_i cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i \
ipl_030_0_0__un3_n N_7 ipl_030_0_0__un1_n gnd_n_n N_10 N_266_i \
ipl_030_0_0__un0_n un1_amiga_bus_enable_low N_18 N_267_i ipl_030_0_1__un3_n \
un3_size N_24 N_254_i ipl_030_0_1__un1_n un4_size N_6 N_317_i \
@ -358,20 +358,20 @@ N_188_0 rw_000_dma_0_un1_n cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n \
cpu_est_i_2__n N_185_i a_15__n cpu_est_i_1__n N_182_i VPA_D_i N_181_i a_14__n \
CLK_000_NE_i CLK_OUT_PRE_D_i sm_amiga_i_1__n N_175_0 a_13__n rst_dly_i_2__n \
N_168_i CLK_030_i AS_030_000_SYNC_i a_12__n rst_dly_i_0__n N_158_i \
rst_dly_i_1__n CLK_000_D0_i a_11__n CLK_000_D1_i N_148_i DTACK_D0_i N_345_i \
a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 a_9__n \
sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n a_8__n AS_000_i N_342_i pos_clk_ipl_n \
sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i a_6__n a_i_29__n \
N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i pos_clk_un8_bg_030_n \
a_i_28__n cpu_est_2_0_2__n a_4__n a_i_25__n N_338_i a_i_26__n N_339_i a_3__n \
N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n N_215_i N_336_i \
pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i DS_000_DMA_i \
N_96_0 un4_as_000_i N_330_i AS_000_INT_i N_90_0 un4_lds_000_i N_328_i \
un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 RW_000_c \
N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n LDS_000_c \
un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 N_310_i size_c_1__n N_305_i \
N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 N_278_i \
N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 \
rst_dly_i_1__n clk_000_d_i_0__n a_11__n clk_000_d_i_1__n N_148_i DTACK_D0_i \
N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 \
a_9__n sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n a_8__n AS_000_i N_342_i \
pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i \
a_6__n a_i_29__n N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i \
pos_clk_un9_bg_030_n a_i_28__n cpu_est_2_0_2__n a_4__n a_i_25__n N_338_i \
a_i_26__n N_339_i a_3__n N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n \
N_215_i N_336_i pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i \
DS_000_DMA_i N_96_0 un4_as_000_i N_330_i AS_000_INT_i N_90_0 un4_lds_000_i \
N_328_i un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 \
RW_000_c N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n \
LDS_000_c un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 N_310_i size_c_1__n \
N_305_i N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 \
N_278_i N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 \
pos_clk_un8_sm_amiga_i_n N_27 A0_c_i N_28 size_c_i_1__n N_29 N_29_i N_32_0 \
N_28_i N_31_0 N_27_i N_30_0 ipl_c_i_2__n N_53_0 ipl_c_i_1__n N_52_0 a_c_16__n \
ipl_c_i_0__n N_51_0 a_c_17__n DTACK_c_i N_56_0 a_c_18__n VPA_c_i N_55_0 \
@ -379,7 +379,7 @@ a_c_19__n nEXP_SPACE_c_i N_54_0 a_c_20__n N_3_i N_49_0 a_c_21__n N_8_i N_45_0 \
a_c_22__n N_17_i N_42_0 a_c_23__n N_19_i N_40_0 a_c_24__n N_20_i N_123 N_39_0 \
cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i \
N_37_0 a_c_27__n N_25_i N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \
BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un8_bg_030_0_n N_80 \
BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \
N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \
pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 \
N_138 nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 \
@ -423,10 +423,8 @@ pos_clk_size_dma_6_0__n N_207_0 sm_amiga_srsts_i_0_m2_5__un0_n N_298 N_354_i \
cpu_est_0_1__un3_n N_281 N_208_0 cpu_est_0_1__un1_n AS_030.OE AS_000.OE \
RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE \
DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_134 G_135 G_136 \
pos_clk_un24_bgack_030_int_i_i_a4_i_x2 pos_clk_CYCLE_DMA_5_0_i_x2 \
pos_clk_un23_bgack_030_int_i_i_a4_i_x2 pos_clk_CYCLE_DMA_5_0_i_x2 \
cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2
.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D
11 1
.names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D
11 1
.names N_137_i_1.BLIF N_137_i_2.BLIF SM_AMIGA_3_.D
@ -453,6 +451,8 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2
11 1
.names N_258_0.BLIF SM_AMIGA_6_.D
0 1
.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D
11 1
.names N_282_i_1.BLIF N_210_0.BLIF CYCLE_DMA_0_.D
11 1
.names N_134_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D
@ -476,14 +476,10 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2
11 1
.names N_259_i_1.BLIF N_259_i_2.BLIF RST_DLY_2_.D
11 1
.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D
.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D
11 1
.names N_261_i_1.BLIF N_322_i.BLIF RST_DLY_0_.D
11 1
.names N_45_0.BLIF inst_AS_000_DMA.D
0 1
.names N_46_0.BLIF inst_AS_030_000_SYNC.D
0 1
.names N_47_0.BLIF inst_AS_000_INT.D
0 1
.names N_48_0.BLIF inst_DSACK1_INTreg.D
@ -524,6 +520,10 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2
0 1
.names N_43_0.BLIF inst_BGACK_030_INTreg.D
0 1
.names N_45_0.BLIF inst_AS_000_DMA.D
0 1
.names N_46_0.BLIF inst_AS_030_000_SYNC.D
0 1
.names N_210_0.BLIF inst_BGACK_030_INT_D.D
0 1
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
@ -726,13 +726,13 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n
0 1
.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_212_0
11 1
.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n
.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n
0 1
.names inst_CLK_000_PE.BLIF CLK_000_PE_i
0 1
.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_211_0
11 1
.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n
.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n
11 1
.names a_c_16__n.BLIF a_i_16__n
0 1
@ -846,17 +846,17 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n
11 1
.names RST_DLY_1_.BLIF rst_dly_i_1__n
0 1
.names inst_CLK_000_D0.BLIF CLK_000_D0_i
.names CLK_000_D_0_.BLIF clk_000_d_i_0__n
0 1
.names inst_CLK_000_D1.BLIF CLK_000_D1_i
.names CLK_000_D_1_.BLIF clk_000_d_i_1__n
0 1
.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_148_i
.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_148_i
11 1
.names inst_DTACK_D0.BLIF DTACK_D0_i
0 1
.names N_345.BLIF N_345_i
0 1
.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n
.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n
11 1
.names RW_000_c.BLIF RW_000_i
0 1
@ -902,7 +902,7 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n
0 1
.names N_361.BLIF N_361_i
0 1
.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n
.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n
0 1
.names a_c_28__n.BLIF a_i_28__n
0 1
@ -1140,7 +1140,7 @@ pos_clk_un8_sm_amiga_i_n
11 1
.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n
0 1
.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n
.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n
11 1
.names N_80_0.BLIF N_80
0 1
@ -1174,7 +1174,7 @@ pos_clk_un8_sm_amiga_i_n
11 1
.names N_144_0.BLIF N_144
0 1
.names pos_clk_un24_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2
.names pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2
11 1
.names N_158_i.BLIF N_158
0 1
@ -1663,7 +1663,7 @@ sm_amiga_srsts_i_0_m2_5__un0_n
11 0
00 0
.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
pos_clk_un24_bgack_030_int_i_i_a4_i_x2
pos_clk_un23_bgack_030_int_i_i_a4_i_x2
01 1
10 1
11 0
@ -1740,9 +1740,6 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2
.names IPL_030DFF_0_reg.BLIF IPL_030_0_
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
1 1
0 0
@ -1782,10 +1779,7 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2
.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
1 1
0 0
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C
.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
1 1
0 0
.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
@ -1911,12 +1905,30 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C
1 1
0 0
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C
1 1
0 0
.names CLK_OSZI_c.BLIF RST_DLY_1_.C
1 1
0 0
.names CLK_OSZI_c.BLIF RST_DLY_2_.C
1 1
0 0
.names CLK_000.BLIF CLK_000_D_0_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_D_0_.C
1 1
0 0
.names CLK_000_D_0_.BLIF CLK_000_D_1_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_D_1_.C
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C
1 1
0 0
@ -1947,12 +1959,6 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2
.names CLK_OSZI_c.BLIF RST_DLY_0_.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
1 1
0 0
@ -2013,18 +2019,15 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2
.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
1 1
0 0
.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D
1 1
0 0
@ -2043,12 +2046,6 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2
.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names CLK_000.BLIF inst_CLK_000_D0.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
1 1
0 0
.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D
1 1
0 0
@ -2061,6 +2058,9 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2
.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names un3_size.BLIF SIZE_1_
1 1
0 0

257
Logic/68030_tk.bl3
View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
#$ DATE Wed Jan 27 21:56:48 2016
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 17 17:45:46 2016
#$ MODULE 68030_tk
#$ PINS 61 SIZE_1_ A_31_ IPL_030_2_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ \
# AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 \
@ -12,7 +12,7 @@
# inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D \
# inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ \
# inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 \
# inst_RESET_OUT inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE \
# inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE \
# CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ \
# inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg \
# SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ \
@ -37,8 +37,8 @@ inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_UDS_000_INT.BLIF \
inst_LDS_000_INT.BLIF inst_CLK_OUT_PRE_D.BLIF inst_DTACK_D0.BLIF \
inst_RESET_OUT.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_000_D1.BLIF \
inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF CLK_000_P_SYNC_9_.BLIF \
inst_RESET_OUT.BLIF inst_CLK_OUT_PRE_50.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF inst_CLK_000_PE.BLIF CLK_000_P_SYNC_9_.BLIF \
inst_CLK_000_NE.BLIF CLK_000_N_SYNC_11_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF \
IPL_D0_2_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF SM_AMIGA_4_.BLIF \
@ -58,63 +58,52 @@ RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C \
SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C \
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \
IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \
IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \
IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \
CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \
CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D \
CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \
SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \
cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \
CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \
CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \
CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \
CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \
CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \
CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \
CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \
CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \
CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \
CLK_000_N_SYNC_8_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \
SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \
SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \
IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \
IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \
SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \
SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \
CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \
CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \
cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \
CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \
CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \
CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \
CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \
CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \
CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \
CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \
CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \
CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \
CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \
CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \
CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \
CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \
CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_DMA.D \
CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D \
inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \
inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \
inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \
inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C \
inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \
inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \
inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C \
inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \
inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \
inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \
inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \
inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \
inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D \
inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \
BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \
inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \
inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D \
inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C \
inst_CLK_000_NE.D inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 \
LDS_000 A0 BERR RW SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \
LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE \
RESET.OE CIIN.OE inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 \
SM_AMIGA_3_.D.X2
.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
101-1- 1
11-0-1 1
11--11 1
---10- 0
-00--- 0
-0--0- 0
-1---0 0
0----- 0
inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D \
inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \
CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_PE.D inst_CLK_000_PE.C \
inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \
inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW \
SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \
SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE \
inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2
.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
SM_AMIGA_4_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D
1-0-11 1
@ -281,8 +270,8 @@ SM_AMIGA_i_7_.D
0------------------- 0
-------------1-----0 0
.names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_6_.BLIF \
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D
11010--0- 1
1----01-1 1
1-----10- 1
@ -294,6 +283,16 @@ SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D
------01- 0
0-------- 0
-------10 0
.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
101-1- 1
11-0-1 1
11--11 1
---10- 0
-00--- 0
-0--0- 0
-1---0 0
0----- 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF \
inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D
10100 1
@ -379,7 +378,7 @@ RST_DLY_2_.BLIF RST_DLY_2_.D
---00 0
--0-0 0
-0--0 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF CLK_000_P_SYNC_0_.D
.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_P_SYNC_0_.D
01 1
1- 0
-0 0
@ -392,43 +391,6 @@ RST_DLY_2_.BLIF RST_DLY_0_.D
-00-- 0
-11-0 0
0---- 0
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
LDS_000.PIN.BLIF inst_AS_000_DMA.D
----00--- 1
----11--- 1
0--1----- 1
------1-- 1
--1------ 1
-0------- 1
-------11 1
-1001000- 0
110-1000- 0
-1000100- 0
110-0100- 0
-100100-0 0
110-100-0 0
-100010-0 0
110-010-0 0
.names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \
inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D
1-00101---1--- 1
----------1-1- 1
----------10-- 1
---------01--- 1
-------0--1--- 1
--------1----- 1
-0------------ 1
-------------0 1
-1----0101-101 0
-1---1-101-101 0
-1--0--101-101 0
-1-1---101-101 0
-11----101-101 0
01-----101-101 0
-1------0-0--1 0
.names RST.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF \
BERR.PIN.BLIF inst_AS_000_INT.D
-10-- 1
@ -533,7 +495,7 @@ SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D
--1-1------ 0
0---------- 0
.names BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF \
inst_CLK_000_D0.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
----01 1
---0-1 1
--0--1 1
@ -625,6 +587,43 @@ AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
-100- 0
-10-0 0
01--- 0
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
LDS_000.PIN.BLIF inst_AS_000_DMA.D
----00--- 1
----11--- 1
0--1----- 1
------1-- 1
--1------ 1
-0------- 1
-------11 1
-1001000- 0
110-1000- 0
-1000100- 0
110-0100- 0
-100100-0 0
110-100-0 0
-100010-0 0
110-010-0 0
.names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \
inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D
1-00101---1--- 1
----------1-1- 1
----------10-- 1
---------01--- 1
-------0--1--- 1
--------1----- 1
-0------------ 1
-------------0 1
-1----0101-101 0
-1---1-101-101 0
-1--0--101-101 0
-1-1---101-101 0
-11----101-101 0
01-----101-101 0
-1------0-0--1 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
0- 1
-1 1
@ -633,7 +632,7 @@ AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
0 1
1 0
.names SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_317_i
-1010------ 1
---------1- 1
@ -738,9 +737,6 @@ inst_AS_030_D0.BLIF CIIN
.names IPL_030DFF_0_reg.BLIF IPL_030_0_
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
1 1
0 0
@ -780,10 +776,7 @@ inst_AS_030_D0.BLIF CIIN
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
1 1
0 0
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
1 1
0 0
.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
@ -857,7 +850,7 @@ inst_AS_030_D0.BLIF CIIN
.names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C
1 1
0 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF CLK_000_N_SYNC_0_.D
.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_N_SYNC_0_.D
10 1
0- 0
-1 0
@ -912,12 +905,30 @@ inst_AS_030_D0.BLIF CIIN
.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C
1 1
0 0
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C
1 1
0 0
.names CLK_OSZI.BLIF RST_DLY_1_.C
1 1
0 0
.names CLK_OSZI.BLIF RST_DLY_2_.C
1 1
0 0
.names CLK_000.BLIF CLK_000_D_0_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_0_.C
1 1
0 0
.names CLK_000_D_0_.BLIF CLK_000_D_1_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_1_.C
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C
1 1
0 0
@ -948,12 +959,6 @@ inst_AS_030_D0.BLIF CIIN
.names CLK_OSZI.BLIF RST_DLY_0_.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_000_INT.C
1 1
0 0
@ -1014,18 +1019,15 @@ inst_AS_030_D0.BLIF CIIN
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D1.C
1 1
0 0
.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D
1 1
0 0
@ -1044,12 +1046,6 @@ inst_AS_030_D0.BLIF CIIN
.names CLK_OSZI.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names CLK_000.BLIF inst_CLK_000_D0.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D0.C
1 1
0 0
.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D
1 1
0 0
@ -1062,6 +1058,9 @@ inst_AS_030_D0.BLIF CIIN
.names CLK_OSZI.BLIF inst_CLK_000_NE.C
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_1_
01 1
1- 0

4
Logic/68030_tk.crf
View File

@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 1.8.00.04.29.14
// ispLEVER Classic 2.0.00.17.20.15
// Design '68030_tk' created Wed Jan 27 21:56:48 2016
// Design '68030_tk' created Wed Aug 17 17:45:46 2016
// LEGEND: '>' Functional Block Port Separator

34
Logic/68030_tk.eq3
View File

@ -1,8 +1,8 @@
ispLEVER Classic 1.8.00.04.29.14 Linked Equations File
Copyright(C), 1992-2014, Lattice Semiconductor Corp.
ispLEVER Classic 2.0.00.17.20.15 Linked Equations File
Copyright(C), 1992-2015, Lattice Semiconductor Corp.
All Rights Reserved.
Design bus68030 created Wed Jan 27 21:56:48 2016
Design bus68030 created Wed Aug 17 17:45:46 2016
P-Terms Fan-in Fan-out Type Name (attributes)
@ -111,10 +111,10 @@ Design bus68030 created Wed Jan 27 21:56:48 2016
1 1 1 Node inst_RESET_OUT.C
1 1 1 Node inst_CLK_OUT_PRE_50.D
1 1 1 Node inst_CLK_OUT_PRE_50.C
1 1 1 Node inst_CLK_000_D1.D
1 1 1 Node inst_CLK_000_D1.C
1 1 1 Node inst_CLK_000_D0.D
1 1 1 Node inst_CLK_000_D0.C
1 1 1 Node CLK_000_D_1_.D
1 1 1 Node CLK_000_D_1_.C
1 1 1 Node CLK_000_D_0_.D
1 1 1 Node CLK_000_D_0_.C
1 1 1 Node inst_CLK_000_PE.D
1 1 1 Node inst_CLK_000_PE.C
1 1 1 Node CLK_000_P_SYNC_9_.D
@ -324,7 +324,7 @@ A0.D = (!RST
A0.C = (CLK_OSZI);
!BG_000.D = (!BG_030 & RST & !BG_000.Q
# !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q);
# !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & CLK_000_D_0_.Q);
BG_000.C = (CLK_OSZI);
@ -362,8 +362,8 @@ RW.C = (CLK_OSZI);
!N_317_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
# !SM_AMIGA_5_.Q & !CLK_000_D_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q
# cpu_est_2_.Q & !cpu_est_1_.Q
@ -504,13 +504,13 @@ inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
CLK_000_D_1_.D = (CLK_000_D_0_.Q);
inst_CLK_000_D1.C = (CLK_OSZI);
CLK_000_D_1_.C = (CLK_OSZI);
inst_CLK_000_D0.D = (CLK_000);
CLK_000_D_0_.D = (CLK_000);
inst_CLK_000_D0.C = (CLK_OSZI);
CLK_000_D_0_.C = (CLK_OSZI);
inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);
@ -586,7 +586,7 @@ RST_DLY_2_.D = (RST & RST_DLY_2_.Q
RST_DLY_2_.C = (CLK_OSZI);
CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q);
CLK_000_P_SYNC_0_.D = (!CLK_000_D_1_.Q & CLK_000_D_0_.Q);
CLK_000_P_SYNC_0_.C = (CLK_OSZI);
@ -622,7 +622,7 @@ CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
CLK_000_P_SYNC_8_.C = (CLK_OSZI);
CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q);
CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
CLK_000_N_SYNC_0_.C = (CLK_OSZI);
@ -668,7 +668,7 @@ CLK_000_N_SYNC_10_.C = (CLK_OSZI);
SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
# RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q);
# RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q);
SM_AMIGA_6_.C = (CLK_OSZI);

12
Logic/68030_tk.fti
View File

@ -36,6 +36,8 @@ DATA LOCATION BG_030:C_*_21 // INP
DATA LOCATION CIIN:E_12_47 // OUT
DATA LOCATION CIIN_0:E_5 // NOD
DATA LOCATION CLK_000:*_*_11 // INP
DATA LOCATION CLK_000_D_0_:B_9 // NOD
DATA LOCATION CLK_000_D_1_:E_8 // NOD
DATA LOCATION CLK_000_N_SYNC_0_:E_9 // NOD
DATA LOCATION CLK_000_N_SYNC_10_:H_2 // NOD
DATA LOCATION CLK_000_N_SYNC_11_:H_6 // NOD
@ -126,8 +128,6 @@ DATA LOCATION inst_AS_000_INT:C_1 // NOD
DATA LOCATION inst_AS_030_000_SYNC:C_4 // NOD
DATA LOCATION inst_AS_030_D0:H_3 // NOD
DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD
DATA LOCATION inst_CLK_000_D0:B_9 // NOD
DATA LOCATION inst_CLK_000_D1:E_8 // NOD
DATA LOCATION inst_CLK_000_NE:G_2 // NOD
DATA LOCATION inst_CLK_000_NE_D0:D_10 // NOD
DATA LOCATION inst_CLK_000_PE:G_5 // NOD
@ -371,10 +371,10 @@ DATA PW_LEVEL inst_RESET_OUT:1
DATA SLEW inst_RESET_OUT:1
DATA PW_LEVEL inst_CLK_OUT_PRE_50:1
DATA SLEW inst_CLK_OUT_PRE_50:1
DATA PW_LEVEL inst_CLK_000_D1:1
DATA SLEW inst_CLK_000_D1:1
DATA PW_LEVEL inst_CLK_000_D0:1
DATA SLEW inst_CLK_000_D0:1
DATA PW_LEVEL CLK_000_D_1_:1
DATA SLEW CLK_000_D_1_:1
DATA PW_LEVEL CLK_000_D_0_:1
DATA SLEW CLK_000_D_0_:1
DATA PW_LEVEL inst_CLK_000_PE:1
DATA SLEW inst_CLK_000_PE:1
DATA PW_LEVEL CLK_000_P_SYNC_9_:1

4
Logic/68030_tk.grp
View File

@ -5,7 +5,7 @@ GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_LDS_000_INT
GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
RN_IPL_030_2_ CLK_EXP inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH
CYCLE_DMA_0_ inst_DTACK_D0 IPL_D0_2_ inst_CLK_000_D0 CLK_000_P_SYNC_1_
CYCLE_DMA_0_ inst_DTACK_D0 IPL_D0_2_ CLK_000_D_0_ CLK_000_P_SYNC_1_
CLK_000_P_SYNC_7_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_
RESET
GROUP MACH_SEG_C inst_AS_030_000_SYNC inst_DS_000_ENABLE CYCLE_DMA_1_ inst_AS_000_INT
@ -15,7 +15,7 @@ GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 inst_RESET_OUT RST_DLY_0_
CLK_000_N_SYNC_5_ inst_CLK_000_NE_D0 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH
AMIGA_ADDR_ENABLE
GROUP MACH_SEG_E CLK_000_P_SYNC_0_ CLK_000_N_SYNC_0_ CLK_000_P_SYNC_3_
inst_CLK_000_D1 CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0
CLK_000_D_1_ CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0
GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_6_ SM_AMIGA_1_
SM_AMIGA_0_ SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_3_ inst_VPA_D CLK_000_N_SYNC_7_
inst_CLK_OUT_PRE_50 N_317_i

2
Logic/68030_tk.ipr
View File

@ -1 +1 @@
<LATTICE_ENCRYPTED_BLIF>910;6<5r } [
<LATTICE_ENCRYPTED_BLIF>755;017}nxñA.c

1114
Logic/68030_tk.jed Normal file
View File

File diff suppressed because it is too large Load Diff

8
Logic/68030_tk.lco
View File

@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = 68030_tk.tt4;
DATE = 1/27/16;
TIME = 21:56:53;
DATE = 8/17/16;
TIME = 17:45:51;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;
@ -162,8 +162,8 @@ inst_CLK_OUT_PRE_D = node,-,-,A,12;
inst_DTACK_D0 = node,-,-,B,15;
inst_RESET_OUT = node,-,-,D,9;
inst_CLK_OUT_PRE_50 = node,-,-,F,13;
inst_CLK_000_D1 = node,-,-,E,8;
inst_CLK_000_D0 = node,-,-,B,9;
CLK_000_D_1_ = node,-,-,E,8;
CLK_000_D_0_ = node,-,-,B,9;
inst_CLK_000_PE = node,-,-,G,5;
CLK_000_P_SYNC_9_ = node,-,-,G,15;
inst_CLK_000_NE = node,-,-,G,2;

1959
Logic/68030_tk.out
View File

File diff suppressed because it is too large Load Diff

8
Logic/68030_tk.plc
View File

@ -1,6 +1,6 @@
|--------------------------------------------|
|- ispLEVER Fitter Report File -|
|- Version 1.8.00.04.29.14 -|
|- Version 2.0.00.17.20.15 -|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|--------------------------------------------|
@ -8,7 +8,7 @@
; Source file 68030_tk.tt4
; FITTER-generated Placements.
; DEVICE mach447a
; DATE Wed Jan 27 21:56:53 2016
; DATE Wed Aug 17 17:45:51 2016
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287
@ -114,8 +114,8 @@ Node 119 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
Node 148 inst_DTACK_D0 Reg ; S6=1 S9=1
Node 187 inst_RESET_OUT Reg ; S6=1 S9=1
Node 241 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
Node 209 inst_CLK_000_D1 Reg ; S6=1 S9=1
Node 139 inst_CLK_000_D0 Reg ; S6=1 S9=1
Node 209 CLK_000_D_1_ Reg ; S6=1 S9=1
Node 139 CLK_000_D_0_ Reg ; S6=1 S9=1
Node 253 inst_CLK_000_PE Reg ; S6=1 S9=1
Node 268 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1
Node 248 inst_CLK_000_NE Reg ; S6=1 S9=1

220
Logic/68030_tk.prd
View File

@ -1,14 +1,14 @@
|--------------------------------------------|
|- ispLEVER Fitter Report File -|
|- Version 1.8.00.04.29.14 -|
|- Version 2.0.00.17.20.15 -|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|--------------------------------------------|
Start: Wed Jan 27 21:56:53 2016
End : Wed Jan 27 21:56:53 2016 $$$ Elapsed time: 00:00:00
Start: Wed Aug 17 17:45:51 2016
End : Wed Aug 17 17:45:51 2016 $$$ Elapsed time: 00:00:00
===========================================================================
Part [C:/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4]
Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4]
* Place/Route options (keycode = 540674)
= Spread Placement: ON
@ -93,115 +93,115 @@ ___|__|__|____|____________________________________________________________
31| 4|OUT| 47|=> ....|....| CIIN
32| 4|NOD| . |=> ....|4...| CIIN_0
33| +|INP| 11|=> .1..|....| CLK_000
34| 4|NOD| . |=> 0...|....| CLK_000_N_SYNC_0_
35| 7|NOD| . |=> ....|...7| CLK_000_N_SYNC_10_
36| 7|NOD| . |=> ....|..6.| CLK_000_N_SYNC_11_
37| 0|NOD| . |=> .1..|....| CLK_000_N_SYNC_1_
38| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_2_
39| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_3_
40| 1|NOD| . |=> ...3|....| CLK_000_N_SYNC_4_
41| 3|NOD| . |=> ....|..6.| CLK_000_N_SYNC_5_
42| 6|NOD| . |=> ....|.5..| CLK_000_N_SYNC_6_
43| 5|NOD| . |=> 0...|....| CLK_000_N_SYNC_7_
44| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_8_
45| 0|NOD| . |=> ....|...7| CLK_000_N_SYNC_9_
46| 4|NOD| . |=> .1..|....| CLK_000_P_SYNC_0_
47| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_1_
48| 6|NOD| . |=> ....|4...| CLK_000_P_SYNC_2_
49| 4|NOD| . |=> ....|..6.| CLK_000_P_SYNC_3_
50| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_4_
51| 6|NOD| . |=> 0...|....| CLK_000_P_SYNC_5_
52| 0|NOD| . |=> .1..|....| CLK_000_P_SYNC_6_
53| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_7_
54| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_8_
55| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_9_
56| +|INP| 64|=> 0...|...7| CLK_030
57| 6|OUT| 65|=> ....|....| CLK_DIV_OUT
58| 1|OUT| 10|=> ....|....| CLK_EXP
59| +|Cin| 61|=> ....|....| CLK_OSZI
60| 1|NOD| . |=> 012.|....| CYCLE_DMA_0_
61| 2|NOD| . |=> 0.2.|....| CYCLE_DMA_1_
62| 7| IO| 81|=> ....|....| DSACK1
34| 1|NOD| . |=> ...3|45..| CLK_000_D_0_
35| 4|NOD| . |=> ....|45..| CLK_000_D_1_
36| 4|NOD| . |=> 0...|....| CLK_000_N_SYNC_0_
37| 7|NOD| . |=> ....|...7| CLK_000_N_SYNC_10_
38| 7|NOD| . |=> ....|..6.| CLK_000_N_SYNC_11_
39| 0|NOD| . |=> .1..|....| CLK_000_N_SYNC_1_
40| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_2_
41| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_3_
42| 1|NOD| . |=> ...3|....| CLK_000_N_SYNC_4_
43| 3|NOD| . |=> ....|..6.| CLK_000_N_SYNC_5_
44| 6|NOD| . |=> ....|.5..| CLK_000_N_SYNC_6_
45| 5|NOD| . |=> 0...|....| CLK_000_N_SYNC_7_
46| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_8_
47| 0|NOD| . |=> ....|...7| CLK_000_N_SYNC_9_
48| 4|NOD| . |=> .1..|....| CLK_000_P_SYNC_0_
49| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_1_
50| 6|NOD| . |=> ....|4...| CLK_000_P_SYNC_2_
51| 4|NOD| . |=> ....|..6.| CLK_000_P_SYNC_3_
52| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_4_
53| 6|NOD| . |=> 0...|....| CLK_000_P_SYNC_5_
54| 0|NOD| . |=> .1..|....| CLK_000_P_SYNC_6_
55| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_7_
56| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_8_
57| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_9_
58| +|INP| 64|=> 0...|...7| CLK_030
59| 6|OUT| 65|=> ....|....| CLK_DIV_OUT
60| 1|OUT| 10|=> ....|....| CLK_EXP
61| +|Cin| 61|=> ....|....| CLK_OSZI
62| 1|NOD| . |=> 012.|....| CYCLE_DMA_0_
63| 2|NOD| . |=> 0.2.|....| CYCLE_DMA_1_
64| 7| IO| 81|=> ....|....| DSACK1
|=> Paired w/: RN_DSACK1
63| 0|OUT| 98|=> ....|....| DS_030
64| 3|INP| 30|=> .1..|....| DTACK
65| 6|OUT| 66|=> ....|....| E
66| 5|INP| 57|=> ..2.|4..7| FC_0_
67| 5|INP| 58|=> ..2.|4..7| FC_1_
68| 7|OUT| 78|=> ....|....| FPU_CS
69| 0|INP| 91|=> ....|4..7| FPU_SENSE
70| 1| IO| 8|=> ....|....| IPL_030_0_
65| 0|OUT| 98|=> ....|....| DS_030
66| 3|INP| 30|=> .1..|....| DTACK
67| 6|OUT| 66|=> ....|....| E
68| 5|INP| 57|=> ..2.|4..7| FC_0_
69| 5|INP| 58|=> ..2.|4..7| FC_1_
70| 7|OUT| 78|=> ....|....| FPU_CS
71| 0|INP| 91|=> ....|4..7| FPU_SENSE
72| 1| IO| 8|=> ....|....| IPL_030_0_
|=> Paired w/: RN_IPL_030_0_
71| 1| IO| 7|=> ....|....| IPL_030_1_
73| 1| IO| 7|=> ....|....| IPL_030_1_
|=> Paired w/: RN_IPL_030_1_
72| 1| IO| 9|=> ....|....| IPL_030_2_
74| 1| IO| 9|=> ....|....| IPL_030_2_
|=> Paired w/: RN_IPL_030_2_
73| 6|INP| 67|=> .1..|..6.| IPL_0_
74| 5|INP| 56|=> .1.3|....| IPL_1_
75| 6|INP| 68|=> .1..|....| IPL_2_
76| 6|NOD| . |=> .1..|....| IPL_D0_0_
77| 3|NOD| . |=> .1..|....| IPL_D0_1_
78| 1|NOD| . |=> .1..|....| IPL_D0_2_
79| 3| IO| 31|=> 0...|..6.| LDS_000
80| 5|NOD| . |=> ....|.5..| N_317_i
81| 1|OUT| 3|=> ....|....| RESET
82| 6|NOD| . |=> ....|..6.| RN_A0
75| 6|INP| 67|=> .1..|..6.| IPL_0_
76| 5|INP| 56|=> .1.3|....| IPL_1_
77| 6|INP| 68|=> .1..|....| IPL_2_
78| 6|NOD| . |=> .1..|....| IPL_D0_0_
79| 3|NOD| . |=> .1..|....| IPL_D0_1_
80| 1|NOD| . |=> .1..|....| IPL_D0_2_
81| 3| IO| 31|=> 0...|..6.| LDS_000
82| 5|NOD| . |=> ....|.5..| N_317_i
83| 1|OUT| 3|=> ....|....| RESET
84| 6|NOD| . |=> ....|..6.| RN_A0
|=> Paired w/: A0
83| 7|NOD| . |=> 0123|4.67| RN_BGACK_030
85| 7|NOD| . |=> 0123|4.67| RN_BGACK_030
|=> Paired w/: BGACK_030
84| 3|NOD| . |=> ...3|....| RN_BG_000
86| 3|NOD| . |=> ...3|....| RN_BG_000
|=> Paired w/: BG_000
85| 7|NOD| . |=> ....|...7| RN_DSACK1
87| 7|NOD| . |=> ....|...7| RN_DSACK1
|=> Paired w/: DSACK1
86| 1|NOD| . |=> .1..|....| RN_IPL_030_0_
88| 1|NOD| . |=> .1..|....| RN_IPL_030_0_
|=> Paired w/: IPL_030_0_
87| 1|NOD| . |=> .1..|....| RN_IPL_030_1_
89| 1|NOD| . |=> .1..|....| RN_IPL_030_1_
|=> Paired w/: IPL_030_1_
88| 1|NOD| . |=> .1..|....| RN_IPL_030_2_
90| 1|NOD| . |=> .1..|....| RN_IPL_030_2_
|=> Paired w/: IPL_030_2_
89| 6|NOD| . |=> ....|..6.| RN_RW
91| 6|NOD| . |=> ....|..6.| RN_RW
|=> Paired w/: RW
90| 7|NOD| . |=> ....|...7| RN_RW_000
92| 7|NOD| . |=> ....|...7| RN_RW_000
|=> Paired w/: RW_000
91| 3|NOD| . |=> ...3|.5..| RN_VMA
93| 3|NOD| . |=> ...3|.5..| RN_VMA
|=> Paired w/: VMA
92| +|INP| 86|=> 0123|.567| RST
93| 3|NOD| . |=> ...3|....| RST_DLY_0_
94| 3|NOD| . |=> ...3|....| RST_DLY_1_
95| 3|NOD| . |=> ...3|....| RST_DLY_2_
96| 6| IO| 71|=> ..2.|...7| RW
94| +|INP| 86|=> 0123|.567| RST
95| 3|NOD| . |=> ...3|....| RST_DLY_0_
96| 3|NOD| . |=> ...3|....| RST_DLY_1_
97| 3|NOD| . |=> ...3|....| RST_DLY_2_
98| 6| IO| 71|=> ..2.|...7| RW
|=> Paired w/: RN_RW
97| 7| IO| 80|=> 0...|4.6.| RW_000
99| 7| IO| 80|=> 0...|4.6.| RW_000
|=> Paired w/: RN_RW_000
98| 6| IO| 70|=> 0...|....| SIZE_0_
99| 7| IO| 79|=> 0...|....| SIZE_1_
100| 6|NOD| . |=> ....|..67| SIZE_DMA_0_
101| 6|NOD| . |=> ....|..67| SIZE_DMA_1_
102| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_0_
103| 5|NOD| . |=> ....|.5.7| SM_AMIGA_1_
104| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_
105| 5|NOD| . |=> ....|.5..| SM_AMIGA_3_
106| 5|NOD| . |=> ..2.|.5..| SM_AMIGA_4_
107| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_5_
108| 5|NOD| . |=> 0.2.|.5..| SM_AMIGA_6_
109| 5|NOD| . |=> ..23|.5.7| SM_AMIGA_i_7_
110| 3| IO| 32|=> 0...|..6.| UDS_000
111| 3| IO| 35|=> ....|....| VMA
100| 6| IO| 70|=> 0...|....| SIZE_0_
101| 7| IO| 79|=> 0...|....| SIZE_1_
102| 6|NOD| . |=> ....|..67| SIZE_DMA_0_
103| 6|NOD| . |=> ....|..67| SIZE_DMA_1_
104| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_0_
105| 5|NOD| . |=> ....|.5.7| SM_AMIGA_1_
106| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_
107| 5|NOD| . |=> ....|.5..| SM_AMIGA_3_
108| 5|NOD| . |=> ..2.|.5..| SM_AMIGA_4_
109| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_5_
110| 5|NOD| . |=> 0.2.|.5..| SM_AMIGA_6_
111| 5|NOD| . |=> ..23|.5.7| SM_AMIGA_i_7_
112| 3| IO| 32|=> 0...|..6.| UDS_000
113| 3| IO| 35|=> ....|....| VMA
|=> Paired w/: RN_VMA
112| +|INP| 36|=> ....|.5..| VPA
113| 3|NOD| . |=> ...3|.5..| cpu_est_0_
114| 3|NOD| . |=> ...3|.56.| cpu_est_1_
115| 3|NOD| . |=> ...3|.56.| cpu_est_2_
116| 5|NOD| . |=> ...3|.56.| cpu_est_3_
117| 1|NOD| . |=> .1.3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH
118| 1|NOD| . |=> .12.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW
119| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA
120| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT
121| 2|NOD| . |=> ..2.|.5..| inst_AS_030_000_SYNC
122| 7|NOD| . |=> ..23|4..7| inst_AS_030_D0
123| 7|NOD| . |=> .12.|..6.| inst_BGACK_030_INT_D
124| 1|NOD| . |=> ...3|45..| inst_CLK_000_D0
125| 4|NOD| . |=> ....|45..| inst_CLK_000_D1
114| +|INP| 36|=> ....|.5..| VPA
115| 3|NOD| . |=> ...3|.5..| cpu_est_0_
116| 3|NOD| . |=> ...3|.56.| cpu_est_1_
117| 3|NOD| . |=> ...3|.56.| cpu_est_2_
118| 5|NOD| . |=> ...3|.56.| cpu_est_3_
119| 1|NOD| . |=> .1.3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH
120| 1|NOD| . |=> .12.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW
121| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA
122| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT
123| 2|NOD| . |=> ..2.|.5..| inst_AS_030_000_SYNC
124| 7|NOD| . |=> ..23|4..7| inst_AS_030_D0
125| 7|NOD| . |=> .12.|..6.| inst_BGACK_030_INT_D
126| 6|NOD| . |=> ...3|.5..| inst_CLK_000_NE
127| 3|NOD| . |=> ...3|.5..| inst_CLK_000_NE_D0
128| 6|NOD| . |=> .123|.5.7| inst_CLK_000_PE
@ -219,7 +219,7 @@ ___|__|__|____|____________________________________________________________
140| +|INP| 14|=> 0...|....| nEXP_SPACE
---------------------------------------------------------------------------
===========================================================================
< C:/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments >
< E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a Device Pin Assignments >
===========================================================================
+- Device Pin No
| Pin Type +- Signal Fixed (*)
@ -549,7 +549,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
6|CLK_000_N_SYNC_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig
7|CLK_000_P_SYNC_1_|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 7] for 1 PT sig
8| IPL_030_0_| IO| | S |10 | 4 to [ 8]| 1 XOR to [ 8] as logic PT
9|inst_CLK_000_D0|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig
9| CLK_000_D_0_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig
10|CLK_000_N_SYNC_3_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [10] for 1 PT sig
11| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig
12| IPL_030_1_| IO| | S |10 | 4 to [12]| 1 XOR to [12] as logic PT
@ -576,7 +576,7 @@ _|_________________|__|__|___|_____|_______________________________________
6|CLK_000_N_SYNC_4_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s)
7|CLK_000_P_SYNC_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s)
8| IPL_030_0_| IO| | S |10 |=> can support up to [ 13] logic PT(s)
9|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 5] logic PT(s)
9| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s)
10|CLK_000_N_SYNC_3_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s)
11| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s)
12| IPL_030_1_| IO| | S |10 |=> can support up to [ 18] logic PT(s)
@ -601,7 +601,7 @@ _|_________________|__|_____|____________________|________________________
6|CLK_000_N_SYNC_4_|NOD| | => | 0 1 2 3 | 10 9 8 7
7|CLK_000_P_SYNC_1_|NOD| | => | 0 1 2 3 | 10 9 8 7
8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6
9|inst_CLK_000_D0|NOD| | => | 1 2 3 4 | 9 8 7 6
9| CLK_000_D_0_|NOD| | => | 1 2 3 4 | 9 8 7 6
10|CLK_000_N_SYNC_3_|NOD| | => | 2 3 4 5 | 8 7 6 5
11| IPL_D0_2_|NOD| | => | 2 3 4 5 | 8 7 6 5
12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4
@ -680,7 +680,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
4 [IOpin 4 | 6|INP A_29_|*|*]
[RegIn 4 |138| -| | ]
[MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_]
[MCell 9 |139|NOD inst_CLK_000_D0| |*]
[MCell 9 |139|NOD CLK_000_D_0_| |*]
5 [IOpin 5 | 5|INP A_30_|*|*]
[RegIn 5 |141| -| | ]
@ -1119,7 +1119,7 @@ Mux02| Mcel 3 1 ( 175)| RN_BG_000
Mux03| Mcel 3 2 ( 176)| cpu_est_1_
Mux04| IOPin 2 6 ( 21)| BG_030
Mux05| Mcel 5 0 ( 221)| SM_AMIGA_i_7_
Mux06| Mcel 1 9 ( 139)| inst_CLK_000_D0
Mux06| Mcel 1 9 ( 139)| CLK_000_D_0_
Mux07| Mcel 2 8 ( 161)| inst_DS_000_ENABLE
Mux08| Mcel 3 7 ( 184)| RST_DLY_2_
Mux09| Mcel 3 3 ( 178)| RST_DLY_0_
@ -1165,7 +1165,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
5| CIIN_0|NOD| | S | 2 | 4 to [ 5]| 1 XOR free
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
8|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig
8| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig
9|CLK_000_N_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
@ -1192,7 +1192,7 @@ _|_________________|__|__|___|_____|_______________________________________
5| CIIN_0|NOD| | S | 2 |=> can support up to [ 19] logic PT(s)
6| | ? | | S | |=> can support up to [ 14] logic PT(s)
7| | ? | | S | |=> can support up to [ 18] logic PT(s)
8|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 19] logic PT(s)
8| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s)
9|CLK_000_N_SYNC_0_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s)
10| | ? | | S | |=> can support up to [ 18] logic PT(s)
11| | ? | | S | |=> can support up to [ 18] logic PT(s)
@ -1217,7 +1217,7 @@ _|_________________|__|_____|____________________|________________________
5| CIIN_0|NOD| | => | 7 0 1 2 | 48 41 42 43
6| | | | => | 0 1 2 3 | 41 42 43 44
7| | | | => | 0 1 2 3 | 41 42 43 44
8|inst_CLK_000_D1|NOD| | => | 1 2 3 4 | 42 43 44 45
8| CLK_000_D_1_|NOD| | => | 1 2 3 4 | 42 43 44 45
9|CLK_000_N_SYNC_0_|NOD| | => | 1 2 3 4 | 42 43 44 45
10| | | | => | 2 3 4 5 | 43 44 45 46
11| | | | => | 2 3 4 5 | 43 44 45 46
@ -1293,7 +1293,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
4 [IOpin 4 | 45| -| | ]
[RegIn 4 |210| -| | ]
[MCell 8 |209|NOD inst_CLK_000_D1| |*]
[MCell 8 |209|NOD CLK_000_D_1_| |*]
[MCell 9 |211|NOD CLK_000_N_SYNC_0_| |*]
5 [IOpin 5 | 46| -| | ]
@ -1323,7 +1323,7 @@ Mux02| IOPin 4 1 ( 42)| AS_000
Mux03| IOPin 2 3 ( 18)| A_25_
Mux04| IOPin 3 7 ( 28)| BGACK_000
Mux05| IOPin 2 4 ( 19)| A_24_
Mux06| Mcel 1 9 ( 139)| inst_CLK_000_D0
Mux06| Mcel 1 9 ( 139)| CLK_000_D_0_
Mux07| IOPin 2 0 ( 15)| A_28_
Mux08| Mcel 6 7 ( 256)| CLK_000_P_SYNC_2_
Mux09| IOPin 7 1 ( 84)| A_22_
@ -1333,7 +1333,7 @@ Mux12| IOPin 0 6 ( 97)| A_19_
Mux13| IOPin 1 4 ( 6)| A_29_
Mux14| Mcel 4 5 ( 205)| CIIN_0
Mux15| IOPin 0 3 ( 94)| A_21_
Mux16| Mcel 4 8 ( 209)| inst_CLK_000_D1
Mux16| Mcel 4 8 ( 209)| CLK_000_D_1_
Mux17| IOPin 2 2 ( 17)| A_26_
Mux18| IOPin 7 0 ( 85)| A_23_
Mux19| IOPin 1 5 ( 5)| A_30_
@ -1529,7 +1529,7 @@ Mux04| Mcel 6 2 ( 248)| inst_CLK_000_NE
Mux05| Mcel 6 6 ( 254)| CLK_000_N_SYNC_6_
Mux06| Mcel 5 13 ( 241)| inst_CLK_OUT_PRE_50
Mux07| ... | ...
Mux08| Mcel 4 8 ( 209)| inst_CLK_000_D1
Mux08| Mcel 4 8 ( 209)| CLK_000_D_1_
Mux09| Mcel 5 2 ( 224)| inst_VPA_D
Mux10| Mcel 5 4 ( 227)| SM_AMIGA_6_
Mux11| Mcel 5 6 ( 230)| SM_AMIGA_3_
@ -1552,7 +1552,7 @@ Mux27| ... | ...
Mux28| ... | ...
Mux29| Mcel 2 4 ( 155)| inst_AS_030_000_SYNC
Mux30| Mcel 3 6 ( 182)| cpu_est_0_
Mux31| Mcel 1 9 ( 139)| inst_CLK_000_D0
Mux31| Mcel 1 9 ( 139)| CLK_000_D_0_
Mux32| Mcel 5 8 ( 233)| SM_AMIGA_5_
---------------------------------------------------------------------------
===========================================================================

56
Logic/68030_tk.rpt
View File

@ -1,6 +1,6 @@
|--------------------------------------------|
|- ispLEVER Fitter Report File -|
|- Version 1.8.00.04.29.14 -|
|- Version 2.0.00.17.20.15 -|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|--------------------------------------------|
@ -12,7 +12,7 @@ Project_Summary
Project Name : 68030_tk
Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
Project Fitted on : Wed Jan 27 21:56:53 2016
Project Fitted on : Wed Aug 17 17:45:51 2016
Device : M4A5-128/64
Package : 100TQFP
@ -394,6 +394,8 @@ Buried_Signal_List
#Mc Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
E5 E 2 COM ----E--- Low Slow CIIN_0
B9 B 1 DFF * * ---DEF-- Low Slow CLK_000_D_0_
E8 E 1 DFF * * ----EF-- Low Slow CLK_000_D_1_
E9 E 1 DFF * * A------- Low Slow CLK_000_N_SYNC_0_
H2 H 1 DFF * * -------H Low Slow CLK_000_N_SYNC_10_
H6 H 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_11_
@ -456,8 +458,6 @@ Buried_Signal_List
C4 C 7 DFF * * --C--F-- Low Slow inst_AS_030_000_SYNC
H3 H 1 DFF * * --CDE--H Low Slow inst_AS_030_D0
H13 H 1 DFF * * -BC---G- Low Slow inst_BGACK_030_INT_D
B9 B 1 DFF * * ---DEF-- Low Slow inst_CLK_000_D0
E8 E 1 DFF * * ----EF-- Low Slow inst_CLK_000_D1
G2 G 1 DFF * * ---D-F-- Low Slow inst_CLK_000_NE
D10 D 1 DFF * * ---D-F-- Low Slow inst_CLK_000_NE_D0
G5 G 1 DFF * * -BCD-F-H Low Slow inst_CLK_000_PE
@ -515,7 +515,7 @@ Signal Source : Fanout List
BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H}
CLK_030{. }: DSACK1{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
: inst_CLK_030_H{ A}
CLK_000{. }:inst_CLK_000_D0{ B}
CLK_000{. }: CLK_000_D_0_{ B}
FPU_SENSE{ B}: BERR{ E} FPU_CS{ H}
DTACK{ E}: inst_DTACK_D0{ B}
VPA{. }: inst_VPA_D{ F}
@ -621,9 +621,9 @@ inst_RESET_OUT{ E}: AS_030{ H} AS_000{ E} DS_030{ A}
: RW_000{ H} A0{ G} RW{ G}
: inst_RESET_OUT{ D}
inst_CLK_OUT_PRE_50{ G}:inst_CLK_OUT_PRE_D{ A}inst_CLK_OUT_PRE_50{ F}
inst_CLK_000_D1{ F}: N_317_i{ F}CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E}
CLK_000_D_1_{ F}: N_317_i{ F}CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E}
: SM_AMIGA_6_{ F}
inst_CLK_000_D0{ C}: BG_000{ D} N_317_i{ F}inst_CLK_000_D1{ E}
CLK_000_D_0_{ C}: BG_000{ D} N_317_i{ F} CLK_000_D_1_{ E}
:CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E} SM_AMIGA_6_{ F}
inst_CLK_000_PE{ H}: RW_000{ H} BGACK_030{ H} VMA{ D}
: SM_AMIGA_5_{ F} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ C}
@ -736,7 +736,7 @@ Equations :
| * | S | BS | BR | CLK_EXP
| | | | | RESET
| * | S | BS | BR | CYCLE_DMA_0_
| * | S | BS | BR | inst_CLK_000_D0
| * | S | BS | BR | CLK_000_D_0_
| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH
| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW
| * | S | BS | BR | RN_IPL_030_0_
@ -814,7 +814,7 @@ Equations :
| | | | | BERR
| | | | | AMIGA_BUS_DATA_DIR
| | | | | CIIN
| * | S | BS | BR | inst_CLK_000_D1
| * | S | BS | BR | CLK_000_D_1_
| | | | | CIIN_0
| * | S | BS | BR | CLK_000_N_SYNC_0_
| * | S | BS | BR | CLK_000_P_SYNC_3_
@ -993,7 +993,7 @@ mx D2 RN_BG_000 mcell D1 mx D19inst_UDS_000_INT mcell A9
mx D3 cpu_est_1_ mcell D2 mx D20inst_CLK_000_NE_D0 mcell D10
mx D4 BG_030 pin 21 mx D21 RST pin 86
mx D5 SM_AMIGA_i_7_ mcell F0 mx D22 inst_CLK_000_PE mcell G5
mx D6 inst_CLK_000_D0 mcell B9 mx D23 inst_CLK_000_NE mcell G2
mx D6 CLK_000_D_0_ mcell B9 mx D23 inst_CLK_000_NE mcell G2
mx D7inst_DS_000_ENABLE mcell C8 mx D24 ... ...
mx D8 RST_DLY_2_ mcell D7 mx D25 ... ...
mx D9 RST_DLY_0_ mcell D3 mx D26 RN_VMA mcell D0
@ -1017,7 +1017,7 @@ mx E2 AS_000 pin 42 mx E19 A_30_ pin 5
mx E3 A_25_ pin 18 mx E20 FC_1_ pin 58
mx E4 BGACK_000 pin 28 mx E21 A_27_ pin 16
mx E5 A_24_ pin 19 mx E22 inst_AS_000_INT mcell C1
mx E6 inst_CLK_000_D0 mcell B9 mx E23 ... ...
mx E6 CLK_000_D_0_ mcell B9 mx E23 ... ...
mx E7 A_28_ pin 15 mx E24 FC_0_ pin 57
mx E8CLK_000_P_SYNC_2_ mcell G7 mx E25 inst_RESET_OUT mcell D9
mx E9 A_22_ pin 84 mx E26 A_16_ pin 96
@ -1027,7 +1027,7 @@ mx E12 A_19_ pin 97 mx E29 A_20_ pin 93
mx E13 A_29_ pin 6 mx E30inst_nEXP_SPACE_D0reg mcell A8
mx E14 CIIN_0 mcell E5 mx E31 A_18_ pin 95
mx E15 A_21_ pin 94 mx E32 AS_030 pin 82
mx E16 inst_CLK_000_D1 mcell E8
mx E16 CLK_000_D_1_ mcell E8
----------------------------------------------------------------------------
@ -1043,13 +1043,13 @@ mx F4 inst_CLK_000_NE mcell G2 mx F21 cpu_est_2_ mcell D13
mx F5CLK_000_N_SYNC_6_ mcell G6 mx F22 inst_CLK_000_PE mcell G5
mx F6inst_CLK_OUT_PRE_50 mcell F13 mx F23 ... ...
mx F7 ... ... mx F24 N_317_i mcell F14
mx F8 inst_CLK_000_D1 mcell E8 mx F25 SM_AMIGA_i_7_ mcell F0
mx F8 CLK_000_D_1_ mcell E8 mx F25 SM_AMIGA_i_7_ mcell F0
mx F9 inst_VPA_D mcell F2 mx F26 RN_VMA mcell D0
mx F10 SM_AMIGA_6_ mcell F4 mx F27 ... ...
mx F11 SM_AMIGA_3_ mcell F6 mx F28 ... ...
mx F12 ... ... mx F29inst_AS_030_000_SYNC mcell C4
mx F13 VPA pin 36 mx F30 cpu_est_0_ mcell D6
mx F14 SM_AMIGA_1_ mcell F5 mx F31 inst_CLK_000_D0 mcell B9
mx F14 SM_AMIGA_1_ mcell F5 mx F31 CLK_000_D_0_ mcell B9
mx F15 SM_AMIGA_0_ mcell F1 mx F32 SM_AMIGA_5_ mcell F8
mx F16 cpu_est_1_ mcell D2
----------------------------------------------------------------------------
@ -1218,10 +1218,10 @@ PostFit_Equations
1 1 1 Node inst_RESET_OUT.C
1 1 1 Node inst_CLK_OUT_PRE_50.D
1 1 1 Node inst_CLK_OUT_PRE_50.C
1 1 1 Node inst_CLK_000_D1.D
1 1 1 Node inst_CLK_000_D1.C
1 1 1 Node inst_CLK_000_D0.D
1 1 1 Node inst_CLK_000_D0.C
1 1 1 Node CLK_000_D_1_.D
1 1 1 Node CLK_000_D_1_.C
1 1 1 Node CLK_000_D_0_.D
1 1 1 Node CLK_000_D_0_.C
1 1 1 Node inst_CLK_000_PE.D
1 1 1 Node inst_CLK_000_PE.C
1 1 1 Node CLK_000_P_SYNC_9_.D
@ -1431,7 +1431,7 @@ A0.D = (!RST
A0.C = (CLK_OSZI);
!BG_000.D = (!BG_030 & RST & !BG_000.Q
# !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q);
# !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & CLK_000_D_0_.Q);
BG_000.C = (CLK_OSZI);
@ -1469,8 +1469,8 @@ RW.C = (CLK_OSZI);
!N_317_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
# !SM_AMIGA_5_.Q & !CLK_000_D_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !SM_AMIGA_5_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q
# cpu_est_2_.Q & !cpu_est_1_.Q
@ -1611,13 +1611,13 @@ inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
CLK_000_D_1_.D = (CLK_000_D_0_.Q);
inst_CLK_000_D1.C = (CLK_OSZI);
CLK_000_D_1_.C = (CLK_OSZI);
inst_CLK_000_D0.D = (CLK_000);
CLK_000_D_0_.D = (CLK_000);
inst_CLK_000_D0.C = (CLK_OSZI);
CLK_000_D_0_.C = (CLK_OSZI);
inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);
@ -1693,7 +1693,7 @@ RST_DLY_2_.D = (RST & RST_DLY_2_.Q
RST_DLY_2_.C = (CLK_OSZI);
CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q);
CLK_000_P_SYNC_0_.D = (!CLK_000_D_1_.Q & CLK_000_D_0_.Q);
CLK_000_P_SYNC_0_.C = (CLK_OSZI);
@ -1729,7 +1729,7 @@ CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
CLK_000_P_SYNC_8_.C = (CLK_OSZI);
CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q);
CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
CLK_000_N_SYNC_0_.C = (CLK_OSZI);
@ -1775,7 +1775,7 @@ CLK_000_N_SYNC_10_.C = (CLK_OSZI);
SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
# RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q);
# RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q);
SM_AMIGA_6_.C = (CLK_OSZI);

4
Logic/68030_tk.tal
View File

@ -50,8 +50,8 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2
SIZE_DMA_1_ 1 1 1 1 .. .. 2 2
inst_UDS_000_INT 1 1 1 1 .. .. 2 2
inst_LDS_000_INT 1 1 1 1 .. .. 2 2
inst_CLK_000_D1 .. .. .. .. .. .. 1 2
inst_CLK_000_D0 1 1 .. .. .. .. 1 2
CLK_000_D_1_ .. .. .. .. .. .. 1 2
CLK_000_D_0_ 1 1 .. .. .. .. 1 2
SM_AMIGA_0_ 1 1 .. .. .. .. 1 2
SM_AMIGA_4_ 1 1 .. .. .. .. 1 2
inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2

10
Logic/68030_tk.tt2
View File

@ -1,13 +1,13 @@
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
#$ DATE Wed Jan 27 21:56:48 2016
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 17 17:45:46 2016
#$ MODULE 68030_tk
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW
#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
.type fr
.i 120
.o 190
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN
.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C RST_DLY_0_.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_000_D0.C inst_CLK_000_PE.C inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN
.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C RST_DLY_0_.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D
.p 554
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10
Logic/68030_tk.tt3
View File

@ -1,13 +1,13 @@
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
#$ DATE Wed Jan 27 21:56:48 2016
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 17 17:45:46 2016
#$ MODULE 68030_tk
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW
#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
.type fr
.i 120
.o 190
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN
.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C RST_DLY_0_.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_000_D0.C inst_CLK_000_PE.C inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN
.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C RST_DLY_0_.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D
.p 554
------------------------------------------------------------------------------------------------------------------------ ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-1---------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

35
Logic/68030_tk.tt4
View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
#$ DATE Wed Jan 27 21:56:48 2016
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 17 17:45:46 2016
#$ MODULE BUS68030
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030
UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
@ -13,17 +13,16 @@
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT
inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT
inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE
CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_
IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_
CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_
CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_
CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_
CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_
CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_
SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
CIIN_0
inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_
inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_
inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_
inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_
CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_
CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_
CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_
CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_
CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_
inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
.type f
.i 121
.o 191
@ -36,7 +35,7 @@
inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q
SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q
inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q
inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q
CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q
inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
@ -68,10 +67,10 @@
inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% inst_DTACK_D0.C
inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C
inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C
inst_CLK_000_NE.D inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C
IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C
CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_000_PE.D
inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D
inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D%
IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C
inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C
inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D
SM_AMIGA_4_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D

35
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View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
#$ DATE Wed Jan 27 21:56:48 2016
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 17 17:45:46 2016
#$ MODULE BUS68030
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030
UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
@ -13,17 +13,16 @@
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT
inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT
inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE
CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_
IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_
CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_
CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_
CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_
CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_
CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_
SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
CIIN_0
inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_
inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_
inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_
inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_
CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_
CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_
CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_
CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_
CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_
inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
.type f
.i 121
.o 191
@ -36,7 +35,7 @@
inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q
SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q
inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q
inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q
CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q
inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
@ -68,10 +67,10 @@
inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- inst_DTACK_D0.C
inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C
inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C
inst_CLK_000_NE.D inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C
IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C
CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_000_PE.D
inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D
inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D-
IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C
inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C
inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D
SM_AMIGA_4_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D

8
Logic/68030_tk.vcl
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 1/27/16;
TIME = 21:56:53;
DATE = 8/17/16;
TIME = 17:45:51;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@ -178,7 +178,7 @@ cpu_est_1_ = NODE,*,3,-;
cpu_est_3_ = NODE,*,5,-;
SM_AMIGA_0_ = NODE,*,5,-;
CYCLE_DMA_0_ = NODE,*,1,-;
inst_CLK_000_D0 = NODE,*,1,-;
CLK_000_D_0_ = NODE,*,1,-;
inst_CLK_OUT_PRE_D = NODE,*,0,-;
inst_BGACK_030_INT_D = NODE,*,7,-;
inst_AS_000_DMA = NODE,*,0,-;
@ -198,7 +198,7 @@ inst_AS_000_INT = NODE,*,2,-;
cpu_est_0_ = NODE,*,3,-;
inst_CLK_000_NE_D0 = NODE,*,3,-;
inst_CLK_000_NE = NODE,*,6,-;
inst_CLK_000_D1 = NODE,*,4,-;
CLK_000_D_1_ = NODE,*,4,-;
inst_CLK_OUT_PRE_50 = NODE,*,5,-;
inst_VPA_D = NODE,*,5,-;
RN_IPL_030_0_ = NODE,-1,1,-;

8
Logic/68030_tk.vco
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 1/27/16;
TIME = 21:56:53;
DATE = 8/17/16;
TIME = 17:45:51;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@ -222,8 +222,8 @@ inst_CLK_OUT_PRE_D = NODE,12, A,-;
inst_DTACK_D0 = NODE,15, B,-;
inst_RESET_OUT = NODE,9, D,-;
inst_CLK_OUT_PRE_50 = NODE,13, F,-;
inst_CLK_000_D1 = NODE,8, E,-;
inst_CLK_000_D0 = NODE,9, B,-;
CLK_000_D_1_ = NODE,8, E,-;
CLK_000_D_0_ = NODE,9, B,-;
inst_CLK_000_PE = NODE,5, G,-;
CLK_000_P_SYNC_9_ = NODE,15, G,-;
inst_CLK_000_NE = NODE,2, G,-;

4
Logic/68030_tk.xrf
View File

@ -1,8 +1,8 @@
Signal Name Cross Reference File
ispLEVER Classic 1.8.00.04.29.14
ispLEVER Classic 2.0.00.17.20.15
Design '68030_tk' created Wed Jan 27 21:56:48 2016
Design '68030_tk' created Wed Aug 17 17:45:46 2016
LEGEND: '>' Functional Block Port Separator

362
Logic/BUS68030.bl0
View File

File diff suppressed because it is too large Load Diff

216
Logic/BUS68030.bl1
View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
#$ DATE Wed Jan 27 21:56:48 2016
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 17 17:45:46 2016
#$ MODULE bus68030
#$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ \
# IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 \
@ -37,17 +37,17 @@
# lds_000_int_0_un0_n inst_CLK_OUT_PRE_D sm_amiga_i_3__n N_350_i rw_000_dma_0_un3_n \
# inst_DTACK_D0 cpu_est_i_0__n N_188_0 rw_000_dma_0_un1_n inst_RESET_OUT \
# cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n inst_CLK_OUT_PRE_50 cpu_est_i_2__n \
# N_185_i a_15__n inst_CLK_000_D1 cpu_est_i_1__n N_182_i inst_CLK_000_D0 VPA_D_i \
# N_181_i a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ \
# N_185_i a_15__n CLK_000_D_1_ cpu_est_i_1__n N_182_i CLK_000_D_0_ VPA_D_i N_181_i \
# a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ \
# sm_amiga_i_1__n N_175_0 a_13__n inst_CLK_000_NE rst_dly_i_2__n N_168_i \
# CLK_000_N_SYNC_11_ CLK_030_i AS_030_000_SYNC_i a_12__n IPL_D0_0_ rst_dly_i_0__n \
# N_158_i IPL_D0_1_ rst_dly_i_1__n CLK_000_D0_i a_11__n IPL_D0_2_ CLK_000_D1_i N_148_i \
# inst_CLK_000_NE_D0 DTACK_D0_i N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i \
# SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH \
# N_158_i IPL_D0_1_ rst_dly_i_1__n clk_000_d_i_0__n a_11__n IPL_D0_2_ clk_000_d_i_1__n \
# N_148_i inst_CLK_000_NE_D0 DTACK_D0_i N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i \
# N_344_i SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH \
# sm_amiga_i_6__n N_138_0 inst_DSACK1_INTreg sm_amiga_i_2__n a_8__n AS_000_i N_342_i \
# pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n SM_AMIGA_4_ A1_i N_124_0 \
# inst_DS_000_ENABLE a_i_31__n N_341_i a_6__n RST_DLY_0_ a_i_29__n N_119_0 RST_DLY_1_ \
# a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un8_bg_030_n a_i_28__n \
# a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un9_bg_030_n a_i_28__n \
# cpu_est_2_0_2__n a_4__n CLK_000_P_SYNC_0_ a_i_25__n N_338_i CLK_000_P_SYNC_1_ \
# a_i_26__n N_339_i a_3__n CLK_000_P_SYNC_2_ N_213_i cpu_est_2_0_1__n \
# CLK_000_P_SYNC_3_ N_214_i N_332_i a_2__n CLK_000_P_SYNC_4_ N_215_i N_336_i \
@ -69,7 +69,7 @@
# N_17_i N_42_0 a_c_23__n N_19_i N_40_0 SM_AMIGA_i_7_ a_c_24__n N_20_i N_123 N_39_0 \
# cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i G_134 \
# N_37_0 G_135 a_c_27__n N_25_i G_136 N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \
# BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un8_bg_030_0_n N_80 \
# BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \
# N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \
# pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 N_138 \
# nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 N_137_i_2 N_175 \
@ -94,7 +94,7 @@
# as_030_000_sync_0_un3_n N_347 N_272_i as_030_000_sync_0_un1_n N_350 N_271_i \
# as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 \
# ds_000_enable_0_un1_n N_361 N_281_0 ds_000_enable_0_un0_n \
# pos_clk_un24_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n \
# pos_clk_un23_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n \
# pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n \
# cpu_est_0_0_x2_0_ N_299_i as_000_int_0_un0_n pos_clk_CYCLE_DMA_5_1_i_x2 \
# pos_clk_size_dma_6_0_1__n dsack1_int_0_un3_n un22_berr_1 un1_as_000_i \
@ -164,14 +164,14 @@ sm_amiga_i_3__n.BLIF N_350_i.BLIF rw_000_dma_0_un3_n.BLIF inst_DTACK_D0.BLIF \
cpu_est_i_0__n.BLIF N_188_0.BLIF rw_000_dma_0_un1_n.BLIF inst_RESET_OUT.BLIF \
cpu_est_i_3__n.BLIF N_187_i.BLIF rw_000_dma_0_un0_n.BLIF \
inst_CLK_OUT_PRE_50.BLIF cpu_est_i_2__n.BLIF N_185_i.BLIF a_15__n.BLIF \
inst_CLK_000_D1.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF inst_CLK_000_D0.BLIF \
CLK_000_D_1_.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF CLK_000_D_0_.BLIF \
VPA_D_i.BLIF N_181_i.BLIF a_14__n.BLIF inst_CLK_000_PE.BLIF CLK_000_NE_i.BLIF \
CLK_OUT_PRE_D_i.BLIF CLK_000_P_SYNC_9_.BLIF sm_amiga_i_1__n.BLIF N_175_0.BLIF \
a_13__n.BLIF inst_CLK_000_NE.BLIF rst_dly_i_2__n.BLIF N_168_i.BLIF \
CLK_000_N_SYNC_11_.BLIF CLK_030_i.BLIF AS_030_000_SYNC_i.BLIF a_12__n.BLIF \
IPL_D0_0_.BLIF rst_dly_i_0__n.BLIF N_158_i.BLIF IPL_D0_1_.BLIF \
rst_dly_i_1__n.BLIF CLK_000_D0_i.BLIF a_11__n.BLIF IPL_D0_2_.BLIF \
CLK_000_D1_i.BLIF N_148_i.BLIF inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF \
rst_dly_i_1__n.BLIF clk_000_d_i_0__n.BLIF a_11__n.BLIF IPL_D0_2_.BLIF \
clk_000_d_i_1__n.BLIF N_148_i.BLIF inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF \
N_345_i.BLIF a_10__n.BLIF pos_clk_un6_bg_030_n.BLIF RW_000_i.BLIF N_344_i.BLIF \
SM_AMIGA_0_.BLIF CLK_030_H_i.BLIF N_144_0.BLIF a_9__n.BLIF \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF sm_amiga_i_6__n.BLIF N_138_0.BLIF \
@ -180,7 +180,7 @@ N_342_i.BLIF pos_clk_ipl_n.BLIF sm_amiga_i_0__n.BLIF N_343_i.BLIF a_7__n.BLIF \
SM_AMIGA_4_.BLIF A1_i.BLIF N_124_0.BLIF inst_DS_000_ENABLE.BLIF a_i_31__n.BLIF \
N_341_i.BLIF a_6__n.BLIF RST_DLY_0_.BLIF a_i_29__n.BLIF N_119_0.BLIF \
RST_DLY_1_.BLIF a_i_30__n.BLIF N_340_i.BLIF a_5__n.BLIF RST_DLY_2_.BLIF \
a_i_27__n.BLIF N_361_i.BLIF pos_clk_un8_bg_030_n.BLIF a_i_28__n.BLIF \
a_i_27__n.BLIF N_361_i.BLIF pos_clk_un9_bg_030_n.BLIF a_i_28__n.BLIF \
cpu_est_2_0_2__n.BLIF a_4__n.BLIF CLK_000_P_SYNC_0_.BLIF a_i_25__n.BLIF \
N_338_i.BLIF CLK_000_P_SYNC_1_.BLIF a_i_26__n.BLIF N_339_i.BLIF a_3__n.BLIF \
CLK_000_P_SYNC_2_.BLIF N_213_i.BLIF cpu_est_2_0_1__n.BLIF \
@ -216,7 +216,7 @@ cpu_est_2_1__n.BLIF a_c_25__n.BLIF N_21_i.BLIF cpu_est_2_2__n.BLIF N_38_0.BLIF \
N_209.BLIF a_c_26__n.BLIF N_22_i.BLIF G_134.BLIF N_37_0.BLIF G_135.BLIF \
a_c_27__n.BLIF N_25_i.BLIF G_136.BLIF N_34_0.BLIF N_217.BLIF a_c_28__n.BLIF \
N_26_i.BLIF N_33_0.BLIF N_61.BLIF a_c_29__n.BLIF BG_030_c_i.BLIF N_127.BLIF \
pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un8_bg_030_0_n.BLIF \
pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un9_bg_030_0_n.BLIF \
N_80.BLIF N_289_0_1.BLIF a_c_31__n.BLIF un1_SM_AMIGA_5_i_1.BLIF N_90.BLIF \
un1_SM_AMIGA_5_i_2.BLIF N_96.BLIF A0_c.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF \
N_99.BLIF N_351_1.BLIF N_119.BLIF A1_c.BLIF N_351_2.BLIF N_124.BLIF \
@ -259,7 +259,7 @@ as_030_000_sync_0_un1_n.BLIF N_350.BLIF N_271_i.BLIF \
as_030_000_sync_0_un0_n.BLIF N_351.BLIF N_279_0.BLIF \
ds_000_enable_0_un3_n.BLIF N_353.BLIF N_280_0.BLIF ds_000_enable_0_un1_n.BLIF \
N_361.BLIF N_281_0.BLIF ds_000_enable_0_un0_n.BLIF \
pos_clk_un24_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF \
pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF \
as_000_int_0_un3_n.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF \
pos_clk_size_dma_6_0_0__n.BLIF as_000_int_0_un1_n.BLIF cpu_est_0_0_x2_0_.BLIF \
N_299_i.BLIF as_000_int_0_un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF \
@ -286,18 +286,17 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \
A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C \
SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \
SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \
IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \
IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \
IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C \
SM_AMIGA_6_.D SM_AMIGA_6_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C \
CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \
CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \
CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \
cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \
SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \
SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \
IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \
IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \
IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \
SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \
CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \
CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \
cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \
CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \
CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \
CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \
@ -306,33 +305,34 @@ CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \
CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \
CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \
CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D \
RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \
CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \
CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \
CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \
CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \
CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \
CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_DMA.D \
inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \
inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \
inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \
inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \
BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D \
inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \
inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \
inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \
inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \
inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \
BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \
inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \
inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D \
inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \
inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D \
inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C \
inst_CLK_000_NE.D inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 \
LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 N_289_0 \
cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 cpu_est_0_2__un0_n \
N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 N_246_i \
cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i \
inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 RW_000 \
UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 \
N_289_0 cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 \
cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 \
N_246_i cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i \
ipl_030_0_0__un3_n N_7 ipl_030_0_0__un1_n gnd_n_n N_10 N_266_i \
ipl_030_0_0__un0_n un1_amiga_bus_enable_low N_18 N_267_i ipl_030_0_1__un3_n \
un3_size N_24 N_254_i ipl_030_0_1__un1_n un4_size N_6 N_317_i \
@ -358,20 +358,20 @@ N_188_0 rw_000_dma_0_un1_n cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n \
cpu_est_i_2__n N_185_i a_15__n cpu_est_i_1__n N_182_i VPA_D_i N_181_i a_14__n \
CLK_000_NE_i CLK_OUT_PRE_D_i sm_amiga_i_1__n N_175_0 a_13__n rst_dly_i_2__n \
N_168_i CLK_030_i AS_030_000_SYNC_i a_12__n rst_dly_i_0__n N_158_i \
rst_dly_i_1__n CLK_000_D0_i a_11__n CLK_000_D1_i N_148_i DTACK_D0_i N_345_i \
a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 a_9__n \
sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n a_8__n AS_000_i N_342_i pos_clk_ipl_n \
sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i a_6__n a_i_29__n \
N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i pos_clk_un8_bg_030_n \
a_i_28__n cpu_est_2_0_2__n a_4__n a_i_25__n N_338_i a_i_26__n N_339_i a_3__n \
N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n N_215_i N_336_i \
pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i DS_000_DMA_i \
N_96_0 un4_as_000_i N_330_i AS_000_INT_i N_90_0 un4_lds_000_i N_328_i \
un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 RW_000_c \
N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n LDS_000_c \
un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 N_310_i size_c_1__n N_305_i \
N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 N_278_i \
N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 \
rst_dly_i_1__n clk_000_d_i_0__n a_11__n clk_000_d_i_1__n N_148_i DTACK_D0_i \
N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 \
a_9__n sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n a_8__n AS_000_i N_342_i \
pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i \
a_6__n a_i_29__n N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i \
pos_clk_un9_bg_030_n a_i_28__n cpu_est_2_0_2__n a_4__n a_i_25__n N_338_i \
a_i_26__n N_339_i a_3__n N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n \
N_215_i N_336_i pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i \
DS_000_DMA_i N_96_0 un4_as_000_i N_330_i AS_000_INT_i N_90_0 un4_lds_000_i \
N_328_i un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 \
RW_000_c N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n \
LDS_000_c un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 N_310_i size_c_1__n \
N_305_i N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 \
N_278_i N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 \
pos_clk_un8_sm_amiga_i_n N_27 A0_c_i N_28 size_c_i_1__n N_29 N_29_i N_32_0 \
N_28_i N_31_0 N_27_i N_30_0 ipl_c_i_2__n N_53_0 ipl_c_i_1__n N_52_0 a_c_16__n \
ipl_c_i_0__n N_51_0 a_c_17__n DTACK_c_i N_56_0 a_c_18__n VPA_c_i N_55_0 \
@ -379,7 +379,7 @@ a_c_19__n nEXP_SPACE_c_i N_54_0 a_c_20__n N_3_i N_49_0 a_c_21__n N_8_i N_45_0 \
a_c_22__n N_17_i N_42_0 a_c_23__n N_19_i N_40_0 a_c_24__n N_20_i N_123 N_39_0 \
cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i \
N_37_0 a_c_27__n N_25_i N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \
BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un8_bg_030_0_n N_80 \
BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \
N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \
pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 \
N_138 nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 \
@ -423,10 +423,8 @@ pos_clk_size_dma_6_0__n N_207_0 sm_amiga_srsts_i_0_m2_5__un0_n N_298 N_354_i \
cpu_est_0_1__un3_n N_281 N_208_0 cpu_est_0_1__un1_n AS_030.OE AS_000.OE \
RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE \
DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_134 G_135 G_136 \
pos_clk_un24_bgack_030_int_i_i_a4_i_x2 pos_clk_CYCLE_DMA_5_0_i_x2 \
pos_clk_un23_bgack_030_int_i_i_a4_i_x2 pos_clk_CYCLE_DMA_5_0_i_x2 \
cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2
.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D
11 1
.names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D
11 1
.names N_137_i_1.BLIF N_137_i_2.BLIF SM_AMIGA_3_.D
@ -453,6 +451,8 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2
11 1
.names N_258_0.BLIF SM_AMIGA_6_.D
0 1
.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D
11 1
.names N_282_i_1.BLIF N_210_0.BLIF CYCLE_DMA_0_.D
11 1
.names N_134_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D
@ -476,14 +476,10 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2
11 1
.names N_259_i_1.BLIF N_259_i_2.BLIF RST_DLY_2_.D
11 1
.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D
.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D
11 1
.names N_261_i_1.BLIF N_322_i.BLIF RST_DLY_0_.D
11 1
.names N_45_0.BLIF inst_AS_000_DMA.D
0 1
.names N_46_0.BLIF inst_AS_030_000_SYNC.D
0 1
.names N_47_0.BLIF inst_AS_000_INT.D
0 1
.names N_48_0.BLIF inst_DSACK1_INTreg.D
@ -524,6 +520,10 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2
0 1
.names N_43_0.BLIF inst_BGACK_030_INTreg.D
0 1
.names N_45_0.BLIF inst_AS_000_DMA.D
0 1
.names N_46_0.BLIF inst_AS_030_000_SYNC.D
0 1
.names N_210_0.BLIF inst_BGACK_030_INT_D.D
0 1
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
@ -726,13 +726,13 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n
0 1
.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_212_0
11 1
.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n
.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n
0 1
.names inst_CLK_000_PE.BLIF CLK_000_PE_i
0 1
.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_211_0
11 1
.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n
.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n
11 1
.names a_c_16__n.BLIF a_i_16__n
0 1
@ -846,17 +846,17 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n
11 1
.names RST_DLY_1_.BLIF rst_dly_i_1__n
0 1
.names inst_CLK_000_D0.BLIF CLK_000_D0_i
.names CLK_000_D_0_.BLIF clk_000_d_i_0__n
0 1
.names inst_CLK_000_D1.BLIF CLK_000_D1_i
.names CLK_000_D_1_.BLIF clk_000_d_i_1__n
0 1
.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_148_i
.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_148_i
11 1
.names inst_DTACK_D0.BLIF DTACK_D0_i
0 1
.names N_345.BLIF N_345_i
0 1
.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n
.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n
11 1
.names RW_000_c.BLIF RW_000_i
0 1
@ -902,7 +902,7 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n
0 1
.names N_361.BLIF N_361_i
0 1
.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n
.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n
0 1
.names a_c_28__n.BLIF a_i_28__n
0 1
@ -1140,7 +1140,7 @@ pos_clk_un8_sm_amiga_i_n
11 1
.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n
0 1
.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n
.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n
11 1
.names N_80_0.BLIF N_80
0 1
@ -1174,7 +1174,7 @@ pos_clk_un8_sm_amiga_i_n
11 1
.names N_144_0.BLIF N_144
0 1
.names pos_clk_un24_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2
.names pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2
11 1
.names N_158_i.BLIF N_158
0 1
@ -1704,9 +1704,6 @@ sm_amiga_srsts_i_0_m2_5__un0_n
.names IPL_030DFF_0_reg.BLIF IPL_030_0_
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
1 1
0 0
@ -1746,10 +1743,7 @@ sm_amiga_srsts_i_0_m2_5__un0_n
.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
1 1
0 0
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C
.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
1 1
0 0
.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
@ -1875,12 +1869,30 @@ sm_amiga_srsts_i_0_m2_5__un0_n
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C
1 1
0 0
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C
1 1
0 0
.names CLK_OSZI_c.BLIF RST_DLY_1_.C
1 1
0 0
.names CLK_OSZI_c.BLIF RST_DLY_2_.C
1 1
0 0
.names CLK_000.BLIF CLK_000_D_0_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_D_0_.C
1 1
0 0
.names CLK_000_D_0_.BLIF CLK_000_D_1_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_D_1_.C
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C
1 1
0 0
@ -1911,12 +1923,6 @@ sm_amiga_srsts_i_0_m2_5__un0_n
.names CLK_OSZI_c.BLIF RST_DLY_0_.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
1 1
0 0
@ -1977,18 +1983,15 @@ sm_amiga_srsts_i_0_m2_5__un0_n
.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
1 1
0 0
.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D
1 1
0 0
@ -2007,12 +2010,6 @@ sm_amiga_srsts_i_0_m2_5__un0_n
.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names CLK_000.BLIF inst_CLK_000_D0.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
1 1
0 0
.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D
1 1
0 0
@ -2025,6 +2022,9 @@ sm_amiga_srsts_i_0_m2_5__un0_n
.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names un3_size.BLIF SIZE_1_
1 1
0 0
@ -2278,7 +2278,7 @@ sm_amiga_srsts_i_0_m2_5__un0_n
11 0
00 0
.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
pos_clk_un24_bgack_030_int_i_i_a4_i_x2
pos_clk_un23_bgack_030_int_i_i_a4_i_x2
01 1
10 1
11 0

130
Logic/BUS68030.edi
View File

@ -4,7 +4,7 @@
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2016 1 27 21 56 45)
(timeStamp 2016 8 17 17 45 43)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R"))
)
@ -140,8 +140,6 @@
(port CIIN (direction OUTPUT))
)
(contents
(instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFF (libraryRef mach)))
@ -168,7 +166,7 @@
)
(instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach)))
(instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
@ -218,10 +216,16 @@
)
(instance (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename RST_DLY_1 "RST_DLY[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename RST_DLY_2 "RST_DLY[2]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename CLK_000_D_1 "CLK_000_D[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
@ -234,10 +238,6 @@
)
(instance (rename RST_DLY_0 "RST_DLY[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance DSACK1_INT (viewRef prim (cellRef DFF (libraryRef mach)))
@ -278,24 +278,24 @@
)
(instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance CLK_OUT_PRE_50 (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance CLK_000_D1 (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance CLK_000_NE_D0 (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance CLK_OUT_PRE_D (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance CLK_000_D0 (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance CLK_000_PE (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance CLK_000_NE (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance CLK_OUT_PRE_50 (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance AS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
(instance AS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
(instance RW_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
@ -459,9 +459,9 @@
(instance (rename SM_AMIGA_srsts_i_i_a2_2 "SM_AMIGA_srsts_i_i_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_nss_i_i_0_o2_1_0_0 "SM_AMIGA_nss_i_i_0_o2_1_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_nss_i_i_0_o2_0 "SM_AMIGA_nss_i_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_o3_1 "pos_clk.un24_bgack_030_int_i_i_a4_i_o3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_o3_2 "pos_clk.un24_bgack_030_int_i_i_a4_i_o3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_o3 "pos_clk.un24_bgack_030_int_i_i_a4_i_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1 "pos_clk.un23_bgack_030_int_i_i_a4_i_o3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2 "pos_clk.un23_bgack_030_int_i_i_a4_i_o3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3 "pos_clk.un23_bgack_030_int_i_i_a4_i_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_srsts_i_0_0_1_3 "SM_AMIGA_srsts_i_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_srsts_i_0_0_2_3 "SM_AMIGA_srsts_i_0_0_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_srsts_i_0_0_3 "SM_AMIGA_srsts_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
@ -476,7 +476,7 @@
(instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename pos_clk_un8_bg_030_i "pos_clk.un8_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename pos_clk_un9_bg_030_i "pos_clk.un9_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename pos_clk_un37_as_030_d0_i_o2_1 "pos_clk.un37_as_030_d0_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un37_as_030_d0_i_o2 "pos_clk.un37_as_030_d0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un1_SM_AMIGA_5_0_o3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
@ -568,7 +568,7 @@
(instance (rename SM_AMIGA_nss_i_i_0_o2_i_0 "SM_AMIGA_nss_i_i_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance RST_DLY_e2_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance N_345_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance N_344_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance RST_DLY_e2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) )
@ -586,7 +586,7 @@
(instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename SM_AMIGA_nss_i_i_0_o2_0_i_0 "SM_AMIGA_nss_i_i_0_o2_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3_i "pos_clk.un5_bgack_030_int_d_i_0_a4_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_o3_i "pos_clk.un24_bgack_030_int_i_i_a4_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3_i "pos_clk.un23_bgack_030_int_i_i_a4_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance N_350_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance DSACK1_INT_0_sqmuxa_i_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) )
@ -792,9 +792,9 @@
(instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance CLK_030_H_2_0_a2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un6_as_030_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_x2 "pos_clk.un24_bgack_030_int_i_i_a4_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) )
(instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_x2 "pos_clk.un23_bgack_030_int_i_i_a4_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) )
(instance RST_DLY_e2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0 "pos_clk.CLK_000_N_SYNC_2_0_a4_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
@ -829,7 +829,7 @@
(instance (rename cpu_est_2_i_0_i_a3_3 "cpu_est_2_i_0_i_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un5_e_i_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance RST_DLY_e2_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_a2 "pos_clk.un24_bgack_030_int_i_i_a4_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_a2 "pos_clk.un23_bgack_030_int_i_i_a4_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_srsts_i_0_0_a2_3 "SM_AMIGA_srsts_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance DSACK1_INT_0_sqmuxa_i_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance RST_DLYlde_i_a4_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
@ -866,6 +866,7 @@
(instance A1_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance G_129 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance N_213_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance N_214_i (viewRef prim (cellRef INV (libraryRef mach))) )
@ -876,7 +877,6 @@
(instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance nEXP_SPACE_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
@ -940,7 +940,7 @@
(instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un8_bg_030 "pos_clk.un8_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un4_uds_000_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance un4_lds_000_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
@ -1114,12 +1114,12 @@
(net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined
(portRef Q (instanceRef CYCLE_DMA_0))
(portRef I1 (instanceRef G_129))
(portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_x2))
(portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_x2))
(portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2))
))
(net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined
(portRef Q (instanceRef CYCLE_DMA_1))
(portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_x2))
(portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_x2))
(portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2))
))
(net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined
@ -1170,17 +1170,17 @@
(portRef I0 (instanceRef CLK_OUT_PRE_50_i))
(portRef D (instanceRef CLK_OUT_PRE_D))
))
(net CLK_000_D1 (joined
(portRef Q (instanceRef CLK_000_D1))
(portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0))
(portRef I0 (instanceRef CLK_000_D1_i))
(net (rename CLK_000_D_1 "CLK_000_D[1]") (joined
(portRef Q (instanceRef CLK_000_D_1))
(portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0))
(portRef I0 (instanceRef CLK_000_D_i_1))
))
(net CLK_000_D0 (joined
(portRef Q (instanceRef CLK_000_D0))
(net (rename CLK_000_D_0 "CLK_000_D[0]") (joined
(portRef Q (instanceRef CLK_000_D_0))
(portRef I0 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a3_0))
(portRef I0 (instanceRef CLK_000_D0_i))
(portRef I0 (instanceRef CLK_000_D_i_0))
(portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_0_a3))
(portRef D (instanceRef CLK_000_D1))
(portRef D (instanceRef CLK_000_D_1))
))
(net CLK_000_PE (joined
(portRef Q (instanceRef CLK_000_PE))
@ -1298,8 +1298,8 @@
(portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2))
(portRef I0 (instanceRef RST_DLY_i_2))
))
(net (rename pos_clk_un8_bg_030 "pos_clk.un8_bg_030") (joined
(portRef O (instanceRef pos_clk_un8_bg_030_i))
(net (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (joined
(portRef O (instanceRef pos_clk_un9_bg_030_i))
(portRef I1 (instanceRef BG_000_0_m))
(portRef I0 (instanceRef BG_000_0_r))
))
@ -1738,7 +1738,7 @@
(portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i_i_a3))
))
(net N_192 (joined
(portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_i))
(portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_i))
(portRef I0 (instanceRef AS_000_DMA_0_m))
))
(net N_193 (joined
@ -1987,7 +1987,7 @@
(portRef I0 (instanceRef N_344_i))
))
(net N_345 (joined
(portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_a2))
(portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_a2))
(portRef I0 (instanceRef N_345_i))
))
(net N_347 (joined
@ -2013,8 +2013,8 @@
(portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_1))
))
(net N_140_i (joined
(portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_x2))
(portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_2))
(portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_x2))
(portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2))
))
(net N_228_i (joined
(portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2))
@ -2189,7 +2189,7 @@
(portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_0))
(portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_1))
(portRef I1 (instanceRef un1_amiga_bus_enable_low))
(portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_1))
(portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1))
))
(net AMIGA_BUS_ENABLE_DMA_LOW_i (joined
(portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i))
@ -2376,8 +2376,8 @@
(portRef I1 (instanceRef RST_DLY_e1_i_0_a3_1))
(portRef I1 (instanceRef RST_DLY_e1_i_0_a3_0))
))
(net CLK_000_D1_i (joined
(portRef O (instanceRef CLK_000_D1_i))
(net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined
(portRef O (instanceRef CLK_000_D_i_1))
(portRef I1 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a3_0))
))
(net DTACK_D0_i (joined
@ -2410,7 +2410,7 @@
(portRef O (instanceRef I_199))
(portRef I0 (instanceRef un6_ds_030))
(portRef I1 (instanceRef un6_as_030_i_0))
(portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_1))
(portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1))
(portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_1))
(portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1))
(portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0_1))
@ -2529,7 +2529,7 @@
(net UDS_000_c (joined
(portRef O (instanceRef UDS_000))
(portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a3))
(portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_a2))
(portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_a2))
(portRef I0 (instanceRef UDS_000_c_i))
))
(net UDS_000 (joined
@ -2538,7 +2538,7 @@
))
(net LDS_000_c (joined
(portRef O (instanceRef LDS_000))
(portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_a2))
(portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_a2))
(portRef I0 (instanceRef LDS_000_c_i))
))
(net LDS_000 (joined
@ -2869,7 +2869,7 @@
))
(net CLK_000_c (joined
(portRef O (instanceRef CLK_000))
(portRef D (instanceRef CLK_000_D0))
(portRef D (instanceRef CLK_000_D_0))
))
(net CLK_000 (joined
(portRef CLK_000)
@ -2887,8 +2887,8 @@
(portRef CLK (instanceRef BGACK_030_INT))
(portRef CLK (instanceRef BGACK_030_INT_D))
(portRef CLK (instanceRef BG_000DFF))
(portRef CLK (instanceRef CLK_000_D0))
(portRef CLK (instanceRef CLK_000_D1))
(portRef CLK (instanceRef CLK_000_D_0))
(portRef CLK (instanceRef CLK_000_D_1))
(portRef CLK (instanceRef CLK_000_NE))
(portRef CLK (instanceRef CLK_000_NE_D0))
(portRef CLK (instanceRef CLK_000_N_SYNC_0))
@ -3519,10 +3519,10 @@
(portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o2_1))
))
(net N_192_0 (joined
(portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3))
(portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3))
(portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i))
(portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i))
(portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_i))
(portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_i))
(portRef I0 (instanceRef CLK_030_H_2_0_a2_i_1))
(portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_1))
))
@ -3583,9 +3583,9 @@
(portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2))
(portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0_i))
))
(net CLK_000_D0_i (joined
(portRef O (instanceRef CLK_000_D0_i))
(portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0))
(net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined
(portRef O (instanceRef CLK_000_D_i_0))
(portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0))
))
(net N_148_i (joined
(portRef O (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0))
@ -3594,7 +3594,7 @@
))
(net N_345_i (joined
(portRef O (instanceRef N_345_i))
(portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_2))
(portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2))
))
(net N_344_i (joined
(portRef O (instanceRef N_344_i))
@ -3977,15 +3977,15 @@
))
(net BG_030_c_i (joined
(portRef O (instanceRef BG_030_c_i))
(portRef I0 (instanceRef pos_clk_un8_bg_030))
(portRef I0 (instanceRef pos_clk_un9_bg_030))
))
(net (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (joined
(portRef O (instanceRef pos_clk_un6_bg_030_i))
(portRef I1 (instanceRef pos_clk_un8_bg_030))
(portRef I1 (instanceRef pos_clk_un9_bg_030))
))
(net (rename pos_clk_un8_bg_030_0 "pos_clk.un8_bg_030_0") (joined
(portRef O (instanceRef pos_clk_un8_bg_030))
(portRef I0 (instanceRef pos_clk_un8_bg_030_i))
(net (rename pos_clk_un9_bg_030_0 "pos_clk.un9_bg_030_0") (joined
(portRef O (instanceRef pos_clk_un9_bg_030))
(portRef I0 (instanceRef pos_clk_un9_bg_030_i))
))
(net N_289_0_1 (joined
(portRef O (instanceRef pos_clk_un37_as_030_d0_i_o2_1))
@ -4016,12 +4016,12 @@
(portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_0))
))
(net N_192_0_1 (joined
(portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_1))
(portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3))
(portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1))
(portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3))
))
(net N_192_0_2 (joined
(portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_2))
(portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3))
(portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2))
(portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3))
))
(net N_137_i_1 (joined
(portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3))

20
Logic/BUS68030.fse
View File

@ -1,20 +1,20 @@
fsm_encoding {7138371381} onehot
fsm_encoding {7134371341} onehot
fsm_state_encoding {7138371381} idle_p {00000000}
fsm_state_encoding {7134371341} idle_p {00000000}
fsm_state_encoding {7138371381} idle_n {00000011}
fsm_state_encoding {7134371341} idle_n {00000011}
fsm_state_encoding {7138371381} as_set_p {00000101}
fsm_state_encoding {7134371341} as_set_p {00000101}
fsm_state_encoding {7138371381} as_set_n {00001001}
fsm_state_encoding {7134371341} as_set_n {00001001}
fsm_state_encoding {7138371381} sample_dtack_p {00010001}
fsm_state_encoding {7134371341} sample_dtack_p {00010001}
fsm_state_encoding {7138371381} data_fetch_n {00100001}
fsm_state_encoding {7134371341} data_fetch_n {00100001}
fsm_state_encoding {7138371381} data_fetch_p {01000001}
fsm_state_encoding {7134371341} data_fetch_p {01000001}
fsm_state_encoding {7138371381} end_cycle_n {10000001}
fsm_state_encoding {7134371341} end_cycle_n {10000001}
fsm_registers {7138371381} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}
fsm_registers {7134371341} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}

2
Logic/BUS68030.prj
View File

@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Wed Jan 27 21:56:36 2016
#-- Written on Wed Aug 17 17:45:34 2016
#device options

3253
Logic/BUS68030.srm
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File diff suppressed because it is too large Load Diff

35
Logic/BUS68030.srr
View File

@ -1,18 +1,18 @@
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: C:\ispLever\synpbase
#install: E:\ispLEVER_Classic2_0\synpbase
#OS: Windows 7 6.2
#Hostname: DEEPTHOUGHT
#Implementation: logic
$ Start of Compile
#Wed Jan 27 21:56:43 2016
#Wed Aug 17 17:45:41 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
@ -22,18 +22,16 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register AMIGA_BUS_ENABLE_INT_4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -44,14 +42,14 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 27 21:56:44 2016
# Wed Aug 17 17:45:41 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -61,7 +59,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 27 21:56:45 2016
# Wed Aug 17 17:45:43 2016
###########################################################]
Map & Optimize Report
@ -70,7 +68,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -81,7 +79,6 @@ original code -> new code
101 -> 00100001
110 -> 01000001
111 -> 10000001
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
---------------------------------------
Resource Usage Report
@ -104,6 +101,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 27 21:56:45 2016
# Wed Aug 17 17:45:43 2016
###########################################################]

BIN
Logic/BUS68030.srs
View File

Binary file not shown.

4
Logic/Programming.xcf
View File

@ -18,8 +18,8 @@
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk-50.jed</File>
<FileTime>01/27/16 21:56:53</FileTime>
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
<FileTime>08/17/16 17:45:51</FileTime>
<JedecChecksum>0x2728</JedecChecksum>
<Operation>Erase,Program,Verify</Operation>
<Option>

112
Logic/bus68030.exf
View File

@ -50,7 +50,7 @@ Section Member Rename Array-Notation Array Number
Port FC_0_ FC[0] 3 1
End
Section Cross Reference File
Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Design 'BUS68030' created Wed Aug 17 17:45:46 2016
Type New Name Original Name
// ----------------------------------------------------------------------
Inst i_z3S3S AS_030
@ -66,7 +66,7 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Inst i_z5V5V RW
Inst i_z6666 CIIN
Inst SM_AMIGA_srsts_i_i_a3_0_2_ SM_AMIGA_srsts_i_i_a3_0[2]
Inst pos_clk_un8_bg_030 pos_clk.un8_bg_030
Inst pos_clk_un9_bg_030 pos_clk.un9_bg_030
Inst SIZE_DMA_i_1_ SIZE_DMA_i[1]
Inst A_i_19_ A_i[19]
Inst A_i_18_ A_i[18]
@ -113,10 +113,10 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Inst pos_clk_SIZE_DMA_6_0_0_a3_0_ pos_clk.SIZE_DMA_6_0_0_a3[0]
Inst SM_AMIGA_nss_i_i_0_o2_0_ SM_AMIGA_nss_i_i_0_o2[0]
Inst pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3 pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3
Inst pos_clk_un24_bgack_030_int_i_i_a4_i_o3_1 pos_clk.un24_bgack_030_int_i_i_a4_i_o3_1
Inst pos_clk_un24_bgack_030_int_i_i_a4_i_o3_2 pos_clk.un24_bgack_030_int_i_i_a4_i_o3_2
Inst pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1 pos_clk.un23_bgack_030_int_i_i_a4_i_o3_1
Inst pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2 pos_clk.un23_bgack_030_int_i_i_a4_i_o3_2
Inst pos_clk_un37_as_030_d0_i_a3_0 pos_clk.un37_as_030_d0_i_a3_0
Inst pos_clk_un24_bgack_030_int_i_i_a4_i_o3 pos_clk.un24_bgack_030_int_i_i_a4_i_o3
Inst pos_clk_un23_bgack_030_int_i_i_a4_i_o3 pos_clk.un23_bgack_030_int_i_i_a4_i_o3
Inst pos_clk_un37_as_030_d0_i_a3 pos_clk.un37_as_030_d0_i_a3
Inst SM_AMIGA_srsts_i_0_0_1_3_ SM_AMIGA_srsts_i_0_0_1[3]
Inst SM_AMIGA_srsts_i_0_0_2_3_ SM_AMIGA_srsts_i_0_0_2[3]
@ -128,106 +128,108 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Inst SM_AMIGA_nss_i_i_0_3_0_ SM_AMIGA_nss_i_i_0_3[0]
Inst SM_AMIGA_nss_i_i_0_0_ SM_AMIGA_nss_i_i_0[0]
Inst pos_clk_un6_bgack_000_0_0 pos_clk.un6_bgack_000_0_0
Inst SM_AMIGA_5_ SM_AMIGA[5]
Inst pos_clk_SIZE_DMA_6_0_0_1_ pos_clk.SIZE_DMA_6_0_0[1]
Inst SM_AMIGA_4_ SM_AMIGA[4]
Inst pos_clk_SIZE_DMA_6_0_0_1_ pos_clk.SIZE_DMA_6_0_0[1]
Inst SM_AMIGA_3_ SM_AMIGA[3]
Inst pos_clk_un6_bg_030_i pos_clk.un6_bg_030_i
Inst pos_clk_SIZE_DMA_6_0_0_0_ pos_clk.SIZE_DMA_6_0_0[0]
Inst SM_AMIGA_3_ SM_AMIGA[3]
Inst pos_clk_un8_bg_030_i pos_clk.un8_bg_030_i
Inst SM_AMIGA_2_ SM_AMIGA[2]
Inst pos_clk_un37_as_030_d0_i_o2_1 pos_clk.un37_as_030_d0_i_o2_1
Inst pos_clk_un9_bg_030_i pos_clk.un9_bg_030_i
Inst SM_AMIGA_1_ SM_AMIGA[1]
Inst pos_clk_un37_as_030_d0_i_o2_1 pos_clk.un37_as_030_d0_i_o2_1
Inst SM_AMIGA_0_ SM_AMIGA[0]
Inst pos_clk_un37_as_030_d0_i_o2 pos_clk.un37_as_030_d0_i_o2
Inst pos_clk_un37_as_030_d0_i pos_clk.un37_as_030_d0_i
Inst SM_AMIGA_0_ SM_AMIGA[0]
Inst A_i_16_ A_i[16]
Inst IPL_030DFF_0_ IPL_030DFF[0]
Inst pos_clk_un6_bgack_000_0_0_a2 pos_clk.un6_bgack_000_0_0_a2
Inst A_i_16_ A_i[16]
Inst IPL_030DFF_1_ IPL_030DFF[1]
Inst pos_clk_un6_bgack_000_0_0_a2 pos_clk.un6_bgack_000_0_0_a2
Inst IPL_030DFF_2_ IPL_030DFF[2]
Inst pos_clk_un8_sm_amiga_1 pos_clk.un8_sm_amiga_1
Inst IPL_D0_0_ IPL_D0[0]
Inst pos_clk_un8_sm_amiga_1 pos_clk.un8_sm_amiga_1
Inst IPL_D0_1_ IPL_D0[1]
Inst pos_clk_un8_sm_amiga pos_clk.un8_sm_amiga
Inst SM_AMIGA_srsts_i_0_m2_1__r SM_AMIGA_srsts_i_0_m2_1_.r
Inst IPL_D0_1_ IPL_D0[1]
Inst IPL_D0_2_ IPL_D0[2]
Inst SM_AMIGA_srsts_i_i_a2_1_2_ SM_AMIGA_srsts_i_i_a2_1[2]
Inst SM_AMIGA_srsts_i_0_m2_1__m SM_AMIGA_srsts_i_0_m2_1_.m
Inst IPL_D0_2_ IPL_D0[2]
Inst SM_AMIGA_srsts_i_0_m2_1__n SM_AMIGA_srsts_i_0_m2_1_.n
Inst SM_AMIGA_i_7_ SM_AMIGA_i[7]
Inst SM_AMIGA_srsts_i_0_m2_1__p SM_AMIGA_srsts_i_0_m2_1_.p
Inst SM_AMIGA_srsts_i_0_m2_1__n SM_AMIGA_srsts_i_0_m2_1_.n
Inst SM_AMIGA_6_ SM_AMIGA[6]
Inst SM_AMIGA_srsts_i_0_m2_1__p SM_AMIGA_srsts_i_0_m2_1_.p
Inst SM_AMIGA_5_ SM_AMIGA[5]
Inst SM_AMIGA_i_4_ SM_AMIGA_i[4]
Inst CLK_000_N_SYNC_9_ CLK_000_N_SYNC[9]
Inst SM_AMIGA_srsts_i_0_o2_4_ SM_AMIGA_srsts_i_0_o2[4]
Inst CLK_000_N_SYNC_10_ CLK_000_N_SYNC[10]
Inst SM_AMIGA_srsts_i_0_o2_4_ SM_AMIGA_srsts_i_0_o2[4]
Inst CLK_000_N_SYNC_11_ CLK_000_N_SYNC[11]
Inst pos_clk_CYCLE_DMA_5_0_i_o3 pos_clk.CYCLE_DMA_5_0_i_o3
Inst CYCLE_DMA_0_ CYCLE_DMA[0]
Inst SM_AMIGA_srsts_i_0_o3_0_ SM_AMIGA_srsts_i_0_o3[0]
Inst pos_clk_CYCLE_DMA_5_0_i_o3 pos_clk.CYCLE_DMA_5_0_i_o3
Inst CYCLE_DMA_1_ CYCLE_DMA[1]
Inst SM_AMIGA_srsts_i_i_o2_2_ SM_AMIGA_srsts_i_i_o2[2]
Inst SM_AMIGA_srsts_i_0_o3_0_ SM_AMIGA_srsts_i_0_o3[0]
Inst SIZE_DMA_0_ SIZE_DMA[0]
Inst SM_AMIGA_srsts_i_i_0_o2_6_ SM_AMIGA_srsts_i_i_0_o2[6]
Inst SM_AMIGA_srsts_i_i_o2_2_ SM_AMIGA_srsts_i_i_o2[2]
Inst SIZE_DMA_1_ SIZE_DMA[1]
Inst pos_clk_SIZE_DMA_6_0_0_o2_0_ pos_clk.SIZE_DMA_6_0_0_o2[0]
Inst SM_AMIGA_srsts_i_i_0_o2_6_ SM_AMIGA_srsts_i_i_0_o2[6]
Inst cpu_est_0_ cpu_est[0]
Inst SM_AMIGA_i_i_7_ SM_AMIGA_i_i[7]
Inst pos_clk_SIZE_DMA_6_0_0_o2_0_ pos_clk.SIZE_DMA_6_0_0_o2[0]
Inst cpu_est_1_ cpu_est[1]
Inst SM_AMIGA_nss_i_i_0_o2_4_0_ SM_AMIGA_nss_i_i_0_o2_4[0]
Inst SM_AMIGA_i_i_7_ SM_AMIGA_i_i[7]
Inst cpu_est_2_ cpu_est[2]
Inst SM_AMIGA_srsts_i_0_o2_0_0_ SM_AMIGA_srsts_i_0_o2_0[0]
Inst SM_AMIGA_nss_i_i_0_o2_4_0_ SM_AMIGA_nss_i_i_0_o2_4[0]
Inst cpu_est_3_ cpu_est[3]
Inst SM_AMIGA_srsts_i_0_o2_0_0_ SM_AMIGA_srsts_i_0_o2_0[0]
Inst CLK_000_P_SYNC_5_ CLK_000_P_SYNC[5]
Inst CLK_000_P_SYNC_6_ CLK_000_P_SYNC[6]
Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.r
Inst CLK_000_P_SYNC_7_ CLK_000_P_SYNC[7]
Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.r
Inst CLK_000_P_SYNC_8_ CLK_000_P_SYNC[8]
Inst IPL_030_1_i_1_ IPL_030_1_i[1]
Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.m
Inst CLK_000_P_SYNC_8_ CLK_000_P_SYNC[8]
Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.n
Inst CLK_000_P_SYNC_9_ CLK_000_P_SYNC[9]
Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.n
Inst CLK_000_N_SYNC_0_ CLK_000_N_SYNC[0]
Inst IPL_030_1_i_0_ IPL_030_1_i[0]
Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.p
Inst CLK_000_N_SYNC_0_ CLK_000_N_SYNC[0]
Inst CLK_000_N_SYNC_1_ CLK_000_N_SYNC[1]
Inst IPL_c_i_2_ IPL_c_i[2]
Inst pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk.CYCLE_DMA_5_0_i_x2
Inst CLK_000_N_SYNC_1_ CLK_000_N_SYNC[1]
Inst CLK_000_N_SYNC_2_ CLK_000_N_SYNC[2]
Inst IPL_D0_0_i_2_ IPL_D0_0_i[2]
Inst SM_AMIGA_srsts_i_0_m2_5__r SM_AMIGA_srsts_i_0_m2_5_.r
Inst CLK_000_N_SYNC_2_ CLK_000_N_SYNC[2]
Inst CLK_000_N_SYNC_3_ CLK_000_N_SYNC[3]
Inst IPL_c_i_1_ IPL_c_i[1]
Inst SM_AMIGA_srsts_i_0_m2_5__m SM_AMIGA_srsts_i_0_m2_5_.m
Inst CLK_000_N_SYNC_3_ CLK_000_N_SYNC[3]
Inst CLK_000_N_SYNC_4_ CLK_000_N_SYNC[4]
Inst IPL_D0_0_i_1_ IPL_D0_0_i[1]
Inst SM_AMIGA_srsts_i_0_m2_5__n SM_AMIGA_srsts_i_0_m2_5_.n
Inst CLK_000_N_SYNC_4_ CLK_000_N_SYNC[4]
Inst CLK_000_N_SYNC_5_ CLK_000_N_SYNC[5]
Inst IPL_c_i_0_ IPL_c_i[0]
Inst SM_AMIGA_srsts_i_0_m2_5__p SM_AMIGA_srsts_i_0_m2_5_.p
Inst CLK_000_N_SYNC_5_ CLK_000_N_SYNC[5]
Inst CLK_000_N_SYNC_6_ CLK_000_N_SYNC[6]
Inst IPL_D0_0_i_0_ IPL_D0_0_i[0]
Inst cpu_est_0_0_x2_0_ cpu_est_0_0_x2[0]
Inst CLK_000_N_SYNC_6_ CLK_000_N_SYNC[6]
Inst pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk.CYCLE_DMA_5_1_i_x2
Inst CLK_000_N_SYNC_7_ CLK_000_N_SYNC[7]
Inst pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk.CYCLE_DMA_5_1_i_x2
Inst CLK_000_N_SYNC_8_ CLK_000_N_SYNC[8]
Inst CLK_000_N_SYNC_9_ CLK_000_N_SYNC[9]
Inst cpu_est_i_2_ cpu_est_i[2]
Inst RST_DLY_1_ RST_DLY[1]
Inst cpu_est_i_1_ cpu_est_i[1]
Inst RST_DLY_2_ RST_DLY[2]
Inst cpu_est_i_0_ cpu_est_i[0]
Inst CLK_000_P_SYNC_0_ CLK_000_P_SYNC[0]
Inst CLK_000_D_0_ CLK_000_D[0]
Inst cpu_est_i_3_ cpu_est_i[3]
Inst CLK_000_P_SYNC_1_ CLK_000_P_SYNC[1]
Inst CLK_000_D_1_ CLK_000_D[1]
Inst SM_AMIGA_i_3_ SM_AMIGA_i[3]
Inst CLK_000_P_SYNC_2_ CLK_000_P_SYNC[2]
Inst CLK_000_P_SYNC_3_ CLK_000_P_SYNC[3]
Inst CLK_000_P_SYNC_0_ CLK_000_P_SYNC[0]
Inst CLK_000_P_SYNC_1_ CLK_000_P_SYNC[1]
Inst SM_AMIGA_srsts_i_i_i_2_ SM_AMIGA_srsts_i_i_i[2]
Inst A_i_24_ A_i[24]
Inst CLK_000_P_SYNC_2_ CLK_000_P_SYNC[2]
Inst CLK_000_P_SYNC_3_ CLK_000_P_SYNC[3]
Inst CLK_000_P_SYNC_4_ CLK_000_P_SYNC[4]
Inst RST_DLY_0_ RST_DLY[0]
Inst pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3 pos_clk.un5_bgack_030_int_d_i_0_a4_i_o3
Inst RST_DLY_0_ RST_DLY[0]
Inst SM_AMIGA_nss_i_i_0_o2_5_0_ SM_AMIGA_nss_i_i_0_o2_5[0]
Inst SM_AMIGA_nss_i_i_0_o2_0_0_ SM_AMIGA_nss_i_i_0_o2_0[0]
Inst SM_AMIGA_srsts_i_i_o2_0_2_ SM_AMIGA_srsts_i_i_o2_0[2]
@ -242,7 +244,8 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Inst SM_AMIGA_srsts_i_0_o2_0_ SM_AMIGA_srsts_i_0_o2[0]
Inst SM_AMIGA_srsts_i_0_0_o2_3_ SM_AMIGA_srsts_i_0_0_o2[3]
Inst SM_AMIGA_srsts_i_i_0_i_6_ SM_AMIGA_srsts_i_i_0_i[6]
Inst pos_clk_un24_bgack_030_int_i_i_a4_i_x2 pos_clk.un24_bgack_030_int_i_i_a4_i_x2
Inst pos_clk_un23_bgack_030_int_i_i_a4_i_x2 pos_clk.un23_bgack_030_int_i_i_a4_i_x2
Inst CLK_000_D_i_1_ CLK_000_D_i[1]
Inst pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0_ pos_clk.CLK_000_N_SYNC_2_0_a4_0_o2[0]
Inst RST_DLY_i_0_ RST_DLY_i[0]
Inst RST_DLY_i_1_ RST_DLY_i[1]
@ -267,10 +270,11 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Inst cpu_est_2_i_0_i_3_ cpu_est_2_i_0_i[3]
Inst SM_AMIGA_nss_i_i_0_o2_i_0_ SM_AMIGA_nss_i_i_0_o2_i[0]
Inst pos_clk_DS_000_DMA_4_f0_i_a2_i_a3 pos_clk.DS_000_DMA_4_f0_i_a2_i_a3
Inst CLK_000_D_i_0_ CLK_000_D_i[0]
Inst cpu_est_2_0_0_0_a3_1_ cpu_est_2_0_0_0_a3[1]
Inst cpu_est_2_0_0_0_a3_2_ cpu_est_2_0_0_0_a3[2]
Inst cpu_est_2_i_0_i_a3_3_ cpu_est_2_i_0_i_a3[3]
Inst pos_clk_un24_bgack_030_int_i_i_a4_i_a2 pos_clk.un24_bgack_030_int_i_i_a4_i_a2
Inst pos_clk_un23_bgack_030_int_i_i_a4_i_a2 pos_clk.un23_bgack_030_int_i_i_a4_i_a2
Inst A_16_ A[16]
Inst SM_AMIGA_srsts_i_0_0_a2_3_ SM_AMIGA_srsts_i_0_0_a2[3]
Inst A_17_ A[17]
@ -298,7 +302,7 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Inst pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3_i pos_clk.un5_bgack_030_int_d_i_0_a4_i_o3_i
Inst SM_AMIGA_srsts_i_0_a3_0_4_ SM_AMIGA_srsts_i_0_a3_0[4]
Inst A_28_ A[28]
Inst pos_clk_un24_bgack_030_int_i_i_a4_i_o3_i pos_clk.un24_bgack_030_int_i_i_a4_i_o3_i
Inst pos_clk_un23_bgack_030_int_i_i_a4_i_o3_i pos_clk.un23_bgack_030_int_i_i_a4_i_o3_i
Inst SM_AMIGA_i_6_ SM_AMIGA_i[6]
Inst A_29_ A[29]
Inst CLK_000_N_SYNC_i_10_ CLK_000_N_SYNC_i[10]
@ -325,15 +329,15 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Inst SM_AMIGA_srsts_i_i_0_o2_i_6_ SM_AMIGA_srsts_i_i_0_o2_i[6]
Inst SM_AMIGA_srsts_i_i_o2_i_2_ SM_AMIGA_srsts_i_i_o2_i[2]
Inst pos_clk_CYCLE_DMA_5_0_i_o3_i pos_clk.CYCLE_DMA_5_0_i_o3_i
Inst A_i_25_ A_i[25]
Inst pos_clk_un37_as_030_d0_i_o2_i pos_clk.un37_as_030_d0_i_o2_i
Inst A_i_26_ A_i[26]
Inst A_i_25_ A_i[25]
Inst SM_AMIGA_srsts_i_0_o2_i_4_ SM_AMIGA_srsts_i_0_o2_i[4]
Inst A_i_26_ A_i[26]
Inst A_i_27_ A_i[27]
Inst A_i_28_ A_i[28]
Inst A_i_29_ A_i[29]
Inst A_i_30_ A_i[30]
Inst FC_0_ FC[0]
Inst A_i_30_ A_i[30]
Inst FC_1_ FC[1]
Inst pos_clk_un37_as_030_d0_i_i pos_clk.un37_as_030_d0_i_i
Inst IPL_D0_0_0_ IPL_D0_0[0]
@ -517,7 +521,9 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Net rw_000_dma_0_un0_n RW_000_DMA_0.un0
Net cpu_est_i_2__n cpu_est_i[2]
Net a_15__n A[15]
Net clk_000_d_1__n CLK_000_D[1]
Net cpu_est_i_1__n cpu_est_i[1]
Net clk_000_d_0__n CLK_000_D[0]
Net a_14__n A[14]
Net clk_000_p_sync_9__n CLK_000_P_SYNC[9]
Net sm_amiga_i_1__n SM_AMIGA_i[1]
@ -529,8 +535,10 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Net rst_dly_i_0__n RST_DLY_i[0]
Net ipl_d0_1__n IPL_D0[1]
Net rst_dly_i_1__n RST_DLY_i[1]
Net clk_000_d_i_0__n CLK_000_D_i[0]
Net a_11__n A[11]
Net ipl_d0_2__n IPL_D0[2]
Net clk_000_d_i_1__n CLK_000_D_i[1]
Net a_10__n A[10]
Net pos_clk_un6_bg_030_n pos_clk.un6_bg_030
Net sm_amiga_0__n SM_AMIGA[0]
@ -552,7 +560,7 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Net a_5__n A[5]
Net rst_dly_2__n RST_DLY[2]
Net a_i_27__n A_i[27]
Net pos_clk_un8_bg_030_n pos_clk.un8_bg_030
Net pos_clk_un9_bg_030_n pos_clk.un9_bg_030
Net a_i_28__n A_i[28]
Net cpu_est_2_0_2__n cpu_est_2_0[2]
Net a_4__n A[4]
@ -629,7 +637,7 @@ Design 'BUS68030' created Wed Jan 27 21:56:48 2016
Net a_29__n A[29]
Net pos_clk_un6_bg_030_i_n pos_clk.un6_bg_030_i
Net a_c_30__n A_c[30]
Net pos_clk_un8_bg_030_0_n pos_clk.un8_bg_030_0
Net pos_clk_un9_bg_030_0_n pos_clk.un9_bg_030_0
Net a_30__n A[30]
Net a_c_31__n A_c[31]
Net pos_clk_un8_sm_amiga_i_1_n pos_clk.un8_sm_amiga_i_1

30
Logic/bus68030.srf
View File

@ -1,18 +1,18 @@
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: C:\ispLever\synpbase
#install: E:\ispLEVER_Classic2_0\synpbase
#OS: Windows 7 6.2
#Hostname: DEEPTHOUGHT
#Implementation: logic
$ Start of Compile
#Wed Jan 27 21:56:43 2016
#Wed Aug 17 17:45:41 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
@ -22,18 +22,16 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register AMIGA_BUS_ENABLE_INT_4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -44,14 +42,14 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 27 21:56:44 2016
# Wed Aug 17 17:45:41 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -61,6 +59,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 27 21:56:45 2016
# Wed Aug 17 17:45:43 2016
###########################################################]

27
Logic/dm/BUS68030_comp.xdm
View File

@ -6,27 +6,26 @@
">
!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S>
<k1Fs#OC>S
S<k1FsROCbB=":#\HbPpCC#s\$LMbN\#CD\HLP\E8#308P"E8R"N=jD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
/>S1S<FOksC=Rb"\B:Hp#bCsPC\M#$b#LNCH\DLE\P8M\#bE#_N_b#b3 oP"E8R"N=4D"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
/>S1S<FOksC=Rb"\B:Hp#bCsPC\M#$b#LNCH\DLE\P80\#8n44cE3P8N"R="".R"D=PDE8"DROH=#0""-4RHbD#"0=-/4">S
S<k1FsROCbB=":#\HbPpCC#s\$LMbN\#CD\HLP\E8MCkls3HOP"E8R"N=dD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
/>S1S<FOksC=Rb"\B:Hp#bCsPC\M#$b#LNCH\DLE\P8l\ksN_Ob3HlP"E8R"N=cD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
/>S1S<FOksC=Rb"\B:Hp#bCsPC\M#$b#LNCH\DLE\P8s\NH30EP"E8R"N=6D"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
/>S1S<FOksC=Rb"\B:Hp#bCsPC\M#$b#LNCH\DLE\P8M\k#MHoCP83ER8"Nn=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
SF<1kCsOR"b=Bk:\##Cs\0lNx8C\FlOkC#M0\0oHE\kLndUjj\0 DHFoOU\nj-djnjUjjk-L#E3P8N"R=""(R"D=PDE8"DROH=#0""-4RHbD#"0=-/4"><
S/k1Fs#OC>S
<-!-R8vFkRDCs0FFR>--
)S<FRF0MI="F3s Anz1Ujjd3ELCNFPHs"ND/
S<k1FsROCb =":#\Hbep B)_D#N#H_O.j$\#MNbL#DC\HPL\E#8\0P83ER8"Nj=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
SF<1kCsOR"b= H:\# bpe_ )B#DN#.HO_#j\$LMbN\#CD\HLP\E8##Mb_bEN# _boE3P8N"R=""4R"D=PDE8"DROH=#0""-4RHbD#"0=-/4">S
S<k1FsROCb =":#\Hbep B)_D#N#H_O.j$\#MNbL#DC\HPL\E#8\0484nPc3ER8"N.=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
SF<1kCsOR"b= H:\# bpe_ )B#DN#.HO_#j\$LMbN\#CD\HLP\E8MCkls3HOP"E8R"N=dD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
/>S1S<FOksC=Rb"\ :Hp#b )e _NBD#O#H.\_j#b$MLCN#\LDH\8PE\skl_bONHPl3ER8"Nc=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
SF<1kCsOR"b= H:\# bpe_ )B#DN#.HO_#j\$LMbN\#CD\HLP\E8N0sHEE3P8N"R=""6R"D=PDE8"DROH=#0""-4RHbD#"0=-/4">S
S<k1FsROCb =":#\Hbep B)_D#N#H_O.j$\#MNbL#DC\HPL\Ek8\Mo#HM3C8P"E8R"N=nD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
/>S1S<FOksC=Rb"\B:ks#C#N\l0\xC8kFOl0CM#H\o0LEk\jnUd j0\oDFHnO\Ujjd-jnUjLj-kP#3ER8"N(=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
<F/1kCsO#
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S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S>
SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
/>SqS<R"M=3ONsEDVHCP"R=""(/S>
SR<qM3="lkF8DHCVDRC"P(=""
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jc3jn6U("
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.6"
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j66n."
/>SqS<R"M=3MOF#M0N0C_soP"R=J"&k;F0ABtqid_jjh_Qa)_u &R4J0kF;>"/
<SSq=RM"03#lH0D#H00lRC"Pj="3jjjj"jj/S>

2
Logic/lattice_cmd.rs2
View File

@ -1 +1 @@
-src 68030_tk.tt4 -type PLA -devfile "C:/ispLever/ispcpld/dat/mach4a/mach447ace.dev" -postfit -lci 68030_tk.lco
-src 68030_tk.tt4 -type PLA -devfile "E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447ace.dev" -lci "68030_tk.lct" -touch "68030_tk.tt4"

2
Logic/run_options.txt
View File

@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version I-2014.03LC
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Wed Jan 27 21:56:43 2016
#-- Written on Wed Aug 17 17:45:41 2016
#project files

60
Logic/syndos.env
View File

@ -1,39 +1,41 @@
ABEL5DEV=C:\ispLever\ispcpld\lib5
DIOEDA_ABEL5DEV=C:\ispLever\ispcpld\lib5
DIOEDA_ActiveHDL=C:\ispLever\active-hdl\BIN
DIOEDA_ActiveHDLPath=C:\ispLever\active-hdl\BIN
DIOEDA_AppNotes=C:\ispLever\ispcpld\bin
DIOEDA_Bin=C:\ispLever\ispcpld\bin
DIOEDA_Config=C:\ispLever\ispcpld\config
ABEL5DEV=E:\ispLEVER_Classic2_0\ispcpld\lib5
DIOEDA_ABEL5DEV=E:\ispLEVER_Classic2_0\ispcpld\lib5
DIOEDA_ActiveHDL=E:\ispLEVER_Classic2_0\active-hdl\BIN
DIOEDA_ActiveHDLPath=E:\ispLEVER_Classic2_0\active-hdl\BIN
DIOEDA_AppNotes=E:\ispLEVER_Classic2_0\ispcpld\bin
DIOEDA_Bin=E:\ispLEVER_Classic2_0\ispcpld\bin
DIOEDA_Config=E:\ispLEVER_Classic2_0\ispcpld\config
DIOEDA_CONTEXT=ispLEVER CLASSIC
DIOEDA_DSPPATH=C:\ispLever\ispLeverDSP
DIOEDA_EPICPATH=C:\ispLever\ispfpga\bin\nt
DIOEDA_Examples=C:\ispLever\examples
DIOEDA_FPGABinPath=C:\ispLever\ispfpga\bin\nt
DIOEDA_FPGAPath=C:\ispLever\ispfpga
DIOEDA_HDLExplorer=C:\ispLever\hdle\win32
DIOEDA_DSPPATH=E:\ispLEVER_Classic2_0\ispLeverDSP
DIOEDA_EPICPATH=E:\ispLEVER_Classic2_0\ispfpga\bin\nt
DIOEDA_Examples=E:\ispLEVER_Classic2_0\examples
DIOEDA_FPGABinPath=E:\ispLEVER_Classic2_0\ispfpga\bin\nt
DIOEDA_FPGAPath=E:\ispLEVER_Classic2_0\ispfpga
DIOEDA_HDLExplorer=E:\ispLEVER_Classic2_0\hdle\win32
DIOEDA_INI=C:\lsc_env
DIOEDA_ispVM=C:\ispLever\ispvmsystem
DIOEDA_ispVMSystem=C:\ispLever\ispvmsystem
DIOEDA_License=C:\ispLever\license
DIOEDA_MachPath=C:\ispLever\ispcpld\bin
DIOEDA_Manuals=C:\ispLever\ispcpld\manuals
DIOEDA_ModelSim=C:\ispLever\modelsim\win32loem
DIOEDA_ModelsimPath=C:\ispLever\modelsim\win32loem
DIOEDA_PDSPath=C:\ispLever\ispcomp
DIOEDA_ispVM=E:\ispLEVER_Classic2_0\ispvmsystem
DIOEDA_ispVMSystem=E:\ispLEVER_Classic2_0\ispvmsystem
DIOEDA_License=E:\ispLEVER_Classic2_0\license
DIOEDA_LSEPath=E:\ispLEVER_Classic2_0\lse
DIOEDA_MachPath=E:\ispLEVER_Classic2_0\ispcpld\bin
DIOEDA_Manuals=E:\ispLEVER_Classic2_0\ispcpld\manuals
DIOEDA_ModelSim=E:\ispLEVER_Classic2_0\modelsim\win32loem
DIOEDA_ModelsimPath=E:\ispLEVER_Classic2_0\modelsim\win32loem
DIOEDA_PDSPath=E:\ispLEVER_Classic2_0\ispcomp
DIOEDA_Precision=C:\isptools\precision
DIOEDA_PrecisionPath=C:\isptools\precision
DIOEDA_ProductName=ispLEVER
DIOEDA_ProductPrefix=SYN
DIOEDA_ProductTitle=ispLEVER
DIOEDA_ProductType=1.8.00.04.29.14_LS_HDL_BASE_PC_N
DIOEDA_ProductVersion=1.8.00.04
DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 1.8
DIOEDA_Root=C:\ispLever\ispcpld
DIOEDA_ProductType=2.0.00.17.20.15_LS_HDL_BASE_PC_N
DIOEDA_ProductVersion=2.0.00.17
DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 2.0
DIOEDA_Root=E:\ispLEVER_Classic2_0\ispcpld
DIOEDA_Spectrum=C:\isptools\spectrum
DIOEDA_SpectrumPath=C:\isptools\spectrum
DIOEDA_Synplify=C:\ispLever\synpbase
DIOEDA_SynplifyPath=C:\ispLever\synpbase
DIOEDA_Tutorial=C:\ispLever\ispcpld\tutorial
DIOEDA_Synplify=E:\ispLEVER_Classic2_0\synpbase
DIOEDA_SynplifyPath=E:\ispLEVER_Classic2_0\synpbase
DIOEDA_Synthesis=E:\ispLEVER_Classic2_0\lse\bin\nt
DIOEDA_Tutorial=E:\ispLEVER_Classic2_0\ispcpld\tutorial
DIOPRODUCT=ispLEVER
PATH=C:\ispLever\ispcpld\bin
PATH=E:\ispLEVER_Classic2_0\ispcpld\bin

2
Logic/synlog/BUS68030_multi_srs_gen.srr
View File

@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 27 21:56:45 2016
# Wed Aug 17 17:45:43 2016
###########################################################]

5
Logic/synlog/bus68030_fpga_mapper.srr
View File

@ -2,7 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -13,7 +13,6 @@ original code -> new code
101 -> 00100001
110 -> 01000001
111 -> 10000001
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
---------------------------------------
Resource Usage Report
@ -36,6 +35,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 27 21:56:45 2016
# Wed Aug 17 17:45:43 2016
###########################################################]

2
Logic/synlog/report/BUS68030_compiler_errors.txt
View File

@ -1,3 +1,3 @@
@E: CG234 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":86:6:86:6|Duplicate definition of e1
@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":380:22:380:22|No identifier "clk_000_ne_d" in scope
@E|Parse errors encountered - exiting

6
Logic/synlog/report/BUS68030_compiler_notes.txt
View File

@ -1,9 +1,9 @@
@N|Running in 64-bit mode
@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register SM_AMIGA
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est

6
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>13</data>
<data>11</data>
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
@ -29,13 +29,13 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Real Time">
<data>0h:00m:01s</data>
<data>0h:00m:00s</data>
</info>
<info name="Peak Memory">
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1453928204</data>
<data type="timestamp">1471448741</data>
</info>
</job_info>
</job_run_status>

16
Logic/synlog/report/BUS68030_compiler_warnings.txt
View File

@ -1,14 +1,12 @@
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register AMIGA_BUS_ENABLE_INT_4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused

4
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -19,7 +19,7 @@ The file contains the job information from mapper to be displayed as part of the
</report_link>
</info>
<info name="Warnings">
<data>1</data>
<data>0</data>
<report_link name="more">
<data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt</data>
</report_link>
@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>105MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1453928205</data>
<data type="timestamp">1471448743</data>
</info>
</job_info>
</job_run_status>

1
Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt
View File

@ -1 +0,0 @@
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE

61
Logic/syntmp/BUS68030_srr.htm
View File

@ -1,41 +1,39 @@
<html><body><samp><pre>
<!@TC:1453928203>
<!@TC:1471448741>
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: C:\ispLever\synpbase
#install: E:\ispLEVER_Classic2_0\synpbase
#OS: Windows 7 6.2
#Hostname: DEEPTHOUGHT
#Implementation: logic
<a name=compilerReport1>$ Start of Compile</a>
#Wed Jan 27 21:56:43 2016
#Wed Aug 17 17:45:41 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1453928204> | Running in 64-bit mode
@N: : <!@TM:1471448741> | Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1453928204> | Setting time resolution to ns
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453928204> | Top entity is set to BUS68030.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1471448741> | Setting time resolution to ns
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1471448741> | Top entity is set to BUS68030.
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453928204> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:65:10:65:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(65)</a><!@TM:1453928204> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:82:14:82:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(82)</a><!@TM:1453928204> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1453928204> | Signal clk_out_pre is undriven </font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1471448741> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:65:10:65:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(65)</a><!@TM:1471448741> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:82:14:82:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(82)</a><!@TM:1471448741> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1471448741> | Signal clk_out_pre is undriven </font>
Post processing for work.bus68030.behavioral
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928204> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928204> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1453928204> | Pruning register CLK_000_D4_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1453928204> | Pruning register CLK_000_D3_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1453928204> | Pruning register CLK_000_D2_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:34:126:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1453928204> | Pruning register CLK_OUT_EXP_INT_1 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1453928204> | Pruning register CLK_OUT_PRE_25_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:155:2:155:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(155)</a><!@TM:1453928204> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:61:134:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1453928204> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453928204> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928204> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928204> | Trying to extract state machine for register SM_AMIGA
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Pruning register AMIGA_BUS_ENABLE_INT_5 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:34:126:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1471448741> | Pruning register CLK_OUT_EXP_INT_1 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1471448741> | Pruning register CLK_OUT_PRE_25_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:151:2:151:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(151)</a><!@TM:1471448741> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:61:130:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1471448741> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:129:55:129:65:@W:CL271:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1471448741> | Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:127:38:127:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1471448741> | Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -46,24 +44,24 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928204> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1453928204> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1471448741> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 27 21:56:44 2016
# Wed Aug 17 17:45:41 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1453928205> | Running in 64-bit mode
@N: : <!@TM:1471448743> | Running in 64-bit mode
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 27 21:56:45 2016
# Wed Aug 17 17:45:43 2016
###########################################################]
Map & Optimize Report
@ -71,8 +69,8 @@ Map & Optimize Report
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1453928205> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N::@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928205> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1471448743> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@N::@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448743> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -83,7 +81,6 @@ original code -> new code
101 -> 00100001
110 -> 01000001
111 -> 10000001
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453928205> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
---------------------------------------
<a name=resourceUsage3>Resource Usage Report</a>
@ -99,14 +96,14 @@ OR2 27 uses
XOR2 7 uses
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1453928205> | Timing Report not generated for this device, please use place and route tools for timing analysis.
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1471448743> | Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 27 21:56:45 2016
# Wed Aug 17 17:45:43 2016
###########################################################]

6
Logic/syntmp/BUS68030_toc.htm
View File

@ -1,7 +1,7 @@
<html>
<head>
<script type="text/javascript" src="file:///C:\ispLever\synpbase\lib\report\reportlog_tree.js"></script>
<link rel="stylesheet" type="text/css" href="file:///C:\ispLever\synpbase\lib\report\reportlog_tree.css" />
<script type="text/javascript" src="file:///E:\ispLEVER_Classic2_0\synpbase\lib\report\reportlog_tree.js"></script>
<link rel="stylesheet" type="text/css" href="file:///E:\ispLEVER_Classic2_0\synpbase\lib\report\reportlog_tree.css" />
</head>
<body style="background-color:#e0e0ff;">
@ -16,7 +16,7 @@
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
<ul rel="open" >
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (21:56 27-Jan)</a>
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (17:45 17-Aug)</a>
<ul ></ul></li> </ul>
</li>
</ul>

2
Logic/syntmp/run_option.xml
View File

@ -3,7 +3,7 @@
Synopsys, Inc.
Version I-2014.03LC
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Wed Jan 27 21:56:43 2016
Written on Wed Aug 17 17:45:41 2016
-->

12
Logic/syntmp/statusReport.html
View File

@ -33,28 +33,28 @@
<tr>
<td class="optionTitle">Compile Input</td><td>Complete</td>
<td>8</td>
<td>13</td>
<td>11</td>
<td>0</td>
<td>-</td>
<td>0m:01s</td>
<td>0m:00s</td>
<td>-</td>
<td><font size="-1">27.01.2016</font><br/><font size="-2">21:56:44</font></td>
<td><font size="-1">17.08.2016</font><br/><font size="-2">17:45:41</font></td>
</tr>
<tr>
<td class="optionTitle">Map & Optimize</td><td>Complete</td>
<td>2</td>
<td>1</td>
<td>0</td>
<td>0</td>
<td>0m:00s</td>
<td>0m:00s</td>
<td>105MB</td>
<td><font size="-1">27.01.2016</font><br/><font size="-2">21:56:45</font></td>
<td><font size="-1">17.08.2016</font><br/><font size="-2">17:45:43</font></td>
</tr>
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">27.01.2016</font><br/><font size="-2">21:56:45</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:01s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">17.08.2016</font><br/><font size="-2">17:45:43</font></td> </tbody>
</table>
</td></tr></table></body>
</html>

20
Logic/synwork/BUS68030_comp.fdep
View File

@ -1,15 +1,15 @@
#defaultlanguage:vhdl
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401224104
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401223722
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453928190
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\bin64\\c_vhdl.exe":1401224104
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\location.map":1310457374
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471448728
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

20
Logic/synwork/BUS68030_comp.fdeporig
View File

@ -1,15 +1,15 @@
#defaultlanguage:vhdl
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401224104
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401223722
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453928190
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\bin64\\c_vhdl.exe":1401224104
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\location.map":1310457374
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471448728
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

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Logic/synwork/BUS68030_comp.srs
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20
Logic/synwork/BUS68030_comp.tlg
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@ -3,18 +3,16 @@
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register AMIGA_BUS_ENABLE_INT_4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -25,5 +23,5 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused

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Logic/synwork/BUS68030_mult.srs
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Logic/synwork/BUS68030_mult_srs/skeleton.srs
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Logic/synwork/BUS68030_s.srs
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