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68030tk/Logic/68030_tk.rpt

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Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
|--------------------------------------------|
|- ispLEVER Fitter Report File -|
|- Version 1.7.00.05.28.13 -|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|--------------------------------------------|
Project_Summary
~~~~~~~~~~~~~~~
Project Name : 68030_tk
Working!
2014-05-15 20:19:03 +00:00
Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
Project Fitted on : Mon Jun 09 10:27:29 2014
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Device : M4A5-128/64
Package : 100TQFP
Speed : -10
Partnumber : M4A5-128/64-10VC
Source Format : Pure_VHDL
// Project '68030_tk' was Fitted Successfully! //
Compilation_Times
~~~~~~~~~~~~~~~~~
Reading/DRC 0 sec
Partition 0 sec
Place 0 sec
Route 0 sec
Jedec/Report generation 0 sec
--------
Fitter 00:00:00
Design_Summary
~~~~~~~~~~~~~~
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
Total Input Pins : 29
Total Output Pins : 18
Total Bidir I/O Pins : 12
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
Total Flip-Flops : 72
Total Product Terms : 151
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Total Reserved Pins : 0
Total Reserved Blocks : 0
Device_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
Total
Available Used Available Utilization
Dedicated Pins
Input-Only Pins 2 2 0 --> 100%
Clock/Input Pins 4 4 0 --> 100%
I/O Pins 64 53 11 --> 82%
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
Logic Macrocells 128 80 48 --> 62%
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Input Registers 64 0 64 --> 0%
Unusable Macrocells .. 0 ..
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
CSM Outputs/Total Block Inputs 264 190 74 --> 71%
Logical Product Terms 640 152 488 --> 23%
Product Term Clusters 128 35 93 --> 27%
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00

Blocks_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
# of PT
I/O Inp Macrocells Macrocells logic clusters
Fanin Pins Reg Used Unusable available PTs available Pwr
---------------------------------------------------------------------------------
Maximum 33 8 8 -- -- 16 80 16 -
---------------------------------------------------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
Block A 19 7 0 11 0 5 21 13 Hi
Block B 21 8 0 11 0 5 21 10 Hi
Block C 18 8 0 11 0 5 15 13 Hi
Block D 31 8 0 10 0 6 23 9 Hi
Block E 29 3 0 7 0 9 8 15 Hi
Block F 21 4 0 10 0 6 18 12 Hi
Block G 23 7 0 10 0 6 24 11 Hi
Block H 28 8 0 10 0 6 22 10 Hi
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
---------------------------------------------------------------------------------
<Note> Four rightmost columns above reflect last status of the placement process.
<Note> Pwr (Power) : Hi = High
Lo = Low.

Optimizer_and_Fitter_Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Pin Assignment : Yes
Group Assignment : No
Pin Reservation : No (1)
Block Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
Balanced Partitioning : Yes
Spread Placement : Yes
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : Yes
D/T Synthesis : Yes
Clock Optimization : No
Input Register Optimization : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 16
Max. P-Term for Splitting : 16
Max. Equation Fanin : 32
Keep Xor : Yes
@Utilization_options
Max. % of macrocells used : 100
Max. % of block inputs used : 100
Max. % of segment lines used : ---
Max. % of macrocells used : ---
@Import_Source_Constraint_Option No
timing enhanced?
2014-05-25 19:20:36 +00:00
@Zero_Hold_Time Yes
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
@Pull_up Yes
@User_Signature #H0
timing enhanced?
2014-05-25 19:20:36 +00:00
@Output_Slew_Rate Default = Slow(2)
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
@Power Default = High(2)
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Burried Signal Lists.

Pinout_Listing
~~~~~~~~~~~~~~
| Pin |Blk |Assigned|
Pin No| Type |Pad |Pin | Signal name
---------------------------------------------------------------
1 | GND | | |
2 | JTAG | | |
3 | I_O | B7 | * |RESET
4 | I_O | B6 | * |A_31_
5 | I_O | B5 | * |A_30_
6 | I_O | B4 | * |A_29_
7 | I_O | B3 | * |IPL_030_1_
8 | I_O | B2 | * |IPL_030_0_
9 | I_O | B1 | * |IPL_030_2_
10 | I_O | B0 | * |CLK_EXP
11 | CkIn | | * |CLK_000
12 | Vcc | | |
13 | GND | | |
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
14 | CkIn | | * |nEXP_SPACE
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
15 | I_O | C0 | * |A_28_
16 | I_O | C1 | * |A_27_
17 | I_O | C2 | * |A_26_
18 | I_O | C3 | * |A_25_
19 | I_O | C4 | * |A_24_
20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW
21 | I_O | C6 | * |BG_030
22 | I_O | C7 | * |AVEC_EXP
23 | JTAG | | |
24 | JTAG | | |
25 | GND | | |
26 | GND | | |
27 | GND | | |
28 | I_O | D7 | * |BGACK_000
29 | I_O | D6 | * |BG_000
30 | I_O | D5 | * |DTACK
31 | I_O | D4 | * |LDS_000
32 | I_O | D3 | * |UDS_000
33 | I_O | D2 | * |AS_000
34 | I_O | D1 | * |AMIGA_BUS_ENABLE
35 | I_O | D0 | * |VMA
36 | Inp | | * |VPA
37 | Vcc | | |
38 | GND | | |
39 | GND | | |
40 | Vcc | | |
41 | I_O | E0 | * |BERR
42 | I_O | E1 | |
43 | I_O | E2 | |
44 | I_O | E3 | |
45 | I_O | E4 | |
46 | I_O | E5 | |
47 | I_O | E6 | * |CIIN
48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR
49 | GND | | |
50 | GND | | |
51 | GND | | |
52 | JTAG | | |
53 | I_O | F7 | |
54 | I_O | F6 | |
55 | I_O | F5 | |
56 | I_O | F4 | * |IPL_1_
57 | I_O | F3 | * |FC_0_
58 | I_O | F2 | * |FC_1_
59 | I_O | F1 | * |A_17_
60 | I_O | F0 | |
61 | CkIn | | * |CLK_OSZI
62 | Vcc | | |
63 | GND | | |
64 | CkIn | | * |CLK_030
65 | I_O | G0 | * |CLK_DIV_OUT
66 | I_O | G1 | * |E
67 | I_O | G2 | * |IPL_0_
68 | I_O | G3 | * |IPL_2_
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
69 | I_O | G4 | * |A0
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
70 | I_O | G5 | * |SIZE_0_
71 | I_O | G6 | * |RW
72 | I_O | G7 | |
73 | JTAG | | |
74 | JTAG | | |
75 | GND | | |
76 | GND | | |
77 | GND | | |
78 | I_O | H7 | * |FPU_CS
79 | I_O | H6 | * |SIZE_1_
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
80 | I_O | H5 | * |RW_000
81 | I_O | H4 | * |DSACK1
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
82 | I_O | H3 | * |AS_030
83 | I_O | H2 | * |BGACK_030
84 | I_O | H1 | * |A_23_
85 | I_O | H0 | * |A_22_
86 | Inp | | * |RST
87 | Vcc | | |
88 | GND | | |
89 | GND | | |
90 | Vcc | | |
91 | I_O | A0 | |
92 | I_O | A1 | * |AVEC
93 | I_O | A2 | * |A_20_
94 | I_O | A3 | * |A_21_
95 | I_O | A4 | * |A_18_
96 | I_O | A5 | * |A_16_
97 | I_O | A6 | * |A_19_
98 | I_O | A7 | * |DS_030
99 | GND | | |
100 | GND | | |
---------------------------------------------------------------------------
<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type :
CkIn : Dedicated input or clock pin
CLK : Dedicated clock pin
INP : Dedicated input pin
JTAG : JTAG Control and test pin
NC : No connected

Input_Signal_List
~~~~~~~~~~~~~~~~~
P R
Pin r e O Input
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
96 A . I/O ----E--H Hi Slow A_16_
59 F . I/O ----E--H Hi Slow A_17_
95 A . I/O ----E--H Hi Slow A_18_
97 A . I/O ----E--H Hi Slow A_19_
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
93 A . I/O ----E--- Hi Slow A_20_
94 A . I/O ----E--- Hi Slow A_21_
85 H . I/O ----E--- Hi Slow A_22_
84 H . I/O ----E--- Hi Slow A_23_
19 C . I/O ----E--- Hi Slow A_24_
18 C . I/O ----E--- Hi Slow A_25_
17 C . I/O ----E--- Hi Slow A_26_
16 C . I/O ----E--- Hi Slow A_27_
15 C . I/O ----E--- Hi Slow A_28_
6 B . I/O ----E--- Hi Slow A_29_
5 B . I/O ----E--- Hi Slow A_30_
4 B . I/O ----E--- Hi Slow A_31_
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
28 D . I/O ----E--H Hi Slow BGACK_000
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
21 C . I/O ---D---- Hi Slow BG_030
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
57 F . I/O ----E--H Hi Slow FC_0_
58 F . I/O ----E--H Hi Slow FC_1_
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
67 G . I/O -B------ Hi Slow IPL_0_
56 F . I/O -B------ Hi Slow IPL_1_
68 G . I/O -B------ Hi Slow IPL_2_
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
11 . . Ck/I ---D-F-- - Slow CLK_000
RW-Fixed
2014-06-07 21:13:48 +00:00
14 . . Ck/I A--DE-GH - Slow nEXP_SPACE
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
36 . . Ded ------G- - Slow VPA
61 . . Ck/I ABCDEFGH - Slow CLK_OSZI
64 . . Ck/I A-----GH - Slow CLK_030
86 . . Ded ABCDEFGH - Slow RST
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Output_Signal_List
~~~~~~~~~~~~~~~~~~
P R
Pin r e O Output
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
48 E 2 COM -------- Hi Slow AMIGA_BUS_DATA_DIR
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
34 D 6 DFF * -------- Hi Slow AMIGA_BUS_ENABLE
20 C 1 DFF * -------- Hi Slow AMIGA_BUS_ENABLE_LOW
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
92 A 1 COM -------- Hi Slow AVEC
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
22 C 1 DFF * -------- Hi Slow AVEC_EXP
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
41 E 1 COM -------- Hi Slow BERR
83 H 2 DFF * -------- Hi Slow BGACK_030
29 D 2 DFF * -------- Hi Slow BG_000
47 E 1 COM -------- Hi Slow CIIN
65 G 1 DFF * -------- Hi Slow CLK_DIV_OUT
10 B 1 DFF * -------- Hi Slow CLK_EXP
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
66 G 4 DFF * -------- Hi Slow E
78 H 1 COM -------- Hi Slow FPU_CS
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
8 B 3 DFF * -------- Hi Slow IPL_030_0_
7 B 3 DFF * -------- Hi Slow IPL_030_1_
9 B 3 DFF * -------- Hi Slow IPL_030_2_
3 B 1 DFF * -------- Hi Slow RESET
35 D 2 DFF * -------- Hi Slow VMA
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Bidir_Signal_List
~~~~~~~~~~~~~~~~~
P R
Pin r e O Bidir
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
69 G 1 DFF * --C----- Hi Slow A0
33 D 2 DFF * A---E-GH Hi Slow AS_000
82 H 4 DFF * -B-DE--H Hi Slow AS_030
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
81 H 2 DFF * ---D---- Hi Slow DSACK1
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
98 A 7 DFF * --C----- Hi Slow DS_030
30 D 1 COM -----F-- Hi Slow DTACK
31 D 1 COM A-----GH Hi Slow LDS_000
71 G 4 DFF * -B--E--H Hi Slow RW
80 H 3 DFF * A-----G- Hi Slow RW_000
70 G 1 DFF * --C----- Hi Slow SIZE_0_
79 H 2 DFF * --C----- Hi Slow SIZE_1_
32 D 1 COM A-----GH Hi Slow UDS_000
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Buried_Signal_List
~~~~~~~~~~~~~~~~~~
P R
Pin r e O Node
#Mc Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
F6 F 1 DFF * A------- Hi Slow CLK_000_N_SYNC_0_
A9 A 1 DFF * A------- Hi Slow CLK_000_N_SYNC_10_
A10 A 1 DFF * A------- Hi Slow CLK_000_N_SYNC_11_
A6 A 1 DFF * ----E--- Hi Slow CLK_000_N_SYNC_1_
E5 E 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_2_
C14 C 1 DFF * A------- Hi Slow CLK_000_N_SYNC_3_
A2 A 1 DFF * A------- Hi Slow CLK_000_N_SYNC_4_
A13 A 1 DFF * -----F-- Hi Slow CLK_000_N_SYNC_5_
F2 F 1 DFF * ----E--- Hi Slow CLK_000_N_SYNC_6_
E1 E 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_7_
C10 C 1 DFF * -----F-- Hi Slow CLK_000_N_SYNC_8_
F13 F 1 DFF * A------- Hi Slow CLK_000_N_SYNC_9_
F9 F 1 DFF * -B------ Hi Slow CLK_000_P_SYNC_0_
B2 B 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_1_
C6 C 1 DFF * A------- Hi Slow CLK_000_P_SYNC_2_
A5 A 1 DFF * ------G- Hi Slow CLK_000_P_SYNC_3_
G6 G 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_4_
C2 C 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_5_
C13 C 1 DFF * A------- Hi Slow CLK_000_P_SYNC_6_
A1 A 1 DFF * -----F-- Hi Slow CLK_000_P_SYNC_7_
F5 F 1 DFF * -B------ Hi Slow CLK_000_P_SYNC_8_
B6 B 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_9_
D5 D 6 DFF * ---D---- Hi - RN_AMIGA_BUS_ENABLE --> AMIGA_BUS_ENABLE
C12 C 1 DFF * -------H Hi - RN_AMIGA_BUS_ENABLE_LOW --> AMIGA_BUS_ENABLE_LOW
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
D4 D 2 DFF * ---D---- Hi - RN_AS_000 --> AS_000
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
H6 H 4 DFF * A--D--GH Hi - RN_AS_030 --> AS_030
C4 C 1 DFF * -B-D-FGH Hi - RN_AVEC_EXP --> AVEC_EXP
H5 H 2 DFF * A--DE-GH Hi - RN_BGACK_030 --> BGACK_030
D13 D 2 DFF * ---D---- Hi - RN_BG_000 --> BG_000
H12 H 2 DFF * -------H Hi - RN_DSACK1 --> DSACK1
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
A0 A 7 DFF * A------- Hi - RN_DS_030 --> DS_030
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
G4 G 4 DFF * ---D-FG- Hi - RN_E --> E
B8 B 3 DFF * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_
B12 B 3 DFF * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_
B4 B 3 DFF * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_
G0 G 4 DFF * ------G- Hi - RN_RW --> RW
H0 H 3 DFF * -------H Hi - RN_RW_000 --> RW_000
D1 D 2 DFF * ---D-F-- Hi - RN_VMA --> VMA
D6 D 2 DFF * ---D---- Hi Slow SM_AMIGA_0_
F8 F 2 DFF * ---D-F-H Hi Slow SM_AMIGA_1_
F1 F 3 DFF * -----F-- Hi Slow SM_AMIGA_2_
F12 F 5 TFF * -----F-- Hi Slow SM_AMIGA_3_
B9 B 2 DFF * -B---F-- Hi Slow SM_AMIGA_4_
B13 B 2 DFF * -B------ Hi Slow SM_AMIGA_5_
G5 G 2 DFF * -B-D--GH Hi Slow SM_AMIGA_6_
D2 D 4 DFF * ---D--GH Hi Slow SM_AMIGA_7_
F4 F 2 DFF * ---D-FG- Hi Slow cpu_est_0_
G9 G 5 DFF * ---D-FG- Hi Slow cpu_est_1_
G13 G 4 DFF * ---D--G- Hi Slow cpu_est_2_
H4 H 5 DFF * ---D--GH Hi Slow inst_AS_030_000_SYNC
H10 H 1 DFF * ---D---- Hi Slow inst_BGACK_030_INT_D
F0 F 1 DFF * -B-D-F-H Hi Slow inst_CLK_000_D0
H9 H 1 DFF * -B-D-FGH Hi Slow inst_CLK_000_D1
D9 D 1 DFF * ---DEFG- Hi Slow inst_CLK_000_D2
E9 E 1 DFF * -----F-- Hi Slow inst_CLK_000_D3
A8 A 1 DFF * -B-D-F-- Hi Slow inst_CLK_000_NE
A12 A 5 DFF A------- Hi Slow inst_CLK_030_H
B10 B 1 DFF * --C----- Hi Slow inst_CLK_OUT_PRE
C1 C 3 DFF * -BC----- Hi Slow inst_CLK_OUT_PRE_25
E8 E 1 DFF * --C-E--H Hi Slow inst_CLK_OUT_PRE_50
H13 H 1 DFF * --C----- Hi Slow inst_CLK_OUT_PRE_50_D
C8 C 1 DFF * -BC---G- Hi Slow inst_CLK_OUT_PRE_D
B5 B 3 DFF * -B-D---- Hi Slow inst_DS_000_ENABLE
C9 C 2 DFF * --CD---- Hi Slow inst_LDS_000_INT
C5 C 2 DFF * --CD---- Hi Slow inst_UDS_000_INT
G2 G 1 DFF * ---D-F-- Hi Slow inst_VPA_D
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Signals_Fanout_List
~~~~~~~~~~~~~~~~~~~
Signal Source : Fanout List
-----------------------------------------------------------------------------
RW-Fixed
2014-06-07 21:13:48 +00:00
A_31_{ C}: CIIN{ E}
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
IPL_2_{ H}: IPL_030_2_{ B}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
A_30_{ C}: CIIN{ E}
A_29_{ C}: CIIN{ E}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
UDS_000{ E}: SIZE_1_{ H} AS_030{ H} SIZE_0_{ G}
: DS_030{ A} A0{ G} RW{ G}
: inst_CLK_030_H{ A}
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
A_28_{ D}: CIIN{ E}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
LDS_000{ E}: SIZE_1_{ H} AS_030{ H} SIZE_0_{ G}
: DS_030{ A} A0{ G} RW{ G}
: inst_CLK_030_H{ A}
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
A_27_{ D}: CIIN{ E}
RW-Fixed
2014-06-07 21:13:48 +00:00
A_26_{ D}: CIIN{ E}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
nEXP_SPACE{. }: DTACK{ D}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H}
: AS_030{ H} SIZE_0_{ G} DS_030{ A}
: A0{ G} BG_000{ D} DSACK1{ H}
:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_7_{ D}
: SM_AMIGA_6_{ G}
RW-Fixed
2014-06-07 21:13:48 +00:00
A_25_{ D}: CIIN{ E}
A_24_{ D}: CIIN{ E}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
BG_030{ D}: BG_000{ D}
RW-Fixed
2014-06-07 21:13:48 +00:00
A_23_{ I}: CIIN{ E}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
A_22_{ I}: CIIN{ E}
A_21_{ B}: CIIN{ E}
BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H}
:inst_AS_030_000_SYNC{ H}
A_20_{ B}: CIIN{ E}
CLK_030{. }: AS_030{ H} DS_030{ A} RW{ G}
: inst_CLK_030_H{ A}
A_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ F}
A_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
A_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
A_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
IPL_1_{ G}: IPL_030_1_{ B}
DTACK{ E}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
IPL_0_{ H}: IPL_030_0_{ B}
FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
VPA{. }: inst_VPA_D{ G}
RST{. }: CLK_DIV_OUT{ G} SIZE_1_{ H} IPL_030_2_{ B}
: AS_030{ H} AS_000{ D} SIZE_0_{ G}
: RW_000{ H} DS_030{ A} A0{ G}
: BG_000{ D} BGACK_030{ H} CLK_EXP{ B}
: IPL_030_1_{ B} IPL_030_0_{ B} DSACK1{ H}
: AVEC_EXP{ C} E{ G} VMA{ D}
: RESET{ B} RW{ G}AMIGA_BUS_ENABLE{ D}
:AMIGA_BUS_ENABLE_LOW{ C}inst_AS_030_000_SYNC{ H}inst_BGACK_030_INT_D{ H}
: inst_VPA_D{ G}inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE{ B}
:inst_CLK_000_D0{ F}inst_CLK_000_D1{ H}inst_CLK_OUT_PRE_50{ E}
:inst_CLK_OUT_PRE_25{ C}inst_CLK_000_D2{ D}inst_CLK_000_D3{ E}
:inst_CLK_000_NE{ A}inst_CLK_OUT_PRE_D{ C}CLK_000_P_SYNC_9_{ B}
:CLK_000_N_SYNC_11_{ A} SM_AMIGA_7_{ D} SM_AMIGA_6_{ G}
: SM_AMIGA_1_{ F} SM_AMIGA_0_{ D} SM_AMIGA_4_{ B}
: inst_CLK_030_H{ A}inst_LDS_000_INT{ C}inst_DS_000_ENABLE{ B}
:inst_UDS_000_INT{ C}CLK_000_N_SYNC_0_{ F}CLK_000_N_SYNC_1_{ A}
:CLK_000_N_SYNC_2_{ E}CLK_000_N_SYNC_3_{ C}CLK_000_N_SYNC_4_{ A}
:CLK_000_N_SYNC_5_{ A}CLK_000_N_SYNC_6_{ F}CLK_000_N_SYNC_7_{ E}
:CLK_000_N_SYNC_8_{ C}CLK_000_N_SYNC_9_{ F}CLK_000_N_SYNC_10_{ A}
:CLK_000_P_SYNC_0_{ F}CLK_000_P_SYNC_1_{ B}CLK_000_P_SYNC_2_{ C}
:CLK_000_P_SYNC_3_{ A}CLK_000_P_SYNC_4_{ G}CLK_000_P_SYNC_5_{ C}
:CLK_000_P_SYNC_6_{ C}CLK_000_P_SYNC_7_{ A}CLK_000_P_SYNC_8_{ F}
: SM_AMIGA_5_{ B} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
: cpu_est_0_{ F} cpu_est_1_{ G} cpu_est_2_{ G}
SIZE_1_{ I}:inst_LDS_000_INT{ C}
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
RN_IPL_030_2_{ C}: IPL_030_2_{ B}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
AS_030{ I}: BERR{ E} FPU_CS{ H} AS_000{ D}
: BG_000{ D} DSACK1{ H}AMIGA_BUS_ENABLE{ D}
:inst_AS_030_000_SYNC{ H}inst_DS_000_ENABLE{ B}
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
RN_AS_030{ I}: DTACK{ D} SIZE_1_{ H} AS_030{ H}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
: SIZE_0_{ G} DS_030{ A} A0{ G}
: inst_CLK_030_H{ A}
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
AS_000{ E}:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
: SIZE_0_{ G} DS_030{ A} A0{ G}
: RW{ G} inst_CLK_030_H{ A}
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
RN_AS_000{ E}: AS_000{ D} VMA{ D}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
SIZE_0_{ H}:inst_LDS_000_INT{ C}
RW_000{ I}: DS_030{ A} RW{ G}
RN_RW_000{ I}: RW_000{ H}
DS_030{ B}:inst_LDS_000_INT{ C}inst_UDS_000_INT{ C}
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
RN_DS_030{ B}: DS_030{ A}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
A0{ H}:inst_LDS_000_INT{ C}inst_UDS_000_INT{ C}
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
RN_BG_000{ E}: BG_000{ D}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
RN_BGACK_030{ I}: UDS_000{ D} LDS_000{ D} DTACK{ D}
RW-Fixed
2014-06-07 21:13:48 +00:00
:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
: AS_000{ D} SIZE_0_{ G} RW_000{ H}
: DS_030{ A} A0{ G} BGACK_030{ H}
: RW{ G}AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}
:inst_BGACK_030_INT_D{ H} inst_CLK_030_H{ A}
RN_IPL_030_1_{ C}: IPL_030_1_{ B}
RN_IPL_030_0_{ C}: IPL_030_0_{ B}
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
DSACK1{ I}: DTACK{ D}
RN_DSACK1{ I}: DSACK1{ H}
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
RN_AVEC_EXP{ D}: AS_000{ D} RW_000{ H} E{ G}
: SM_AMIGA_7_{ D} SM_AMIGA_6_{ G} SM_AMIGA_1_{ F}
: SM_AMIGA_0_{ D} SM_AMIGA_4_{ B}inst_DS_000_ENABLE{ B}
: SM_AMIGA_5_{ B} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
: cpu_est_0_{ F} cpu_est_1_{ G} cpu_est_2_{ G}
RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F} cpu_est_1_{ G} cpu_est_2_{ G}
RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
RW{ H}:AMIGA_BUS_DATA_DIR{ E} RW_000{ H}inst_DS_000_ENABLE{ B}
RN_RW{ H}: RW{ G}
RN_AMIGA_BUS_ENABLE{ E}:AMIGA_BUS_ENABLE{ D}
RN_AMIGA_BUS_ENABLE_LOW{ D}: DSACK1{ H}
inst_AS_030_000_SYNC{ I}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_7_{ D}
: SM_AMIGA_6_{ G}
inst_BGACK_030_INT_D{ I}:AMIGA_BUS_ENABLE{ D}
inst_VPA_D{ H}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
inst_CLK_OUT_PRE_50_D{ I}:inst_CLK_OUT_PRE_25{ C}
inst_CLK_OUT_PRE{ C}:AMIGA_BUS_ENABLE_LOW{ C}inst_CLK_OUT_PRE_D{ C}
inst_CLK_000_D0{ G}: IPL_030_2_{ B} BGACK_030{ H} IPL_030_1_{ B}
: IPL_030_0_{ B} VMA{ D}inst_CLK_000_D1{ H}
:CLK_000_N_SYNC_0_{ F}CLK_000_P_SYNC_0_{ F}
inst_CLK_000_D1{ I}: IPL_030_2_{ B} BGACK_030{ H} IPL_030_1_{ B}
: IPL_030_0_{ B} DSACK1{ H}AMIGA_BUS_ENABLE{ D}
:inst_CLK_000_D2{ D} SM_AMIGA_7_{ D} SM_AMIGA_6_{ G}
:CLK_000_N_SYNC_0_{ F}CLK_000_P_SYNC_0_{ F}
inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE_50{ E}inst_CLK_OUT_PRE_25{ C}
inst_CLK_OUT_PRE_25{ D}:inst_CLK_OUT_PRE{ B}inst_CLK_OUT_PRE_25{ C}
inst_CLK_000_D2{ E}:AMIGA_BUS_ENABLE{ D}inst_CLK_000_D3{ E} SM_AMIGA_7_{ D}
: SM_AMIGA_6_{ G}CLK_000_N_SYNC_0_{ F}CLK_000_P_SYNC_0_{ F}
inst_CLK_000_D3{ F}:CLK_000_N_SYNC_0_{ F}CLK_000_P_SYNC_0_{ F}
inst_CLK_000_NE{ B}:AMIGA_BUS_ENABLE{ D} SM_AMIGA_1_{ F} SM_AMIGA_0_{ D}
: SM_AMIGA_4_{ B} SM_AMIGA_5_{ B} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F}
inst_CLK_OUT_PRE_D{ D}: CLK_DIV_OUT{ G} CLK_EXP{ B}AMIGA_BUS_ENABLE_LOW{ C}
CLK_000_P_SYNC_9_{ C}: AVEC_EXP{ C}
CLK_000_N_SYNC_11_{ B}:inst_CLK_000_NE{ A}
SM_AMIGA_7_{ E}: RW_000{ H} BG_000{ D}AMIGA_BUS_ENABLE{ D}
:inst_AS_030_000_SYNC{ H} SM_AMIGA_7_{ D} SM_AMIGA_6_{ G}
SM_AMIGA_6_{ H}: AS_000{ D} RW_000{ H} SM_AMIGA_6_{ G}
:inst_DS_000_ENABLE{ B} SM_AMIGA_5_{ B}
SM_AMIGA_1_{ G}: DSACK1{ H}AMIGA_BUS_ENABLE{ D} SM_AMIGA_1_{ F}
: SM_AMIGA_0_{ D}
SM_AMIGA_0_{ E}:AMIGA_BUS_ENABLE{ D} SM_AMIGA_7_{ D} SM_AMIGA_0_{ D}
SM_AMIGA_4_{ C}: SM_AMIGA_4_{ B}inst_DS_000_ENABLE{ B} SM_AMIGA_3_{ F}
inst_CLK_030_H{ B}: DS_030{ A} inst_CLK_030_H{ A}
inst_LDS_000_INT{ D}: LDS_000{ D}inst_LDS_000_INT{ C}
inst_DS_000_ENABLE{ C}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ B}
inst_UDS_000_INT{ D}: UDS_000{ D}inst_UDS_000_INT{ C}
CLK_000_N_SYNC_0_{ G}:CLK_000_N_SYNC_1_{ A}
CLK_000_N_SYNC_1_{ B}:CLK_000_N_SYNC_2_{ E}
CLK_000_N_SYNC_2_{ F}:CLK_000_N_SYNC_3_{ C}
CLK_000_N_SYNC_3_{ D}:CLK_000_N_SYNC_4_{ A}
CLK_000_N_SYNC_4_{ B}:CLK_000_N_SYNC_5_{ A}
CLK_000_N_SYNC_5_{ B}:CLK_000_N_SYNC_6_{ F}
CLK_000_N_SYNC_6_{ G}:CLK_000_N_SYNC_7_{ E}
CLK_000_N_SYNC_7_{ F}:CLK_000_N_SYNC_8_{ C}
CLK_000_N_SYNC_8_{ D}:CLK_000_N_SYNC_9_{ F}
CLK_000_N_SYNC_9_{ G}:CLK_000_N_SYNC_10_{ A}
CLK_000_N_SYNC_10_{ B}:CLK_000_N_SYNC_11_{ A}
CLK_000_P_SYNC_0_{ G}:CLK_000_P_SYNC_1_{ B}
CLK_000_P_SYNC_1_{ C}:CLK_000_P_SYNC_2_{ C}
CLK_000_P_SYNC_2_{ D}:CLK_000_P_SYNC_3_{ A}
CLK_000_P_SYNC_3_{ B}:CLK_000_P_SYNC_4_{ G}
CLK_000_P_SYNC_4_{ H}:CLK_000_P_SYNC_5_{ C}
CLK_000_P_SYNC_5_{ D}:CLK_000_P_SYNC_6_{ C}
CLK_000_P_SYNC_6_{ D}:CLK_000_P_SYNC_7_{ A}
CLK_000_P_SYNC_7_{ B}:CLK_000_P_SYNC_8_{ F}
CLK_000_P_SYNC_8_{ G}:CLK_000_P_SYNC_9_{ B}
SM_AMIGA_5_{ C}: SM_AMIGA_4_{ B} SM_AMIGA_5_{ B}
SM_AMIGA_3_{ G}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
SM_AMIGA_2_{ G}: SM_AMIGA_1_{ F} SM_AMIGA_2_{ F}
cpu_est_0_{ G}: E{ G} VMA{ D} cpu_est_0_{ F}
: cpu_est_1_{ G} cpu_est_2_{ G}
cpu_est_1_{ H}: E{ G} VMA{ D} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F} cpu_est_1_{ G} cpu_est_2_{ G}
cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ G}
: cpu_est_2_{ G}
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
-----------------------------------------------------------------------------
<Note> {.} : Indicates block location of signal

Set_Reset_Summary
~~~~~~~~~~~~~~~~~
Block A
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
block level set pt : !RST
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
block level reset pt :
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
| * | S | BS | BR | DS_030
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
| | | | | AVEC
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BR | BS | inst_CLK_000_NE
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
| * | S | BS | BR | RN_DS_030
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BR | BR | inst_CLK_030_H
| * | S | BR | BS | CLK_000_P_SYNC_7_
| * | S | BR | BS | CLK_000_P_SYNC_3_
| * | S | BR | BS | CLK_000_N_SYNC_10_
| * | S | BR | BS | CLK_000_N_SYNC_5_
| * | S | BR | BS | CLK_000_N_SYNC_4_
| * | S | BR | BS | CLK_000_N_SYNC_1_
| * | S | BR | BS | CLK_000_N_SYNC_11_
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
| | | | | A_19_
| | | | | A_16_
| | | | | A_18_
| | | | | A_21_
| | | | | A_20_
Block B
block level set pt : !RST
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
block level reset pt :
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| * | S | BS | BR | IPL_030_2_
| * | S | BS | BR | IPL_030_0_
| * | S | BS | BR | IPL_030_1_
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
| * | S | BR | BS | CLK_EXP
| * | S | BR | BS | RESET
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BR | BS | inst_DS_000_ENABLE
| * | S | BR | BS | SM_AMIGA_4_
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
| * | S | BS | BR | RN_IPL_030_0_
| * | S | BS | BR | RN_IPL_030_1_
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
| * | S | BS | BR | RN_IPL_030_2_
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BR | BS | SM_AMIGA_5_
| * | S | BR | BS | CLK_000_P_SYNC_1_
| * | S | BR | BS | CLK_000_P_SYNC_9_
| * | S | BR | BS | inst_CLK_OUT_PRE
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
| | | | | A_29_
| | | | | A_30_
| | | | | A_31_
Block C
RW-Fixed
2014-06-07 21:13:48 +00:00
block level set pt :
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
block level reset pt : !RST
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | AVEC_EXP
| * | S | BS | BR | AMIGA_BUS_ENABLE_LOW
| * | S | BS | BR | RN_AVEC_EXP
| * | S | BS | BR | inst_CLK_OUT_PRE_D
| * | S | BS | BR | inst_CLK_OUT_PRE_25
| * | S | BR | BS | inst_UDS_000_INT
| * | S | BR | BS | inst_LDS_000_INT
| * | S | BS | BR | RN_AMIGA_BUS_ENABLE_LOW
| * | S | BS | BR | CLK_000_P_SYNC_6_
| * | S | BS | BR | CLK_000_P_SYNC_5_
| * | S | BS | BR | CLK_000_P_SYNC_2_
| * | S | BS | BR | CLK_000_N_SYNC_8_
| * | S | BS | BR | CLK_000_N_SYNC_3_
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
| | | | | BG_030
| | | | | A_24_
| | | | | A_25_
| | | | | A_26_
| | | | | A_27_
| | | | | A_28_
Block D
block level set pt : !RST
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
block level reset pt :
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
| * | S | BS | BR | AS_000
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| | | | | UDS_000
| | | | | LDS_000
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
| | | | | DTACK
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | AMIGA_BUS_ENABLE
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
| * | S | BS | BR | VMA
better amiga timing
2014-05-24 13:17:08 +00:00
| * | S | BS | BR | BG_000
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | inst_CLK_000_D2
| * | S | BS | BR | SM_AMIGA_7_
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
| * | S | BS | BR | RN_VMA
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | RN_AMIGA_BUS_ENABLE
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
| * | S | BS | BR | RN_BG_000
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
| * | S | BS | BR | RN_AS_000
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BR | BS | SM_AMIGA_0_
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
| | | | | BGACK_000
Block E
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
block level set pt :
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
block level reset pt : !RST
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| | | | | AMIGA_BUS_DATA_DIR
| | | | | CIIN
| | | | | BERR
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | inst_CLK_OUT_PRE_50
| * | S | BS | BR | CLK_000_N_SYNC_7_
| * | S | BS | BR | CLK_000_N_SYNC_2_
| * | S | BR | BS | inst_CLK_000_D3
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Block F
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
block level set pt : !RST
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
block level reset pt :
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | inst_CLK_000_D0
| * | S | BR | BS | cpu_est_0_
| * | S | BR | BS | SM_AMIGA_1_
| * | S | BR | BS | SM_AMIGA_3_
| * | S | BR | BS | SM_AMIGA_2_
| * | S | BR | BS | CLK_000_P_SYNC_8_
| * | S | BR | BS | CLK_000_P_SYNC_0_
| * | S | BR | BS | CLK_000_N_SYNC_9_
| * | S | BR | BS | CLK_000_N_SYNC_6_
| * | S | BR | BS | CLK_000_N_SYNC_0_
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
| | | | | A_17_
| | | | | FC_1_
| | | | | FC_0_
| | | | | IPL_1_
Block G
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
block level set pt : !RST
block level reset pt :
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | RW
| * | S | BS | BR | SIZE_0_
| * | S | BS | BR | A0
| * | S | BR | BS | E
| * | S | BR | BS | CLK_DIV_OUT
| * | S | BR | BS | SM_AMIGA_6_
| * | S | BR | BS | cpu_est_1_
| * | S | BR | BS | RN_E
| * | S | BR | BS | cpu_est_2_
| * | S | BS | BR | inst_VPA_D
| * | S | BS | BR | RN_RW
| * | S | BR | BS | CLK_000_P_SYNC_4_
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
| | | | | IPL_2_
| | | | | IPL_0_
Block H
block level set pt : !RST
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
block level reset pt :
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
| * | S | BS | BR | AS_030
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | RW_000
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
| * | S | BS | BR | DSACK1
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
| * | S | BS | BR | SIZE_1_
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
| * | S | BS | BR | BGACK_030
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| | | | | FPU_CS
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
| * | S | BS | BR | RN_BGACK_030
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | inst_CLK_000_D1
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
| * | S | BS | BR | RN_AS_030
RW-Fixed
2014-06-07 21:13:48 +00:00
| * | S | BS | BR | inst_AS_030_000_SYNC
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | RN_RW_000
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
| * | S | BS | BR | RN_DSACK1
| * | S | BR | BS | inst_CLK_OUT_PRE_50_D
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
| * | S | BS | BR | inst_BGACK_030_INT_D
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
| | | | | A_22_
| | | | | A_23_
<Note> (S) means the macrocell is configured in synchronous mode
i.e. it uses the block-level set and reset pt.
(A) means the macrocell is configured in asynchronous mode
i.e. it can have its independant set or reset pt.
(BS) means the block-level set pt is selected.
(BR) means the block-level reset pt is selected.

DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
BLOCK_A_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx A0 RST pin 86 mx A17 ... ...
mx A1CLK_000_N_SYNC_0_ mcell F6 mx A18 ... ...
mx A2CLK_000_N_SYNC_10_ mcell A9 mx A19 ... ...
mx A3 ... ... mx A20 ... ...
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
mx A4 CLK_030 pin 64 mx A21 RN_AS_030 mcell H6
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx A5 nEXP_SPACE pin 14 mx A22CLK_000_N_SYNC_4_ mcell A2
mx A6CLK_000_N_SYNC_9_ mcell F13 mx A23 AS_000 pin 33
mx A7CLK_000_N_SYNC_3_ mcell C14 mx A24 LDS_000 pin 31
mx A8CLK_000_N_SYNC_11_ mcell A10 mx A25 ... ...
mx A9CLK_000_P_SYNC_2_ mcell C6 mx A26 ... ...
mx A10 ... ... mx A27 ... ...
mx A11CLK_000_P_SYNC_6_ mcell C13 mx A28 RW_000 pin 80
mx A12 UDS_000 pin 32 mx A29 RN_DS_030 mcell A0
mx A13 RN_BGACK_030 mcell H5 mx A30 ... ...
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
mx A14 ... ... mx A31 ... ...
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx A15 inst_CLK_030_H mcell A12 mx A32 ... ...
timing enhanced?
2014-05-25 19:20:36 +00:00
mx A16 ... ...
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
----------------------------------------------------------------------------
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
BLOCK_B_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx B0 IPL_0_ pin 67 mx B17 ... ...
mx B1CLK_000_P_SYNC_0_ mcell F9 mx B18 inst_CLK_000_NE mcell A8
mx B2 ... ... mx B19 AS_030 pin 82
mx B3 IPL_1_ pin 56 mx B20 ... ...
RW-Fixed
2014-06-07 21:13:48 +00:00
mx B4 IPL_2_ pin 68 mx B21 RST pin 86
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx B5 inst_CLK_000_D0 mcell F0 mx B22inst_CLK_OUT_PRE_25 mcell C1
mx B6 SM_AMIGA_4_ mcell B9 mx B23 ... ...
mx B7inst_CLK_OUT_PRE_D mcell C8 mx B24 ... ...
mx B8 RN_IPL_030_0_ mcell B8 mx B25 RW pin 71
mx B9CLK_000_P_SYNC_8_ mcell F5 mx B26 ... ...
mx B10 SM_AMIGA_5_ mcell B13 mx B27 RN_IPL_030_2_ mcell B4
mx B11 inst_CLK_000_D1 mcell H9 mx B28inst_DS_000_ENABLE mcell B5
mx B12 RN_IPL_030_1_ mcell B12 mx B29 ... ...
mx B13 ... ... mx B30 ... ...
mx B14 RN_AVEC_EXP mcell C4 mx B31 ... ...
mx B15 ... ... mx B32 SM_AMIGA_6_ mcell G5
mx B16 ... ...
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
----------------------------------------------------------------------------
BLOCK_C_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx C0 RST pin 86 mx C17 ... ...
mx C1inst_CLK_OUT_PRE_25 mcell C1 mx C18 A0 pin 69
mx C2inst_CLK_OUT_PRE mcell B10 mx C19 ... ...
mx C3CLK_000_N_SYNC_2_ mcell E5 mx C20 ... ...
RW-Fixed
2014-06-07 21:13:48 +00:00
mx C4 ... ... mx C21 ... ...
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx C5CLK_000_N_SYNC_7_ mcell E1 mx C22CLK_000_P_SYNC_5_ mcell C2
mx C6 SIZE_1_ pin 79 mx C23CLK_000_P_SYNC_4_ mcell G6
mx C7inst_CLK_OUT_PRE_50_D mcell H13 mx C24 ... ...
mx C8inst_CLK_OUT_PRE_50 mcell E8 mx C25 ... ...
RW-Fixed
2014-06-07 21:13:48 +00:00
mx C9 ... ... mx C26 ... ...
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx C10CLK_000_P_SYNC_1_ mcell B2 mx C27 ... ...
mx C11CLK_000_P_SYNC_9_ mcell B6 mx C28 ... ...
mx C12 DS_030 pin 98 mx C29 ... ...
mx C13inst_LDS_000_INT mcell C9 mx C30 ... ...
mx C14 SIZE_0_ pin 70 mx C31 ... ...
mx C15inst_UDS_000_INT mcell C5 mx C32 ... ...
mx C16inst_CLK_OUT_PRE_D mcell C8
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
----------------------------------------------------------------------------
BLOCK_D_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx D0inst_AS_030_000_SYNC mcell H4 mx D17 DSACK1 pin 81
mx D1 RN_BG_000 mcell D13 mx D18inst_BGACK_030_INT_D mcell H10
mx D2 RN_VMA mcell D1 mx D19 AS_030 pin 82
mx D3 SM_AMIGA_7_ mcell D2 mx D20 SM_AMIGA_1_ mcell F8
mx D4 RN_BGACK_030 mcell H5 mx D21 RST pin 86
mx D5 inst_CLK_000_D1 mcell H9 mx D22 BG_030 pin 21
mx D6 RN_AVEC_EXP mcell C4 mx D23 inst_VPA_D mcell G2
mx D7 RN_AS_030 mcell H6 mx D24RN_AMIGA_BUS_ENABLE mcell D5
mx D8 ... ... mx D25 inst_CLK_000_D0 mcell F0
mx D9 cpu_est_2_ mcell G13 mx D26 ... ...
mx D10 RN_AS_000 mcell D4 mx D27 cpu_est_1_ mcell G9
mx D11 RN_E mcell G4 mx D28inst_UDS_000_INT mcell C5
mx D12 inst_CLK_000_D2 mcell D9 mx D29 cpu_est_0_ mcell F4
mx D13inst_LDS_000_INT mcell C9 mx D30 inst_CLK_000_NE mcell A8
mx D14 CLK_000 pin 11 mx D31inst_DS_000_ENABLE mcell B5
mx D15 nEXP_SPACE pin 14 mx D32 SM_AMIGA_6_ mcell G5
mx D16 SM_AMIGA_0_ mcell D6
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
----------------------------------------------------------------------------
BLOCK_E_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx E0 RST pin 86 mx E17 FC_0_ pin 57
mx E1 A_31_ pin 4 mx E18 A_22_ pin 85
mx E2 ... ... mx E19 AS_030 pin 82
mx E3 A_27_ pin 16 mx E20 FC_1_ pin 58
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
mx E4 A_29_ pin 6 mx E21 nEXP_SPACE pin 14
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx E5 A_21_ pin 94 mx E22 ... ...
mx E6 A_19_ pin 97 mx E23 AS_000 pin 33
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
mx E7 A_28_ pin 15 mx E24 ... ...
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx E8 RW pin 71 mx E25 inst_CLK_000_D2 mcell D9
mx E9 A_26_ pin 17 mx E26 A_16_ pin 96
mx E10CLK_000_N_SYNC_1_ mcell A6 mx E27 RN_BGACK_030 mcell H5
mx E11 A_23_ pin 84 mx E28 A_30_ pin 5
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
mx E12 A_25_ pin 18 mx E29 A_20_ pin 93
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx E13 A_17_ pin 59 mx E30 ... ...
mx E14 A_24_ pin 19 mx E31 A_18_ pin 95
mx E15CLK_000_N_SYNC_6_ mcell F2 mx E32 BGACK_000 pin 28
mx E16inst_CLK_OUT_PRE_50 mcell E8
----------------------------------------------------------------------------
BLOCK_F_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx F0 RST pin 86 mx F17 RN_VMA mcell D1
mx F1 SM_AMIGA_3_ mcell F12 mx F18 inst_CLK_000_NE mcell A8
mx F2 inst_CLK_000_D3 mcell E9 mx F19 ... ...
mx F3 CLK_000 pin 11 mx F20 SM_AMIGA_1_ mcell F8
mx F4 inst_VPA_D mcell G2 mx F21 ... ...
mx F5 inst_CLK_000_D0 mcell F0 mx F22 ... ...
mx F6 SM_AMIGA_4_ mcell B9 mx F23 DTACK pin 30
mx F7 inst_CLK_000_D2 mcell D9 mx F24 ... ...
mx F8CLK_000_N_SYNC_8_ mcell C10 mx F25CLK_000_N_SYNC_5_ mcell A13
mx F9CLK_000_P_SYNC_7_ mcell A1 mx F26 ... ...
mx F10 SM_AMIGA_2_ mcell F1 mx F27 inst_CLK_000_D1 mcell H9
mx F11 RN_E mcell G4 mx F28 ... ...
mx F12 cpu_est_1_ mcell G9 mx F29 RN_AVEC_EXP mcell C4
mx F13 ... ... mx F30 ... ...
mx F14 cpu_est_0_ mcell F4 mx F31 ... ...
mx F15 ... ... mx F32 ... ...
mx F16 ... ...
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
----------------------------------------------------------------------------
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
BLOCK_G_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx G0 RST pin 86 mx G17 RN_RW mcell G0
mx G1 ... ... mx G18 ... ...
mx G2CLK_000_P_SYNC_3_ mcell A5 mx G19 ... ...
mx G3 SM_AMIGA_7_ mcell D2 mx G20inst_AS_030_000_SYNC mcell H4
mx G4 CLK_030 pin 64 mx G21 RN_AS_030 mcell H6
mx G5 nEXP_SPACE pin 14 mx G22 SM_AMIGA_6_ mcell G5
mx G6 RN_AVEC_EXP mcell C4 mx G23 AS_000 pin 33
mx G7inst_CLK_OUT_PRE_D mcell C8 mx G24 LDS_000 pin 31
mx G8 UDS_000 pin 32 mx G25 inst_CLK_000_D2 mcell D9
mx G9 cpu_est_2_ mcell G13 mx G26 ... ...
mx G10 VPA pin 36 mx G27 inst_CLK_000_D1 mcell H9
mx G11 RN_E mcell G4 mx G28 RW_000 pin 80
mx G12 cpu_est_1_ mcell G9 mx G29 ... ...
mx G13 RN_BGACK_030 mcell H5 mx G30 ... ...
mx G14 cpu_est_0_ mcell F4 mx G31 ... ...
mx G15 ... ... mx G32 ... ...
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
mx G16 ... ...
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
----------------------------------------------------------------------------
BLOCK_H_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx H0inst_AS_030_000_SYNC mcell H4 mx H17 FC_0_ pin 57
mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28
mx H2 SM_AMIGA_1_ mcell F8 mx H19 ... ...
mx H3 SM_AMIGA_7_ mcell D2 mx H20 CLK_030 pin 64
mx H4 A_18_ pin 95 mx H21 RST pin 86
mx H5 inst_CLK_000_D1 mcell H9 mx H22 SM_AMIGA_6_ mcell G5
mx H6 A_19_ pin 97 mx H23RN_AMIGA_BUS_ENABLE_LOW mcell C12
mx H7 RN_AS_030 mcell H6 mx H24 LDS_000 pin 31
mx H8 RW pin 71 mx H25 inst_CLK_000_D0 mcell F0
RW-Fixed
2014-06-07 21:13:48 +00:00
mx H9 AS_030 pin 82 mx H26 AS_000 pin 33
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
mx H10 ... ... mx H27 A_17_ pin 59
mx H11 A_16_ pin 96 mx H28 ... ...
mx H12 UDS_000 pin 32 mx H29 RN_DSACK1 mcell H12
mx H13 RN_BGACK_030 mcell H5 mx H30 RN_RW_000 mcell H0
mx H14 RN_AVEC_EXP mcell C4 mx H31 ... ...
mx H15 nEXP_SPACE pin 14 mx H32 ... ...
mx H16inst_CLK_OUT_PRE_50 mcell E8
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
----------------------------------------------------------------------------
<Note> CSM indicates the mux inputs from the Central Switch Matrix.
<Note> Source indicates where the signal comes from (pin or macrocell).

PostFit_Equations
~~~~~~~~~~~~~~~~~
P-Terms Fan-in Fan-out Type Name (attributes)
--------- ------ ------- ---- -----------------
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
1 2 1 Pin UDS_000-
1 1 1 Pin UDS_000.OE
1 2 1 Pin LDS_000-
1 1 1 Pin LDS_000.OE
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
0 0 1 Pin BERR
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
1 8 1 Pin BERR.OE
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Pin CLK_DIV_OUT.AR
Before clean up
2014-05-15 20:51:43 +00:00
1 1 1 Pin CLK_DIV_OUT.D
1 1 1 Pin CLK_DIV_OUT.C
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
1 8 1 Pin FPU_CS-
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
1 1 1 Pin DTACK
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
1 3 1 Pin DTACK.OE
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
1 0 1 Pin AVEC
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
2 4 1 Pin AMIGA_BUS_DATA_DIR
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
1 4 1 Pin CIIN
1 8 1 Pin CIIN.OE
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
1 3 1 Pin SIZE_1_.OE
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
2 4 1 Pin SIZE_1_.D-
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
1 1 1 Pin SIZE_1_.AP
1 1 1 Pin SIZE_1_.C
Cleaned up version This version is the base for all future experiments.
2014-05-15 21:05:08 +00:00
3 4 1 Pin IPL_030_2_.D
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
1 1 1 Pin IPL_030_2_.AP
1 1 1 Pin IPL_030_2_.C
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
1 3 1 Pin AS_030.OE
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
4 6 1 Pin AS_030.D
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
1 1 1 Pin AS_030.AP
1 1 1 Pin AS_030.C
timing enhanced?
2014-05-25 19:20:36 +00:00
1 1 1 Pin AS_000.OE
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
2 4 1 Pin AS_000.D-
timing enhanced?
2014-05-25 19:20:36 +00:00
1 1 1 Pin AS_000.AP
1 1 1 Pin AS_000.C
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
1 3 1 Pin SIZE_0_.OE
1 4 1 Pin SIZE_0_.D-
1 1 1 Pin SIZE_0_.AP
1 1 1 Pin SIZE_0_.C
1 1 1 Pin RW_000.OE
3 5 1 Pin RW_000.D-
1 1 1 Pin RW_000.AP
1 1 1 Pin RW_000.C
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
1 3 1 Pin DS_030.OE
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
7 9 1 Pin DS_030.D
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
1 1 1 Pin DS_030.AP
1 1 1 Pin DS_030.C
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
1 3 1 Pin A0.OE
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
1 4 1 Pin A0.D
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
1 1 1 Pin A0.AP
1 1 1 Pin A0.C
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
2 6 1 Pin BG_000.D-
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
1 1 1 Pin BG_000.AP
1 1 1 Pin BG_000.C
2 4 1 Pin BGACK_030.D
1 1 1 Pin BGACK_030.AP
1 1 1 Pin BGACK_030.C
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
1 1 1 Pin CLK_EXP.AR
1 1 1 Pin CLK_EXP.D
1 1 1 Pin CLK_EXP.C
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
3 4 1 Pin IPL_030_1_.D
1 1 1 Pin IPL_030_1_.AP
1 1 1 Pin IPL_030_1_.C
3 4 1 Pin IPL_030_0_.D
1 1 1 Pin IPL_030_0_.AP
1 1 1 Pin IPL_030_0_.C
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
1 1 1 Pin DSACK1.OE
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
2 5 1 Pin DSACK1.D-
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
1 1 1 Pin DSACK1.AP
1 1 1 Pin DSACK1.C
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
1 1 1 Pin AVEC_EXP.AR
1 1 1 Pin AVEC_EXP.D
1 1 1 Pin AVEC_EXP.C
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Pin E.AR
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
4 5 1 Pin E.D-
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
1 1 1 Pin E.C
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
2 7 1 PinX1 VMA.D.X1
1 5 1 PinX2 VMA.D.X2
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
1 1 1 Pin VMA.AP
1 1 1 Pin VMA.C
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Pin RESET.AR
1 0 1 Pin RESET.D
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
1 1 1 Pin RESET.C
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
1 1 1 Pin RW.OE
4 7 1 Pin RW.D-
1 1 1 Pin RW.AP
1 1 1 Pin RW.C
6 12 1 Pin AMIGA_BUS_ENABLE.D-
1 1 1 Pin AMIGA_BUS_ENABLE.AP
1 1 1 Pin AMIGA_BUS_ENABLE.C
1 1 1 Pin AMIGA_BUS_ENABLE_LOW.AR
1 2 1 Pin AMIGA_BUS_ENABLE_LOW.D
1 1 1 Pin AMIGA_BUS_ENABLE_LOW.C
5 12 1 Node inst_AS_030_000_SYNC.D
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
1 1 1 Node inst_AS_030_000_SYNC.AP
1 1 1 Node inst_AS_030_000_SYNC.C
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
1 1 1 Node inst_BGACK_030_INT_D.D
1 1 1 Node inst_BGACK_030_INT_D.AP
1 1 1 Node inst_BGACK_030_INT_D.C
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
1 1 1 Node inst_VPA_D.D
1 1 1 Node inst_VPA_D.AP
1 1 1 Node inst_VPA_D.C
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
1 1 1 Node inst_CLK_OUT_PRE_50_D.AR
1 1 1 Node inst_CLK_OUT_PRE_50_D.D
1 1 1 Node inst_CLK_OUT_PRE_50_D.C
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
1 1 1 Node inst_CLK_OUT_PRE.AR
1 1 1 Node inst_CLK_OUT_PRE.D
1 1 1 Node inst_CLK_OUT_PRE.C
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
1 1 1 Node inst_CLK_000_D0.D
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Node inst_CLK_000_D0.AP
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
1 1 1 Node inst_CLK_000_D0.C
1 1 1 Node inst_CLK_000_D1.D
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Node inst_CLK_000_D1.AP
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
1 1 1 Node inst_CLK_000_D1.C
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
1 1 1 Node inst_CLK_OUT_PRE_50.AR
1 1 1 Node inst_CLK_OUT_PRE_50.D
1 1 1 Node inst_CLK_OUT_PRE_50.C
1 1 1 Node inst_CLK_OUT_PRE_25.AR
3 3 1 Node inst_CLK_OUT_PRE_25.D
1 1 1 Node inst_CLK_OUT_PRE_25.C
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
1 1 1 Node inst_CLK_000_D2.D
1 1 1 Node inst_CLK_000_D2.AP
1 1 1 Node inst_CLK_000_D2.C
1 1 1 Node inst_CLK_000_D3.D
1 1 1 Node inst_CLK_000_D3.AP
1 1 1 Node inst_CLK_000_D3.C
1 1 1 Node inst_CLK_000_NE.AR
1 1 1 Node inst_CLK_000_NE.D
1 1 1 Node inst_CLK_000_NE.C
1 1 1 Node inst_CLK_OUT_PRE_D.AR
1 1 1 Node inst_CLK_OUT_PRE_D.D
1 1 1 Node inst_CLK_OUT_PRE_D.C
1 1 1 Node CLK_000_P_SYNC_9_.AR
1 1 1 Node CLK_000_P_SYNC_9_.D
1 1 1 Node CLK_000_P_SYNC_9_.C
1 1 1 Node CLK_000_N_SYNC_11_.AR
1 1 1 Node CLK_000_N_SYNC_11_.D
1 1 1 Node CLK_000_N_SYNC_11_.C
4 7 1 Node SM_AMIGA_7_.D-
1 1 1 Node SM_AMIGA_7_.AP
1 1 1 Node SM_AMIGA_7_.C
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Node SM_AMIGA_6_.AR
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
2 7 1 Node SM_AMIGA_6_.D
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Node SM_AMIGA_6_.C
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
1 1 1 Node SM_AMIGA_1_.AR
2 4 1 Node SM_AMIGA_1_.D
1 1 1 Node SM_AMIGA_1_.C
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
1 1 1 Node SM_AMIGA_0_.AR
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
2 4 1 Node SM_AMIGA_0_.D
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
1 1 1 Node SM_AMIGA_0_.C
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
1 1 1 Node SM_AMIGA_4_.AR
2 4 1 Node SM_AMIGA_4_.D
1 1 1 Node SM_AMIGA_4_.C
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
5 8 1 Node inst_CLK_030_H.D
1 1 1 Node inst_CLK_030_H.C
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
2 5 1 Node inst_LDS_000_INT.D
1 1 1 Node inst_LDS_000_INT.AP
1 1 1 Node inst_LDS_000_INT.C
1 1 1 Node inst_DS_000_ENABLE.AR
3 6 1 Node inst_DS_000_ENABLE.D
1 1 1 Node inst_DS_000_ENABLE.C
2 3 1 Node inst_UDS_000_INT.D
1 1 1 Node inst_UDS_000_INT.AP
1 1 1 Node inst_UDS_000_INT.C
1 1 1 Node CLK_000_N_SYNC_0_.AR
1 4 1 Node CLK_000_N_SYNC_0_.D
1 1 1 Node CLK_000_N_SYNC_0_.C
1 1 1 Node CLK_000_N_SYNC_1_.AR
1 1 1 Node CLK_000_N_SYNC_1_.D
1 1 1 Node CLK_000_N_SYNC_1_.C
1 1 1 Node CLK_000_N_SYNC_2_.AR
1 1 1 Node CLK_000_N_SYNC_2_.D
1 1 1 Node CLK_000_N_SYNC_2_.C
1 1 1 Node CLK_000_N_SYNC_3_.AR
1 1 1 Node CLK_000_N_SYNC_3_.D
1 1 1 Node CLK_000_N_SYNC_3_.C
1 1 1 Node CLK_000_N_SYNC_4_.AR
1 1 1 Node CLK_000_N_SYNC_4_.D
1 1 1 Node CLK_000_N_SYNC_4_.C
1 1 1 Node CLK_000_N_SYNC_5_.AR
1 1 1 Node CLK_000_N_SYNC_5_.D
1 1 1 Node CLK_000_N_SYNC_5_.C
1 1 1 Node CLK_000_N_SYNC_6_.AR
1 1 1 Node CLK_000_N_SYNC_6_.D
1 1 1 Node CLK_000_N_SYNC_6_.C
1 1 1 Node CLK_000_N_SYNC_7_.AR
1 1 1 Node CLK_000_N_SYNC_7_.D
1 1 1 Node CLK_000_N_SYNC_7_.C
1 1 1 Node CLK_000_N_SYNC_8_.AR
1 1 1 Node CLK_000_N_SYNC_8_.D
1 1 1 Node CLK_000_N_SYNC_8_.C
1 1 1 Node CLK_000_N_SYNC_9_.AR
1 1 1 Node CLK_000_N_SYNC_9_.D
1 1 1 Node CLK_000_N_SYNC_9_.C
1 1 1 Node CLK_000_N_SYNC_10_.AR
1 1 1 Node CLK_000_N_SYNC_10_.D
1 1 1 Node CLK_000_N_SYNC_10_.C
1 1 1 Node CLK_000_P_SYNC_0_.AR
1 4 1 Node CLK_000_P_SYNC_0_.D
1 1 1 Node CLK_000_P_SYNC_0_.C
1 1 1 Node CLK_000_P_SYNC_1_.AR
1 1 1 Node CLK_000_P_SYNC_1_.D
1 1 1 Node CLK_000_P_SYNC_1_.C
1 1 1 Node CLK_000_P_SYNC_2_.AR
1 1 1 Node CLK_000_P_SYNC_2_.D
1 1 1 Node CLK_000_P_SYNC_2_.C
1 1 1 Node CLK_000_P_SYNC_3_.AR
1 1 1 Node CLK_000_P_SYNC_3_.D
1 1 1 Node CLK_000_P_SYNC_3_.C
1 1 1 Node CLK_000_P_SYNC_4_.AR
1 1 1 Node CLK_000_P_SYNC_4_.D
1 1 1 Node CLK_000_P_SYNC_4_.C
1 1 1 Node CLK_000_P_SYNC_5_.AR
1 1 1 Node CLK_000_P_SYNC_5_.D
1 1 1 Node CLK_000_P_SYNC_5_.C
1 1 1 Node CLK_000_P_SYNC_6_.AR
1 1 1 Node CLK_000_P_SYNC_6_.D
1 1 1 Node CLK_000_P_SYNC_6_.C
1 1 1 Node CLK_000_P_SYNC_7_.AR
1 1 1 Node CLK_000_P_SYNC_7_.D
1 1 1 Node CLK_000_P_SYNC_7_.C
1 1 1 Node CLK_000_P_SYNC_8_.AR
1 1 1 Node CLK_000_P_SYNC_8_.D
1 1 1 Node CLK_000_P_SYNC_8_.C
RW-Fixed
2014-06-07 21:13:48 +00:00
1 1 1 Node SM_AMIGA_5_.AR
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
2 4 1 Node SM_AMIGA_5_.D
RW-Fixed
2014-06-07 21:13:48 +00:00
1 1 1 Node SM_AMIGA_5_.C
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
1 1 1 Node SM_AMIGA_3_.AR
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
5 9 1 Node SM_AMIGA_3_.T
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
1 1 1 Node SM_AMIGA_3_.C
RW-Fixed
2014-06-07 21:13:48 +00:00
1 1 1 Node SM_AMIGA_2_.AR
3 9 1 Node SM_AMIGA_2_.D
1 1 1 Node SM_AMIGA_2_.C
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Node cpu_est_0_.AR
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
2 2 1 Node cpu_est_0_.D
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Node cpu_est_0_.C
1 1 1 Node cpu_est_1_.AR
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
5 5 1 Node cpu_est_1_.D
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Node cpu_est_1_.C
1 1 1 Node cpu_est_2_.AR
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
4 5 1 Node cpu_est_2_.D
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
1 1 1 Node cpu_est_2_.C
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
=========
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
308 P-Term Total: 308
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Total Pins: 59
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
Total Nodes: 50
Average P-Term/Output: 1
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Equations:
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
UDS_000.OE = (BGACK_030.Q);
!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
LDS_000.OE = (BGACK_030.Q);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
BERR = (0);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
BERR.OE = (FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
CLK_DIV_OUT.AR = (!RST);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
Before clean up
2014-05-15 20:51:43 +00:00
CLK_DIV_OUT.C = (CLK_OSZI);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
!FPU_CS = (FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
DTACK = (DSACK1.PIN);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
AVEC = (1);
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN
# !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
CIIN = (A_23_ & A_22_ & A_21_ & A_20_);
CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_);
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
!SIZE_1_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN
# !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
SIZE_1_.AP = (!RST);
SIZE_1_.C = (CLK_OSZI);
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q
# inst_CLK_000_D1.Q & IPL_030_2_.Q
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
# IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
IPL_030_2_.AP = (!RST);
IPL_030_2_.C = (CLK_OSZI);
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
AS_030.D = (BGACK_030.Q
# AS_000.PIN
# CLK_030 & AS_030.Q
# UDS_000.PIN & LDS_000.PIN);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
AS_030.AP = (!RST);
AS_030.C = (CLK_OSZI);
timing enhanced?
2014-05-25 19:20:36 +00:00
AS_000.OE = (BGACK_030.Q);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
!AS_000.D = (AVEC_EXP.Q & SM_AMIGA_6_.Q
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
# !AS_000.Q & !AS_030.PIN);
timing enhanced?
2014-05-25 19:20:36 +00:00
AS_000.AP = (!RST);
AS_000.C = (CLK_OSZI);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN);
SIZE_0_.AP = (!RST);
SIZE_0_.C = (CLK_OSZI);
RW_000.OE = (BGACK_030.Q);
!RW_000.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q & !RW_000.Q
# !SM_AMIGA_7_.Q & !SM_AMIGA_6_.Q & !RW_000.Q
# AVEC_EXP.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q & !RW.PIN);
RW_000.AP = (!RST);
RW_000.C = (CLK_OSZI);
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
DS_030.D = (BGACK_030.Q
# AS_000.PIN
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
# AS_030.Q & RW_000.PIN
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
# UDS_000.PIN & LDS_000.PIN
# !CLK_030 & AS_030.Q & inst_CLK_030_H.Q
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
# CLK_030 & DS_030.Q & !RW_000.PIN
# !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
DS_030.AP = (!RST);
DS_030.C = (CLK_OSZI);
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
A0.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
A0.AP = (!RST);
A0.C = (CLK_OSZI);
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
!BG_000.D = (!BG_030 & !BG_000.Q
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
# nEXP_SPACE & !BG_030 & CLK_000 & SM_AMIGA_7_.Q & AS_030.PIN);
Cleaned up version This version is the base for all future experiments.
2014-05-15 21:05:08 +00:00
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
BG_000.AP = (!RST);
Cleaned up version This version is the base for all future experiments.
2014-05-15 21:05:08 +00:00
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
BG_000.C = (CLK_OSZI);
Cleaned up version This version is the base for all future experiments.
2014-05-15 21:05:08 +00:00
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
BGACK_030.D = (BGACK_000 & BGACK_030.Q
# BGACK_000 & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
Cleaned up version This version is the base for all future experiments.
2014-05-15 21:05:08 +00:00
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
BGACK_030.AP = (!RST);
Cleaned up version This version is the base for all future experiments.
2014-05-15 21:05:08 +00:00
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
BGACK_030.C = (CLK_OSZI);
Cleaned up version This version is the base for all future experiments.
2014-05-15 21:05:08 +00:00
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
CLK_EXP.AR = (!RST);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
CLK_EXP.C = (CLK_OSZI);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q
# inst_CLK_000_D1.Q & IPL_030_1_.Q
# IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
timing enhanced?
2014-05-25 19:20:36 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
IPL_030_1_.AP = (!RST);
timing enhanced?
2014-05-25 19:20:36 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
IPL_030_1_.C = (CLK_OSZI);
IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q
# inst_CLK_000_D1.Q & IPL_030_0_.Q
# IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
IPL_030_0_.AP = (!RST);
IPL_030_0_.C = (CLK_OSZI);
timing enhanced?
2014-05-25 19:20:36 +00:00
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
DSACK1.OE = (nEXP_SPACE);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
!DSACK1.D = (!DSACK1.Q & !AS_030.PIN
# !AMIGA_BUS_ENABLE_LOW.Q & inst_CLK_000_D1.Q & SM_AMIGA_1_.Q);
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
DSACK1.AP = (!RST);
DSACK1.C = (CLK_OSZI);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
AVEC_EXP.AR = (!RST);
AVEC_EXP.D = (CLK_000_P_SYNC_9_.Q);
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
AVEC_EXP.C = (CLK_OSZI);
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
E.AR = (!RST);
Working!
2014-05-15 20:19:03 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
!E.D = (!AVEC_EXP.Q & !E.Q
# cpu_est_2_.Q & !E.Q
# AVEC_EXP.Q & cpu_est_1_.Q & cpu_est_2_.Q
# !cpu_est_0_.Q & cpu_est_1_.Q & !E.Q);
Working!
2014-05-15 20:19:03 +00:00
E.C = (CLK_OSZI);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
VMA.D.X1 = (VMA.Q
# !VMA.Q & inst_CLK_000_D0.Q & AS_000.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q);
VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q);
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
VMA.AP = (!RST);
Working!
2014-05-15 20:19:03 +00:00
VMA.C = (CLK_OSZI);
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
RESET.AR = (!RST);
RESET.D = (1);
Working!
2014-05-15 20:19:03 +00:00
RESET.C = (CLK_OSZI);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
RW.OE = (!BGACK_030.Q);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
!RW.D = (CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !UDS_000.PIN
# !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN
# CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !LDS_000.PIN
# !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
RW.AP = (!RST);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
RW.C = (CLK_OSZI);
!AMIGA_BUS_ENABLE.D = (!BGACK_030.Q
# !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN
# !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN
# !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_NE.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q
# !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q
# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
AMIGA_BUS_ENABLE.AP = (!RST);
RW-Fixed
2014-06-07 21:13:48 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
AMIGA_BUS_ENABLE.C = (CLK_OSZI);
RW-Fixed
2014-06-07 21:13:48 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
AMIGA_BUS_ENABLE_LOW.AR = (!RST);
RW-Fixed
2014-06-07 21:13:48 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
AMIGA_BUS_ENABLE_LOW.D = (!inst_CLK_OUT_PRE.Q & inst_CLK_OUT_PRE_D.Q);
AMIGA_BUS_ENABLE_LOW.C = (CLK_OSZI);
inst_AS_030_000_SYNC.D = (AS_030.PIN
better amiga timing
2014-05-24 13:17:08 +00:00
# !nEXP_SPACE & inst_AS_030_000_SYNC.Q
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
# !BGACK_030.Q & inst_AS_030_000_SYNC.Q
better amiga timing
2014-05-24 13:17:08 +00:00
# inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q
# FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
inst_AS_030_000_SYNC.AP = (!RST);
inst_AS_030_000_SYNC.C = (CLK_OSZI);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_BGACK_030_INT_D.D = (BGACK_030.Q);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_BGACK_030_INT_D.AP = (!RST);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_BGACK_030_INT_D.C = (CLK_OSZI);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
DMA-(potentially) working version but only 25Mhz
2014-05-25 19:00:40 +00:00
inst_VPA_D.D = (VPA);
inst_VPA_D.AP = (!RST);
inst_VPA_D.C = (CLK_OSZI);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_CLK_OUT_PRE_50_D.AR = (!RST);
inst_CLK_OUT_PRE_50_D.D = (inst_CLK_OUT_PRE_50.Q);
inst_CLK_OUT_PRE_50_D.C = (CLK_OSZI);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_CLK_OUT_PRE.AR = (!RST);
inst_CLK_OUT_PRE.D = (inst_CLK_OUT_PRE_25.Q);
inst_CLK_OUT_PRE.C = (CLK_OSZI);
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
inst_CLK_000_D0.D = (CLK_000);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
inst_CLK_000_D0.AP = (!RST);
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
inst_CLK_000_D0.C = (CLK_OSZI);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
inst_CLK_000_D1.AP = (!RST);
Fixed external interface flaws
2014-05-16 18:18:55 +00:00
inst_CLK_000_D1.C = (CLK_OSZI);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_CLK_OUT_PRE_50.AR = (!RST);
timing enhanced?
2014-05-25 19:20:36 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
timing enhanced?
2014-05-25 19:20:36 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
timing enhanced?
2014-05-25 19:20:36 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_CLK_OUT_PRE_25.AR = (!RST);
better amiga timing
2014-05-24 13:17:08 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q
# !inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
# !inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q);
better amiga timing
2014-05-24 13:17:08 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
50Mhz Clock working
2014-05-19 05:35:45 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_CLK_000_D2.D = (inst_CLK_000_D1.Q);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_CLK_000_D2.AP = (!RST);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_CLK_000_D2.C = (CLK_OSZI);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_CLK_000_D3.D = (inst_CLK_000_D2.Q);
Working!
2014-05-15 20:19:03 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_CLK_000_D3.AP = (!RST);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_CLK_000_D3.C = (CLK_OSZI);
Working!
2014-05-15 20:19:03 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_CLK_000_NE.AR = (!RST);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_CLK_000_NE.C = (CLK_OSZI);
inst_CLK_OUT_PRE_D.AR = (!RST);
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE.Q);
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
CLK_000_P_SYNC_9_.AR = (!RST);
CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
CLK_000_P_SYNC_9_.C = (CLK_OSZI);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
CLK_000_N_SYNC_11_.AR = (!RST);
CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);
CLK_000_N_SYNC_11_.C = (CLK_OSZI);
!SM_AMIGA_7_.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q
# !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q
# nEXP_SPACE & !AVEC_EXP.Q & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q
# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & !SM_AMIGA_0_.Q);
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
RW-Fixed
2014-06-07 21:13:48 +00:00
SM_AMIGA_7_.AP = (!RST);
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
RW-Fixed
2014-06-07 21:13:48 +00:00
SM_AMIGA_7_.C = (CLK_OSZI);
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
SM_AMIGA_6_.AR = (!RST);
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
SM_AMIGA_6_.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q
# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & SM_AMIGA_7_.Q);
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
SM_AMIGA_6_.C = (CLK_OSZI);
New PCB and start for RW-Signal-Optimization
2014-06-01 20:50:01 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
SM_AMIGA_1_.AR = (!RST);
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
SM_AMIGA_1_.D = (!inst_CLK_000_NE.Q & SM_AMIGA_1_.Q
# AVEC_EXP.Q & SM_AMIGA_2_.Q);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
SM_AMIGA_1_.C = (CLK_OSZI);
SM_AMIGA_0_.AR = (!RST);
SM_AMIGA_0_.D = (!AVEC_EXP.Q & SM_AMIGA_0_.Q
# inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q);
SM_AMIGA_0_.C = (CLK_OSZI);
SM_AMIGA_4_.AR = (!RST);
SM_AMIGA_4_.D = (!AVEC_EXP.Q & SM_AMIGA_4_.Q
# inst_CLK_000_NE.Q & SM_AMIGA_5_.Q);
SM_AMIGA_4_.C = (CLK_OSZI);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q
# !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
# !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
# CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !UDS_000.PIN
# CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !LDS_000.PIN);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
inst_CLK_030_H.C = (CLK_OSZI);
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_LDS_000_INT.D = (inst_LDS_000_INT.Q & DS_030.PIN
# !DS_030.PIN & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);
RW-Fixed
2014-06-07 21:13:48 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_LDS_000_INT.AP = (!RST);
RW-Fixed
2014-06-07 21:13:48 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_LDS_000_INT.C = (CLK_OSZI);
RW-Fixed
2014-06-07 21:13:48 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_DS_000_ENABLE.AR = (!RST);
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_DS_000_ENABLE.D = (AVEC_EXP.Q & SM_AMIGA_4_.Q
# inst_DS_000_ENABLE.Q & !AS_030.PIN
# AVEC_EXP.Q & SM_AMIGA_6_.Q & RW.PIN);
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
inst_DS_000_ENABLE.C = (CLK_OSZI);
inst_UDS_000_INT.D = (inst_UDS_000_INT.Q & DS_030.PIN
# !DS_030.PIN & A0.PIN);
inst_UDS_000_INT.AP = (!RST);
inst_UDS_000_INT.C = (CLK_OSZI);
CLK_000_N_SYNC_0_.AR = (!RST);
CLK_000_N_SYNC_0_.D = (!inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & inst_CLK_000_D3.Q);
CLK_000_N_SYNC_0_.C = (CLK_OSZI);
CLK_000_N_SYNC_1_.AR = (!RST);
CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);
CLK_000_N_SYNC_1_.C = (CLK_OSZI);
CLK_000_N_SYNC_2_.AR = (!RST);
CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q);
CLK_000_N_SYNC_2_.C = (CLK_OSZI);
CLK_000_N_SYNC_3_.AR = (!RST);
CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q);
CLK_000_N_SYNC_3_.C = (CLK_OSZI);
CLK_000_N_SYNC_4_.AR = (!RST);
CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);
CLK_000_N_SYNC_4_.C = (CLK_OSZI);
CLK_000_N_SYNC_5_.AR = (!RST);
CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);
CLK_000_N_SYNC_5_.C = (CLK_OSZI);
CLK_000_N_SYNC_6_.AR = (!RST);
CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q);
CLK_000_N_SYNC_6_.C = (CLK_OSZI);
CLK_000_N_SYNC_7_.AR = (!RST);
CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q);
CLK_000_N_SYNC_7_.C = (CLK_OSZI);
CLK_000_N_SYNC_8_.AR = (!RST);
CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q);
CLK_000_N_SYNC_8_.C = (CLK_OSZI);
CLK_000_N_SYNC_9_.AR = (!RST);
CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q);
CLK_000_N_SYNC_9_.C = (CLK_OSZI);
CLK_000_N_SYNC_10_.AR = (!RST);
CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);
CLK_000_N_SYNC_10_.C = (CLK_OSZI);
CLK_000_P_SYNC_0_.AR = (!RST);
CLK_000_P_SYNC_0_.D = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & !inst_CLK_000_D3.Q);
CLK_000_P_SYNC_0_.C = (CLK_OSZI);
CLK_000_P_SYNC_1_.AR = (!RST);
CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);
CLK_000_P_SYNC_1_.C = (CLK_OSZI);
CLK_000_P_SYNC_2_.AR = (!RST);
CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);
CLK_000_P_SYNC_2_.C = (CLK_OSZI);
CLK_000_P_SYNC_3_.AR = (!RST);
CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);
CLK_000_P_SYNC_3_.C = (CLK_OSZI);
CLK_000_P_SYNC_4_.AR = (!RST);
CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);
CLK_000_P_SYNC_4_.C = (CLK_OSZI);
CLK_000_P_SYNC_5_.AR = (!RST);
CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);
CLK_000_P_SYNC_5_.C = (CLK_OSZI);
CLK_000_P_SYNC_6_.AR = (!RST);
CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);
CLK_000_P_SYNC_6_.C = (CLK_OSZI);
CLK_000_P_SYNC_7_.AR = (!RST);
CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);
CLK_000_P_SYNC_7_.C = (CLK_OSZI);
CLK_000_P_SYNC_8_.AR = (!RST);
CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
CLK_000_P_SYNC_8_.C = (CLK_OSZI);
SM_AMIGA_5_.AR = (!RST);
SM_AMIGA_5_.D = (AVEC_EXP.Q & SM_AMIGA_6_.Q
# !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q);
SM_AMIGA_5_.C = (CLK_OSZI);
DMA working on Amiga-side
2014-05-24 17:59:59 +00:00
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
SM_AMIGA_3_.AR = (!RST);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
SM_AMIGA_3_.T = (AVEC_EXP.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
# !AVEC_EXP.Q & inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !DTACK.PIN
# inst_VPA_D.Q & inst_CLK_000_NE.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & !DTACK.PIN
# !AVEC_EXP.Q & !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q
# !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);
dma-working and prework for turbo side
2014-05-28 19:34:35 +00:00
SM_AMIGA_3_.C = (CLK_OSZI);
RW-Fixed
2014-06-07 21:13:48 +00:00
SM_AMIGA_2_.AR = (!RST);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
SM_AMIGA_2_.D = (!AVEC_EXP.Q & SM_AMIGA_2_.Q
# inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !DTACK.PIN
# !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);
DMA-TK-Side first non working version
2014-05-24 19:59:56 +00:00
RW-Fixed
2014-06-07 21:13:48 +00:00
SM_AMIGA_2_.C = (CLK_OSZI);
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
cpu_est_0_.AR = (!RST);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
cpu_est_0_.D = (!AVEC_EXP.Q & cpu_est_0_.Q
# AVEC_EXP.Q & !cpu_est_0_.Q);
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
cpu_est_0_.C = (CLK_OSZI);
cpu_est_1_.AR = (!RST);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
cpu_est_1_.D = (!AVEC_EXP.Q & cpu_est_1_.Q
# !cpu_est_0_.Q & cpu_est_1_.Q
# AVEC_EXP.Q & cpu_est_0_.Q & !cpu_est_1_.Q
# AVEC_EXP.Q & cpu_est_2_.Q & E.Q
# AVEC_EXP.Q & !cpu_est_2_.Q & !E.Q);
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
cpu_est_1_.C = (CLK_OSZI);
cpu_est_2_.AR = (!RST);
PE/NE-Sync started
2014-06-09 08:29:32 +00:00
cpu_est_2_.D = (!AVEC_EXP.Q & cpu_est_2_.Q
# cpu_est_1_.Q & cpu_est_2_.Q
# AVEC_EXP.Q & !cpu_est_0_.Q & !cpu_est_1_.Q
# AVEC_EXP.Q & cpu_est_0_.Q & E.Q);
33MHz @100MHz basis working
2014-05-24 14:03:26 +00:00
cpu_est_2_.C = (CLK_OSZI);
Initial push First VErsion after I decided to use version controll ;)
2014-05-15 19:16:29 +00:00
Reverse-Polarity Equations:
Reference in New Issue Copy Permalink