2016-01-24 19:26:06 +00:00
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|- ispLEVER Fitter Report File -|
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|- Version 1.8.00.04.29.14 -|
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|- (c)Copyright, Lattice Semiconductor 2002 -|
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|--------------------------------------------|
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Project_Summary
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~~~~~~~~~~~~~~~
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Project Name : 68030_tk
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Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
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2016-01-28 20:34:20 +00:00
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Project Fitted on : Wed Jan 27 21:56:53 2016
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2016-01-24 19:26:06 +00:00
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Device : M4A5-128/64
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Package : 100TQFP
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Speed : -10
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Partnumber : M4A5-128/64-10VC
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Source Format : Pure_VHDL
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// Project '68030_tk' was Fitted Successfully! //
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Compilation_Times
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~~~~~~~~~~~~~~~~~
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Reading/DRC 0 sec
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Partition 0 sec
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Place 0 sec
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Route 0 sec
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Jedec/Report generation 0 sec
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--------
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Fitter 00:00:00
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Design_Summary
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~~~~~~~~~~~~~~
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Total Input Pins : 32
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Total Output Pins : 19
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Total Bidir I/O Pins : 10
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2016-01-25 17:02:53 +00:00
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Total Flip-Flops : 79
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Total Product Terms : 233
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2016-01-24 19:26:06 +00:00
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Total Reserved Pins : 0
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Total Reserved Blocks : 0
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Device_Resource_Summary
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~~~~~~~~~~~~~~~~~~~~~~~
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Total
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Available Used Available Utilization
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Dedicated Pins
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Input-Only Pins 2 2 0 --> 100%
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Clock/Input Pins 4 4 0 --> 100%
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I/O Pins 64 55 9 --> 85%
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2016-01-25 17:02:53 +00:00
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Logic Macrocells 128 98 30 --> 76%
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2016-01-24 19:26:06 +00:00
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Input Registers 64 0 64 --> 0%
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Unusable Macrocells .. 0 ..
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2016-01-25 17:02:53 +00:00
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CSM Outputs/Total Block Inputs 264 222 42 --> 84%
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Logical Product Terms 640 233 407 --> 36%
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Product Term Clusters 128 54 74 --> 42%
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2016-01-24 19:26:06 +00:00
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Blocks_Resource_Summary
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~~~~~~~~~~~~~~~~~~~~~~~
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# of PT
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I/O Inp Macrocells Macrocells logic clusters
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Fanin Pins Reg Used Unusable available PTs available Pwr
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---------------------------------------------------------------------------------
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Maximum 33 8 8 -- -- 16 80 16 -
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---------------------------------------------------------------------------------
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2016-01-25 17:02:53 +00:00
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Block A 26 8 0 13 0 3 37 8 Lo
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Block B 27 8 0 16 0 0 46 6 Lo
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Block C 26 7 0 5 0 11 18 11 Lo
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Block D 27 8 0 16 0 0 33 6 Lo
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Block E 32 4 0 9 0 7 11 14 Lo
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2016-01-25 17:02:53 +00:00
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Block F 28 5 0 13 0 3 47 4 Lo
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Block G 25 7 0 16 0 0 24 11 Lo
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Block H 31 8 0 10 0 6 17 13 Lo
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2016-01-24 19:26:06 +00:00
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---------------------------------------------------------------------------------
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<Note> Four rightmost columns above reflect last status of the placement process.
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<Note> Pwr (Power) : Hi = High
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Lo = Low.
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Optimizer_and_Fitter_Options
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Pin Assignment : Yes
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Group Assignment : No
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Pin Reservation : No (1)
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Block Reservation : No
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@Ignore_Project_Constraints :
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Pin Assignments : No
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Keep Block Assignment --
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Keep Segment Assignment --
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Group Assignments : No
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Macrocell Assignment : No
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Keep Block Assignment --
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Keep Segment Assignment --
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@Backannotate_Project_Constraints
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Pin Assignments : No
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Pin And Block Assignments : No
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Pin, Macrocell and Block : No
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@Timing_Constraints : No
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@Global_Project_Optimization :
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Balanced Partitioning : Yes
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Spread Placement : Yes
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Note :
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Pack Design :
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Balanced Partitioning = No
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Spread Placement = No
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Spread Design :
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Balanced Partitioning = Yes
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Spread Placement = Yes
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@Logic_Synthesis :
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Logic Reduction : Yes
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Node Collapsing : Yes
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D/T Synthesis : Yes
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Clock Optimization : No
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Input Register Optimization : Yes
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XOR Synthesis : Yes
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Max. P-Term for Collapsing : 16
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Max. P-Term for Splitting : 16
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Max. Equation Fanin : 32
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Keep Xor : Yes
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@Utilization_options
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Max. % of macrocells used : 100
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Max. % of block inputs used : 100
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Max. % of segment lines used : ---
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Max. % of macrocells used : ---
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@Import_Source_Constraint_Option No
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@Zero_Hold_Time Yes
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@Pull_up Yes
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@User_Signature #H0
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@Output_Slew_Rate Default = Slow(2)
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@Power Default = High(2)
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Device Options:
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<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
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follow the drive level set for the Global Configure Unused I/O Option.
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<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
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Bidir and Burried Signal Lists.
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Pinout_Listing
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~~~~~~~~~~~~~~
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| Pin |Blk |Assigned|
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Pin No| Type |Pad |Pin | Signal name
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---------------------------------------------------------------
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1 | GND | | |
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2 | JTAG | | |
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3 | I_O | B7 | * |RESET
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4 | I_O | B6 | * |A_31_
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5 | I_O | B5 | * |A_30_
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6 | I_O | B4 | * |A_29_
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7 | I_O | B3 | * |IPL_030_1_
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8 | I_O | B2 | * |IPL_030_0_
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9 | I_O | B1 | * |IPL_030_2_
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10 | I_O | B0 | * |CLK_EXP
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11 | CkIn | | * |CLK_000
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12 | Vcc | | |
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13 | GND | | |
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14 | CkIn | | * |nEXP_SPACE
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15 | I_O | C0 | * |A_28_
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16 | I_O | C1 | * |A_27_
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17 | I_O | C2 | * |A_26_
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18 | I_O | C3 | * |A_25_
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19 | I_O | C4 | * |A_24_
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20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW
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21 | I_O | C6 | * |BG_030
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22 | I_O | C7 | |
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23 | JTAG | | |
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24 | JTAG | | |
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25 | GND | | |
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26 | GND | | |
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27 | GND | | |
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28 | I_O | D7 | * |BGACK_000
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29 | I_O | D6 | * |BG_000
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30 | I_O | D5 | * |DTACK
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31 | I_O | D4 | * |LDS_000
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32 | I_O | D3 | * |UDS_000
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33 | I_O | D2 | * |AMIGA_ADDR_ENABLE
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34 | I_O | D1 | * |AMIGA_BUS_ENABLE_HIGH
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35 | I_O | D0 | * |VMA
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36 | Inp | | * |VPA
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37 | Vcc | | |
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38 | GND | | |
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39 | GND | | |
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40 | Vcc | | |
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41 | I_O | E0 | * |BERR
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42 | I_O | E1 | * |AS_000
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43 | I_O | E2 | |
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44 | I_O | E3 | |
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45 | I_O | E4 | |
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46 | I_O | E5 | |
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47 | I_O | E6 | * |CIIN
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48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR
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49 | GND | | |
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50 | GND | | |
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51 | GND | | |
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52 | JTAG | | |
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53 | I_O | F7 | |
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54 | I_O | F6 | |
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55 | I_O | F5 | |
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56 | I_O | F4 | * |IPL_1_
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57 | I_O | F3 | * |FC_0_
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58 | I_O | F2 | * |FC_1_
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59 | I_O | F1 | * |A_17_
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60 | I_O | F0 | * |A1
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61 | CkIn | | * |CLK_OSZI
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62 | Vcc | | |
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63 | GND | | |
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64 | CkIn | | * |CLK_030
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65 | I_O | G0 | * |CLK_DIV_OUT
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66 | I_O | G1 | * |E
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67 | I_O | G2 | * |IPL_0_
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68 | I_O | G3 | * |IPL_2_
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69 | I_O | G4 | * |A0
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70 | I_O | G5 | * |SIZE_0_
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71 | I_O | G6 | * |RW
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72 | I_O | G7 | |
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73 | JTAG | | |
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74 | JTAG | | |
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75 | GND | | |
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76 | GND | | |
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77 | GND | | |
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78 | I_O | H7 | * |FPU_CS
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79 | I_O | H6 | * |SIZE_1_
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80 | I_O | H5 | * |RW_000
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81 | I_O | H4 | * |DSACK1
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82 | I_O | H3 | * |AS_030
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83 | I_O | H2 | * |BGACK_030
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84 | I_O | H1 | * |A_22_
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85 | I_O | H0 | * |A_23_
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86 | Inp | | * |RST
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87 | Vcc | | |
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88 | GND | | |
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89 | GND | | |
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90 | Vcc | | |
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91 | I_O | A0 | * |FPU_SENSE
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92 | I_O | A1 | * |AVEC
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93 | I_O | A2 | * |A_20_
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94 | I_O | A3 | * |A_21_
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95 | I_O | A4 | * |A_18_
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96 | I_O | A5 | * |A_16_
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97 | I_O | A6 | * |A_19_
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98 | I_O | A7 | * |DS_030
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99 | GND | | |
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100 | GND | | |
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---------------------------------------------------------------------------
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<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
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<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
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<Note> Pin Type :
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CkIn : Dedicated input or clock pin
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CLK : Dedicated clock pin
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INP : Dedicated input pin
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JTAG : JTAG Control and test pin
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NC : No connected
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Input_Signal_List
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~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Input
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Pin Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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60 F . I/O -B------ Low Slow A1
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96 A . I/O --C-E--H Low Slow A_16_
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59 F . I/O --C-E--H Low Slow A_17_
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95 A . I/O --C-E--H Low Slow A_18_
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97 A . I/O --C-E--H Low Slow A_19_
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93 A . I/O ----E--- Low Slow A_20_
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94 A . I/O ----E--- Low Slow A_21_
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84 H . I/O ----E--- Low Slow A_22_
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85 H . I/O ----E--- Low Slow A_23_
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19 C . I/O ----E--- Low Slow A_24_
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18 C . I/O ----E--- Low Slow A_25_
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17 C . I/O ----E--- Low Slow A_26_
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16 C . I/O ----E--- Low Slow A_27_
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15 C . I/O ----E--- Low Slow A_28_
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6 B . I/O ----E--- Low Slow A_29_
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5 B . I/O ----E--- Low Slow A_30_
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4 B . I/O ----E--- Low Slow A_31_
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28 D . I/O ----E--H Low Slow BGACK_000
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21 C . I/O ---D---- Low Slow BG_030
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2016-01-25 17:02:53 +00:00
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30 D . I/O -B------ Low Slow DTACK
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57 F . I/O --C-E--H Low Slow FC_0_
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58 F . I/O --C-E--H Low Slow FC_1_
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91 A . I/O ----E--H Low Slow FPU_SENSE
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67 G . I/O -B----G- Low Slow IPL_0_
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56 F . I/O -B-D---- Low Slow IPL_1_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
68 G . I/O -B------ Low Slow IPL_2_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
11 . . Ck/I -B------ - Slow CLK_000
|
|
|
|
|
14 . . Ck/I A------- - Slow nEXP_SPACE
|
|
|
|
|
36 . . Ded -----F-- - Slow VPA
|
2016-01-24 19:26:06 +00:00
|
|
|
|
61 . . Ck/I ABCDEFGH - Slow CLK_OSZI
|
|
|
|
|
64 . . Ck/I A------H - Slow CLK_030
|
2016-01-25 17:02:53 +00:00
|
|
|
|
86 . . Ded ABCD-FGH - Slow RST
|
2016-01-24 19:26:06 +00:00
|
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
<Note> Power : Hi = High
|
|
|
|
|
MH = Medium High
|
|
|
|
|
ML = Medium Low
|
|
|
|
|
Lo = Low
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Output_Signal_List
|
|
|
|
|
~~~~~~~~~~~~~~~~~~
|
|
|
|
|
P R
|
|
|
|
|
Pin r e O Output
|
|
|
|
|
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
33 D 1 COM -------- Low Fast AMIGA_ADDR_ENABLE
|
|
|
|
|
48 E 2 COM -------- Low Fast AMIGA_BUS_DATA_DIR
|
|
|
|
|
34 D 2 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH
|
|
|
|
|
20 C 1 COM -------- Low Fast AMIGA_BUS_ENABLE_LOW
|
|
|
|
|
92 A 1 COM -------- Low Slow AVEC
|
|
|
|
|
83 H 3 DFF * * -------- Low Slow BGACK_030
|
|
|
|
|
29 D 2 DFF * * -------- Low Slow BG_000
|
|
|
|
|
47 E 1 COM -------- Low Slow CIIN
|
|
|
|
|
65 G 1 DFF * * -------- Low Fast CLK_DIV_OUT
|
2016-01-25 17:02:53 +00:00
|
|
|
|
10 B 1 DFF * * -------- Low Fast CLK_EXP
|
2016-01-24 19:26:06 +00:00
|
|
|
|
81 H 4 DFF * * -------- Low Slow DSACK1
|
|
|
|
|
98 A 1 COM -------- Low Slow DS_030
|
|
|
|
|
66 G 2 COM -------- Low Slow E
|
|
|
|
|
78 H 1 COM -------- Low Fast FPU_CS
|
|
|
|
|
8 B 10 DFF * * -------- Low Slow IPL_030_0_
|
|
|
|
|
7 B 10 DFF * * -------- Low Slow IPL_030_1_
|
|
|
|
|
9 B 10 DFF * * -------- Low Slow IPL_030_2_
|
|
|
|
|
3 B 1 COM -------- Low Slow RESET
|
|
|
|
|
35 D 3 TFF * * -------- Low Slow VMA
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
<Note> Power : Hi = High
|
|
|
|
|
MH = Medium High
|
|
|
|
|
ML = Medium Low
|
|
|
|
|
Lo = Low
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Bidir_Signal_List
|
|
|
|
|
~~~~~~~~~~~~~~~~~
|
|
|
|
|
P R
|
|
|
|
|
Pin r e O Bidir
|
|
|
|
|
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
69 G 3 DFF * * A------- Low Slow A0
|
2016-01-25 17:02:53 +00:00
|
|
|
|
42 E 1 COM ABC-E--H Low Slow AS_000
|
2016-01-24 19:26:06 +00:00
|
|
|
|
82 H 1 COM ----E--H Low Slow AS_030
|
2016-01-25 17:02:53 +00:00
|
|
|
|
41 E 1 COM --C--F-H Low Slow BERR
|
2016-01-24 19:26:06 +00:00
|
|
|
|
31 D 1 COM A-----G- Low Slow LDS_000
|
|
|
|
|
71 G 2 DFF * * --C----H Low Slow RW
|
|
|
|
|
80 H 3 DFF * * A---E-G- Low Slow RW_000
|
|
|
|
|
70 G 1 COM A------- Low Slow SIZE_0_
|
|
|
|
|
79 H 1 COM A------- Low Slow SIZE_1_
|
|
|
|
|
32 D 1 COM A-----G- Low Slow UDS_000
|
|
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
<Note> Power : Hi = High
|
|
|
|
|
MH = Medium High
|
|
|
|
|
ML = Medium Low
|
|
|
|
|
Lo = Low
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Buried_Signal_List
|
|
|
|
|
~~~~~~~~~~~~~~~~~~
|
|
|
|
|
P R
|
|
|
|
|
Pin r e O Node
|
|
|
|
|
#Mc Blk PTs Type e s E Fanout Pwr Slew Signal
|
|
|
|
|
----------------------------------------------------------------------
|
2016-01-25 17:02:53 +00:00
|
|
|
|
E5 E 2 COM ----E--- Low Slow CIIN_0
|
|
|
|
|
E9 E 1 DFF * * A------- Low Slow CLK_000_N_SYNC_0_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
H2 H 1 DFF * * -------H Low Slow CLK_000_N_SYNC_10_
|
|
|
|
|
H6 H 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_11_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
A14 A 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_1_
|
|
|
|
|
B14 B 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_2_
|
|
|
|
|
B10 B 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_3_
|
|
|
|
|
B6 B 1 DFF * * ---D---- Low Slow CLK_000_N_SYNC_4_
|
|
|
|
|
D11 D 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_5_
|
|
|
|
|
G6 G 1 DFF * * -----F-- Low Slow CLK_000_N_SYNC_6_
|
|
|
|
|
F3 F 1 DFF * * A------- Low Slow CLK_000_N_SYNC_7_
|
|
|
|
|
A10 A 1 DFF * * A------- Low Slow CLK_000_N_SYNC_8_
|
|
|
|
|
A6 A 1 DFF * * -------H Low Slow CLK_000_N_SYNC_9_
|
|
|
|
|
E2 E 1 DFF * * -B------ Low Slow CLK_000_P_SYNC_0_
|
|
|
|
|
B7 B 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_1_
|
|
|
|
|
G7 G 1 DFF * * ----E--- Low Slow CLK_000_P_SYNC_2_
|
|
|
|
|
E13 E 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_3_
|
|
|
|
|
G3 G 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_4_
|
|
|
|
|
G14 G 1 DFF * * A------- Low Slow CLK_000_P_SYNC_5_
|
|
|
|
|
A3 A 1 DFF * * -B------ Low Slow CLK_000_P_SYNC_6_
|
|
|
|
|
B3 B 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_7_
|
|
|
|
|
G10 G 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_8_
|
|
|
|
|
G15 G 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_9_
|
|
|
|
|
B5 B 2 DFF * * ABC----- Low Slow CYCLE_DMA_0_
|
|
|
|
|
C12 C 3 DFF * * A-C----- Low Slow CYCLE_DMA_1_
|
|
|
|
|
G11 G 1 DFF * * -B------ Low Slow IPL_D0_0_
|
|
|
|
|
D15 D 1 DFF * * -B------ Low Slow IPL_D0_1_
|
|
|
|
|
B11 B 1 DFF * * -B------ Low Slow IPL_D0_2_
|
|
|
|
|
F14 F 4 COM -----F-- Low Slow N_317_i
|
2016-01-24 19:26:06 +00:00
|
|
|
|
G8 G 3 DFF * * ------G- Low - RN_A0 --> A0
|
|
|
|
|
H4 H 3 DFF * * ABCDE-GH Low - RN_BGACK_030 --> BGACK_030
|
|
|
|
|
D1 D 2 DFF * * ---D---- Low - RN_BG_000 --> BG_000
|
|
|
|
|
H9 H 4 DFF * * -------H Low - RN_DSACK1 --> DSACK1
|
|
|
|
|
B8 B 10 DFF * * -B------ Low - RN_IPL_030_0_ --> IPL_030_0_
|
|
|
|
|
B12 B 10 DFF * * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_
|
|
|
|
|
B4 B 10 DFF * * -B------ Low - RN_IPL_030_2_ --> IPL_030_2_
|
|
|
|
|
G0 G 2 DFF * * ------G- Low - RN_RW --> RW
|
|
|
|
|
H0 H 3 DFF * * -------H Low - RN_RW_000 --> RW_000
|
|
|
|
|
D0 D 3 TFF * * ---D-F-- Low - RN_VMA --> VMA
|
2016-01-25 17:02:53 +00:00
|
|
|
|
D3 D 3 DFF * * ---D---- Low Slow RST_DLY_0_
|
|
|
|
|
D14 D 4 DFF * * ---D---- Low Slow RST_DLY_1_
|
|
|
|
|
D7 D 2 DFF * * ---D---- Low Slow RST_DLY_2_
|
|
|
|
|
G13 G 3 DFF * * ------GH Low Slow SIZE_DMA_0_
|
|
|
|
|
G9 G 3 DFF * * ------GH Low Slow SIZE_DMA_1_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
F1 F 2 DFF * * --C--F-H Low Slow SM_AMIGA_0_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
F5 F 3 DFF * * -----F-H Low Slow SM_AMIGA_1_
|
|
|
|
|
F10 F 4 DFF * * -----F-- Low Slow SM_AMIGA_2_
|
|
|
|
|
F6 F 5 TFF * * -----F-- Low Slow SM_AMIGA_3_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
F9 F 3 DFF * * --C--F-- Low Slow SM_AMIGA_4_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
F8 F 3 DFF * * --C--F-H Low Slow SM_AMIGA_5_
|
|
|
|
|
F4 F 3 DFF * * A-C--F-- Low Slow SM_AMIGA_6_
|
|
|
|
|
F0 F 14 DFF * * --CD-F-H Low Slow SM_AMIGA_i_7_
|
|
|
|
|
D6 D 2 DFF * * ---D-F-- Low Slow cpu_est_0_
|
|
|
|
|
D2 D 3 DFF * * ---D-FG- Low Slow cpu_est_1_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
D13 D 4 DFF * * ---D-FG- Low Slow cpu_est_2_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
F12 F 3 DFF * * ---D-FG- Low Slow cpu_est_3_
|
|
|
|
|
B13 B 2 DFF * * -B-D---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
|
|
|
|
B2 B 2 DFF * * -BC----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW
|
|
|
|
|
A1 A 7 DFF * * A------H Low Slow inst_AS_000_DMA
|
|
|
|
|
C1 C 2 DFF * * --C-E--- Low Slow inst_AS_000_INT
|
|
|
|
|
C4 C 7 DFF * * --C--F-- Low Slow inst_AS_030_000_SYNC
|
|
|
|
|
H3 H 1 DFF * * --CDE--H Low Slow inst_AS_030_D0
|
|
|
|
|
H13 H 1 DFF * * -BC---G- Low Slow inst_BGACK_030_INT_D
|
|
|
|
|
B9 B 1 DFF * * ---DEF-- Low Slow inst_CLK_000_D0
|
|
|
|
|
E8 E 1 DFF * * ----EF-- Low Slow inst_CLK_000_D1
|
|
|
|
|
G2 G 1 DFF * * ---D-F-- Low Slow inst_CLK_000_NE
|
|
|
|
|
D10 D 1 DFF * * ---D-F-- Low Slow inst_CLK_000_NE_D0
|
|
|
|
|
G5 G 1 DFF * * -BCD-F-H Low Slow inst_CLK_000_PE
|
|
|
|
|
A2 A 8 DFF * * A------- Low Slow inst_CLK_030_H
|
|
|
|
|
F13 F 1 DFF * * A----F-- Low Slow inst_CLK_OUT_PRE_50
|
|
|
|
|
A12 A 1 DFF * * -B----GH Low Slow inst_CLK_OUT_PRE_D
|
|
|
|
|
A13 A 9 DFF * * A------- Low Slow inst_DS_000_DMA
|
|
|
|
|
C8 C 5 DFF * * --CD---- Low Slow inst_DS_000_ENABLE
|
|
|
|
|
B15 B 1 DFF * * -----F-- Low Slow inst_DTACK_D0
|
|
|
|
|
A5 A 3 DFF * * A--D---- Low Slow inst_LDS_000_INT
|
|
|
|
|
D9 D 2 DFF * * AB-DE-GH Low Slow inst_RESET_OUT
|
|
|
|
|
A9 A 2 DFF * * A--D---- Low Slow inst_UDS_000_INT
|
|
|
|
|
F2 F 1 DFF * * ---D-F-- Low Slow inst_VPA_D
|
|
|
|
|
A8 A 1 DFF * * A-CDEFGH Low Slow inst_nEXP_SPACE_D0reg
|
2016-01-24 19:26:06 +00:00
|
|
|
|
----------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
<Note> Power : Hi = High
|
|
|
|
|
MH = Medium High
|
|
|
|
|
ML = Medium Low
|
|
|
|
|
Lo = Low
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Signals_Fanout_List
|
|
|
|
|
~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
Signal Source : Fanout List
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
SIZE_1_{ I}:inst_LDS_000_INT{ A}
|
|
|
|
|
A_31_{ C}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
|
|
|
|
: IPL_D0_2_{ B}
|
|
|
|
|
IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
: IPL_D0_1_{ D}
|
|
|
|
|
FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
|
|
|
|
IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
|
|
|
|
: IPL_D0_0_{ G}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H}
|
|
|
|
|
: inst_AS_030_D0{ H}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E}
|
|
|
|
|
: BGACK_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
: CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ C} inst_CLK_030_H{ A}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
UDS_000{ E}: A0{ G}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
|
|
|
|
|
: SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
|
|
|
|
|
LDS_000{ E}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} SIZE_DMA_0_{ G}
|
|
|
|
|
: SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
|
|
|
|
|
A1{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
nEXP_SPACE{. }:inst_nEXP_SPACE_D0reg{ A}
|
|
|
|
|
BERR{ F}: DSACK1{ H}inst_AS_000_INT{ C} SM_AMIGA_5_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
:inst_AS_030_000_SYNC{ C} SM_AMIGA_0_{ F} SM_AMIGA_4_{ F}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
:inst_DS_000_ENABLE{ C} SM_AMIGA_6_{ F} SM_AMIGA_1_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
|
|
|
|
BG_030{ D}: BG_000{ D}
|
|
|
|
|
BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H}
|
|
|
|
|
CLK_030{. }: DSACK1{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
|
|
|
|
|
: inst_CLK_030_H{ A}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
CLK_000{. }:inst_CLK_000_D0{ B}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
FPU_SENSE{ B}: BERR{ E} FPU_CS{ H}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
DTACK{ E}: inst_DTACK_D0{ B}
|
|
|
|
|
VPA{. }: inst_VPA_D{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
RST{. }: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
|
|
|
|
: RW_000{ H} A0{ G} BG_000{ D}
|
|
|
|
|
: BGACK_030{ H} DSACK1{ H} VMA{ D}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
: RW{ G}inst_AS_000_INT{ C} SM_AMIGA_5_{ F}
|
|
|
|
|
:inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} inst_AS_030_D0{ H}inst_nEXP_SPACE_D0reg{ A}
|
|
|
|
|
:inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A}
|
|
|
|
|
:inst_DS_000_DMA{ A} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ C}
|
|
|
|
|
: SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_VPA_D{ F}
|
|
|
|
|
:inst_UDS_000_INT{ A}inst_LDS_000_INT{ A} inst_DTACK_D0{ B}
|
|
|
|
|
: inst_RESET_OUT{ D} IPL_D0_0_{ G} IPL_D0_1_{ D}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: IPL_D0_2_{ B} SM_AMIGA_0_{ F}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
: SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C} RST_DLY_0_{ D}
|
|
|
|
|
: RST_DLY_1_{ D} RST_DLY_2_{ D} SM_AMIGA_6_{ F}
|
|
|
|
|
: inst_CLK_030_H{ A} SM_AMIGA_1_{ F} SM_AMIGA_3_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
|
|
|
|
SIZE_0_{ H}:inst_LDS_000_INT{ A}
|
|
|
|
|
A_30_{ C}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_29_{ C}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_28_{ D}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_27_{ D}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_26_{ D}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_25_{ D}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_24_{ D}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_23_{ I}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_22_{ I}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_21_{ B}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_20_{ B}: CIIN{ E} CIIN_0{ E}
|
|
|
|
|
A_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
|
|
|
|
A_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
|
|
|
|
A_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
|
|
|
|
A_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
|
|
|
|
RN_IPL_030_2_{ C}: IPL_030_2_{ B}
|
|
|
|
|
RN_IPL_030_1_{ C}: IPL_030_1_{ B}
|
|
|
|
|
RN_IPL_030_0_{ C}: IPL_030_0_{ B}
|
|
|
|
|
RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ A}
|
|
|
|
|
RN_RW_000{ I}: RW_000{ H}
|
|
|
|
|
A0{ H}:inst_UDS_000_INT{ A}inst_LDS_000_INT{ A}
|
|
|
|
|
RN_A0{ H}: A0{ G}
|
|
|
|
|
RN_BG_000{ E}: BG_000{ D}
|
|
|
|
|
RN_BGACK_030{ I}: SIZE_1_{ H} AS_030{ H} AS_000{ E}
|
|
|
|
|
: DS_030{ A} UDS_000{ D} LDS_000{ D}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
: SIZE_0_{ G}AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
:AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H} A0{ G}
|
|
|
|
|
: BGACK_030{ H} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
:inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A}
|
|
|
|
|
:inst_DS_000_DMA{ A} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ C}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}
|
|
|
|
|
: inst_CLK_030_H{ A}
|
|
|
|
|
RN_DSACK1{ I}: DSACK1{ H}
|
|
|
|
|
RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
|
|
|
|
: SM_AMIGA_i_7_{ F}
|
|
|
|
|
RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ C}
|
|
|
|
|
RN_RW{ H}: RW{ G}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
N_317_i{ G}: SM_AMIGA_i_7_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_2_{ D}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
: cpu_est_3_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_i_7_{ F}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
cpu_est_3_{ G}: E{ G} VMA{ D} cpu_est_3_{ F}
|
|
|
|
|
: cpu_est_1_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_i_7_{ F}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
cpu_est_0_{ E}: VMA{ D} cpu_est_2_{ D} cpu_est_3_{ F}
|
|
|
|
|
: cpu_est_0_{ D} cpu_est_1_{ D} SM_AMIGA_3_{ F}
|
|
|
|
|
: SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
|
|
|
|
cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_2_{ D}
|
|
|
|
|
: cpu_est_3_{ F} cpu_est_1_{ D} SM_AMIGA_3_{ F}
|
|
|
|
|
: SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
|
|
|
|
inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C}
|
|
|
|
|
SM_AMIGA_5_{ G}: RW_000{ H} N_317_i{ F}inst_AS_000_INT{ C}
|
|
|
|
|
: SM_AMIGA_5_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_i_7_{ F}
|
|
|
|
|
inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}
|
|
|
|
|
inst_AS_030_D0{ I}: CIIN{ E} BG_000{ D} DSACK1{ H}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
:inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ C}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: CIIN_0{ E}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
inst_nEXP_SPACE_D0reg{ B}: SIZE_1_{ H} AS_030{ H} DS_030{ A}
|
|
|
|
|
: SIZE_0_{ G}AMIGA_BUS_DATA_DIR{ E} A0{ G}
|
|
|
|
|
: BG_000{ D} DSACK1{ H} N_317_i{ F}
|
|
|
|
|
:inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ F} CIIN_0{ E}
|
|
|
|
|
inst_AS_030_000_SYNC{ D}: N_317_i{ F}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ F}
|
|
|
|
|
inst_BGACK_030_INT_D{ I}: A0{ G} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
:inst_AS_030_000_SYNC{ C} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}
|
|
|
|
|
:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}
|
|
|
|
|
inst_AS_000_DMA{ B}: AS_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
|
|
|
|
|
: inst_CLK_030_H{ A}
|
|
|
|
|
inst_DS_000_DMA{ B}: DS_030{ A}inst_DS_000_DMA{ A}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
CYCLE_DMA_0_{ C}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ B}
|
|
|
|
|
: CYCLE_DMA_1_{ C} inst_CLK_030_H{ A}
|
|
|
|
|
CYCLE_DMA_1_{ D}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_1_{ C}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: inst_CLK_030_H{ A}
|
|
|
|
|
SIZE_DMA_0_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_0_{ G}
|
|
|
|
|
SIZE_DMA_1_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_1_{ G}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
inst_VPA_D{ G}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_i_7_{ F}
|
|
|
|
|
inst_UDS_000_INT{ B}: UDS_000{ D}inst_UDS_000_INT{ A}
|
|
|
|
|
inst_LDS_000_INT{ B}: LDS_000{ D}inst_LDS_000_INT{ A}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
inst_CLK_OUT_PRE_D{ B}: CLK_DIV_OUT{ G} CLK_EXP{ B} DSACK1{ H}
|
|
|
|
|
inst_DTACK_D0{ C}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
|
|
|
|
inst_RESET_OUT{ E}: AS_030{ H} AS_000{ E} DS_030{ A}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: UDS_000{ D} LDS_000{ D} RESET{ B}
|
|
|
|
|
: RW_000{ H} A0{ G} RW{ G}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
: inst_RESET_OUT{ D}
|
|
|
|
|
inst_CLK_OUT_PRE_50{ G}:inst_CLK_OUT_PRE_D{ A}inst_CLK_OUT_PRE_50{ F}
|
|
|
|
|
inst_CLK_000_D1{ F}: N_317_i{ F}CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E}
|
|
|
|
|
: SM_AMIGA_6_{ F}
|
|
|
|
|
inst_CLK_000_D0{ C}: BG_000{ D} N_317_i{ F}inst_CLK_000_D1{ E}
|
|
|
|
|
:CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E} SM_AMIGA_6_{ F}
|
|
|
|
|
inst_CLK_000_PE{ H}: RW_000{ H} BGACK_030{ H} VMA{ D}
|
|
|
|
|
: SM_AMIGA_5_{ F} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ C}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_0_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
: SM_AMIGA_6_{ F} SM_AMIGA_1_{ F} SM_AMIGA_3_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
CLK_000_P_SYNC_9_{ H}:inst_CLK_000_PE{ G}
|
|
|
|
|
inst_CLK_000_NE{ H}: VMA{ D} SM_AMIGA_5_{ F} inst_RESET_OUT{ D}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
:inst_CLK_000_NE_D0{ D} SM_AMIGA_0_{ F} SM_AMIGA_4_{ F}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
: RST_DLY_0_{ D} RST_DLY_1_{ D} RST_DLY_2_{ D}
|
|
|
|
|
: SM_AMIGA_1_{ F} SM_AMIGA_i_7_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
CLK_000_N_SYNC_11_{ I}:inst_CLK_000_NE{ G}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
IPL_D0_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
|
|
|
|
IPL_D0_1_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
IPL_D0_2_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
inst_CLK_000_NE_D0{ E}: cpu_est_2_{ D} cpu_est_3_{ F} cpu_est_0_{ D}
|
|
|
|
|
: cpu_est_1_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_i_7_{ F}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
SM_AMIGA_0_{ G}: RW_000{ H} N_317_i{ F} SM_AMIGA_0_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
:inst_DS_000_ENABLE{ C} SM_AMIGA_i_7_{ F}
|
|
|
|
|
inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
SM_AMIGA_4_{ G}: N_317_i{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_3_{ F} SM_AMIGA_i_7_{ F}
|
|
|
|
|
inst_DS_000_ENABLE{ D}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ C}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
RST_DLY_0_{ E}: inst_RESET_OUT{ D} RST_DLY_0_{ D} RST_DLY_1_{ D}
|
|
|
|
|
: RST_DLY_2_{ D}
|
|
|
|
|
RST_DLY_1_{ E}: inst_RESET_OUT{ D} RST_DLY_0_{ D} RST_DLY_1_{ D}
|
|
|
|
|
: RST_DLY_2_{ D}
|
|
|
|
|
RST_DLY_2_{ E}: inst_RESET_OUT{ D} RST_DLY_0_{ D} RST_DLY_1_{ D}
|
|
|
|
|
: RST_DLY_2_{ D}
|
|
|
|
|
CLK_000_P_SYNC_0_{ F}:CLK_000_P_SYNC_1_{ B}
|
|
|
|
|
CLK_000_P_SYNC_1_{ C}:CLK_000_P_SYNC_2_{ G}
|
|
|
|
|
CLK_000_P_SYNC_2_{ H}:CLK_000_P_SYNC_3_{ E}
|
|
|
|
|
CLK_000_P_SYNC_3_{ F}:CLK_000_P_SYNC_4_{ G}
|
|
|
|
|
CLK_000_P_SYNC_4_{ H}:CLK_000_P_SYNC_5_{ G}
|
|
|
|
|
CLK_000_P_SYNC_5_{ H}:CLK_000_P_SYNC_6_{ A}
|
|
|
|
|
CLK_000_P_SYNC_6_{ B}:CLK_000_P_SYNC_7_{ B}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
CLK_000_P_SYNC_7_{ C}:CLK_000_P_SYNC_8_{ G}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
CLK_000_P_SYNC_8_{ H}:CLK_000_P_SYNC_9_{ G}
|
|
|
|
|
CLK_000_N_SYNC_0_{ F}:CLK_000_N_SYNC_1_{ A}
|
|
|
|
|
CLK_000_N_SYNC_1_{ B}:CLK_000_N_SYNC_2_{ B}
|
|
|
|
|
CLK_000_N_SYNC_2_{ C}:CLK_000_N_SYNC_3_{ B}
|
|
|
|
|
CLK_000_N_SYNC_3_{ C}:CLK_000_N_SYNC_4_{ B}
|
|
|
|
|
CLK_000_N_SYNC_4_{ C}:CLK_000_N_SYNC_5_{ D}
|
|
|
|
|
CLK_000_N_SYNC_5_{ E}:CLK_000_N_SYNC_6_{ G}
|
|
|
|
|
CLK_000_N_SYNC_6_{ H}:CLK_000_N_SYNC_7_{ F}
|
|
|
|
|
CLK_000_N_SYNC_7_{ G}:CLK_000_N_SYNC_8_{ A}
|
|
|
|
|
CLK_000_N_SYNC_8_{ B}:CLK_000_N_SYNC_9_{ A}
|
|
|
|
|
CLK_000_N_SYNC_9_{ B}: DSACK1{ H}CLK_000_N_SYNC_10_{ H}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
CLK_000_N_SYNC_10_{ I}: DSACK1{ H}CLK_000_N_SYNC_11_{ H}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
SM_AMIGA_6_{ G}: N_317_i{ F} SM_AMIGA_5_{ F}inst_UDS_000_INT{ A}
|
|
|
|
|
:inst_LDS_000_INT{ A}inst_DS_000_ENABLE{ C} SM_AMIGA_6_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_i_7_{ F}
|
|
|
|
|
inst_CLK_030_H{ B}:inst_DS_000_DMA{ A} inst_CLK_030_H{ A}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
SM_AMIGA_1_{ G}: DSACK1{ H} N_317_i{ F} SM_AMIGA_0_{ F}
|
|
|
|
|
: SM_AMIGA_1_{ F} SM_AMIGA_i_7_{ F}
|
|
|
|
|
SM_AMIGA_3_{ G}: N_317_i{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_i_7_{ F}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
SM_AMIGA_2_{ G}: N_317_i{ F} SM_AMIGA_1_{ F} SM_AMIGA_2_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
: SM_AMIGA_i_7_{ F}
|
|
|
|
|
SM_AMIGA_i_7_{ G}:AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H}inst_AS_030_000_SYNC{ C}
|
2016-01-25 17:02:53 +00:00
|
|
|
|
:inst_DS_000_ENABLE{ C} SM_AMIGA_6_{ F}
|
2016-01-24 19:26:06 +00:00
|
|
|
|
CIIN_0{ F}: CIIN{ E}
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
<Note> {.} : Indicates block location of signal
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Set_Reset_Summary
|
|
|
|
|
~~~~~~~~~~~~~~~~~
|
|
|
|
|
|
|
|
|
|
Block A
|
|
|
|
|
block level set pt : GND
|
|
|
|
|
block level reset pt : GND
|
|
|
|
|
Equations :
|
|
|
|
|
| | |Block|Block| Signal
|
|
|
|
|
| Reg |Mode |Set |Reset| Name
|
|
|
|
|
+-----+-----+-----+-----+------------------------
|
|
|
|
|
| | | | | DS_030
|
|
|
|
|
| | | | | AVEC
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | inst_nEXP_SPACE_D0reg
|
|
|
|
|
| * | S | BS | BR | inst_CLK_OUT_PRE_D
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | inst_AS_000_DMA
|
|
|
|
|
| * | S | BS | BR | inst_LDS_000_INT
|
|
|
|
|
| * | S | BS | BR | inst_UDS_000_INT
|
|
|
|
|
| * | S | BS | BR | inst_DS_000_DMA
|
|
|
|
|
| * | S | BS | BR | inst_CLK_030_H
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_9_
|
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_8_
|
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_1_
|
|
|
|
|
| * | S | BS | BR | CLK_000_P_SYNC_6_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| | | | | A_19_
|
|
|
|
|
| | | | | A_16_
|
|
|
|
|
| | | | | A_18_
|
|
|
|
|
| | | | | FPU_SENSE
|
|
|
|
|
| | | | | A_21_
|
|
|
|
|
| | | | | A_20_
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Block B
|
|
|
|
|
block level set pt : GND
|
|
|
|
|
block level reset pt : GND
|
|
|
|
|
Equations :
|
|
|
|
|
| | |Block|Block| Signal
|
|
|
|
|
| Reg |Mode |Set |Reset| Name
|
|
|
|
|
+-----+-----+-----+-----+------------------------
|
|
|
|
|
| * | S | BS | BR | IPL_030_2_
|
|
|
|
|
| * | S | BS | BR | IPL_030_0_
|
|
|
|
|
| * | S | BS | BR | IPL_030_1_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | CLK_EXP
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| | | | | RESET
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | CYCLE_DMA_0_
|
|
|
|
|
| * | S | BS | BR | inst_CLK_000_D0
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
|
|
|
|
| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW
|
|
|
|
|
| * | S | BS | BR | RN_IPL_030_0_
|
|
|
|
|
| * | S | BS | BR | RN_IPL_030_1_
|
|
|
|
|
| * | S | BS | BR | RN_IPL_030_2_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_4_
|
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_3_
|
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_2_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | CLK_000_P_SYNC_7_
|
|
|
|
|
| * | S | BS | BR | CLK_000_P_SYNC_1_
|
|
|
|
|
| * | S | BS | BR | IPL_D0_2_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | inst_DTACK_D0
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| | | | | A_29_
|
|
|
|
|
| | | | | A_30_
|
|
|
|
|
| | | | | A_31_
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Block C
|
|
|
|
|
block level set pt : GND
|
|
|
|
|
block level reset pt : GND
|
|
|
|
|
Equations :
|
|
|
|
|
| | |Block|Block| Signal
|
|
|
|
|
| Reg |Mode |Set |Reset| Name
|
|
|
|
|
+-----+-----+-----+-----+------------------------
|
|
|
|
|
| | | | | AMIGA_BUS_ENABLE_LOW
|
|
|
|
|
| * | S | BS | BR | inst_AS_030_000_SYNC
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | inst_DS_000_ENABLE
|
|
|
|
|
| * | S | BS | BR | CYCLE_DMA_1_
|
|
|
|
|
| * | S | BS | BR | inst_AS_000_INT
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| | | | | BG_030
|
|
|
|
|
| | | | | A_24_
|
|
|
|
|
| | | | | A_25_
|
|
|
|
|
| | | | | A_26_
|
|
|
|
|
| | | | | A_27_
|
|
|
|
|
| | | | | A_28_
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Block D
|
|
|
|
|
block level set pt : GND
|
|
|
|
|
block level reset pt : GND
|
|
|
|
|
Equations :
|
|
|
|
|
| | |Block|Block| Signal
|
|
|
|
|
| Reg |Mode |Set |Reset| Name
|
|
|
|
|
+-----+-----+-----+-----+------------------------
|
|
|
|
|
| | | | | UDS_000
|
|
|
|
|
| | | | | LDS_000
|
|
|
|
|
| * | S | BS | BR | VMA
|
|
|
|
|
| | | | | AMIGA_BUS_ENABLE_HIGH
|
|
|
|
|
| * | S | BS | BR | BG_000
|
|
|
|
|
| | | | | AMIGA_ADDR_ENABLE
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | inst_RESET_OUT
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | cpu_est_2_
|
|
|
|
|
| * | S | BS | BR | cpu_est_1_
|
|
|
|
|
| * | S | BS | BR | RN_VMA
|
|
|
|
|
| * | S | BS | BR | cpu_est_0_
|
|
|
|
|
| * | S | BS | BR | inst_CLK_000_NE_D0
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | RST_DLY_1_
|
|
|
|
|
| * | S | BS | BR | RST_DLY_0_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | RN_BG_000
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | RST_DLY_2_
|
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_5_
|
|
|
|
|
| * | S | BS | BR | IPL_D0_1_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| | | | | BGACK_000
|
|
|
|
|
| | | | | DTACK
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Block E
|
|
|
|
|
block level set pt : GND
|
|
|
|
|
block level reset pt : GND
|
|
|
|
|
Equations :
|
|
|
|
|
| | |Block|Block| Signal
|
|
|
|
|
| Reg |Mode |Set |Reset| Name
|
|
|
|
|
+-----+-----+-----+-----+------------------------
|
|
|
|
|
| | | | | AS_000
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| | | | | BERR
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| | | | | AMIGA_BUS_DATA_DIR
|
|
|
|
|
| | | | | CIIN
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | inst_CLK_000_D1
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| | | | | CIIN_0
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_0_
|
|
|
|
|
| * | S | BS | BR | CLK_000_P_SYNC_3_
|
|
|
|
|
| * | S | BS | BR | CLK_000_P_SYNC_0_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Block F
|
|
|
|
|
block level set pt : GND
|
|
|
|
|
block level reset pt : GND
|
|
|
|
|
Equations :
|
|
|
|
|
| | |Block|Block| Signal
|
|
|
|
|
| Reg |Mode |Set |Reset| Name
|
|
|
|
|
+-----+-----+-----+-----+------------------------
|
|
|
|
|
| * | S | BS | BR | SM_AMIGA_i_7_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | SM_AMIGA_6_
|
|
|
|
|
| * | S | BS | BR | SM_AMIGA_5_
|
|
|
|
|
| * | S | BS | BR | cpu_est_3_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | SM_AMIGA_0_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | SM_AMIGA_1_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | SM_AMIGA_4_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | inst_CLK_OUT_PRE_50
|
|
|
|
|
| * | S | BS | BR | inst_VPA_D
|
|
|
|
|
| * | S | BS | BR | SM_AMIGA_3_
|
|
|
|
|
| * | S | BS | BR | SM_AMIGA_2_
|
|
|
|
|
| | | | | N_317_i
|
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_7_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| | | | | A_17_
|
|
|
|
|
| | | | | FC_1_
|
|
|
|
|
| | | | | FC_0_
|
|
|
|
|
| | | | | IPL_1_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| | | | | A1
|
2016-01-24 19:26:06 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Block G
|
|
|
|
|
block level set pt : GND
|
|
|
|
|
block level reset pt : GND
|
|
|
|
|
Equations :
|
|
|
|
|
| | |Block|Block| Signal
|
|
|
|
|
| Reg |Mode |Set |Reset| Name
|
|
|
|
|
+-----+-----+-----+-----+------------------------
|
|
|
|
|
| * | S | BS | BR | RW
|
|
|
|
|
| * | S | BS | BR | A0
|
|
|
|
|
| | | | | SIZE_0_
|
|
|
|
|
| | | | | E
|
|
|
|
|
| * | S | BS | BR | CLK_DIV_OUT
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | inst_CLK_000_PE
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | SIZE_DMA_1_
|
|
|
|
|
| * | S | BS | BR | SIZE_DMA_0_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | inst_CLK_000_NE
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | RN_A0
|
|
|
|
|
| * | S | BS | BR | RN_RW
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_6_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | CLK_000_P_SYNC_8_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | CLK_000_P_SYNC_5_
|
|
|
|
|
| * | S | BS | BR | CLK_000_P_SYNC_4_
|
|
|
|
|
| * | S | BS | BR | CLK_000_P_SYNC_2_
|
|
|
|
|
| * | S | BS | BR | IPL_D0_0_
|
|
|
|
|
| * | S | BS | BR | CLK_000_P_SYNC_9_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| | | | | IPL_0_
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| | | | | IPL_2_
|
2016-01-24 19:26:06 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Block H
|
|
|
|
|
block level set pt : GND
|
|
|
|
|
block level reset pt : GND
|
|
|
|
|
Equations :
|
|
|
|
|
| | |Block|Block| Signal
|
|
|
|
|
| Reg |Mode |Set |Reset| Name
|
|
|
|
|
+-----+-----+-----+-----+------------------------
|
|
|
|
|
| * | S | BS | BR | RW_000
|
|
|
|
|
| | | | | AS_030
|
|
|
|
|
| | | | | SIZE_1_
|
|
|
|
|
| * | S | BS | BR | DSACK1
|
|
|
|
|
| * | S | BS | BR | BGACK_030
|
|
|
|
|
| | | | | FPU_CS
|
|
|
|
|
| * | S | BS | BR | RN_BGACK_030
|
|
|
|
|
| * | S | BS | BR | inst_AS_030_D0
|
2016-01-25 17:02:53 +00:00
|
|
|
|
| * | S | BS | BR | inst_BGACK_030_INT_D
|
2016-01-24 19:26:06 +00:00
|
|
|
|
| * | S | BS | BR | RN_DSACK1
|
|
|
|
|
| * | S | BS | BR | RN_RW_000
|
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_10_
|
|
|
|
|
| * | S | BS | BR | CLK_000_N_SYNC_11_
|
|
|
|
|
| | | | | A_23_
|
|
|
|
|
| | | | | A_22_
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
<Note> (S) means the macrocell is configured in synchronous mode
|
|
|
|
|
i.e. it uses the block-level set and reset pt.
|
|
|
|
|
(A) means the macrocell is configured in asynchronous mode
|
|
|
|
|
i.e. it can have its independant set or reset pt.
|
|
|
|
|
(BS) means the block-level set pt is selected.
|
|
|
|
|
(BR) means the block-level reset pt is selected.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BLOCK_A_LOGIC_ARRAY_FANIN
|
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
CSM Signal Source CSM Signal Source
|
|
|
|
|
------------------------------------ ------------------------------------
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx A0 A0 pin 69 mx A17 SIZE_0_ pin 70
|
|
|
|
|
mx A1 ... ... mx A18inst_LDS_000_INT mcell A5
|
|
|
|
|
mx A2CLK_000_N_SYNC_0_ mcell E9 mx A19inst_UDS_000_INT mcell A9
|
|
|
|
|
mx A3inst_nEXP_SPACE_D0reg mcell A8 mx A20 CLK_030 pin 64
|
|
|
|
|
mx A4 CYCLE_DMA_1_ mcell C12 mx A21 RST pin 86
|
|
|
|
|
mx A5 nEXP_SPACE pin 14 mx A22 inst_CLK_030_H mcell A2
|
|
|
|
|
mx A6 RW_000 pin 80 mx A23 RN_BGACK_030 mcell H4
|
|
|
|
|
mx A7CLK_000_N_SYNC_7_ mcell F3 mx A24 LDS_000 pin 31
|
|
|
|
|
mx A8 UDS_000 pin 32 mx A25 inst_DS_000_DMA mcell A13
|
|
|
|
|
mx A9 inst_AS_000_DMA mcell A1 mx A26 ... ...
|
|
|
|
|
mx A10 SM_AMIGA_6_ mcell F4 mx A27 SIZE_1_ pin 79
|
|
|
|
|
mx A11CLK_000_P_SYNC_5_ mcell G14 mx A28 CYCLE_DMA_0_ mcell B5
|
|
|
|
|
mx A12 inst_RESET_OUT mcell D9 mx A29 ... ...
|
|
|
|
|
mx A13 ... ... mx A30 ... ...
|
|
|
|
|
mx A14CLK_000_N_SYNC_8_ mcell A10 mx A31 ... ...
|
|
|
|
|
mx A15inst_CLK_OUT_PRE_50 mcell F13 mx A32 ... ...
|
2016-01-24 19:26:06 +00:00
|
|
|
|
mx A16 AS_000 pin 42
|
|
|
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BLOCK_B_LOGIC_ARRAY_FANIN
|
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
CSM Signal Source CSM Signal Source
|
|
|
|
|
------------------------------------ ------------------------------------
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx B0 IPL_0_ pin 67 mx B17 ... ...
|
|
|
|
|
mx B1 RN_IPL_030_1_ mcell B12 mx B18 ... ...
|
|
|
|
|
mx B2 IPL_D0_1_ mcell D15 mx B19inst_BGACK_030_INT_D mcell H13
|
|
|
|
|
mx B3 CLK_000 pin 11 mx B20CLK_000_N_SYNC_1_ mcell A14
|
2016-01-24 19:26:06 +00:00
|
|
|
|
mx B4 IPL_2_ pin 68 mx B21 IPL_1_ pin 56
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx B5 ... ... mx B22 inst_CLK_000_PE mcell G5
|
|
|
|
|
mx B6CLK_000_P_SYNC_6_ mcell A3 mx B23 RN_BGACK_030 mcell H4
|
|
|
|
|
mx B7 IPL_D0_2_ mcell B11 mx B24 RST pin 86
|
|
|
|
|
mx B8 RN_IPL_030_0_ mcell B8 mx B25 inst_RESET_OUT mcell D9
|
|
|
|
|
mx B9inst_CLK_OUT_PRE_D mcell A12 mx B26 ... ...
|
|
|
|
|
mx B10inst_AMIGA_BUS_ENABLE_DMA_LOW mcell B2 mx B27 RN_IPL_030_2_ mcell B4
|
|
|
|
|
mx B11 A1 pin 60 mx B28inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell B13
|
|
|
|
|
mx B12CLK_000_N_SYNC_3_ mcell B10 mx B29CLK_000_N_SYNC_2_ mcell B14
|
|
|
|
|
mx B13 IPL_D0_0_ mcell G11 mx B30 ... ...
|
|
|
|
|
mx B14 DTACK pin 30 mx B31 CYCLE_DMA_0_ mcell B5
|
|
|
|
|
mx B15CLK_000_P_SYNC_0_ mcell E2 mx B32 ... ...
|
|
|
|
|
mx B16 AS_000 pin 42
|
2016-01-24 19:26:06 +00:00
|
|
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BLOCK_C_LOGIC_ARRAY_FANIN
|
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
CSM Signal Source CSM Signal Source
|
|
|
|
|
------------------------------------ ------------------------------------
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx C0 RN_BGACK_030 mcell H4 mx C17 FC_0_ pin 57
|
|
|
|
|
mx C1 inst_AS_000_INT mcell C1 mx C18 SM_AMIGA_4_ mcell F9
|
|
|
|
|
mx C2 SM_AMIGA_5_ mcell F8 mx C19inst_BGACK_030_INT_D mcell H13
|
|
|
|
|
mx C3inst_nEXP_SPACE_D0reg mcell A8 mx C20 FC_1_ pin 58
|
|
|
|
|
mx C4 A_18_ pin 95 mx C21 RST pin 86
|
|
|
|
|
mx C5 SM_AMIGA_i_7_ mcell F0 mx C22 inst_CLK_000_PE mcell G5
|
|
|
|
|
mx C6 A_16_ pin 96 mx C23 ... ...
|
|
|
|
|
mx C7inst_DS_000_ENABLE mcell C8 mx C24 ... ...
|
|
|
|
|
mx C8 RW pin 71 mx C25 BERR pin 41
|
|
|
|
|
mx C9 ... ... mx C26 ... ...
|
|
|
|
|
mx C10inst_AMIGA_BUS_ENABLE_DMA_LOW mcell B2 mx C27 ... ...
|
|
|
|
|
mx C11 inst_AS_030_D0 mcell H3 mx C28 CYCLE_DMA_0_ mcell B5
|
|
|
|
|
mx C12 A_19_ pin 97 mx C29 SM_AMIGA_6_ mcell F4
|
|
|
|
|
mx C13 A_17_ pin 59 mx C30 SM_AMIGA_0_ mcell F1
|
|
|
|
|
mx C14inst_AS_030_000_SYNC mcell C4 mx C31 ... ...
|
|
|
|
|
mx C15 CYCLE_DMA_1_ mcell C12 mx C32 ... ...
|
|
|
|
|
mx C16 AS_000 pin 42
|
2016-01-24 19:26:06 +00:00
|
|
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BLOCK_D_LOGIC_ARRAY_FANIN
|
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
CSM Signal Source CSM Signal Source
|
|
|
|
|
------------------------------------ ------------------------------------
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx D0 RN_BGACK_030 mcell H4 mx D17 RST_DLY_1_ mcell D14
|
|
|
|
|
mx D1 cpu_est_3_ mcell F12 mx D18 inst_AS_030_D0 mcell H3
|
|
|
|
|
mx D2 RN_BG_000 mcell D1 mx D19inst_UDS_000_INT mcell A9
|
|
|
|
|
mx D3 cpu_est_1_ mcell D2 mx D20inst_CLK_000_NE_D0 mcell D10
|
|
|
|
|
mx D4 BG_030 pin 21 mx D21 RST pin 86
|
|
|
|
|
mx D5 SM_AMIGA_i_7_ mcell F0 mx D22 inst_CLK_000_PE mcell G5
|
|
|
|
|
mx D6 inst_CLK_000_D0 mcell B9 mx D23 inst_CLK_000_NE mcell G2
|
|
|
|
|
mx D7inst_DS_000_ENABLE mcell C8 mx D24 ... ...
|
|
|
|
|
mx D8 RST_DLY_2_ mcell D7 mx D25 ... ...
|
|
|
|
|
mx D9 RST_DLY_0_ mcell D3 mx D26 RN_VMA mcell D0
|
|
|
|
|
mx D10inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell B13 mx D27 ... ...
|
|
|
|
|
mx D11CLK_000_N_SYNC_4_ mcell B6 mx D28inst_LDS_000_INT mcell A5
|
|
|
|
|
mx D12 inst_RESET_OUT mcell D9 mx D29 cpu_est_2_ mcell D13
|
|
|
|
|
mx D13 ... ... mx D30inst_nEXP_SPACE_D0reg mcell A8
|
|
|
|
|
mx D14 ... ... mx D31 IPL_1_ pin 56
|
|
|
|
|
mx D15 inst_VPA_D mcell F2 mx D32 ... ...
|
|
|
|
|
mx D16 cpu_est_0_ mcell D6
|
2016-01-24 19:26:06 +00:00
|
|
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BLOCK_E_LOGIC_ARRAY_FANIN
|
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
CSM Signal Source CSM Signal Source
|
|
|
|
|
------------------------------------ ------------------------------------
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx E0 RN_BGACK_030 mcell H4 mx E17 A_26_ pin 17
|
|
|
|
|
mx E1 A_31_ pin 4 mx E18 A_23_ pin 85
|
|
|
|
|
mx E2 AS_000 pin 42 mx E19 A_30_ pin 5
|
|
|
|
|
mx E3 A_25_ pin 18 mx E20 FC_1_ pin 58
|
|
|
|
|
mx E4 BGACK_000 pin 28 mx E21 A_27_ pin 16
|
|
|
|
|
mx E5 A_24_ pin 19 mx E22 inst_AS_000_INT mcell C1
|
|
|
|
|
mx E6 inst_CLK_000_D0 mcell B9 mx E23 ... ...
|
2016-01-24 19:26:06 +00:00
|
|
|
|
mx E7 A_28_ pin 15 mx E24 FC_0_ pin 57
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx E8CLK_000_P_SYNC_2_ mcell G7 mx E25 inst_RESET_OUT mcell D9
|
|
|
|
|
mx E9 A_22_ pin 84 mx E26 A_16_ pin 96
|
|
|
|
|
mx E10 inst_AS_030_D0 mcell H3 mx E27 A_17_ pin 59
|
|
|
|
|
mx E11 FPU_SENSE pin 91 mx E28 RW_000 pin 80
|
|
|
|
|
mx E12 A_19_ pin 97 mx E29 A_20_ pin 93
|
|
|
|
|
mx E13 A_29_ pin 6 mx E30inst_nEXP_SPACE_D0reg mcell A8
|
|
|
|
|
mx E14 CIIN_0 mcell E5 mx E31 A_18_ pin 95
|
2016-01-24 19:26:06 +00:00
|
|
|
|
mx E15 A_21_ pin 94 mx E32 AS_030 pin 82
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx E16 inst_CLK_000_D1 mcell E8
|
2016-01-24 19:26:06 +00:00
|
|
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BLOCK_F_LOGIC_ARRAY_FANIN
|
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
CSM Signal Source CSM Signal Source
|
|
|
|
|
------------------------------------ ------------------------------------
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx F0 RST pin 86 mx F17 cpu_est_3_ mcell F12
|
|
|
|
|
mx F1 BERR pin 41 mx F18 SM_AMIGA_4_ mcell F9
|
|
|
|
|
mx F2 SM_AMIGA_2_ mcell F10 mx F19 inst_DTACK_D0 mcell B15
|
|
|
|
|
mx F3inst_nEXP_SPACE_D0reg mcell A8 mx F20inst_CLK_000_NE_D0 mcell D10
|
|
|
|
|
mx F4 inst_CLK_000_NE mcell G2 mx F21 cpu_est_2_ mcell D13
|
|
|
|
|
mx F5CLK_000_N_SYNC_6_ mcell G6 mx F22 inst_CLK_000_PE mcell G5
|
|
|
|
|
mx F6inst_CLK_OUT_PRE_50 mcell F13 mx F23 ... ...
|
|
|
|
|
mx F7 ... ... mx F24 N_317_i mcell F14
|
|
|
|
|
mx F8 inst_CLK_000_D1 mcell E8 mx F25 SM_AMIGA_i_7_ mcell F0
|
|
|
|
|
mx F9 inst_VPA_D mcell F2 mx F26 RN_VMA mcell D0
|
|
|
|
|
mx F10 SM_AMIGA_6_ mcell F4 mx F27 ... ...
|
|
|
|
|
mx F11 SM_AMIGA_3_ mcell F6 mx F28 ... ...
|
|
|
|
|
mx F12 ... ... mx F29inst_AS_030_000_SYNC mcell C4
|
|
|
|
|
mx F13 VPA pin 36 mx F30 cpu_est_0_ mcell D6
|
|
|
|
|
mx F14 SM_AMIGA_1_ mcell F5 mx F31 inst_CLK_000_D0 mcell B9
|
|
|
|
|
mx F15 SM_AMIGA_0_ mcell F1 mx F32 SM_AMIGA_5_ mcell F8
|
|
|
|
|
mx F16 cpu_est_1_ mcell D2
|
2016-01-24 19:26:06 +00:00
|
|
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BLOCK_G_LOGIC_ARRAY_FANIN
|
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
CSM Signal Source CSM Signal Source
|
|
|
|
|
------------------------------------ ------------------------------------
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx G0 IPL_0_ pin 67 mx G17 RN_RW mcell G0
|
|
|
|
|
mx G1CLK_000_P_SYNC_1_ mcell B7 mx G18inst_nEXP_SPACE_D0reg mcell A8
|
|
|
|
|
mx G2CLK_000_P_SYNC_9_ mcell G15 mx G19CLK_000_P_SYNC_7_ mcell B3
|
|
|
|
|
mx G3CLK_000_N_SYNC_5_ mcell D11 mx G20 RN_BGACK_030 mcell H4
|
|
|
|
|
mx G4 ... ... mx G21 RST pin 86
|
|
|
|
|
mx G5CLK_000_P_SYNC_4_ mcell G3 mx G22CLK_000_P_SYNC_8_ mcell G10
|
|
|
|
|
mx G6 RW_000 pin 80 mx G23 ... ...
|
|
|
|
|
mx G7CLK_000_N_SYNC_11_ mcell H6 mx G24 LDS_000 pin 31
|
|
|
|
|
mx G8 UDS_000 pin 32 mx G25 inst_RESET_OUT mcell D9
|
|
|
|
|
mx G9 SIZE_DMA_0_ mcell G13 mx G26 ... ...
|
|
|
|
|
mx G10 RN_A0 mcell G8 mx G27 ... ...
|
|
|
|
|
mx G11 ... ... mx G28inst_BGACK_030_INT_D mcell H13
|
|
|
|
|
mx G12 SIZE_DMA_1_ mcell G9 mx G29 cpu_est_2_ mcell D13
|
|
|
|
|
mx G13CLK_000_P_SYNC_3_ mcell E13 mx G30 ... ...
|
|
|
|
|
mx G14 ... ... mx G31 cpu_est_3_ mcell F12
|
|
|
|
|
mx G15inst_CLK_OUT_PRE_D mcell A12 mx G32 ... ...
|
|
|
|
|
mx G16 cpu_est_1_ mcell D2
|
2016-01-24 19:26:06 +00:00
|
|
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BLOCK_H_LOGIC_ARRAY_FANIN
|
|
|
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
|
CSM Signal Source CSM Signal Source
|
|
|
|
|
------------------------------------ ------------------------------------
|
2016-01-25 17:02:53 +00:00
|
|
|
|
mx H0 RN_BGACK_030 mcell H4 mx H17 A_18_ pin 95
|
|
|
|
|
mx H1 BERR pin 41 mx H18 inst_AS_030_D0 mcell H3
|
|
|
|
|
mx H2 SM_AMIGA_5_ mcell F8 mx H19 FPU_SENSE pin 91
|
|
|
|
|
mx H3inst_nEXP_SPACE_D0reg mcell A8 mx H20 CLK_030 pin 64
|
|
|
|
|
mx H4 BGACK_000 pin 28 mx H21 RST pin 86
|
|
|
|
|
mx H5 SM_AMIGA_i_7_ mcell F0 mx H22 inst_CLK_000_PE mcell G5
|
|
|
|
|
mx H6 FC_0_ pin 57 mx H23 RN_RW_000 mcell H0
|
|
|
|
|
mx H7 inst_RESET_OUT mcell D9 mx H24inst_CLK_OUT_PRE_D mcell A12
|
|
|
|
|
mx H8 RW pin 71 mx H25 SIZE_DMA_0_ mcell G13
|
|
|
|
|
mx H9 inst_AS_000_DMA mcell A1 mx H26 A_16_ pin 96
|
|
|
|
|
mx H10 SIZE_DMA_1_ mcell G9 mx H27 A_19_ pin 97
|
|
|
|
|
mx H11 RN_DSACK1 mcell H9 mx H28CLK_000_N_SYNC_10_ mcell H2
|
|
|
|
|
mx H12 FC_1_ pin 58 mx H29 ... ...
|
|
|
|
|
mx H13 A_17_ pin 59 mx H30 SM_AMIGA_0_ mcell F1
|
|
|
|
|
mx H14 SM_AMIGA_1_ mcell F5 mx H31 ... ...
|
|
|
|
|
mx H15CLK_000_N_SYNC_9_ mcell A6 mx H32 AS_030 pin 82
|
2016-01-24 19:26:06 +00:00
|
|
|
|
mx H16 AS_000 pin 42
|
|
|
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
<Note> CSM indicates the mux inputs from the Central Switch Matrix.
|
|
|
|
|
<Note> Source indicates where the signal comes from (pin or macrocell).
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PostFit_Equations
|
|
|
|
|
~~~~~~~~~~~~~~~~~
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P-Terms Fan-in Fan-out Type Name (attributes)
|
|
|
|
|
--------- ------ ------- ---- -----------------
|
|
|
|
|
1 2 1 Pin SIZE_1_
|
|
|
|
|
1 2 1 Pin SIZE_1_.OE
|
|
|
|
|
1 2 1 Pin AS_030-
|
|
|
|
|
1 3 1 Pin AS_030.OE
|
|
|
|
|
1 2 1 Pin AS_000-
|
|
|
|
|
1 2 1 Pin AS_000.OE
|
|
|
|
|
1 2 1 Pin DS_030-
|
|
|
|
|
1 3 1 Pin DS_030.OE
|
|
|
|
|
1 2 1 Pin UDS_000-
|
|
|
|
|
1 2 1 Pin UDS_000.OE
|
|
|
|
|
1 2 1 Pin LDS_000-
|
|
|
|
|
1 2 1 Pin LDS_000.OE
|
|
|
|
|
0 0 1 Pin BERR
|
|
|
|
|
1 9 1 Pin BERR.OE
|
2016-01-25 17:02:53 +00:00
|
|
|
|
1 1 1 Pin CLK_DIV_OUT.D
|
|
|
|
|
1 1 1 Pin CLK_DIV_OUT.C
|
2016-01-24 19:26:06 +00:00
|
|
|
|
1 9 1 Pin FPU_CS-
|
|
|
|
|
1 0 1 Pin AVEC
|
|
|
|
|
2 3 1 Pin E
|
|
|
|
|
0 0 1 Pin RESET
|
|
|
|
|
1 1 1 Pin RESET.OE
|
|
|
|
|
0 0 1 Pin AMIGA_ADDR_ENABLE
|
|
|
|
|
1 2 1 Pin SIZE_0_
|
|
|
|
|
1 2 1 Pin SIZE_0_.OE
|
2016-01-25 17:02:53 +00:00
|
|
|
|
2 4 1 Pin AMIGA_BUS_DATA_DIR
|
2016-01-24 19:26:06 +00:00
|
|
|
|
1 2 1 Pin AMIGA_BUS_ENABLE_LOW-
|
|
|
|
|
2 3 1 Pin AMIGA_BUS_ENABLE_HIGH
|
|
|
|
|
1 13 1 Pin CIIN
|
|
|
|
|
1 1 1 Pin CIIN.OE
|
|
|
|
|
10 8 1 Pin IPL_030_2_.D-
|
|
|
|
|
1 1 1 Pin IPL_030_2_.C
|
|
|
|
|
10 8 1 Pin IPL_030_1_.D-
|
|
|
|
|
1 1 1 Pin IPL_030_1_.C
|
|
|
|
|
10 8 1 Pin IPL_030_0_.D-
|
|
|
|
|
1 1 1 Pin IPL_030_0_.C
|
|
|
|
|
1 2 1 Pin RW_000.OE
|
|
|
|
|
3 7 1 Pin RW_000.D-
|
|
|
|
|
1 1 1 Pin RW_000.C
|
|
|
|
|
1 3 1 Pin A0.OE
|
|
|
|
|
3 5 1 Pin A0.D
|
|
|
|
|
1 1 1 Pin A0.C
|
|
|
|
|
2 6 1 Pin BG_000.D-
|
|
|
|
|
1 1 1 Pin BG_000.C
|
|
|
|
|
3 5 1 Pin BGACK_030.D
|
|
|
|
|
1 1 1 Pin BGACK_030.C
|
2016-01-25 17:02:53 +00:00
|
|
|
|
1 1 1 Pin CLK_EXP.D
|
|
|
|
|
1 1 1 Pin CLK_EXP.C
|
2016-01-24 19:26:06 +00:00
|
|
|
|
1 1 1 Pin DSACK1.OE
|
|
|
|
|
4 9 1 Pin DSACK1.D-
|
|
|
|
|
1 1 1 Pin DSACK1.C
|
|
|
|
|
3 9 1 Pin VMA.T
|
|
|
|
|
1 1 1 Pin VMA.C
|
|
|
|
|
1 2 1 Pin RW.OE
|
|
|
|
|
2 5 1 Pin RW.D-
|
|
|
|
|
1 1 1 Pin RW.C
|
2016-01-25 17:02:53 +00:00
|
|
|
|
4 11 1 Node N_317_i-
|
2016-01-24 19:26:06 +00:00
|
|
|
|
4 4 1 Node cpu_est_2_.D
|
|
|
|
|
1 1 1 Node cpu_est_2_.C
|
|
|
|
|
3 5 1 Node cpu_est_3_.D
|
|
|
|
|
1 1 1 Node cpu_est_3_.C
|
2016-01-25 17:02:53 +00:00
|
|
|
|
2 2 1 Node cpu_est_0_.D
|
|
|
|
|
1 1 1 Node cpu_est_0_.C
|
|
|
|
|
3 4 1 Node cpu_est_1_.D
|
|
|
|
|
1 1 1 Node cpu_est_1_.C
|
2016-01-24 19:26:06 +00:00
|
|
|
|
2 5 1 Node inst_AS_000_INT.D-
|
|
|
|
|
1 1 1 Node inst_AS_000_INT.C
|
|
|
|
|
3 6 1 Node SM_AMIGA_5_.D
|
|
|
|
|
1 1 1 Node SM_AMIGA_5_.C
|
|
|
|
|
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
|
|
|
|
|
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C
|
|
|
|
|
1 2 1 Node inst_AS_030_D0.D-
|
|
|
|
|
1 1 1 Node inst_AS_030_D0.C
|
|
|
|
|
1 2 1 Node inst_nEXP_SPACE_D0reg.D-
|
|
|
|
|
1 1 1 Node inst_nEXP_SPACE_D0reg.C
|
|
|
|
|
7 14 1 Node inst_AS_030_000_SYNC.D-
|
|
|
|
|
1 1 1 Node inst_AS_030_000_SYNC.C
|
|
|
|
|
1 2 1 Node inst_BGACK_030_INT_D.D-
|
|
|
|
|
1 1 1 Node inst_BGACK_030_INT_D.C
|
|
|
|
|
7 9 1 Node inst_AS_000_DMA.D
|
|
|
|
|
1 1 1 Node inst_AS_000_DMA.C
|
|
|
|
|
9 12 1 Node inst_DS_000_DMA.D
|
|
|
|
|
1 1 1 Node inst_DS_000_DMA.C
|
|
|
|
|
2 5 1 Node CYCLE_DMA_0_.D
|
|
|
|
|
1 1 1 Node CYCLE_DMA_0_.C
|
|
|
|
|
3 6 1 Node CYCLE_DMA_1_.D
|
|
|
|
|
1 1 1 Node CYCLE_DMA_1_.C
|
|
|
|
|
3 6 1 Node SIZE_DMA_0_.D-
|
|
|
|
|
1 1 1 Node SIZE_DMA_0_.C
|
|
|
|
|
3 6 1 Node SIZE_DMA_1_.D
|
|
|
|
|
1 1 1 Node SIZE_DMA_1_.C
|
|
|
|
|
1 2 1 Node inst_VPA_D.D-
|
|
|
|
|
1 1 1 Node inst_VPA_D.C
|
|
|
|
|
2 4 1 Node inst_UDS_000_INT.D-
|
|
|
|
|
1 1 1 Node inst_UDS_000_INT.C
|
|
|
|
|
3 6 1 Node inst_LDS_000_INT.D
|
|
|
|
|
1 1 1 Node inst_LDS_000_INT.C
|
|
|
|
|
1 1 1 Node inst_CLK_OUT_PRE_D.D
|
|
|
|
|
1 1 1 Node inst_CLK_OUT_PRE_D.C
|
|
|
|
|
1 2 1 Node inst_DTACK_D0.D-
|
|
|
|
|
1 1 1 Node inst_DTACK_D0.C
|
|
|
|
|
2 6 1 Node inst_RESET_OUT.D
|
|
|
|
|
1 1 1 Node inst_RESET_OUT.C
|
|
|
|
|
1 1 1 Node inst_CLK_OUT_PRE_50.D
|
|
|
|
|
1 1 1 Node inst_CLK_OUT_PRE_50.C
|
|
|
|
|
1 1 1 Node inst_CLK_000_D1.D
|
|
|
|
|
1 1 1 Node inst_CLK_000_D1.C
|
|
|
|
|
1 1 1 Node inst_CLK_000_D0.D
|
|
|
|
|
1 1 1 Node inst_CLK_000_D0.C
|
|
|
|
|
1 1 1 Node inst_CLK_000_PE.D
|
|
|
|
|
1 1 1 Node inst_CLK_000_PE.C
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_9_.D
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_9_.C
|
|
|
|
|
1 1 1 Node inst_CLK_000_NE.D
|
|
|
|
|
1 1 1 Node inst_CLK_000_NE.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_11_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_11_.C
|
|
|
|
|
1 2 1 Node IPL_D0_0_.D-
|
|
|
|
|
1 1 1 Node IPL_D0_0_.C
|
|
|
|
|
1 2 1 Node IPL_D0_1_.D-
|
|
|
|
|
1 1 1 Node IPL_D0_1_.C
|
|
|
|
|
1 2 1 Node IPL_D0_2_.D-
|
|
|
|
|
1 1 1 Node IPL_D0_2_.C
|
|
|
|
|
1 1 1 Node inst_CLK_000_NE_D0.D
|
|
|
|
|
1 1 1 Node inst_CLK_000_NE_D0.C
|
|
|
|
|
2 6 1 Node SM_AMIGA_0_.D
|
|
|
|
|
1 1 1 Node SM_AMIGA_0_.C
|
|
|
|
|
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
|
|
|
|
|
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
|
|
|
|
|
3 6 1 Node SM_AMIGA_4_.D
|
|
|
|
|
1 1 1 Node SM_AMIGA_4_.C
|
|
|
|
|
5 11 1 Node inst_DS_000_ENABLE.D
|
|
|
|
|
1 1 1 Node inst_DS_000_ENABLE.C
|
|
|
|
|
3 5 1 Node RST_DLY_0_.D
|
|
|
|
|
1 1 1 Node RST_DLY_0_.C
|
|
|
|
|
4 5 1 Node RST_DLY_1_.D
|
|
|
|
|
1 1 1 Node RST_DLY_1_.C
|
|
|
|
|
2 5 1 Node RST_DLY_2_.D
|
|
|
|
|
1 1 1 Node RST_DLY_2_.C
|
|
|
|
|
1 2 1 Node CLK_000_P_SYNC_0_.D
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_0_.C
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_1_.D
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_1_.C
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_2_.D
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_2_.C
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_3_.D
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_3_.C
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_4_.D
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_4_.C
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_5_.D
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_5_.C
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_6_.D
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_6_.C
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_7_.D
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_7_.C
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_8_.D
|
|
|
|
|
1 1 1 Node CLK_000_P_SYNC_8_.C
|
|
|
|
|
1 2 1 Node CLK_000_N_SYNC_0_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_0_.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_1_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_1_.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_2_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_2_.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_3_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_3_.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_4_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_4_.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_5_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_5_.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_6_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_6_.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_7_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_7_.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_8_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_8_.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_9_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_9_.C
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_10_.D
|
|
|
|
|
1 1 1 Node CLK_000_N_SYNC_10_.C
|
|
|
|
|
3 9 1 Node SM_AMIGA_6_.D
|
|
|
|
|
1 1 1 Node SM_AMIGA_6_.C
|
|
|
|
|
8 10 1 Node inst_CLK_030_H.D
|
|
|
|
|
1 1 1 Node inst_CLK_030_H.C
|
|
|
|
|
3 6 1 Node SM_AMIGA_1_.D
|
|
|
|
|
1 1 1 Node SM_AMIGA_1_.C
|
|
|
|
|
5 13 1 Node SM_AMIGA_3_.T
|
|
|
|
|
1 1 1 Node SM_AMIGA_3_.C
|
|
|
|
|
4 13 1 Node SM_AMIGA_2_.D
|
|
|
|
|
1 1 1 Node SM_AMIGA_2_.C
|
|
|
|
|
14 20 1 Node SM_AMIGA_i_7_.D
|
|
|
|
|
1 1 1 Node SM_AMIGA_i_7_.C
|
|
|
|
|
2 14 1 Node CIIN_0
|
|
|
|
|
=========
|
2016-01-25 17:02:53 +00:00
|
|
|
|
323 P-Term Total: 323
|
2016-01-24 19:26:06 +00:00
|
|
|
|
Total Pins: 61
|
2016-01-25 17:02:53 +00:00
|
|
|
|
Total Nodes: 69
|
2016-01-24 19:26:06 +00:00
|
|
|
|
Average P-Term/Output: 2
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Equations:
|
|
|
|
|
|
|
|
|
|
SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
|
|
|
|
|
|
|
|
|
|
SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
|
|
|
|
|
|
|
|
|
|
!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
|
|
|
|
|
|
|
|
|
|
AS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
|
|
|
|
|
|
|
|
|
|
!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
|
|
|
|
|
|
|
|
|
|
AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
|
|
|
|
|
|
|
|
|
|
!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
|
|
|
|
|
|
|
|
|
|
DS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
|
|
|
|
|
|
|
|
|
|
!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q);
|
|
|
|
|
|
|
|
|
|
UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
|
|
|
|
|
|
|
|
|
|
!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
|
|
|
|
|
|
|
|
|
|
LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
|
|
|
|
|
|
|
|
|
|
BERR = (0);
|
|
|
|
|
|
|
|
|
|
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
|
|
|
|
|
|
2016-01-25 17:02:53 +00:00
|
|
|
|
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
|
|
|
|
|
|
|
|
|
|
CLK_DIV_OUT.C = (CLK_OSZI);
|
2016-01-24 19:26:06 +00:00
|
|
|
|
|
|
|
|
|
!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
|
|
|
|
|
|
|
|
|
|
AVEC = (1);
|
|
|
|
|
|
2016-01-25 17:02:53 +00:00
|
|
|
|
E = (cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_1_.Q
|
|
|
|
|
# !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_1_.Q);
|
2016-01-24 19:26:06 +00:00
|
|
|
|
|
|
|
|
|
RESET = (0);
|
|
|
|
|
|
|
|
|
|
RESET.OE = (!inst_RESET_OUT.Q);
|
|
|
|
|
|
|
|
|
|
AMIGA_ADDR_ENABLE = (0);
|
|
|
|
|
|
|
|
|
|
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
|
|
|
|
|
|
|
|
|
|
SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
|
|
|
|
|
|
2016-01-25 17:02:53 +00:00
|
|
|
|
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
|
|
|
|
|
# !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN);
|
|
|
|
|
|
2016-01-24 19:26:06 +00:00
|
|
|
|
!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
|
|
|
|
|
|
|
|
|
|
AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q
|
|
|
|
|
# BGACK_030.Q & !SM_AMIGA_i_7_.Q);
|
|
|
|
|
|
|
|
|
|
CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
|
|
|
|
|
|
|
|
|
|
CIIN.OE = (CIIN_0);
|
|
|
|
|
|
|
|
|
|
!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
|
|
|
|
|
# RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
|
|
|
|
|
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
|
|
|
|
|
# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q
|
|
|
|
|
# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q
|
|
|
|
|
# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q
|
|
|
|
|
# !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
|
|
|
|
|
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
|
|
|
|
|
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
|
|
|
|
|
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
|
|
|
|
|
|
|
|
|
|
IPL_030_2_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
|
|
|
|
|
# RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
|
|
|
|
|
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
|
|
|
|
|
# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q
|
|
|
|
|
# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q
|
|
|
|
|
# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q
|
|
|
|
|
# IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
|
|
|
|
|
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
|
|
|
|
|
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
|
|
|
|
|
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
|
|
|
|
|
|
|
|
|
|
IPL_030_1_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q
|
|
|
|
|
# RST & !IPL_D0_0_.Q & !IPL_030_0_.Q
|
|
|
|
|
# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q
|
|
|
|
|
# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q
|
|
|
|
|
# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q
|
|
|
|
|
# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q
|
|
|
|
|
# IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q
|
|
|
|
|
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
|
|
|
|
|
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
|
|
|
|
|
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
|
|
|
|
|
|
|
|
|
|
IPL_030_0_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
|
|
|
|
|
|
|
|
|
|
!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN
|
|
|
|
|
# RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
|
|
|
|
|
# RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q);
|
|
|
|
|
|
|
|
|
|
RW_000.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
A0.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
|
|
|
|
|
|
|
|
|
|
A0.D = (!RST
|
|
|
|
|
# !BGACK_030.Q & UDS_000.PIN
|
|
|
|
|
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q);
|
|
|
|
|
|
|
|
|
|
A0.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!BG_000.D = (!BG_030 & RST & !BG_000.Q
|
|
|
|
|
# !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q);
|
|
|
|
|
|
|
|
|
|
BG_000.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
BGACK_030.D = (!RST
|
|
|
|
|
# BGACK_000 & BGACK_030.Q
|
|
|
|
|
# BGACK_000 & inst_CLK_000_PE.Q & AS_000.PIN);
|
|
|
|
|
|
|
|
|
|
BGACK_030.C = (CLK_OSZI);
|
|
|
|
|
|
2016-01-25 17:02:53 +00:00
|
|
|
|
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
|
2016-01-24 19:26:06 +00:00
|
|
|
|
|
2016-01-25 17:02:53 +00:00
|
|
|
|
CLK_EXP.C = (CLK_OSZI);
|
2016-01-24 19:26:06 +00:00
|
|
|
|
|
|
|
|
|
DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q);
|
|
|
|
|
|
|
|
|
|
!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q
|
|
|
|
|
# !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
|
|
|
|
|
# RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
|
|
|
|
|
# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);
|
|
|
|
|
|
|
|
|
|
DSACK1.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
VMA.T = (!RST & !VMA.Q
|
2016-01-25 17:02:53 +00:00
|
|
|
|
# !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_PE.Q
|
|
|
|
|
# RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q);
|
2016-01-24 19:26:06 +00:00
|
|
|
|
|
|
|
|
|
VMA.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
|
|
|
|
|
|
|
|
|
|
!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
|
|
|
|
|
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
|
|
|
|
|
|
|
|
|
|
RW.C = (CLK_OSZI);
|
|
|
|
|
|
2016-01-25 17:02:53 +00:00
|
|
|
|
!N_317_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
|
|
|
|
# !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
|
|
|
|
# !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
|
|
|
|
# !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
|
|
|
|
|
|
|
|
|
|
cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q
|
|
|
|
|
# cpu_est_2_.Q & !cpu_est_1_.Q
|
|
|
|
|
# cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q
|
|
|
|
|
# !cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);
|
|
|
|
|
|
|
|
|
|
cpu_est_2_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
cpu_est_3_.D = (cpu_est_3_.Q & !inst_CLK_000_NE_D0.Q
|
|
|
|
|
# !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q
|
|
|
|
|
# cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);
|
|
|
|
|
|
|
|
|
|
cpu_est_3_.C = (CLK_OSZI);
|
|
|
|
|
|
2016-01-24 19:26:06 +00:00
|
|
|
|
cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
|
|
|
|
|
# cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q);
|
|
|
|
|
|
|
|
|
|
cpu_est_0_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q
|
|
|
|
|
# cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q
|
2016-01-25 17:02:53 +00:00
|
|
|
|
# !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);
|
2016-01-24 19:26:06 +00:00
|
|
|
|
|
|
|
|
|
cpu_est_1_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q
|
|
|
|
|
# RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
|
|
|
|
|
|
|
|
|
|
inst_AS_000_INT.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q
|
|
|
|
|
# RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN
|
|
|
|
|
# RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN);
|
|
|
|
|
|
|
|
|
|
SM_AMIGA_5_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q
|
|
|
|
|
# RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q);
|
|
|
|
|
|
|
|
|
|
inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!inst_AS_030_D0.D = (RST & !AS_030.PIN);
|
|
|
|
|
|
|
|
|
|
inst_AS_030_D0.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST);
|
|
|
|
|
|
|
|
|
|
inst_nEXP_SPACE_D0reg.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN
|
|
|
|
|
# !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
|
|
|
|
# RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
|
|
|
|
# RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
|
|
|
|
# RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
|
|
|
|
# RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
|
|
|
|
# RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);
|
|
|
|
|
|
|
|
|
|
inst_AS_030_000_SYNC.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q);
|
|
|
|
|
|
|
|
|
|
inst_BGACK_030_INT_D.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_AS_000_DMA.D = (!RST
|
|
|
|
|
# BGACK_030.Q
|
|
|
|
|
# AS_000.PIN
|
|
|
|
|
# !CLK_030 & inst_AS_000_DMA.Q
|
|
|
|
|
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
|
|
|
|
|
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
|
|
|
|
|
# UDS_000.PIN & LDS_000.PIN);
|
|
|
|
|
|
|
|
|
|
inst_AS_000_DMA.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_DS_000_DMA.D = (!RST
|
|
|
|
|
# BGACK_030.Q
|
|
|
|
|
# AS_000.PIN
|
|
|
|
|
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
|
|
|
|
|
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
|
|
|
|
|
# UDS_000.PIN & LDS_000.PIN
|
|
|
|
|
# !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN
|
|
|
|
|
# inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN
|
|
|
|
|
# CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN);
|
|
|
|
|
|
|
|
|
|
inst_DS_000_DMA.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN
|
|
|
|
|
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN);
|
|
|
|
|
|
|
|
|
|
CYCLE_DMA_0_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
|
|
|
|
|
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN
|
|
|
|
|
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN);
|
|
|
|
|
|
|
|
|
|
CYCLE_DMA_1_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q
|
|
|
|
|
# RST & BGACK_030.Q & !SIZE_DMA_0_.Q
|
|
|
|
|
# RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
|
|
|
|
|
|
|
|
|
|
SIZE_DMA_0_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
SIZE_DMA_1_.D = (!RST
|
|
|
|
|
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q
|
|
|
|
|
# !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
|
|
|
|
|
|
|
|
|
|
SIZE_DMA_1_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!inst_VPA_D.D = (!VPA & RST);
|
|
|
|
|
|
|
|
|
|
inst_VPA_D.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
|
|
|
|
|
# RST & SM_AMIGA_6_.Q & !A0.PIN);
|
|
|
|
|
|
|
|
|
|
inst_UDS_000_INT.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_LDS_000_INT.D = (!RST
|
|
|
|
|
# inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
|
|
|
|
|
# SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);
|
|
|
|
|
|
|
|
|
|
inst_LDS_000_INT.C = (CLK_OSZI);
|
|
|
|
|
|
2016-01-25 17:02:53 +00:00
|
|
|
|
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q);
|
2016-01-24 19:26:06 +00:00
|
|
|
|
|
|
|
|
|
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!inst_DTACK_D0.D = (!DTACK & RST);
|
|
|
|
|
|
|
|
|
|
inst_DTACK_D0.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q
|
|
|
|
|
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
|
|
|
|
|
|
|
|
|
|
inst_RESET_OUT.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
|
|
|
|
|
|
|
|
|
|
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
|
|
|
|
|
|
|
|
|
|
inst_CLK_000_D1.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_CLK_000_D0.D = (CLK_000);
|
|
|
|
|
|
|
|
|
|
inst_CLK_000_D0.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);
|
|
|
|
|
|
|
|
|
|
inst_CLK_000_PE.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
|
|
|
|
|
|
|
|
|
|
CLK_000_P_SYNC_9_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);
|
|
|
|
|
|
|
|
|
|
inst_CLK_000_NE.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);
|
|
|
|
|
|
|
|
|
|
CLK_000_N_SYNC_11_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!IPL_D0_0_.D = (RST & !IPL_0_);
|
|
|
|
|
|
|
|
|
|
IPL_D0_0_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!IPL_D0_1_.D = (RST & !IPL_1_);
|
|
|
|
|
|
|
|
|
|
IPL_D0_1_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!IPL_D0_2_.D = (!IPL_2_ & RST);
|
|
|
|
|
|
|
|
|
|
IPL_D0_2_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q);
|
|
|
|
|
|
|
|
|
|
inst_CLK_000_NE_D0.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q
|
|
|
|
|
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN);
|
|
|
|
|
|
|
|
|
|
SM_AMIGA_0_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q
|
|
|
|
|
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
|
|
|
|
|
|
|
|
|
|
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q
|
|
|
|
|
# RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q
|
|
|
|
|
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN);
|
|
|
|
|
|
|
|
|
|
SM_AMIGA_4_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
|
|
|
|
|
# RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q
|
|
|
|
|
# RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q
|
|
|
|
|
# RST & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN
|
|
|
|
|
# RST & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN);
|
|
|
|
|
|
|
|
|
|
inst_DS_000_ENABLE.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q
|
|
|
|
|
# RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q
|
|
|
|
|
# RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
|
|
|
|
|
|
|
|
|
|
RST_DLY_0_.C = (CLK_OSZI);
|
|
|
|
|
|
|
|
|
|
RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q
|
|
|
|
|
# RST & !RST_DLY_0_.Q & RST_DLY_1_.Q
|
|
|
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# RST & RST_DLY_1_.Q & RST_DLY_2_.Q
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# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q);
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RST_DLY_1_.C = (CLK_OSZI);
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RST_DLY_2_.D = (RST & RST_DLY_2_.Q
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# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q);
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RST_DLY_2_.C = (CLK_OSZI);
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CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q);
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CLK_000_P_SYNC_0_.C = (CLK_OSZI);
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CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);
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CLK_000_P_SYNC_1_.C = (CLK_OSZI);
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CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);
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CLK_000_P_SYNC_2_.C = (CLK_OSZI);
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CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);
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CLK_000_P_SYNC_3_.C = (CLK_OSZI);
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CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);
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CLK_000_P_SYNC_4_.C = (CLK_OSZI);
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CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);
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CLK_000_P_SYNC_5_.C = (CLK_OSZI);
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CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);
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CLK_000_P_SYNC_6_.C = (CLK_OSZI);
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CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);
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CLK_000_P_SYNC_7_.C = (CLK_OSZI);
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CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
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CLK_000_P_SYNC_8_.C = (CLK_OSZI);
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CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q);
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CLK_000_N_SYNC_0_.C = (CLK_OSZI);
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CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);
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CLK_000_N_SYNC_1_.C = (CLK_OSZI);
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CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q);
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CLK_000_N_SYNC_2_.C = (CLK_OSZI);
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CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q);
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CLK_000_N_SYNC_3_.C = (CLK_OSZI);
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CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);
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CLK_000_N_SYNC_4_.C = (CLK_OSZI);
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CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);
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CLK_000_N_SYNC_5_.C = (CLK_OSZI);
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CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q);
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CLK_000_N_SYNC_6_.C = (CLK_OSZI);
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CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q);
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CLK_000_N_SYNC_7_.C = (CLK_OSZI);
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CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q);
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CLK_000_N_SYNC_8_.C = (CLK_OSZI);
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CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q);
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CLK_000_N_SYNC_9_.C = (CLK_OSZI);
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CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);
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CLK_000_N_SYNC_10_.C = (CLK_OSZI);
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SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q
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# RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
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# RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q);
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SM_AMIGA_6_.C = (CLK_OSZI);
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inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
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# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
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# RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
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# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
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# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
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# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
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# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN
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# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN);
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inst_CLK_030_H.C = (CLK_OSZI);
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SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q
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# RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN
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# RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN);
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SM_AMIGA_1_.C = (CLK_OSZI);
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SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
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# SM_AMIGA_3_.Q & !BERR.PIN
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# RST & inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
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# inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q
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2016-01-25 17:02:53 +00:00
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# !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q);
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2016-01-24 19:26:06 +00:00
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SM_AMIGA_3_.C = (CLK_OSZI);
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SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q
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# RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN
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# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q
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2016-01-25 17:02:53 +00:00
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# RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q);
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2016-01-24 19:26:06 +00:00
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SM_AMIGA_2_.C = (CLK_OSZI);
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2016-01-25 17:02:53 +00:00
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SM_AMIGA_i_7_.D = (RST & N_317_i & !inst_CLK_000_PE.Q & BERR.PIN
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# RST & N_317_i & !SM_AMIGA_0_.Q & BERR.PIN
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# RST & N_317_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q
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# RST & N_317_i & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q
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# RST & N_317_i & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
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# RST & N_317_i & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
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# RST & N_317_i & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
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# RST & N_317_i & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
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# RST & N_317_i & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
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# RST & N_317_i & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q
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# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
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# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
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# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
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# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
|
2016-01-24 19:26:06 +00:00
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SM_AMIGA_i_7_.C = (CLK_OSZI);
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CIIN_0 = (inst_nEXP_SPACE_D0reg.Q
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# !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
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Reverse-Polarity Equations:
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