Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N:<ahref="@N:CD720:@XP_HELP">CD720</a> : <ahref="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1431550755> | Setting time resolution to ns
@N: : <ahref="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1431550755> | Top entity is set to BUS68030.
<fontcolor=#A52A2A>@W:<ahref="@W:CD638:@XP_HELP">CD638</a> : <ahref="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:7:126:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1431550755> | Signal clk_out_pre is undriven </font>
<fontcolor=#A52A2A>@W:<ahref="@W:CL265:@XP_HELP">CL265</a> : <ahref="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:135:61:135:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(135)</a><!@TM:1431550755> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
<fontcolor=#A52A2A>@W:<ahref="@W:CL271:@XP_HELP">CL271</a> : <ahref="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1431550755> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
<fontcolor=#A52A2A>@W:<ahref="@W:CL189:@XP_HELP">CL189</a> : <ahref="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1431550755> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
@N:<ahref="@N:CL201:@XP_HELP">CL201</a> : <ahref="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1431550755> | Trying to extract state machine for register SM_AMIGA
@N:<ahref="@N:CL201:@XP_HELP">CL201</a> : <ahref="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1431550755> | Trying to extract state machine for register cpu_est
<fontcolor=#A52A2A>@W:<ahref="@W:CL246:@XP_HELP">CL246</a> : <ahref="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1431550755> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
<aname=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
@N:<ahref="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1431550756> | Running in 64-bit mode.
<fontcolor=#A52A2A>@W:<ahref="@W:MO111:@XP_HELP">MO111</a> : <ahref="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:497:16:497:19:@W:MO111:@XP_MSG">68030-68000-bus.vhd(497)</a><!@TM:1431550756> | Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) </font>
@N:<ahref="@N:MO106:@XP_HELP">MO106</a> : <ahref="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:190:4:190:8:@N:MO106:@XP_MSG">68030-68000-bus.vhd(190)</a><!@TM:1431550756> | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
<fontcolor=#A52A2A>@W:<ahref="@W:BN132:@XP_HELP">BN132</a> : <ahref="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1431550756> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
@N:<ahref="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1431550756> | Timing Report not generated for this device, please use place and route tools for timing analysis.