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68030tk
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DMA Working

This commit is contained in:
MHeinrichs 2015-01-12 22:16:53 +01:00
parent a8cfe5adb5
commit 0b8d4d780d
20 changed files with 3174 additions and 75 deletions
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33
Logic/68030-68000-bus.vhd
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@ -440,17 +440,19 @@ begin
--dma stuff --dma stuff
--as can only be done if we know the uds/lds! --as can only be done if we know the uds/lds!
if(BGACK_030_INT='0' and AS_000='0' and (UDS_000='0' or LDS_000='0'))then if(BGACK_030_INT='0' and AS_000='0' and (UDS_000='0' or LDS_000='0'))then
RW_000_DMA <= RW_000;
--set AS_000 --set AS_000
if( CLK_030='1') then if( CLK_030='1') then
AS_000_DMA <= '0'; --sampled on rising edges! AS_000_DMA <= '0'; --sampled on rising edges!
RW_000_DMA <= RW_000; end if;
elsif(AS_000_DMA = '0' and CLK_030='0')then
--delayed clock for write cycle
if(AS_000_DMA = '0' and CLK_030='0')then
CLK_030_H <= '1'; CLK_030_H <= '1';
end if; end if;
if(RW_000='1') then if(RW_000='1') then
DS_000_DMA <=AS_000_DMA; DS_000_DMA <='0';
elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then
DS_000_DMA <=AS_000_DMA; -- write: one clock delayed! DS_000_DMA <=AS_000_DMA; -- write: one clock delayed!
end if; end if;
@ -475,7 +477,7 @@ begin
else else
AS_000_DMA <= '1'; AS_000_DMA <= '1';
DS_000_DMA <= '1'; DS_000_DMA <= '1';
SIZE_DMA <= "11"; SIZE_DMA <= "00";
A0_DMA <= '0'; A0_DMA <= '0';
RW_000_DMA <= '1'; RW_000_DMA <= '1';
CLK_030_H <= '0'; CLK_030_H <= '0';
@ -501,27 +503,28 @@ begin
AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ '0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE_D0 = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space '1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE_D0 = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND nEXP_SPACE_D0 = '0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space '0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
'0'; --Point towarts TK '0'; --Point towarts TK
--dma stuff --dma stuff
DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' OR AS_000_DMA ='1' else DTACK <= 'Z';
'0' when DSACK1 ='0' else --DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
'1'; -- '0' when DSACK1 ='0' else
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' OR AS_000_DMA ='1' else -- '1';
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
'0' when AS_000_DMA ='0' else '0' when AS_000_DMA ='0' else
'1'; '1';
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' OR AS_000_DMA ='1' else DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
'0' when DS_000_DMA ='0' else '0' when DS_000_DMA ='0' else
'1'; '1';
A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' OR AS_000_DMA ='1' else A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
'0' when A0_DMA ='0' else '0' when A0_DMA ='0' else
'1'; '1';
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' OR AS_000_DMA ='1' else SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
"10" when SIZE_DMA ="10" else "10" when SIZE_DMA ="10" else
"01" when SIZE_DMA ="01" else "01" when SIZE_DMA ="01" else
"11"; "00";
--fpu --fpu
FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0' FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0'

12
Logic/68030_TK.STY
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@ -1,10 +1,6 @@
[STRATEGY-LIST]
<<<<<<< HEAD
Normal=True, 1412327082
=======
Normal=True, 1385910337
[TOUCHED-REPORT]
Design.tt4File=1410033670
>>>>>>> parent of a42d9d7... More stability in constraints
[synthesis-type] [synthesis-type]
tool=Synplify tool=Synplify
[STRATEGY-LIST]
Normal=True, 1412327082
[TOUCHED-REPORT]
Design.tt4File=1421011839

2
Logic/68030_TK.cmi
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@ -2,7 +2,7 @@
MAIN_WINDOW_POSITION=0,185,1920,1200 MAIN_WINDOW_POSITION=0,185,1920,1200
LEFT_PANE_WIDTH=634 LEFT_PANE_WIDTH=634
CHILD_FRAME_STATE=Maximal CHILD_FRAME_STATE=Maximal
CHILD_WINDOW_SIZE=1920,790 CHILD_WINDOW_SIZE=1920,789
CHILD_WINDOW_POS=-8,-30 CHILD_WINDOW_POS=-8,-30
[GUI SETTING] [GUI SETTING]
Remember_Setting=1 Remember_Setting=1

4
Logic/68030_TK.lci
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@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision] [Revision]
Parent = m4a5.lci; Parent = m4a5.lci;
DATE = 09/06/2014; DATE = 01/11/2015;
TIME = 22:01:10; TIME = 22:30:39;
Source_Format = Pure_VHDL; Source_Format = Pure_VHDL;
Synthesis = Synplify; Synthesis = Synplify;

4
Logic/68030_TK.lct
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@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision] [Revision]
Parent = m4a5.lci; Parent = m4a5.lci;
DATE = 09/06/2014; DATE = 01/11/2015;
TIME = 22:01:10; TIME = 22:30:39;
Source_Format = Pure_VHDL; Source_Format = Pure_VHDL;
Synthesis = Synplify; Synthesis = Synplify;

1985
Logic/68030_TK.tcl
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File diff suppressed because it is too large Load Diff

1115
Logic/68030_tk - DMA-Working@50MHz.jed Normal file
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File diff suppressed because it is too large Load Diff

2
Logic/68030_tk.crf
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@ -1,7 +1,7 @@
// Signal Name Cross Reference File // Signal Name Cross Reference File
// ispLEVER Classic 1.7.00.05.28.13 // ispLEVER Classic 1.7.00.05.28.13
// Design '68030_tk' created Thu Oct 16 21:59:11 2014 // Design '68030_tk' created Mon Jan 12 22:00:38 2015
// LEGEND: '>' Functional Block Port Separator // LEGEND: '>' Functional Block Port Separator

2
Logic/68030_tk.ipr
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@ -1 +1 @@
<LATTICE_ENCRYPTED_BLIF>147:<15po'Cb <LATTICE_ENCRYPTED_BLIF>9265=57FG g

2
Logic/BUS68030.prj
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@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd. #-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Thu Oct 16 21:59:04 2014 #-- Written on Mon Jan 12 22:00:32 2015
#device options #device options

4
Logic/Programming.xcf
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@ -19,8 +19,8 @@
<BScanVal>0</BScanVal> <BScanVal>0</BScanVal>
</Bypass> </Bypass>
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File> <File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
<FileTime>10/16/14 21:59:16</FileTime> <FileTime>01/12/15 22:00:44</FileTime>
<JedecChecksum>0xC45A</JedecChecksum> <JedecChecksum>0x34AF</JedecChecksum>
<Operation>Erase,Program,Verify</Operation> <Operation>Erase,Program,Verify</Operation>
<Option> <Option>
<SVFVendor>JTAG STANDARD</SVFVendor> <SVFVendor>JTAG STANDARD</SVFVendor>

20
Logic/bus68030.srf
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@ -6,7 +6,7 @@
#Implementation: logic #Implementation: logic
$ Start of Compile $ Start of Compile
#Thu Oct 16 21:59:04 2014 #Mon Jan 12 22:00:32 2015
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode @N|Running in 64-bit mode
@ -46,7 +46,7 @@ State machine has 8 reachable states with original encodings of:
111 111
@END @END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Oct 16 21:59:04 2014 # Mon Jan 12 22:00:32 2015
###########################################################] ###########################################################]
Map & Optimize Report Map & Optimize Report
@ -70,16 +70,16 @@ original code -> new code
Resource Usage Report Resource Usage Report
Simple gate primitives: Simple gate primitives:
DFFRH 18 uses
DFFSH 28 uses DFFSH 28 uses
DFFRH 18 uses
DFF 34 uses DFF 34 uses
BI_DIR 13 uses BI_DIR 11 uses
IBUF 31 uses IBUF 32 uses
OBUF 16 uses OBUF 16 uses
BUFTH 1 use BUFTH 2 uses
AND2 238 uses AND2 237 uses
INV 181 uses INV 177 uses
OR2 22 uses OR2 21 uses
XOR2 9 uses XOR2 9 uses
@ -90,6 +90,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB) At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Oct 16 21:59:06 2014 # Mon Jan 12 22:00:34 2015
###########################################################] ###########################################################]

2
Logic/run_options.txt
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@ -1,7 +1,7 @@
#-- Synopsys, Inc. #-- Synopsys, Inc.
#-- Version G-2012.09LC-SP1 #-- Version G-2012.09LC-SP1
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Thu Oct 16 21:59:04 2014 #-- Written on Mon Jan 12 22:00:32 2015
#project files #project files

16
Logic/synlog/bus68030_fpga_mapper.srr
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@ -17,16 +17,16 @@ original code -> new code
Resource Usage Report Resource Usage Report
Simple gate primitives: Simple gate primitives:
DFFRH 18 uses
DFFSH 28 uses DFFSH 28 uses
DFFRH 18 uses
DFF 34 uses DFF 34 uses
BI_DIR 13 uses BI_DIR 11 uses
IBUF 31 uses IBUF 32 uses
OBUF 16 uses OBUF 16 uses
BUFTH 1 use BUFTH 2 uses
AND2 238 uses AND2 237 uses
INV 181 uses INV 177 uses
OR2 22 uses OR2 21 uses
XOR2 9 uses XOR2 9 uses
@ -37,6 +37,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB) At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Oct 16 21:59:06 2014 # Mon Jan 12 22:00:34 2015
###########################################################] ###########################################################]

2
Logic/synlog/report/BUS68030_compiler_runstatus.xml
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@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data> <data>-</data>
</info> </info>
<info name="Date &amp;Time"> <info name="Date &amp;Time">
<data type="timestamp">1413489544</data> <data type="timestamp">1421096432</data>
</info> </info>
</job_info> </job_info>
</job_run_status> </job_run_status>

2
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
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@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>96MB</data> <data>96MB</data>
</info> </info>
<info name="Date &amp; Time"> <info name="Date &amp; Time">
<data type="timestamp">1413489546</data> <data type="timestamp">1421096434</data>
</info> </info>
</job_info> </job_info>
</job_run_status> </job_run_status>

2
Logic/syntmp/run_option.xml
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@ -3,7 +3,7 @@
Synopsys, Inc. Synopsys, Inc.
Version G-2012.09LC-SP1 Version G-2012.09LC-SP1
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Thu Oct 16 21:59:04 2014 Written on Mon Jan 12 22:00:32 2015
--> -->

20
Logic/synwork/BUS68030_compiler.fdep
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@ -1,16 +1,16 @@
%%% protect protected_file %%% protect protected_file
#defaultlanguage:vhdl #defaultlanguage:vhdl
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-dfltencoding|sequential|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|on|-autosm|-ignore_undefined_lib|-lib|work" #OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-dfltencoding|sequential|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|on|-autosm|-ignore_undefined_lib|-lib|work"
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1363693660 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1363690060
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\location.map":1310460974 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1413489533 #CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1421096420
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list) # Dependency Lists (Uses list)

20
Logic/synwork/BUS68030_compiler.fdeporig
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@ -1,16 +1,16 @@
%%% protect protected_file %%% protect protected_file
#defaultlanguage:vhdl #defaultlanguage:vhdl
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-dfltencoding|sequential|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|on|-autosm|-ignore_undefined_lib|-lib|work" #OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-dfltencoding|sequential|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|on|-autosm|-ignore_undefined_lib|-lib|work"
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1363693660 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1363690060
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\location.map":1310460974 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1413489533 #CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1421096420
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list) # Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_compiler.srs
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