mirror of https://github.com/kr239/68030tk.git
Cleaned up
This commit is contained in:
MHeinrichs
parent
40e9ea0f2e
commit
a8cfe5adb5
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@ -1,58 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity clk_div_2by3 is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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clk_2by3 : out std_logic
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clk_1by3 : out std_logic);
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end clk_div_2by3;
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architecture clk_div_2by3_arch of clk_div_2by3 is
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signal clk_div_by3_pos : std_logic_vector(1 downto 0);
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signal clk_div_by3_neg : std_logic_vector(1 downto 0);
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begin -- behavior
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clk_2by3 <= (not clk_div_by3_neg(0) and clk_div_by3_pos(0)) or
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(clk_div_by3_neg(1) and clk_div_by3_pos(1));
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pos_edge: process (clk, rst_n)
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begin -- process posedge
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if rst_n = '0' then -- asynchronous reset (active low)
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clk_div_by3_pos <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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if clk_div_by3_pos = "10" then
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clk_div_by3_pos <= (others => '0');
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else
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clk_div_by3_pos <= clk_div_by3_pos + 1;
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end if;
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end if;
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end process pos_edge;
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neg_edge: process (clk, rst_n)
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begin -- process posedge
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if rst_n = '0' then -- asynchronous reset (active low)
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clk_div_by3_neg <= (others => '0');
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elsif clk'event and clk = '0' then -- rising clock edge
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if clk_div_by3_neg = "10" then
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clk_div_by3_neg <= (others => '0');
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else
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clk_div_by3_neg <= clk_div_by3_neg + 1;
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end if;
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end if;
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end process neg_edge;
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half_clk: process(clk_2by3, rst_n)
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begin
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if rst_n = '0' then -- asynchronous reset (active low)
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clk_1by3 <= '0';
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elsif rising_edge(clk_2by3) then -- rising clock edge
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clk_1by3 <= not clk_1by3;
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end if;
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end process half_clk;
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end clk_div_2by3_arch;
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@ -1,403 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity BUS68030 is
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port(
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AS_030: inout std_logic ;
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AS_000: inout std_logic ;
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-- DS_030: inout std_logic ;
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UDS_000: inout std_logic;
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LDS_000: inout std_logic;
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SIZE: inout std_logic_vector ( 1 downto 0 );
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A: inout std_logic_vector ( 31 downto 0 );
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CPU_SPACE: in std_logic ;
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-- BERR: inout std_logic ; --error: this is connected to a global input pin :(
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BG_030: in std_logic ;
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BG_000: out std_logic ;
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BGACK_030: out std_logic ;
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BGACK_000: in std_logic ;
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CLK_030: in std_logic ;
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CLK_000: in std_logic ;
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CLK_OSZI: in std_logic ;
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CLK_DIV_OUT: out std_logic ;
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CLK_EXP: out std_logic ;
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FPU_CS: out std_logic ;
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IPL_030: out std_logic_vector ( 2 downto 0 );
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IPL: in std_logic_vector ( 2 downto 0 );
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DSACK: inout std_logic_vector ( 1 downto 0 );
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DTACK: inout std_logic ;
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AVEC: out std_logic ;
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-- AVEC_EXP: inout std_logic ; --this is a "free pin"
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E: out std_logic ;
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VPA: in std_logic ;
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VMA: out std_logic ;
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RST: in std_logic ;
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RESET: out std_logic ;
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RW: in std_logic ;
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-- D: inout std_logic_vector ( 31 downto 28 );
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FC: in std_logic_vector ( 1 downto 0 );
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AMIGA_BUS_ENABLE: out std_logic ;
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AMIGA_BUS_DATA_DIR: out std_logic ;
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AMIGA_BUS_ENABLE_LOW: out std_logic;
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CIIN: out std_logic
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);
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end BUS68030;
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architecture Behavioral of BUS68030 is
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subtype ESTATE is std_logic_vector(3 downto 0);
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constant E1 : ESTATE := "0110";
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constant E2 : ESTATE := "0111";
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constant E3 : ESTATE := "0100";
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constant E4 : ESTATE := "0101";
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constant E5 : ESTATE := "0010";
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constant E6 : ESTATE := "0011";
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constant E7 : ESTATE := "1010";
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constant E8 : ESTATE := "1011";
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constant E9 : ESTATE := "1100";
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constant E10 : ESTATE := "1111";
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-- Illegal states
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constant E20 : ESTATE := "0000";
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constant E4a : ESTATE := "0001";
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constant E21 : ESTATE := "1000";
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constant E22 : ESTATE := "1001";
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constant E23 : ESTATE := "1101";
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constant E24 : ESTATE := "1110";
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signal cpu_est : ESTATE := E20;
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subtype AMIGA_STATE is std_logic_vector(1 downto 0);
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constant IDLE : AMIGA_STATE := "00";
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constant AS_SET : AMIGA_STATE := "01";
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constant DATA_FETCH : AMIGA_STATE := "10";
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constant END_CYCLE : AMIGA_STATE := "11";
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signal SM_AMIGA : AMIGA_STATE;
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signal SM_AMIGA_LAST : AMIGA_STATE;
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--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
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signal ZorroII:STD_LOGIC:= '0';
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signal AS_000_INT:STD_LOGIC:= '1';
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signal AS_000_INT_D:STD_LOGIC:= '1';
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signal BGACK_030_INT:STD_LOGIC:= '1';
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signal DTACK_DMA:STD_LOGIC:= '1';
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signal DTACK_INT:STD_LOGIC:= '1';
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signal DTACK_SYNC:STD_LOGIC:= '1';
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signal DTACK_SYNC_D:STD_LOGIC:= '1';
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signal DTACK_SYNC_DD:STD_LOGIC:= '1';
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signal FPU_CS_INT:STD_LOGIC:= '1';
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signal E_INT: STD_LOGIC:='1';
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signal VPA_SYNC: STD_LOGIC:='1';
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signal VMA_INT: STD_LOGIC:='1';
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signal VMA_INT_D: STD_LOGIC:='1';
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signal UDS_000_INT: STD_LOGIC:='1';
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signal LDS_000_INT: STD_LOGIC:='1';
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signal UDS_LOGIC: STD_LOGIC:='1';
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signal LDS_LOGIC: STD_LOGIC:='1';
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--signal AS_030_delay: STD_LOGIC:='1';
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signal AS_AMIGA_ENABLE: STD_LOGIC:='1';
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--signal DS_030_INT: STD_LOGIC:='Z';
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--signal A_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
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--signal SIZE_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
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signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
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signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
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signal CLK_OUT_INT: STD_LOGIC:='1';
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signal CLK_000_D: STD_LOGIC := '1';
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begin
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--clk generation : up to now just half the clock
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cpu_clk: process(CLK_OSZI)
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begin
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if(rising_edge(CLK_OSZI)) then
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if(CLK_CNT="10") then
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CLK_OUT_INT <= not CLK_OUT_INT;
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CLK_CNT <= "00";
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else
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CLK_CNT <= CLK_CNT+1;
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end if;
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end if;
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end process cpu_clk;
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CLK_DIV_OUT <= CLK_OUT_INT;
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CLK_EXP <= CLK_OUT_INT;
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clk_delay: process(CLK_OSZI)
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begin
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if(rising_edge(CLK_OSZI)) then
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CLK_000_D <= CLK_000;
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end if;
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end process clk_delay;
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--ZORROII (Amiga) space?
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ZorroII <= '1' when (A(31 downto 24)= x"00") else '0'; -- 24-bit addres space.
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--BG_ACK is simple:
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BGACK_030_gen: process (CLK_000,BGACK_000) begin
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if(BGACK_000='0') then
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BGACK_030_INT <= '0';
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elsif rising_edge(CLK_000) then
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BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
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end if;
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end process BGACK_030_gen;
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BGACK_030 <= BGACK_030_INT;
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--DTACK
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DTACK <= 'Z' when BGACK_030_INT ='1' else
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DTACK_DMA;
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DTACK_DMA <= '0' when AS_000_INT ='0' AND DSACK(1) ='0' else
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'1';
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--CO-Processor Chip select
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FPU_CS_INT <= '0' when FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='0'
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else '1';
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FPU_CS <= FPU_CS_INT;
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--if no copro is installed:
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-- BERR <= 'Z' when FPU_CS_INT ='1' else '0';
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--reset buffer
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RESET <= RST;
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--cache inhibit: For now: disable
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CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
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'1' WHEN A(31 downto 16) = x"00E0" ELSE
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'0';
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--bus buffers
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AMIGA_BUS_ENABLE <= '0'; --for now: allways on
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AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
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AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
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-- vma and e clock
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e_clk: process (CLK_000)
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begin
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if rising_edge(CLK_000) then
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-- next state.
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case (cpu_est) is
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when E1 => cpu_est <= E2 ;
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when E2 => cpu_est <= E3 ;
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when E3 => cpu_est <= E4;
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when E4 => cpu_est <= E5 ;
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when E5 => cpu_est <= E6 ;
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when E6 => cpu_est <= E7 ;
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when E7 => cpu_est <= E8 ;
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when E8 => cpu_est <= E9 ;
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when E9 => cpu_est <= E10;
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when E10 => cpu_est <= E1 ;
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-- Illegal states
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when E4a => cpu_est <= E5 ;
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when E20 => cpu_est <= E10;
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when E21 => cpu_est <= E10;
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when E22 => cpu_est <= E9 ;
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when E23 => cpu_est <= E9 ;
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when E24 => cpu_est <= E10;
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when others =>
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null;
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end case;
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end if;
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end process e_clk;
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vma_gen: process (CLK_000,AS_030) begin
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if(AS_030='1') then
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VMA_INT <= '1';
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VPA_SYNC <= '1';
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elsif falling_edge(CLK_000) then
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VPA_SYNC <= VPA;
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if(cpu_est = E3 AND VPA_SYNC = '0' AND AS_000_INT = '0') then
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VMA_INT <= '0'; -- low active !
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end if;
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if(cpu_est = E10) then
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VMA_INT <= '1';
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end if;
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end if;
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end process vma_gen;
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vma_delay: process(CLK_030)
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begin
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if(rising_edge(CLK_030)) then
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VMA_INT_D<=VMA_INT;
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end if;
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end process vma_delay;
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E_INT <= cpu_est(3);
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E <= E_INT;
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VMA <= VMA_INT AND VMA_INT_D;
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--AVEC
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--AVEC <= '0' WHEN VMA='1' AND cpu_est = E10 --
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-- ELSE '1';
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AVEC <= '1';
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--IPL: Buffer interrupts for a CPU-Cycle to avoid fake interupts
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ipl_amiga: process(CLK_000)
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begin
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if(rising_edge(CLK_000)) then
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IPL_030<=IPL;
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end if;
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end process ipl_amiga;
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--BG
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bg_amiga: process(CLK_030,BG_030)
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begin
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if(BG_030= '1')then
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BG_000 <= '1';
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elsif(falling_edge(CLK_030)) then
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if(SM_AMIGA = IDLE and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
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BG_000 <= '0';
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else
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BG_000 <='1';
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end if;
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end if;
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end process bg_amiga;
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--as uds/lds generation
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UDS_LOGIC <= '0' WHEN AS_030 = '0' AND A(0)='0' ELSE '1';
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LDS_LOGIC <= '0' WHEN AS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1') ELSE '1';
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as_amiga: process(AS_030, CLK_030)
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begin
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if(AS_030 = '1') then
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AS_000_INT <= '1';
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UDS_000_INT<= '1';
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LDS_000_INT<= '1';
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elsif(rising_edge(CLK_030)) then --as is sampled at rising edge on a 68020/030
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if ( AS_030 = '0' AND -- obviously as must be low
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CPU_SPACE = '0' AND -- expansion board not in action
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SM_AMIGA = IDLE AND -- last cycle completed
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AS_AMIGA_ENABLE = '1' --indicator ready
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AND CLK_000 = '1' --AND CLK_000_D = '1' -- as is sampled at falling edge on a 68000/010 thus it is set during high CLK_000
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) then
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AS_000_INT <= '0';
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if (RW='1') then --read: set udl/lds
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UDS_000_INT <= UDS_LOGIC;
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LDS_000_INT <= LDS_LOGIC;
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end if;
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elsif(RW='0' AND AS_000_INT_D='0')then --write: uds/lds have to wait for one 7m-clock later
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UDS_000_INT <= UDS_LOGIC;
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LDS_000_INT <= LDS_LOGIC;
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end if;
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end if;
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end process as_amiga;
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--helper signal for a delayed version of AS_000
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as_pe_amiga: process(AS_030, CLK_000)
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begin
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if(AS_030 ='1') then
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AS_000_INT_D <= '1';
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elsif(rising_edge(CLK_000)) then -- positive edge delayed AS_000
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AS_000_INT_D <= AS_000_INT;
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end if;
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end process as_pe_amiga;
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--state machine for amiga-cycle
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sm_amiga: process(RST, CLK_000)
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begin
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if(RST='0') then
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SM_AMIGA <= IDLE;
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DTACK_INT<= '1';
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elsif(falling_edge(CLK_000)) then
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case (SM_AMIGA) is
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when IDLE =>
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if(AS_000_INT='0') then
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SM_AMIGA <= AS_SET;
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end if;
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when AS_SET =>
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if(VPA_SYNC = '1' AND DTACK_SYNC='0') then
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DTACK_INT<= '0';
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SM_AMIGA <= DATA_FETCH ;
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elsif(E10=cpu_est AND VPA_SYNC='0' AND VMA_INT='0') then --vpa/vma cycle
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DTACK_INT<= '0';
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SM_AMIGA <= DATA_FETCH ;
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end if;
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when DATA_FETCH => --here the data is written/read
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SM_AMIGA <= END_CYCLE;
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when END_CYCLE => -- internal DTACK is high here. end cycle!
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DTACK_INT<= '1';
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SM_AMIGA <= IDLE ;
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end case;
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end if;
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end process sm_amiga;
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--positive edge deleyed statemachine
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state_amiga_pe: process(CLK_000)
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begin
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if(rising_edge(CLK_000)) then --as is sampled at rising edge on a 68020/030
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SM_AMIGA_LAST <= SM_AMIGA;
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end if;
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end process state_amiga_pe;
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AS_000 <= 'Z' when BGACK_030_INT ='0' else
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AS_000_INT;
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UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
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UDS_000_INT;
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LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
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LDS_000_INT;
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--dsack generation
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dtack_sync: process(CLK_030)
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begin
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if(rising_edge(CLK_030)) then
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DTACK_SYNC <= DTACK; --for the AMIGA state machine
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DTACK_SYNC_D <= DTACK_SYNC;
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DTACK_SYNC_DD <= DTACK_SYNC_D;
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end if;
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end process dtack_sync;
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--dsack generation
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dsack_CPU: process(AS_030,CLK_030)
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begin
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if(AS_030 ='1') then
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DSACK_INT<="11";
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AS_AMIGA_ENABLE <='0';
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elsif(rising_edge(CLK_030)) then
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-- this is a indicator, that we have been in idle state
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-- this avoids that an "old" DTACK is used a second time in a new memory cycle
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if(SM_AMIGA = IDLE) then
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AS_AMIGA_ENABLE <= '1';
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end if;
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if(SM_AMIGA = END_CYCLE AND AS_AMIGA_ENABLE = '1') then
|
||||
DSACK_INT<="01";
|
||||
AS_AMIGA_ENABLE<='0';
|
||||
end if;
|
||||
end if;
|
||||
end process dsack_CPU;
|
||||
|
||||
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||
DSACK_INT;
|
||||
|
||||
-- signal assignment
|
||||
--DS_030 <= "ZZ";
|
||||
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- DS_030_INT;
|
||||
|
||||
--A(1) <= 'Z';
|
||||
--A(0) <= 'Z';
|
||||
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- A_INT;
|
||||
|
||||
--SIZE <= "ZZ";
|
||||
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- SIZE_INT;
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -1,402 +0,0 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity BUS68030 is
|
||||
|
||||
port(
|
||||
AS_030: inout std_logic ;
|
||||
AS_000: inout std_logic ;
|
||||
-- DS_030: inout std_logic ;
|
||||
UDS_000: inout std_logic;
|
||||
LDS_000: inout std_logic;
|
||||
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||
A: inout std_logic_vector ( 31 downto 0 );
|
||||
CPU_SPACE: in std_logic ;
|
||||
-- BERR: inout std_logic ; --error: this is connected to a global input pin :(
|
||||
BG_030: in std_logic ;
|
||||
BG_000: out std_logic ;
|
||||
BGACK_030: out std_logic ;
|
||||
BGACK_000: in std_logic ;
|
||||
CLK_030: in std_logic ;
|
||||
CLK_000: in std_logic ;
|
||||
CLK_OSZI: in std_logic ;
|
||||
CLK_DIV_OUT: out std_logic ;
|
||||
CLK_EXP: out std_logic ;
|
||||
FPU_CS: out std_logic ;
|
||||
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||
IPL: in std_logic_vector ( 2 downto 0 );
|
||||
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||
DTACK: inout std_logic ;
|
||||
AVEC: out std_logic ;
|
||||
-- AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||
E: out std_logic ;
|
||||
VPA: in std_logic ;
|
||||
VMA: out std_logic ;
|
||||
RST: in std_logic ;
|
||||
RESET: out std_logic ;
|
||||
RW: in std_logic ;
|
||||
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||
FC: in std_logic_vector ( 1 downto 0 );
|
||||
AMIGA_BUS_ENABLE: out std_logic ;
|
||||
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||
CIIN: out std_logic
|
||||
);
|
||||
end BUS68030;
|
||||
|
||||
architecture Behavioral of BUS68030 is
|
||||
|
||||
|
||||
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||
|
||||
constant E1 : ESTATE := "0110";
|
||||
constant E2 : ESTATE := "0111";
|
||||
constant E3 : ESTATE := "0100";
|
||||
constant E4 : ESTATE := "0101";
|
||||
constant E5 : ESTATE := "0010";
|
||||
constant E6 : ESTATE := "0011";
|
||||
constant E7 : ESTATE := "1010";
|
||||
constant E8 : ESTATE := "1011";
|
||||
constant E9 : ESTATE := "1100";
|
||||
constant E10 : ESTATE := "1111";
|
||||
-- Illegal states
|
||||
constant E20 : ESTATE := "0000";
|
||||
constant E4a : ESTATE := "0001";
|
||||
constant E21 : ESTATE := "1000";
|
||||
constant E22 : ESTATE := "1001";
|
||||
constant E23 : ESTATE := "1101";
|
||||
constant E24 : ESTATE := "1110";
|
||||
|
||||
signal cpu_est : ESTATE := E20;
|
||||
|
||||
subtype AMIGA_STATE is std_logic_vector(1 downto 0);
|
||||
|
||||
constant IDLE : AMIGA_STATE := "00";
|
||||
constant AS_SET : AMIGA_STATE := "01";
|
||||
constant DATA_FETCH : AMIGA_STATE := "10";
|
||||
constant END_CYCLE : AMIGA_STATE := "11";
|
||||
|
||||
signal SM_AMIGA : AMIGA_STATE;
|
||||
signal SM_AMIGA_LAST : AMIGA_STATE;
|
||||
|
||||
|
||||
|
||||
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
signal ZorroII:STD_LOGIC:= '0';
|
||||
signal AS_000_INT:STD_LOGIC:= '1';
|
||||
signal AS_000_INT_D:STD_LOGIC:= '1';
|
||||
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||
signal DTACK_INT:STD_LOGIC:= '1';
|
||||
signal DTACK_SYNC:STD_LOGIC:= '1';
|
||||
signal DTACK_SYNC_D:STD_LOGIC:= '1';
|
||||
signal DTACK_SYNC_DD:STD_LOGIC:= '1';
|
||||
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||
signal E_INT: STD_LOGIC:='1';
|
||||
signal VPA_SYNC: STD_LOGIC:='1';
|
||||
signal VMA_INT: STD_LOGIC:='1';
|
||||
signal VMA_INT_D: STD_LOGIC:='1';
|
||||
signal UDS_000_INT: STD_LOGIC:='1';
|
||||
signal LDS_000_INT: STD_LOGIC:='1';
|
||||
signal UDS_LOGIC: STD_LOGIC:='1';
|
||||
signal LDS_LOGIC: STD_LOGIC:='1';
|
||||
--signal AS_030_delay: STD_LOGIC:='1';
|
||||
signal AS_AMIGA_ENABLE: STD_LOGIC:='1';
|
||||
--signal DS_030_INT: STD_LOGIC:='Z';
|
||||
--signal A_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
--signal SIZE_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||
signal CLK_000_D: STD_LOGIC := '1';
|
||||
|
||||
begin
|
||||
|
||||
--clk generation : up to now just half the clock
|
||||
cpu_clk: process(CLK_OSZI)
|
||||
begin
|
||||
if(rising_edge(CLK_OSZI)) then
|
||||
|
||||
if(CLK_CNT="00") then
|
||||
CLK_OUT_INT <= not CLK_OUT_INT;
|
||||
CLK_CNT <= "00";
|
||||
else
|
||||
CLK_CNT <= CLK_CNT+1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process cpu_clk;
|
||||
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||
CLK_EXP <= CLK_OUT_INT;
|
||||
|
||||
|
||||
clk_delay: process(CLK_OSZI)
|
||||
begin
|
||||
if(rising_edge(CLK_OSZI)) then
|
||||
CLK_000_D <= CLK_000;
|
||||
end if;
|
||||
|
||||
end process clk_delay;
|
||||
|
||||
--ZORROII (Amiga) space?
|
||||
ZorroII <= '1' when (A(31 downto 24)= x"00") else '0'; -- 24-bit addres space.
|
||||
|
||||
--BG_ACK is simple:
|
||||
BGACK_030_gen: process (CLK_000,BGACK_000) begin
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif rising_edge(CLK_000) then
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
end process BGACK_030_gen;
|
||||
BGACK_030 <= BGACK_030_INT;
|
||||
|
||||
--DTACK
|
||||
DTACK <= 'Z' when BGACK_030_INT ='1' else
|
||||
DTACK_DMA;
|
||||
DTACK_DMA <= '0' when AS_000_INT ='0' AND DSACK(1) ='0' else
|
||||
'1';
|
||||
|
||||
--CO-Processor Chip select
|
||||
FPU_CS_INT <= '0' when FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='0'
|
||||
else '1';
|
||||
FPU_CS <= FPU_CS_INT;
|
||||
|
||||
--if no copro is installed:
|
||||
-- BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||
|
||||
--reset buffer
|
||||
RESET <= RST;
|
||||
|
||||
--cache inhibit: For now: disable
|
||||
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||
'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||
'0';
|
||||
|
||||
--bus buffers
|
||||
AMIGA_BUS_ENABLE <= '0'; --for now: allways on
|
||||
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||
|
||||
|
||||
-- vma and e clock
|
||||
e_clk: process (CLK_000)
|
||||
begin
|
||||
if rising_edge(CLK_000) then
|
||||
-- next state.
|
||||
case (cpu_est) is
|
||||
when E1 => cpu_est <= E2 ;
|
||||
when E2 => cpu_est <= E3 ;
|
||||
when E3 => cpu_est <= E4;
|
||||
when E4 => cpu_est <= E5 ;
|
||||
when E5 => cpu_est <= E6 ;
|
||||
when E6 => cpu_est <= E7 ;
|
||||
when E7 => cpu_est <= E8 ;
|
||||
when E8 => cpu_est <= E9 ;
|
||||
when E9 => cpu_est <= E10;
|
||||
when E10 => cpu_est <= E1 ;
|
||||
-- Illegal states
|
||||
when E4a => cpu_est <= E5 ;
|
||||
when E20 => cpu_est <= E10;
|
||||
when E21 => cpu_est <= E10;
|
||||
when E22 => cpu_est <= E9 ;
|
||||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end process e_clk;
|
||||
|
||||
vma_gen: process (CLK_000,AS_030) begin
|
||||
if(AS_030='1') then
|
||||
VMA_INT <= '1';
|
||||
VPA_SYNC <= '1';
|
||||
elsif falling_edge(CLK_000) then
|
||||
VPA_SYNC <= VPA;
|
||||
if(cpu_est = E3 AND VPA_SYNC = '0' AND AS_000_INT = '0') then
|
||||
VMA_INT <= '0'; -- low active !
|
||||
end if;
|
||||
if(cpu_est = E10) then
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process vma_gen;
|
||||
|
||||
vma_delay: process(CLK_030)
|
||||
begin
|
||||
if(rising_edge(CLK_030)) then
|
||||
VMA_INT_D<=VMA_INT;
|
||||
end if;
|
||||
end process vma_delay;
|
||||
|
||||
E_INT <= cpu_est(3);
|
||||
E <= E_INT;
|
||||
VMA <= VMA_INT AND VMA_INT_D;
|
||||
|
||||
|
||||
--AVEC
|
||||
--AVEC <= '0' WHEN VMA='1' AND cpu_est = E10 --
|
||||
-- ELSE '1';
|
||||
AVEC <= '1';
|
||||
|
||||
--IPL: Buffer interrupts for a CPU-Cycle to avoid fake interupts
|
||||
ipl_amiga: process(CLK_000)
|
||||
begin
|
||||
if(rising_edge(CLK_000)) then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
end process ipl_amiga;
|
||||
|
||||
--BG
|
||||
bg_amiga: process(CLK_030,BG_030)
|
||||
begin
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif(falling_edge(CLK_030)) then
|
||||
if(SM_AMIGA = IDLE and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
else
|
||||
BG_000 <='1';
|
||||
end if;
|
||||
end if;
|
||||
end process bg_amiga;
|
||||
|
||||
|
||||
|
||||
--as uds/lds generation
|
||||
UDS_LOGIC <= '0' WHEN AS_030 = '0' AND A(0)='0' ELSE '1';
|
||||
LDS_LOGIC <= '0' WHEN AS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1') ELSE '1';
|
||||
|
||||
as_amiga: process(AS_030, CLK_030)
|
||||
begin
|
||||
if(rising_edge(CLK_030)) then --as is sampled at rising edge on a 68020/030
|
||||
|
||||
if ( AS_030 = '0' AND -- obviously as must be low
|
||||
CPU_SPACE = '0' AND -- expansion board not in action
|
||||
SM_AMIGA = IDLE AND -- last cycle completed
|
||||
AS_AMIGA_ENABLE = '1' --indicator ready
|
||||
AND CLK_000 = '1' --AND CLK_000_D = '1' -- as is sampled at falling edge on a 68000/010 thus it is set during high CLK_000
|
||||
) then
|
||||
AS_000_INT <= '0';
|
||||
if (RW='1') then --read: set udl/lds
|
||||
UDS_000_INT <= UDS_LOGIC;
|
||||
LDS_000_INT <= LDS_LOGIC;
|
||||
end if;
|
||||
elsif(RW='0' AND SM_AMIGA = AS_SET)then --write: uds/lds have to wait for one 7m-clock later
|
||||
UDS_000_INT <= UDS_LOGIC;
|
||||
LDS_000_INT <= LDS_LOGIC;
|
||||
elsif(AS_030 = '1' and (SM_AMIGA = END_CYCLE OR SM_AMIGA = IDLE)) then
|
||||
AS_000_INT <= '1';
|
||||
UDS_000_INT<= '1';
|
||||
LDS_000_INT<= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process as_amiga;
|
||||
|
||||
--helper signal for a delayed version of AS_000
|
||||
as_pe_amiga: process(AS_030, CLK_000)
|
||||
begin
|
||||
if(AS_030 ='1') then
|
||||
AS_000_INT_D <= '1';
|
||||
elsif(rising_edge(CLK_000)) then -- positive edge delayed AS_000
|
||||
AS_000_INT_D <= AS_000_INT;
|
||||
end if;
|
||||
end process as_pe_amiga;
|
||||
|
||||
|
||||
--state machine for amiga-cycle
|
||||
sm_amiga: process(RST, CLK_000)
|
||||
begin
|
||||
if(RST='0') then
|
||||
SM_AMIGA <= IDLE;
|
||||
DTACK_INT<= '1';
|
||||
elsif(falling_edge(CLK_000)) then
|
||||
case (SM_AMIGA) is
|
||||
when IDLE =>
|
||||
if(AS_000_INT='0') then
|
||||
SM_AMIGA <= AS_SET;
|
||||
end if;
|
||||
when AS_SET =>
|
||||
if(VPA_SYNC = '1' AND DTACK_SYNC='0') then
|
||||
DTACK_INT<= '0';
|
||||
SM_AMIGA <= DATA_FETCH ;
|
||||
elsif(E10=cpu_est AND VPA_SYNC='0' AND VMA_INT='0') then --vpa/vma cycle
|
||||
DTACK_INT<= '0';
|
||||
SM_AMIGA <= DATA_FETCH ;
|
||||
end if;
|
||||
when DATA_FETCH => --here the data is written/read
|
||||
SM_AMIGA <= END_CYCLE;
|
||||
when END_CYCLE => -- internal DTACK is high here. end cycle!
|
||||
DTACK_INT<= '1';
|
||||
SM_AMIGA <= IDLE ;
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end process sm_amiga;
|
||||
|
||||
--positive edge deleyed statemachine
|
||||
state_amiga_pe: process(CLK_000)
|
||||
begin
|
||||
if(rising_edge(CLK_000)) then --as is sampled at rising edge on a 68020/030
|
||||
SM_AMIGA_LAST <= SM_AMIGA;
|
||||
end if;
|
||||
end process state_amiga_pe;
|
||||
|
||||
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
AS_000_INT;
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
UDS_000_INT;
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
LDS_000_INT;
|
||||
--dsack generation
|
||||
dtack_sync: process(CLK_030)
|
||||
begin
|
||||
if(rising_edge(CLK_030)) then
|
||||
DTACK_SYNC <= DTACK; --for the AMIGA state machine
|
||||
DTACK_SYNC_D <= DTACK_SYNC;
|
||||
DTACK_SYNC_DD <= DTACK_SYNC_D;
|
||||
end if;
|
||||
end process dtack_sync;
|
||||
|
||||
--dsack generation
|
||||
dsack_CPU: process(AS_030,CLK_030)
|
||||
begin
|
||||
if(AS_030 ='1') then
|
||||
DSACK_INT<="11";
|
||||
AS_AMIGA_ENABLE <='0';
|
||||
elsif(rising_edge(CLK_030)) then
|
||||
-- this is a indicator, that we have been in idle state
|
||||
-- this avoids that an "old" DTACK is used a second time in a new memory cycle
|
||||
if(SM_AMIGA = IDLE) then
|
||||
AS_AMIGA_ENABLE <= '1';
|
||||
end if;
|
||||
if(SM_AMIGA = DATA_FETCH AND CLK_000='1' AND AS_AMIGA_ENABLE = '1') then
|
||||
DSACK_INT<="01";
|
||||
AS_AMIGA_ENABLE<='0';
|
||||
end if;
|
||||
end if;
|
||||
end process dsack_CPU;
|
||||
|
||||
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||
DSACK_INT;
|
||||
|
||||
-- signal assignment
|
||||
--DS_030 <= "ZZ";
|
||||
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- DS_030_INT;
|
||||
|
||||
--A(1) <= 'Z';
|
||||
--A(0) <= 'Z';
|
||||
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- A_INT;
|
||||
|
||||
--SIZE <= "ZZ";
|
||||
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- SIZE_INT;
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -1,593 +0,0 @@
|
|||
-- Copyright: Matthias Heinrichs 2014
|
||||
-- Free for non-comercial use
|
||||
-- No warranty just for fun
|
||||
-- If you want to earn money with this code, ask me first!
|
||||
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity BUS68030 is
|
||||
|
||||
port(
|
||||
AS_030: inout std_logic ;
|
||||
AS_000: inout std_logic ;
|
||||
RW_000: inout std_logic ;
|
||||
DS_030: inout std_logic ;
|
||||
UDS_000: inout std_logic;
|
||||
LDS_000: inout std_logic;
|
||||
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||
A: in std_logic_vector ( 31 downto 16 );
|
||||
A0: inout std_logic;
|
||||
nEXP_SPACE: in std_logic ;
|
||||
BERR: inout std_logic ;
|
||||
BG_030: in std_logic ;
|
||||
BG_000: out std_logic ;
|
||||
BGACK_030: out std_logic ;
|
||||
BGACK_000: in std_logic ;
|
||||
CLK_030: in std_logic ;
|
||||
CLK_000: in std_logic ;
|
||||
CLK_OSZI: in std_logic ;
|
||||
CLK_DIV_OUT: out std_logic ;
|
||||
CLK_EXP: out std_logic ;
|
||||
FPU_CS: out std_logic ;
|
||||
FPU_SENSE: in std_logic ;
|
||||
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||
IPL: in std_logic_vector ( 2 downto 0 );
|
||||
DSACK1: inout std_logic;
|
||||
DTACK: inout std_logic ;
|
||||
AVEC: out std_logic ;
|
||||
E: out std_logic ;
|
||||
VPA: in std_logic ;
|
||||
VMA: out std_logic ;
|
||||
RST: in std_logic ;
|
||||
RESET: out std_logic ;
|
||||
RW: inout std_logic ;
|
||||
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||
FC: in std_logic_vector ( 1 downto 0 );
|
||||
AMIGA_ADDR_ENABLE: out std_logic ;
|
||||
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||
AMIGA_BUS_ENABLE_HIGH: out std_logic;
|
||||
CIIN: out std_logic
|
||||
);
|
||||
end BUS68030;
|
||||
|
||||
architecture Behavioral of BUS68030 is
|
||||
|
||||
|
||||
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||
|
||||
constant E1 : ESTATE := "0110";
|
||||
constant E2 : ESTATE := "0111";
|
||||
constant E3 : ESTATE := "0100";
|
||||
constant E4 : ESTATE := "0101";
|
||||
constant E5 : ESTATE := "0010";
|
||||
constant E6 : ESTATE := "0011";
|
||||
constant E7 : ESTATE := "1010";
|
||||
constant E8 : ESTATE := "1011";
|
||||
constant E9 : ESTATE := "1100";
|
||||
constant E10 : ESTATE := "1111";
|
||||
-- Illegal states
|
||||
constant E20 : ESTATE := "0000";
|
||||
constant E4a : ESTATE := "0001";
|
||||
constant E21 : ESTATE := "1000";
|
||||
constant E22 : ESTATE := "1001";
|
||||
constant E23 : ESTATE := "1101";
|
||||
constant E24 : ESTATE := "1110";
|
||||
|
||||
signal cpu_est : ESTATE;
|
||||
|
||||
subtype AMIGA_STATE is std_logic_vector(2 downto 0);
|
||||
|
||||
constant IDLE_P : AMIGA_STATE := "000";
|
||||
constant IDLE_N : AMIGA_STATE := "001";
|
||||
constant AS_SET_P : AMIGA_STATE := "010";
|
||||
constant AS_SET_N : AMIGA_STATE := "011";
|
||||
constant SAMPLE_DTACK_P: AMIGA_STATE := "100";
|
||||
constant DATA_FETCH_N: AMIGA_STATE := "101";
|
||||
constant DATA_FETCH_P : AMIGA_STATE := "110";
|
||||
constant END_CYCLE_N : AMIGA_STATE := "111";
|
||||
|
||||
signal SM_AMIGA_P : AMIGA_STATE;
|
||||
signal SM_AMIGA_N : AMIGA_STATE;
|
||||
|
||||
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
signal AS_000_INT:STD_LOGIC := '1';
|
||||
signal RW_000_INT:STD_LOGIC := '1';
|
||||
signal AMIGA_BUS_ENABLE_INT:STD_LOGIC := '1';
|
||||
signal AS_030_D0:STD_LOGIC := '1';
|
||||
signal DS_030_D0:STD_LOGIC := '1';
|
||||
signal AS_030_000_SYNC:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT_D:STD_LOGIC := '1';
|
||||
signal AS_000_DMA:STD_LOGIC := '1';
|
||||
signal DS_000_DMA:STD_LOGIC := '1';
|
||||
signal RW_000_DMA:STD_LOGIC := '1';
|
||||
signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||
signal A0_DMA: STD_LOGIC := '1';
|
||||
signal VMA_INT: STD_LOGIC := '1';
|
||||
signal VPA_D: STD_LOGIC := '1';
|
||||
signal UDS_000_INT: STD_LOGIC := '1';
|
||||
signal LDS_000_INT: STD_LOGIC := '1';
|
||||
signal DS_000_ENABLE: STD_LOGIC := '0';
|
||||
signal DSACK1_INT: STD_LOGIC := '1';
|
||||
signal CLK_CNT_P: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_CNT_N: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
|
||||
signal CLK_OUT_PRE_50: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_50_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_25: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_33: STD_LOGIC := '1';
|
||||
signal CLK_PRE_66:STD_LOGIC := '0';
|
||||
signal CLK_OUT_PRE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_NE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_INT: STD_LOGIC := '1';
|
||||
signal CLK_030_H: STD_LOGIC := '1';
|
||||
signal CLK_000_D0: STD_LOGIC := '1';
|
||||
signal CLK_000_D1: STD_LOGIC := '1';
|
||||
signal CLK_000_D2: STD_LOGIC := '1';
|
||||
signal CLK_000_D3: STD_LOGIC := '1';
|
||||
signal CLK_000_D4: STD_LOGIC := '1';
|
||||
signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
|
||||
signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
|
||||
signal CLK_000_PE: STD_LOGIC := '0';
|
||||
signal CLK_000_NE: STD_LOGIC := '0';
|
||||
signal CLK_000_E_ADVANCE: STD_LOGIC := '0';
|
||||
signal DTACK_D0: STD_LOGIC := '1';
|
||||
|
||||
begin
|
||||
|
||||
|
||||
--the clocks
|
||||
neg_clk: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_CNT_N <= "10";
|
||||
elsif(falling_edge(CLK_OSZI)) then
|
||||
if(CLK_CNT_N = "10") then
|
||||
CLK_CNT_N <= "00";
|
||||
else
|
||||
CLK_CNT_N <= CLK_CNT_N+1;
|
||||
end if;
|
||||
end if;
|
||||
end process neg_clk;
|
||||
|
||||
--the 68000-posedge statemachine
|
||||
state_machine_p: process(RST, CLK_000)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
SM_AMIGA_P <= IDLE_P;
|
||||
AS_000_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
BG_000 <= '1';
|
||||
BGACK_030_INT <= '1';
|
||||
IPL_030 <= "000";
|
||||
elsif(rising_edge(CLK_000)) then
|
||||
|
||||
--now: 68000 state machine and signals
|
||||
|
||||
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif ( BGACK_000='1'
|
||||
) then
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
|
||||
|
||||
--bus grant only in idle state
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
|
||||
and nEXP_SPACE = '1' and AS_030_D0='1'
|
||||
) then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
end if;
|
||||
|
||||
--interrupt buffering to avoid ghost interrupts
|
||||
IPL_030<=IPL;
|
||||
|
||||
--Amiga statemachine p-edge
|
||||
case (SM_AMIGA_P) is
|
||||
when IDLE_P => --68000:S0 wait for a falling edge
|
||||
if( SM_AMIGA_N = IDLE_N)then
|
||||
AS_000_INT <= '0';
|
||||
RW_000_INT <= RW;
|
||||
if (RW='1' ) then --read: set udl/lds
|
||||
DS_000_ENABLE <= '1';
|
||||
end if;
|
||||
SM_AMIGA_P<=AS_SET_P; --go to s2
|
||||
else
|
||||
AS_000_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
end if;
|
||||
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
|
||||
if(SM_AMIGA_N = AS_SET_N)then --go to s4
|
||||
DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
|
||||
-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
|
||||
SM_AMIGA_P<=SAMPLE_DTACK_P;
|
||||
end if;
|
||||
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
|
||||
if( SM_AMIGA_N = DATA_FETCH_N
|
||||
)then --go to s6
|
||||
SM_AMIGA_P<=DATA_FETCH_P;
|
||||
end if;
|
||||
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
|
||||
if( SM_AMIGA_N = END_CYCLE_N) then -- go to s0
|
||||
AS_000_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
SM_AMIGA_P<= IDLE_P;
|
||||
end if;
|
||||
when others =>
|
||||
AS_000_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
SM_AMIGA_P<= IDLE_P;
|
||||
end case;
|
||||
end if;
|
||||
end process state_machine_p;
|
||||
|
||||
--the 68000-negedge statemachine
|
||||
state_machine_n: process(RST, CLK_000)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
cpu_est <= E20;
|
||||
SM_AMIGA_N <= END_CYCLE_N;
|
||||
VMA_INT <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
elsif(falling_edge(CLK_000)) then
|
||||
--now: 68000 state machine and signals
|
||||
|
||||
-- e-clock is changed on the FALLING edge!
|
||||
case (cpu_est) is
|
||||
when E1 => cpu_est <= E2 ;
|
||||
when E2 => cpu_est <= E3 ;
|
||||
when E3 => cpu_est <= E4;
|
||||
when E4 => cpu_est <= E5 ;
|
||||
when E5 => cpu_est <= E6 ;
|
||||
when E6 => cpu_est <= E7 ;
|
||||
when E7 => cpu_est <= E8 ;
|
||||
when E8 => cpu_est <= E9 ;
|
||||
when E9 => cpu_est <= E10;
|
||||
when E10 => cpu_est <= E1 ;
|
||||
-- Illegal states
|
||||
when E4a => cpu_est <= E5 ;
|
||||
when E20 => cpu_est <= E10;
|
||||
when E21 => cpu_est <= E10;
|
||||
when E22 => cpu_est <= E9 ;
|
||||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
|
||||
--switch amiga bus on for DMA-Cycles
|
||||
--if(BGACK_030_INT='0')then
|
||||
-- AMIGA_BUS_ENABLE_INT <= '0' ;
|
||||
--elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then
|
||||
-- AMIGA_BUS_ENABLE_INT <= '1' ;
|
||||
--end if;
|
||||
|
||||
|
||||
-- VMA generation
|
||||
if(VPA_D='0' AND cpu_est = E4)then --assert
|
||||
VMA_INT <= '0';
|
||||
end if;
|
||||
--Amiga statemachine
|
||||
|
||||
case (SM_AMIGA_N) is
|
||||
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
||||
if(SM_AMIGA_P = AS_SET_P)then --go to s3
|
||||
SM_AMIGA_n <= AS_SET_N; --as for amiga set!
|
||||
end if;
|
||||
when AS_SET_N => --68000:S3: nothing happens here; wait for dtack or VPA for atransition to s5:
|
||||
if(SM_AMIGA_P= SAMPLE_DTACK_P and
|
||||
((VPA = '1' AND DTACK='0') OR --DTACK end cycle
|
||||
(VPA='0' AND cpu_est=E9 AND VMA_INT='0') OR --VPA end cycle
|
||||
BERR = '0' )--bus error
|
||||
)then --goto S5
|
||||
SM_AMIGA_N <= DATA_FETCH_N;
|
||||
end if;
|
||||
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||
if(SM_AMIGA_P = DATA_FETCH_P)then --go to s7
|
||||
VMA_INT <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
SM_AMIGA_N<=END_CYCLE_N;
|
||||
end if;
|
||||
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle
|
||||
if(SM_AMIGA_P = IDLE_P and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then --goto S1
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
|
||||
SM_AMIGA_N<=IDLE_N; --go to s1
|
||||
else
|
||||
VMA_INT <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
end if;
|
||||
when others =>
|
||||
VMA_INT <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
SM_AMIGA_N<=END_CYCLE_N;
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end process state_machine_n;
|
||||
|
||||
|
||||
--the state machine
|
||||
state_machine: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_CNT_P <= "00";
|
||||
RESET <= '0';
|
||||
CLK_OUT_PRE_50 <= '0';
|
||||
CLK_OUT_PRE_50_D <= '0';
|
||||
--CLK_OUT_PRE_33 <= '0';
|
||||
CLK_OUT_PRE_25 <= '0';
|
||||
CLK_OUT_PRE <= '0';
|
||||
CLK_OUT_PRE_D <= '0';
|
||||
CLK_OUT_NE <= '0';
|
||||
CLK_OUT_INT <= '0';
|
||||
CLK_000_D0 <= '1';
|
||||
CLK_000_D1 <= '1';
|
||||
CLK_000_D2 <= '1';
|
||||
CLK_000_D3 <= '1';
|
||||
CLK_000_D4 <= '1';
|
||||
VPA_D <= '1';
|
||||
DTACK_D0 <= '1';
|
||||
RW_000_DMA <= '1';
|
||||
AS_030_000_SYNC <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
CLK_REF <= "00";
|
||||
BGACK_030_INT_D <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
CLK_000_P_SYNC <= "0000000000000";
|
||||
CLK_000_N_SYNC <= "0000000000000";
|
||||
CLK_000_PE <= '0';
|
||||
CLK_000_NE <= '0';
|
||||
CLK_000_E_ADVANCE <= '0';
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "11";
|
||||
A0_DMA <= '1';
|
||||
AS_030_D0 <= '1';
|
||||
DS_030_D0 <= '1';
|
||||
CLK_030_H <= '0';
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
--reset buffer
|
||||
RESET <= '1';
|
||||
|
||||
--clk generation :
|
||||
|
||||
CLK_OUT_PRE_50 <= not CLK_OUT_PRE_50;
|
||||
CLK_OUT_PRE_50_D<= CLK_OUT_PRE_50;
|
||||
if(CLK_CNT_P = "10") then
|
||||
CLK_CNT_P <= "00";
|
||||
else
|
||||
CLK_CNT_P <= CLK_CNT_P+1;
|
||||
end if;
|
||||
|
||||
if(CLK_OUT_PRE_50='1' and CLK_OUT_PRE_50_D='0')then
|
||||
CLK_OUT_PRE_25 <= not CLK_OUT_PRE_25;
|
||||
end if;
|
||||
|
||||
--here the clock is selected
|
||||
CLK_OUT_PRE <= CLK_OUT_PRE_25;
|
||||
CLK_OUT_PRE_D <= CLK_OUT_PRE;
|
||||
|
||||
--a negative edge is comming next cycle
|
||||
if(CLK_OUT_PRE_D='1' and CLK_OUT_PRE='0' )then
|
||||
CLK_OUT_NE <= '1';
|
||||
else
|
||||
CLK_OUT_NE <= '0';
|
||||
end if;
|
||||
-- the external clock to the processor is generated here
|
||||
CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
|
||||
--delayed Clocks and signals for edge detection
|
||||
CLK_000_D0 <= CLK_000;
|
||||
CLK_000_D1 <= CLK_000_D0;
|
||||
CLK_000_D2 <= CLK_000_D1;
|
||||
CLK_000_D3 <= CLK_000_D2;
|
||||
CLK_000_D4 <= CLK_000_D3;
|
||||
|
||||
--shift registers for edge detection
|
||||
CLK_000_P_SYNC( 12 downto 1 ) <= CLK_000_P_SYNC( 11 downto 0 );
|
||||
CLK_000_P_SYNC(0) <= CLK_000_D0 AND NOT CLK_000_D1;
|
||||
CLK_000_N_SYNC( 12 downto 1 ) <= CLK_000_N_SYNC( 11 downto 0 );
|
||||
CLK_000_N_SYNC(0) <= NOT CLK_000_D0 AND CLK_000_D1;
|
||||
|
||||
-- values are determined empiracally for 7.09 MHz Clock
|
||||
-- since the clock is not symmetrically these values differ!
|
||||
CLK_000_PE <= CLK_000_P_SYNC(9);
|
||||
CLK_000_NE <= CLK_000_N_SYNC(11);
|
||||
DTACK_D0 <= DTACK;
|
||||
VPA_D <= VPA;
|
||||
|
||||
|
||||
|
||||
AS_030_D0 <= AS_030;
|
||||
DS_030_D0 <= DS_030;
|
||||
|
||||
BGACK_030_INT_D <= BGACK_030_INT;
|
||||
|
||||
|
||||
|
||||
|
||||
-- as030-sampling and FPU-Select
|
||||
|
||||
if(AS_030_D0 ='1' or BERR='0') then -- "async" reset of various signals
|
||||
AS_030_000_SYNC <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
elsif(
|
||||
AS_030_D0 = '0' AND --as set
|
||||
BGACK_000='1' AND --no dma -cycle
|
||||
NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
|
||||
nEXP_SPACE ='1' and --not an expansion space cycle
|
||||
SM_AMIGA_P = IDLE_P --last amiga cycle terminated
|
||||
) then
|
||||
AS_030_000_SYNC <= '0';
|
||||
end if;
|
||||
|
||||
--uds/lds precalculation
|
||||
if (DS_030_D0 = '0') then --DS: set udl/lds
|
||||
if(A0='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
--Set DSACK1 in the right moment of the Amiga statemachine
|
||||
|
||||
if (SM_AMIGA_P = DATA_FETCH_P and BERR = '1') then --wait for the right amiga cycle and no bus error!
|
||||
if( (CLK_000_D3 ='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
|
||||
(CLK_000_D4 ='1' )
|
||||
)then
|
||||
DSACK1_INT <='0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
--dma stuff
|
||||
--as can only be done if we know the uds/lds!
|
||||
if(BGACK_030_INT='0' and AS_000='0' and (UDS_000='0' or LDS_000='0'))then
|
||||
|
||||
--set AS_000
|
||||
if( CLK_030='1') then
|
||||
AS_000_DMA <= '0'; --sampled on rising edges!
|
||||
RW_000_DMA <= RW_000;
|
||||
elsif(AS_000_DMA = '0' and CLK_030='0')then
|
||||
CLK_030_H <= '1';
|
||||
end if;
|
||||
|
||||
if(RW_000='1') then
|
||||
DS_000_DMA <=AS_000_DMA;
|
||||
elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then
|
||||
DS_000_DMA <=AS_000_DMA; -- write: one clock delayed!
|
||||
end if;
|
||||
-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
|
||||
if(UDS_000='0' and LDS_000='0') then
|
||||
SIZE_DMA <= "10"; --16bit
|
||||
else
|
||||
SIZE_DMA <= "01"; --8 bit
|
||||
end if;
|
||||
|
||||
--now calculate the offset:
|
||||
--if uds is set low, a0 is so too.
|
||||
--if only lds is set a1 is high
|
||||
--therefore a1 = uds
|
||||
--great! life is simple here!
|
||||
A0_DMA <= UDS_000;
|
||||
|
||||
--A1 is set by the amiga side
|
||||
else
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "11";
|
||||
A0_DMA <= '0';
|
||||
RW_000_DMA <= '1';
|
||||
CLK_030_H <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process state_machine;
|
||||
|
||||
CLK_PRE_66 <= (not CLK_CNT_N(0) and CLK_CNT_P(0)) or
|
||||
(CLK_CNT_N(1) and CLK_CNT_P(1));
|
||||
|
||||
process_33_clk:process(RST, CLK_PRE_66)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_OUT_PRE_33 <= '0';
|
||||
elsif(rising_edge(CLK_PRE_66)) then
|
||||
CLK_OUT_PRE_33 <= not CLK_OUT_PRE_33;
|
||||
end if;
|
||||
end process process_33_clk;
|
||||
|
||||
|
||||
|
||||
--output clock assignment
|
||||
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||
CLK_EXP <= CLK_OUT_INT;
|
||||
|
||||
-- bus drivers
|
||||
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
|
||||
AMIGA_BUS_ENABLE_HIGH <= AMIGA_BUS_ENABLE_INT;
|
||||
AMIGA_BUS_ENABLE_LOW <= '1';
|
||||
AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
|
||||
'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
|
||||
'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
|
||||
'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
|
||||
'0'; --Point towarts TK
|
||||
|
||||
|
||||
--dma stuff
|
||||
DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
DSACK1;
|
||||
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
AS_000_DMA;
|
||||
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
DS_000_DMA;
|
||||
A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
A0_DMA;
|
||||
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
SIZE_DMA;
|
||||
|
||||
--fpu
|
||||
FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0'
|
||||
else '1';
|
||||
|
||||
--if no copro is installed:
|
||||
BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1'
|
||||
else 'Z';
|
||||
--BERR <= 'Z';
|
||||
|
||||
|
||||
|
||||
--cache inhibit: Tristate for expansion (it decides) and off for the Amiga
|
||||
CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
|
||||
'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE = '0' ELSE --Tristate for expansion (it decides)
|
||||
'0'; --off for the Amiga
|
||||
|
||||
|
||||
--e and VMA
|
||||
E <= cpu_est(3);
|
||||
VMA <= VMA_INT;
|
||||
|
||||
|
||||
--AVEC
|
||||
AVEC <= '1';
|
||||
|
||||
--as and uds/lds
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
AS_000_INT;
|
||||
RW_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
RW_000_INT;
|
||||
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
'1' when DS_000_ENABLE ='0' else -- datastrobe not ready jet
|
||||
UDS_000_INT;
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
'1' when DS_000_ENABLE ='0' else -- datastrobe not ready jet
|
||||
LDS_000_INT;
|
||||
|
||||
--dsack
|
||||
DSACK1 <= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle
|
||||
DSACK1_INT;
|
||||
--rw
|
||||
RW <= 'Z' when BGACK_030_INT ='1' else
|
||||
RW_000_DMA;
|
||||
|
||||
BGACK_030 <= BGACK_030_INT;
|
||||
end Behavioral;
|
||||
|
|
@ -1,403 +0,0 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity BUS68030 is
|
||||
|
||||
port(
|
||||
AS_030: inout std_logic ;
|
||||
AS_000: inout std_logic ;
|
||||
-- DS_030: inout std_logic ;
|
||||
UDS_000: inout std_logic;
|
||||
LDS_000: inout std_logic;
|
||||
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||
A: inout std_logic_vector ( 31 downto 0 );
|
||||
CPU_SPACE: in std_logic ;
|
||||
-- BERR: inout std_logic ; --error: this is connected to a global input pin :(
|
||||
BG_030: in std_logic ;
|
||||
BG_000: out std_logic ;
|
||||
BGACK_030: out std_logic ;
|
||||
BGACK_000: in std_logic ;
|
||||
CLK_030: in std_logic ;
|
||||
CLK_000: in std_logic ;
|
||||
CLK_OSZI: in std_logic ;
|
||||
CLK_DIV_OUT: out std_logic ;
|
||||
CLK_EXP: out std_logic ;
|
||||
FPU_CS: out std_logic ;
|
||||
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||
IPL: in std_logic_vector ( 2 downto 0 );
|
||||
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||
DTACK: inout std_logic ;
|
||||
AVEC: out std_logic ;
|
||||
AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||
E: out std_logic ;
|
||||
VPA: in std_logic ;
|
||||
VMA: out std_logic ;
|
||||
RST: in std_logic ;
|
||||
RESET: out std_logic ;
|
||||
RW: in std_logic ;
|
||||
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||
FC: in std_logic_vector ( 1 downto 0 );
|
||||
AMIGA_BUS_ENABLE: out std_logic ;
|
||||
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||
CIIN: out std_logic
|
||||
);
|
||||
end BUS68030;
|
||||
|
||||
architecture Behavioral of BUS68030 is
|
||||
|
||||
|
||||
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||
|
||||
constant E1 : ESTATE := "0110";
|
||||
constant E2 : ESTATE := "0111";
|
||||
constant E3 : ESTATE := "0100";
|
||||
constant E4 : ESTATE := "0101";
|
||||
constant E5 : ESTATE := "0010";
|
||||
constant E6 : ESTATE := "0011";
|
||||
constant E7 : ESTATE := "1010";
|
||||
constant E8 : ESTATE := "1011";
|
||||
constant E9 : ESTATE := "1100";
|
||||
constant E10 : ESTATE := "1111";
|
||||
-- Illegal states
|
||||
constant E20 : ESTATE := "0000";
|
||||
constant E4a : ESTATE := "0001";
|
||||
constant E21 : ESTATE := "1000";
|
||||
constant E22 : ESTATE := "1001";
|
||||
constant E23 : ESTATE := "1101";
|
||||
constant E24 : ESTATE := "1110";
|
||||
|
||||
signal cpu_est : ESTATE := E20;
|
||||
|
||||
subtype AMIGA_STATE is std_logic_vector(2 downto 0);
|
||||
|
||||
constant IDLE_P : AMIGA_STATE := "000";
|
||||
constant IDLE_N : AMIGA_STATE := "001";
|
||||
constant AS_SET_P : AMIGA_STATE := "010";
|
||||
constant AS_SET_N : AMIGA_STATE := "011";
|
||||
constant DATA_FETCH_P: AMIGA_STATE := "100";
|
||||
constant DATA_FETCH_N: AMIGA_STATE := "101";
|
||||
constant END_CYCLE_P : AMIGA_STATE := "110";
|
||||
constant END_CYCLE_N : AMIGA_STATE := "111";
|
||||
|
||||
signal SM_AMIGA : AMIGA_STATE := IDLE_P;
|
||||
|
||||
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
signal AS_000_INT:STD_LOGIC:= '1';
|
||||
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||
signal E_INT: STD_LOGIC:='1';
|
||||
signal VPA_SYNC: STD_LOGIC:='1';
|
||||
signal VMA_INT: STD_LOGIC:='1';
|
||||
signal VMA_INT_D: STD_LOGIC:='1';
|
||||
signal UDS_000_INT: STD_LOGIC:='1';
|
||||
signal LDS_000_INT: STD_LOGIC:='1';
|
||||
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
|
||||
signal CLK_OUT_PRE: STD_LOGIC:='1';
|
||||
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||
signal CLK_030_D: STD_LOGIC:='1';
|
||||
signal CLK_000_D: STD_LOGIC := '1';
|
||||
signal RISING_CLK_AMIGA: STD_LOGIC :='0';
|
||||
signal FALLING_CLK_AMIGA: STD_LOGIC :='0';
|
||||
--signal RISING_CLK_030: STD_LOGIC :='0';
|
||||
--signal FALLING_CLK_030: STD_LOGIC :='0';
|
||||
|
||||
begin
|
||||
|
||||
|
||||
|
||||
--the clocks
|
||||
clk: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(rising_edge(CLK_OSZI)) then
|
||||
--reset buffer
|
||||
RESET <= RST;
|
||||
|
||||
--clk generation : up to now just half the clock
|
||||
if(CLK_CNT=CLK_REF) then
|
||||
CLK_OUT_PRE <= not CLK_OUT_PRE;
|
||||
CLK_CNT <= "00";
|
||||
else
|
||||
CLK_CNT <= CLK_CNT+1;
|
||||
end if;
|
||||
-- the external clock to the processor is generated here
|
||||
CLK_OUT_INT <= CLK_OUT_PRE;
|
||||
--delayed Clocks for edge detection
|
||||
CLK_000_D <= CLK_000;
|
||||
|
||||
--RISING_CLK_030 <= CLK_OUT_PRE and not CLK_030;
|
||||
--FALLING_CLK_030 <= not CLK_OUT_PRE and CLK_030;
|
||||
--edge detection stuff
|
||||
RISING_CLK_AMIGA <= not CLK_000_D and CLK_000;
|
||||
FALLING_CLK_AMIGA <= CLK_000_D and not CLK_000;
|
||||
-- e clock
|
||||
if(CLK_000_D='0' and CLK_000='1')then
|
||||
case (cpu_est) is
|
||||
when E1 => cpu_est <= E2 ;
|
||||
when E2 => cpu_est <= E3 ;
|
||||
when E3 => cpu_est <= E4;
|
||||
when E4 => cpu_est <= E5 ;
|
||||
when E5 => cpu_est <= E6 ;
|
||||
when E6 => cpu_est <= E7 ;
|
||||
when E7 => cpu_est <= E8 ;
|
||||
when E8 => cpu_est <= E9 ;
|
||||
when E9 => cpu_est <= E10;
|
||||
when E10 => cpu_est <= E1 ;
|
||||
-- Illegal states
|
||||
when E4a => cpu_est <= E5 ;
|
||||
when E20 => cpu_est <= E10;
|
||||
when E21 => cpu_est <= E10;
|
||||
when E22 => cpu_est <= E9 ;
|
||||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
E_INT <= cpu_est(3);
|
||||
VPA_SYNC <= VPA;
|
||||
end if;
|
||||
end process clk;
|
||||
|
||||
|
||||
|
||||
|
||||
--the state process
|
||||
state_machine: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
SM_AMIGA <= IDLE_P;
|
||||
AS_000_INT <='1';
|
||||
UDS_000_INT <='1';
|
||||
LDS_000_INT <='1';
|
||||
CLK_REF <= "11";
|
||||
VMA_INT <= '1';
|
||||
VMA_INT_D <= '1';
|
||||
FPU_CS_INT <= '1';
|
||||
BG_000 <= '1';
|
||||
BGACK_030_INT <= '1';
|
||||
DSACK_INT <= "11";
|
||||
DTACK_DMA <= '1';
|
||||
IPL_030 <= "111";
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
|
||||
|
||||
|
||||
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif (BGACK_000='1' AND RISING_CLK_AMIGA='1') then -- BGACK_000 is high here!
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
|
||||
--bus grant only in idle state
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif(CLK_030 ='0') then
|
||||
if( BG_030= '0' AND (SM_AMIGA = IDLE_N or SM_AMIGA = IDLE_P)
|
||||
and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
else
|
||||
BG_000 <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
--CO-Processor Chip select
|
||||
if(FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1') then
|
||||
FPU_CS_INT <= '0';
|
||||
else
|
||||
FPU_CS_INT <= '1';
|
||||
end if;
|
||||
|
||||
|
||||
|
||||
--interrupt buffering to avoid ghost interrupts
|
||||
if(RISING_CLK_AMIGA='1')then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
|
||||
--vma generation
|
||||
if (CLK_000='0') then
|
||||
if(cpu_est = E3 AND VPA_SYNC = '0' AND AS_000_INT = '0') then
|
||||
VMA_INT <= '0'; -- low active !
|
||||
end if;
|
||||
end if;
|
||||
|
||||
--Amiga statemachine
|
||||
case (SM_AMIGA) is
|
||||
when IDLE_P => --68000:S0 wait for a falling edge
|
||||
if(AS_030 ='1') then
|
||||
DSACK_INT<="11";
|
||||
AS_000_INT <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
VMA_INT <= '1';
|
||||
if(CLK_000='0')then
|
||||
SM_AMIGA<=IDLE_N;
|
||||
end if;
|
||||
end if;
|
||||
when IDLE_N => --68000:S1 wait for rising edge and look for as
|
||||
if(CLK_000='1')then
|
||||
if( CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||
AS_030 = '0' AND -- obviously as must be low
|
||||
CPU_SPACE = '0'
|
||||
)then
|
||||
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||
AS_000_INT <= '0';
|
||||
if (RW='1') then --read: set udl/lds
|
||||
if(AS_030 = '0' AND A(0)='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if(AS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when AS_SET_P => --68000:S2 nothing happens here just wait for negative clock
|
||||
if(CLK_000='0')then
|
||||
SM_AMIGA<=AS_SET_N;
|
||||
end if;
|
||||
when AS_SET_N => --68000:S3 sample dtack and set uds/lds on write and high clock
|
||||
if(CLK_000='1')then
|
||||
if (RW='0') then --write: set udl/lds
|
||||
if(AS_030 = '0' AND A(0)='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if(AS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
if(VPA_SYNC = '1' AND DTACK='0') then
|
||||
SM_AMIGA <= DATA_FETCH_P ;
|
||||
elsif(E10=cpu_est AND VPA_SYNC='0' AND VMA_INT='0') then --vpa/vma cycle
|
||||
SM_AMIGA <= DATA_FETCH_P ;
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when DATA_FETCH_P=> --68000:S4 nothing happens here just wait for negative clock
|
||||
if(CLK_000='0')then
|
||||
SM_AMIGA<=DATA_FETCH_N;
|
||||
end if;
|
||||
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||
if(CLK_000='1')then
|
||||
SM_AMIGA<=END_CYCLE_P;
|
||||
DSACK_INT<="01";
|
||||
end if;
|
||||
when END_CYCLE_P => --68000:S6: propagate dsack to 68030
|
||||
if(AS_030 ='1') then
|
||||
DSACK_INT<="11";
|
||||
AS_000_INT <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
if(CLK_000='0')then
|
||||
SM_AMIGA<=END_CYCLE_N;
|
||||
end if;
|
||||
when END_CYCLE_N =>--68000:S7: deassert signals and go to IDLE on high clock
|
||||
if(AS_030 ='1') then
|
||||
DSACK_INT<="11";
|
||||
AS_000_INT <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
if(CLK_000='1')then
|
||||
SM_AMIGA<=IDLE_P;
|
||||
end if;
|
||||
end case;
|
||||
|
||||
--delay for hold time of CIAs
|
||||
VMA_INT_D <= VMA_INT;
|
||||
|
||||
|
||||
--dma stuff
|
||||
--DTACK for DMA cycles
|
||||
if(AS_000_INT ='0' AND DSACK(1) ='0') then
|
||||
DTACK_DMA <= '0';
|
||||
else
|
||||
DTACK_DMA <= '1';
|
||||
end if;
|
||||
|
||||
|
||||
|
||||
end if;
|
||||
end process state_machine;
|
||||
|
||||
--output clock assignment
|
||||
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||
CLK_EXP <= CLK_OUT_INT;
|
||||
AVEC_EXP <= SM_AMIGA(0);
|
||||
|
||||
--dtack for dma
|
||||
DTACK <= 'Z' when BGACK_030_INT ='1' else
|
||||
DTACK_DMA;
|
||||
|
||||
--fpu
|
||||
FPU_CS <= FPU_CS_INT;
|
||||
|
||||
--if no copro is installed:
|
||||
-- BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||
|
||||
|
||||
|
||||
--cache inhibit: For now: disable
|
||||
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||
'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||
'Z' WHEN not(A(31 downto 24) = x"00") ELSE
|
||||
'0';
|
||||
|
||||
--bus buffers
|
||||
AMIGA_BUS_ENABLE <= '0'; --for now: allways on
|
||||
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||
|
||||
--e and VMA
|
||||
E <= E_INT;
|
||||
VMA <= VMA_INT AND VMA_INT_D;
|
||||
|
||||
|
||||
--AVEC
|
||||
AVEC <= '1';
|
||||
|
||||
--as and uds/lds
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
AS_000_INT;
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
UDS_000_INT;
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
LDS_000_INT;
|
||||
|
||||
--dsack
|
||||
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||
DSACK_INT;
|
||||
|
||||
-- signal assignment
|
||||
--DS_030 <= "ZZ";
|
||||
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- DS_030_INT;
|
||||
|
||||
--A(1) <= 'Z';
|
||||
--A(0) <= 'Z';
|
||||
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- A_INT;
|
||||
|
||||
--SIZE <= "ZZ";
|
||||
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- SIZE_INT;
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -1,453 +0,0 @@
|
|||
-- Copyright: Matthias Heinrichs 2014
|
||||
-- Free for non-comercial use
|
||||
-- No warranty just for fun
|
||||
-- I you want to earn money with this code, ask me first!
|
||||
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity BUS68030 is
|
||||
|
||||
port(
|
||||
AS_030: inout std_logic ;
|
||||
AS_000: inout std_logic ;
|
||||
DS_030: inout std_logic ;
|
||||
UDS_000: inout std_logic;
|
||||
LDS_000: inout std_logic;
|
||||
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||
A: inout std_logic_vector ( 31 downto 0 );
|
||||
nEXP_SPACE: in std_logic ;
|
||||
BERR: inout std_logic ;
|
||||
BG_030: in std_logic ;
|
||||
BG_000: out std_logic ;
|
||||
BGACK_030: out std_logic ;
|
||||
BGACK_000: in std_logic ;
|
||||
CLK_030: in std_logic ;
|
||||
CLK_000: in std_logic ;
|
||||
CLK_OSZI: in std_logic ;
|
||||
CLK_DIV_OUT: out std_logic ;
|
||||
CLK_EXP: out std_logic ;
|
||||
FPU_CS: out std_logic ;
|
||||
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||
IPL: in std_logic_vector ( 2 downto 0 );
|
||||
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||
DTACK: inout std_logic ;
|
||||
AVEC: out std_logic ;
|
||||
AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||
E: out std_logic ;
|
||||
VPA: in std_logic ;
|
||||
VMA: out std_logic ;
|
||||
RST: in std_logic ;
|
||||
RESET: out std_logic ;
|
||||
RW: in std_logic ;
|
||||
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||
FC: in std_logic_vector ( 1 downto 0 );
|
||||
AMIGA_BUS_ENABLE: out std_logic ;
|
||||
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||
CIIN: out std_logic
|
||||
);
|
||||
end BUS68030;
|
||||
|
||||
architecture Behavioral of BUS68030 is
|
||||
|
||||
|
||||
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||
|
||||
constant E1 : ESTATE := "0110";
|
||||
constant E2 : ESTATE := "0111";
|
||||
constant E3 : ESTATE := "0100";
|
||||
constant E4 : ESTATE := "0101";
|
||||
constant E5 : ESTATE := "0010";
|
||||
constant E6 : ESTATE := "0011";
|
||||
constant E7 : ESTATE := "1010";
|
||||
constant E8 : ESTATE := "1011";
|
||||
constant E9 : ESTATE := "1100";
|
||||
constant E10 : ESTATE := "1111";
|
||||
-- Illegal states
|
||||
constant E20 : ESTATE := "0000";
|
||||
constant E4a : ESTATE := "0001";
|
||||
constant E21 : ESTATE := "1000";
|
||||
constant E22 : ESTATE := "1001";
|
||||
constant E23 : ESTATE := "1101";
|
||||
constant E24 : ESTATE := "1110";
|
||||
|
||||
signal cpu_est : ESTATE := E20;
|
||||
signal cpu_est_d : ESTATE := E20;
|
||||
|
||||
subtype AMIGA_STATE is std_logic_vector(2 downto 0);
|
||||
|
||||
constant IDLE_P : AMIGA_STATE := "000";
|
||||
constant IDLE_N : AMIGA_STATE := "001";
|
||||
constant AS_SET_P : AMIGA_STATE := "010";
|
||||
constant AS_SET_N : AMIGA_STATE := "011";
|
||||
constant SAMPLE_DTACK_P: AMIGA_STATE := "100";
|
||||
constant DATA_FETCH_N: AMIGA_STATE := "101";
|
||||
constant DATA_FETCH_P : AMIGA_STATE := "110";
|
||||
constant END_CYCLE_N : AMIGA_STATE := "111";
|
||||
|
||||
signal SM_AMIGA : AMIGA_STATE := IDLE_P;
|
||||
|
||||
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
signal AS_000_INT:STD_LOGIC:= '1';
|
||||
signal AS_030_000_SYNC:STD_LOGIC:= '1';
|
||||
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||
signal DTACK_SYNC:STD_LOGIC:= '1';
|
||||
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||
signal VPA_D: STD_LOGIC:='1';
|
||||
signal VPA_SYNC: STD_LOGIC:='1';
|
||||
signal VMA_INT: STD_LOGIC:='1';
|
||||
signal UDS_000_INT: STD_LOGIC:='1';
|
||||
signal LDS_000_INT: STD_LOGIC:='1';
|
||||
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||
signal CLK_CNT_P: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_CNT_N: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
|
||||
signal CLK_OUT_PRE: STD_LOGIC:='1';
|
||||
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||
signal CLK_030_D: STD_LOGIC:='1';
|
||||
signal CLK_000_D0: STD_LOGIC := '1';
|
||||
signal CLK_000_D1: STD_LOGIC := '1';
|
||||
signal CLK_000_D2: STD_LOGIC := '1';
|
||||
signal CLK_000_D3: STD_LOGIC := '1';
|
||||
signal CLK_000_D4: STD_LOGIC := '1';
|
||||
signal CLK_000_D5: STD_LOGIC := '1';
|
||||
signal CLK_000_D6: STD_LOGIC := '1';
|
||||
|
||||
begin
|
||||
|
||||
|
||||
--the clocks
|
||||
neg_clk: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_CNT_N <= "10";
|
||||
elsif(falling_edge(CLK_OSZI)) then
|
||||
--clk generation : up to now just half the clock
|
||||
if(CLK_CNT_N = "10") then
|
||||
--CLK_OUT_PRE <= not CLK_OUT_PRE;
|
||||
CLK_CNT_N <= "00";
|
||||
else
|
||||
CLK_CNT_N <= CLK_CNT_N+1;
|
||||
end if;
|
||||
end if;
|
||||
end process neg_clk;
|
||||
--the clocks
|
||||
clk: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_CNT_P <= "00";
|
||||
RESET <= '0';
|
||||
CLK_OUT_PRE <= '0';
|
||||
CLK_OUT_INT <= '0';
|
||||
cpu_est <= E20;
|
||||
cpu_est_d <= E20;
|
||||
VPA_D <= '1';
|
||||
CLK_000_D0 <= '1';
|
||||
CLK_000_D1 <= '1';
|
||||
CLK_000_D2 <= '1';
|
||||
CLK_000_D3 <= '1';
|
||||
CLK_000_D4 <= '1';
|
||||
CLK_000_D5 <= '1';
|
||||
CLK_000_D6 <= '1';
|
||||
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
--reset buffer
|
||||
RESET <= '1';
|
||||
|
||||
--clk generation : up to now just half the clock
|
||||
if(CLK_CNT_P = "10") then
|
||||
--CLK_OUT_PRE <= not CLK_OUT_PRE;
|
||||
CLK_CNT_P <= "00";
|
||||
else
|
||||
CLK_CNT_P <= CLK_CNT_P+1;
|
||||
end if;
|
||||
if(CLK_CNT_P ="00" or CLK_CNT_N ="00")then --33MHz Clock
|
||||
CLK_OUT_PRE <= '0';
|
||||
else
|
||||
CLK_OUT_PRE <= '1';
|
||||
end if;
|
||||
-- the external clock to the processor is generated here
|
||||
CLK_OUT_INT <= CLK_OUT_PRE; --this way we know the clock of the next state: Its like looking in the future, cool!
|
||||
--delayed Clocks for edge detection
|
||||
CLK_000_D0 <= CLK_000;
|
||||
CLK_000_D1 <= CLK_000_D0;
|
||||
CLK_000_D2 <= CLK_000_D1;
|
||||
CLK_000_D3 <= CLK_000_D2;
|
||||
CLK_000_D4 <= CLK_000_D3;
|
||||
CLK_000_D5 <= CLK_000_D4;
|
||||
CLK_000_D6 <= CLK_000_D5;
|
||||
|
||||
|
||||
|
||||
-- e-clock
|
||||
if(CLK_000_D1 = '0' and CLK_000_D0 = '1') then
|
||||
case (cpu_est) is
|
||||
when E1 => cpu_est <= E2 ;
|
||||
when E2 => cpu_est <= E3 ;
|
||||
when E3 => cpu_est <= E4;
|
||||
when E4 => cpu_est <= E5 ;
|
||||
when E5 => cpu_est <= E6 ;
|
||||
when E6 => cpu_est <= E7 ;
|
||||
when E7 => cpu_est <= E8 ;
|
||||
when E8 => cpu_est <= E9 ;
|
||||
when E9 => cpu_est <= E10;
|
||||
when E10 => cpu_est <= E1 ;
|
||||
-- Illegal states
|
||||
when E4a => cpu_est <= E5 ;
|
||||
when E20 => cpu_est <= E10;
|
||||
when E21 => cpu_est <= E10;
|
||||
when E22 => cpu_est <= E9 ;
|
||||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
cpu_est_d <= cpu_est;
|
||||
VPA_D <= VPA;
|
||||
end if;
|
||||
end process clk;
|
||||
|
||||
|
||||
--the state process
|
||||
state_machine: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
SM_AMIGA <= IDLE_P;
|
||||
AS_000_INT <= '1';
|
||||
AS_030_000_SYNC <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
CLK_REF <= "00";
|
||||
VMA_INT <= '1';
|
||||
FPU_CS_INT <= '1';
|
||||
BG_000 <= '1';
|
||||
BGACK_030_INT <= '1';
|
||||
DSACK_INT <= "11";
|
||||
DTACK_DMA <= '1';
|
||||
DTACK_SYNC <= '1';
|
||||
VPA_SYNC <= '1';
|
||||
IPL_030 <= "111";
|
||||
AMIGA_BUS_ENABLE <= '1';
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
|
||||
|
||||
|
||||
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif (BGACK_000='1' AND CLK_000_D1='0' and CLK_000_D0='1') then -- BGACK_000 is high here!
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
|
||||
--bus grant only in idle state
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif( BG_030= '0' AND (SM_AMIGA = IDLE_P)
|
||||
and nEXP_SPACE = '1' and AS_030='1'
|
||||
and CLK_000='1' ) then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
--interrupt buffering to avoid ghost interrupts
|
||||
if(CLK_000_D1='0' and CLK_000_D0='1')then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
|
||||
-- as030-sampling and FPU-Select
|
||||
|
||||
|
||||
if(AS_030 ='1') then -- "async" reset of various signals
|
||||
AS_030_000_SYNC <= '1';
|
||||
FPU_CS_INT <= '1';
|
||||
DSACK_INT <="11";
|
||||
AS_000_INT <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
DTACK_SYNC <= '1';
|
||||
VPA_SYNC <= '1';
|
||||
AMIGA_BUS_ENABLE <= '1';
|
||||
elsif( CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||
AS_030 = '0') then
|
||||
if(FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1') then
|
||||
FPU_CS_INT <= '0';
|
||||
else
|
||||
if(nEXP_SPACE ='1' and SM_AMIGA = IDLE_P )then
|
||||
AS_030_000_SYNC <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- VMA generation
|
||||
if(CLK_000_D0='0' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
VMA_INT <= '0';
|
||||
elsif(CLK_000_D0='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
|
||||
|
||||
--Amiga statemachine
|
||||
case (SM_AMIGA) is
|
||||
when IDLE_P => --68000:S0 wait for a falling edge
|
||||
if( CLK_000_D2='0' and CLK_000_D3= '1' and AS_030_000_SYNC = '0')then
|
||||
SM_AMIGA<=IDLE_N; --go to s1
|
||||
end if;
|
||||
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
||||
if(nEXP_SPACE ='1')then
|
||||
AMIGA_BUS_ENABLE <= '0' ;--for now: allways on for amiga
|
||||
else -- if this a delayed expansion space detection, aboard this cycle!
|
||||
AMIGA_BUS_ENABLE <= '1';
|
||||
AS_030_000_SYNC <= '1';
|
||||
SM_AMIGA <= IDLE_P; --aboard
|
||||
end if;
|
||||
|
||||
if(CLK_000_D0='1')then --go to s2
|
||||
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||
end if;
|
||||
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
|
||||
AS_000_INT <= '0';
|
||||
if (RW='1' and DS_030 = '0') then --read: set udl/lds
|
||||
if(A(0)='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
if(CLK_000_D0='0')then --go to s3
|
||||
SM_AMIGA<=AS_SET_N;
|
||||
end if;
|
||||
when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
|
||||
if (RW='0' and DS_030 = '0') then --write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
|
||||
if(A(0)='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
if(CLK_000_D0='1')then --go to s4
|
||||
SM_AMIGA <= SAMPLE_DTACK_P;
|
||||
end if;
|
||||
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
|
||||
if(CLK_000_D0='0' )then --go to s5
|
||||
if(DTACK_SYNC = '0' OR VPA_SYNC ='0')then
|
||||
SM_AMIGA<=DATA_FETCH_N;
|
||||
end if;
|
||||
elsif(CLK_000_D0='1' )then -- high clock: sample DTACK
|
||||
if(VPA_D = '1' AND DTACK='0') then
|
||||
DTACK_SYNC <= '0';
|
||||
elsif(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0') then --vpa/vma cycle: sync VPA on E9: one 7M-clock to latch!
|
||||
VPA_SYNC <= '0';
|
||||
end if;
|
||||
end if;
|
||||
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||
if(CLK_000_D0='1')then --go to s6
|
||||
SM_AMIGA<=DATA_FETCH_P;
|
||||
end if;
|
||||
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
|
||||
if( CLK_000_D5 ='1' AND CLK_000_D6 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
DSACK_INT<="01";
|
||||
AS_030_000_SYNC <= '1'; --cycle end
|
||||
elsif( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--DSACK_INT<="01";
|
||||
SM_AMIGA<=END_CYCLE_N;
|
||||
--AS_030_000_SYNC <= '1'; --cycle end
|
||||
end if;
|
||||
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
|
||||
if(CLK_000_D0='1' and AS_000_INT = '1' )then --go to s0
|
||||
SM_AMIGA<=IDLE_P;
|
||||
end if;
|
||||
end case;
|
||||
|
||||
|
||||
--dma stuff
|
||||
--DTACK for DMA cycles
|
||||
if(AS_000_INT ='0' AND DSACK(1) ='0') then
|
||||
DTACK_DMA <= '0';
|
||||
else
|
||||
DTACK_DMA <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process state_machine;
|
||||
|
||||
--output clock assignment
|
||||
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||
CLK_EXP <= CLK_OUT_INT;
|
||||
AVEC_EXP <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||
|
||||
--dtack for dma
|
||||
DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else
|
||||
DTACK_DMA;
|
||||
|
||||
--fpu
|
||||
FPU_CS <= FPU_CS_INT;
|
||||
|
||||
--if no copro is installed:
|
||||
BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||
|
||||
|
||||
|
||||
--cache inhibit: For now: disable
|
||||
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||
--'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||
'Z' WHEN not(A(31 downto 24) = x"00") ELSE
|
||||
'0';
|
||||
|
||||
--bus buffers
|
||||
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||
|
||||
--e and VMA
|
||||
E <= cpu_est(3);
|
||||
VMA <= VMA_INT;
|
||||
|
||||
|
||||
--AVEC
|
||||
AVEC <= '1';
|
||||
|
||||
--as and uds/lds
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
AS_000_INT;
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
UDS_000_INT;
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
LDS_000_INT;
|
||||
|
||||
--dsack
|
||||
DSACK <= "ZZ" when nEXP_SPACE = '0' else -- output on amiga cycle
|
||||
DSACK_INT;
|
||||
BGACK_030 <= BGACK_030_INT;
|
||||
-- signal assignment
|
||||
--DS_030 <= "ZZ";
|
||||
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- DS_030_INT;
|
||||
|
||||
--A(1) <= 'Z';
|
||||
--A(0) <= 'Z';
|
||||
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- A_INT;
|
||||
|
||||
--SIZE <= "ZZ";
|
||||
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- SIZE_INT;
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -1,582 +0,0 @@
|
|||
-- Copyright: Matthias Heinrichs 2014
|
||||
-- Free for non-comercial use
|
||||
-- No warranty just for fun
|
||||
-- If you want to earn money with this code, ask me first!
|
||||
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity BUS68030 is
|
||||
|
||||
port(
|
||||
AS_030: inout std_logic ;
|
||||
AS_000: inout std_logic ;
|
||||
RW_000: inout std_logic ;
|
||||
DS_030: inout std_logic ;
|
||||
UDS_000: inout std_logic;
|
||||
LDS_000: inout std_logic;
|
||||
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||
A: in std_logic_vector ( 31 downto 16 );
|
||||
A0: inout std_logic;
|
||||
nEXP_SPACE: in std_logic ;
|
||||
BERR: inout std_logic ;
|
||||
BG_030: in std_logic ;
|
||||
BG_000: out std_logic ;
|
||||
BGACK_030: out std_logic ;
|
||||
BGACK_000: in std_logic ;
|
||||
CLK_030: in std_logic ;
|
||||
CLK_000: in std_logic ;
|
||||
CLK_OSZI: in std_logic ;
|
||||
CLK_DIV_OUT: out std_logic ;
|
||||
CLK_EXP: out std_logic ;
|
||||
FPU_CS: out std_logic ;
|
||||
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||
IPL: in std_logic_vector ( 2 downto 0 );
|
||||
DSACK1: inout std_logic;
|
||||
DTACK: inout std_logic ;
|
||||
AVEC: out std_logic ;
|
||||
AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||
E: out std_logic ;
|
||||
VPA: in std_logic ;
|
||||
VMA: out std_logic ;
|
||||
RST: in std_logic ;
|
||||
RESET: out std_logic ;
|
||||
RW: inout std_logic ;
|
||||
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||
FC: in std_logic_vector ( 1 downto 0 );
|
||||
AMIGA_BUS_ENABLE: out std_logic ;
|
||||
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||
CIIN: out std_logic
|
||||
);
|
||||
end BUS68030;
|
||||
|
||||
architecture Behavioral of BUS68030 is
|
||||
|
||||
|
||||
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||
|
||||
constant E1 : ESTATE := "0110";
|
||||
constant E2 : ESTATE := "0111";
|
||||
constant E3 : ESTATE := "0100";
|
||||
constant E4 : ESTATE := "0101";
|
||||
constant E5 : ESTATE := "0010";
|
||||
constant E6 : ESTATE := "0011";
|
||||
constant E7 : ESTATE := "1010";
|
||||
constant E8 : ESTATE := "1011";
|
||||
constant E9 : ESTATE := "1100";
|
||||
constant E10 : ESTATE := "1111";
|
||||
-- Illegal states
|
||||
constant E20 : ESTATE := "0000";
|
||||
constant E4a : ESTATE := "0001";
|
||||
constant E21 : ESTATE := "1000";
|
||||
constant E22 : ESTATE := "1001";
|
||||
constant E23 : ESTATE := "1101";
|
||||
constant E24 : ESTATE := "1110";
|
||||
|
||||
signal cpu_est : ESTATE;
|
||||
|
||||
subtype AMIGA_STATE is std_logic_vector(2 downto 0);
|
||||
|
||||
constant IDLE_P : AMIGA_STATE := "000";
|
||||
constant IDLE_N : AMIGA_STATE := "001";
|
||||
constant AS_SET_P : AMIGA_STATE := "010";
|
||||
constant AS_SET_N : AMIGA_STATE := "011";
|
||||
constant SAMPLE_DTACK_P: AMIGA_STATE := "100";
|
||||
constant DATA_FETCH_N: AMIGA_STATE := "101";
|
||||
constant DATA_FETCH_P : AMIGA_STATE := "110";
|
||||
constant END_CYCLE_N : AMIGA_STATE := "111";
|
||||
|
||||
signal SM_AMIGA : AMIGA_STATE;
|
||||
|
||||
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
signal AS_000_INT:STD_LOGIC := '1';
|
||||
signal RW_000_INT:STD_LOGIC := '1';
|
||||
signal AMIGA_BUS_ENABLE_INT:STD_LOGIC := '1';
|
||||
signal AS_030_000_SYNC:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT_D:STD_LOGIC := '1';
|
||||
signal AS_000_DMA:STD_LOGIC := '1';
|
||||
signal DS_000_DMA:STD_LOGIC := '1';
|
||||
signal RW_000_DMA:STD_LOGIC := '1';
|
||||
signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||
signal A0_DMA: STD_LOGIC := '1';
|
||||
signal FPU_CS_INT:STD_LOGIC := '1';
|
||||
signal VMA_INT: STD_LOGIC := '1';
|
||||
signal VPA_D: STD_LOGIC := '1';
|
||||
signal UDS_000_INT: STD_LOGIC := '1';
|
||||
signal LDS_000_INT: STD_LOGIC := '1';
|
||||
signal DS_000_ENABLE: STD_LOGIC := '0';
|
||||
signal DSACK1_INT: STD_LOGIC := '1';
|
||||
signal CLK_CNT_P: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_CNT_N: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
|
||||
signal CLK_OUT_PRE_50: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_50_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_25: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_33: STD_LOGIC := '1';
|
||||
signal CLK_PRE_66:STD_LOGIC := '0';
|
||||
signal CLK_OUT_PRE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_NE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_INT: STD_LOGIC := '1';
|
||||
signal CLK_030_H: STD_LOGIC := '1';
|
||||
signal CLK_000_D0: STD_LOGIC := '1';
|
||||
signal CLK_000_D1: STD_LOGIC := '1';
|
||||
signal CLK_000_D2: STD_LOGIC := '1';
|
||||
signal CLK_000_D3: STD_LOGIC := '1';
|
||||
signal CLK_000_D4: STD_LOGIC := '1';
|
||||
signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
|
||||
signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
|
||||
signal CLK_000_PE: STD_LOGIC := '0';
|
||||
signal CLK_000_NE: STD_LOGIC := '0';
|
||||
signal CLK_000_NE_D: STD_LOGIC := '0';
|
||||
signal DTACK_D0: STD_LOGIC := '1';
|
||||
begin
|
||||
|
||||
|
||||
--the clocks
|
||||
neg_clk: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_CNT_N <= "10";
|
||||
elsif(falling_edge(CLK_OSZI)) then
|
||||
if(CLK_CNT_N = "10") then
|
||||
CLK_CNT_N <= "00";
|
||||
else
|
||||
CLK_CNT_N <= CLK_CNT_N+1;
|
||||
end if;
|
||||
end if;
|
||||
end process neg_clk;
|
||||
--the state machine
|
||||
state_machine: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_CNT_P <= "00";
|
||||
RESET <= '0';
|
||||
CLK_OUT_PRE_50 <= '0';
|
||||
CLK_OUT_PRE_50_D <= '0';
|
||||
--CLK_OUT_PRE_33 <= '0';
|
||||
CLK_OUT_PRE_25 <= '0';
|
||||
CLK_OUT_PRE <= '0';
|
||||
CLK_OUT_PRE_D <= '0';
|
||||
CLK_OUT_NE <= '0';
|
||||
CLK_OUT_INT <= '0';
|
||||
cpu_est <= E20;
|
||||
CLK_000_D0 <= '1';
|
||||
CLK_000_D1 <= '1';
|
||||
CLK_000_D2 <= '1';
|
||||
CLK_000_D3 <= '1';
|
||||
CLK_000_D4 <= '1';
|
||||
VPA_D <= '1';
|
||||
DTACK_D0 <= '1';
|
||||
SM_AMIGA <= IDLE_P;
|
||||
AS_000_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
RW_000_DMA <= '1';
|
||||
AS_030_000_SYNC <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
CLK_REF <= "00";
|
||||
VMA_INT <= '1';
|
||||
FPU_CS_INT <= '1';
|
||||
BG_000 <= '1';
|
||||
BGACK_030_INT <= '1';
|
||||
BGACK_030_INT_D <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
IPL_030 <= "111";
|
||||
CLK_000_P_SYNC <= "0000000000000";
|
||||
CLK_000_N_SYNC <= "0000000000000";
|
||||
CLK_000_PE <= '0';
|
||||
CLK_000_NE <= '0';
|
||||
CLK_000_NE_D <= '0';
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "11";
|
||||
A0_DMA <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
--reset buffer
|
||||
RESET <= '1';
|
||||
|
||||
--clk generation :
|
||||
|
||||
CLK_OUT_PRE_50 <= not CLK_OUT_PRE_50;
|
||||
CLK_OUT_PRE_50_D<= CLK_OUT_PRE_50;
|
||||
if(CLK_CNT_P = "10") then
|
||||
CLK_CNT_P <= "00";
|
||||
else
|
||||
CLK_CNT_P <= CLK_CNT_P+1;
|
||||
end if;
|
||||
|
||||
--if(CLK_CNT_P ="00" or CLK_CNT_N ="00")then --33MHz Clock
|
||||
-- CLK_OUT_PRE_33 <= '0';
|
||||
--else
|
||||
-- CLK_OUT_PRE_33 <= '1';
|
||||
--end if;
|
||||
|
||||
if(CLK_OUT_PRE_50='1' and CLK_OUT_PRE_50_D='0')then
|
||||
CLK_OUT_PRE_25 <= not CLK_OUT_PRE_25;
|
||||
end if;
|
||||
|
||||
--here the clock is selected
|
||||
CLK_OUT_PRE <= CLK_OUT_PRE_25;
|
||||
CLK_OUT_PRE_D <= CLK_OUT_PRE;
|
||||
|
||||
--a negative edge is comming next cycle
|
||||
if(CLK_OUT_PRE_D='1' and CLK_OUT_PRE='0' )then
|
||||
CLK_OUT_NE <= '1';
|
||||
else
|
||||
CLK_OUT_NE <= '0';
|
||||
end if;
|
||||
-- the external clock to the processor is generated here
|
||||
CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
|
||||
--delayed Clocks and signals for edge detection
|
||||
CLK_000_D0 <= CLK_000;
|
||||
CLK_000_D1 <= CLK_000_D0;
|
||||
CLK_000_D2 <= CLK_000_D1;
|
||||
CLK_000_D3 <= CLK_000_D2;
|
||||
CLK_000_D4 <= CLK_000_D3;
|
||||
|
||||
--shift registers for edge detection
|
||||
CLK_000_P_SYNC( 12 downto 1 ) <= CLK_000_P_SYNC( 11 downto 0 );
|
||||
CLK_000_P_SYNC(0) <= CLK_000_D0 AND NOT CLK_000_D1 AND NOT CLK_000_D2 AND NOT CLK_000_D3;
|
||||
CLK_000_N_SYNC( 12 downto 1 ) <= CLK_000_N_SYNC( 11 downto 0 );
|
||||
CLK_000_N_SYNC(0) <= NOT CLK_000_D0 AND CLK_000_D1 AND CLK_000_D2 AND CLK_000_D3;
|
||||
|
||||
-- values are determined empiracally for 7.09 MHz Clock
|
||||
-- since the clock is not symmetrically these values differ!
|
||||
CLK_000_PE <= CLK_000_P_SYNC(9);
|
||||
CLK_000_NE <= CLK_000_N_SYNC(11);
|
||||
CLK_000_NE_D <= CLK_000_NE;
|
||||
DTACK_D0 <= DTACK;
|
||||
VPA_D <= VPA;
|
||||
|
||||
--now: 68000 state machine and signals
|
||||
|
||||
-- e-clock
|
||||
if(CLK_000_PE = '1') then
|
||||
--if(CLK_000_D1 = '0' and CLK_000_D0 = '1') then
|
||||
case (cpu_est) is
|
||||
when E1 => cpu_est <= E2 ;
|
||||
when E2 => cpu_est <= E3 ;
|
||||
when E3 => cpu_est <= E4;
|
||||
when E4 => cpu_est <= E5 ;
|
||||
when E5 => cpu_est <= E6 ;
|
||||
when E6 => cpu_est <= E7 ;
|
||||
when E7 => cpu_est <= E8 ;
|
||||
when E8 => cpu_est <= E9 ;
|
||||
when E9 => cpu_est <= E10;
|
||||
when E10 => cpu_est <= E1 ;
|
||||
-- Illegal states
|
||||
when E4a => cpu_est <= E5 ;
|
||||
when E20 => cpu_est <= E10;
|
||||
when E21 => cpu_est <= E10;
|
||||
when E22 => cpu_est <= E9 ;
|
||||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
|
||||
|
||||
|
||||
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif ( BGACK_000='1'
|
||||
AND CLK_000_PE='1'
|
||||
--AND CLK_000_D1='0' and CLK_000_D0='1'
|
||||
) then -- BGACK_000 is high here!
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
BGACK_030_INT_D <= BGACK_030_INT;
|
||||
|
||||
--bus grant only in idle state
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
|
||||
and nEXP_SPACE = '1' and AS_030='1'
|
||||
and CLK_000='1'
|
||||
--and CLK_000_D0='1' AND CLK_000_D1='0'
|
||||
) then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
--interrupt buffering to avoid ghost interrupts
|
||||
if(CLK_000_PE='1')then
|
||||
--if(CLK_000_D1='0' and CLK_000_D0='1')then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
|
||||
-- as030-sampling and FPU-Select
|
||||
|
||||
|
||||
if(AS_030 ='1' or BERR='0') then -- "async" reset of various signals
|
||||
AS_030_000_SYNC <= '1';
|
||||
FPU_CS_INT <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
AS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||
AS_030 = '0') then
|
||||
if(FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1') then
|
||||
FPU_CS_INT <= '0';
|
||||
else
|
||||
if( nEXP_SPACE ='1' and --not an expansion space cycle
|
||||
SM_AMIGA = IDLE_P AND --last amiga cycle terminated
|
||||
BGACK_030_INT = '1' --no dma -cycle
|
||||
)then
|
||||
AS_030_000_SYNC <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
-- VMA generation
|
||||
if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
VMA_INT <= '0';
|
||||
elsif(CLK_000_PE='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
|
||||
--uds/lds precalculation
|
||||
if (DS_030 = '0') then --DS: set udl/lds
|
||||
if(A0='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
--Amiga statemachine
|
||||
|
||||
if(BERR='0')then --"async" reset on errors
|
||||
SM_AMIGA<=IDLE_P;
|
||||
end if;
|
||||
|
||||
case (SM_AMIGA) is
|
||||
when IDLE_P => --68000:S0 wait for a falling edge
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0')then
|
||||
if(nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
|
||||
SM_AMIGA<=IDLE_N; --go to s1
|
||||
end if;
|
||||
end if;
|
||||
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
||||
if(CLK_000_PE='1')then --go to s2
|
||||
--if(CLK_000_D0='1')then --go to s2
|
||||
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||
AS_000_INT <= '0';
|
||||
RW_000_INT <= RW;
|
||||
if (RW='1' ) then --read: set udl/lds
|
||||
DS_000_ENABLE <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
|
||||
if(CLK_000_NE='1')then --go to s3
|
||||
--if(CLK_000_D0='0')then --go to s3
|
||||
SM_AMIGA<=AS_SET_N;
|
||||
end if;
|
||||
when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
|
||||
|
||||
if(CLK_000_PE='1')then --go to s4
|
||||
--if(CLK_000_D0='1')then --go to s4
|
||||
DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
|
||||
-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
|
||||
SM_AMIGA <= SAMPLE_DTACK_P;
|
||||
end if;
|
||||
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
|
||||
if( CLK_000_NE='1' and --falling edge
|
||||
--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
|
||||
((VPA = '1' AND DTACK='0') OR --DTACK end cycle
|
||||
(VPA='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
|
||||
)then --go to s5
|
||||
SM_AMIGA<=DATA_FETCH_N;
|
||||
end if;
|
||||
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||
if(CLK_000_PE = '1')then --go to s6
|
||||
--if(CLK_000_D0='1')then --go to s6
|
||||
SM_AMIGA<=DATA_FETCH_P;
|
||||
end if;
|
||||
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
|
||||
if( CLK_000_N_SYNC(6)='1') then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
|
||||
DSACK1_INT <='0';
|
||||
end if;
|
||||
--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
-- DSACK1_INT <='0';
|
||||
--end if;
|
||||
if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
SM_AMIGA<=END_CYCLE_N;
|
||||
if(AS_030 ='1') then
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
|
||||
if(AS_030 ='1') then
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
end if;
|
||||
|
||||
if(CLK_000_PE='1')then --go to s0
|
||||
--if(CLK_000_D0='1')then --go to s0
|
||||
SM_AMIGA<=IDLE_P;
|
||||
end if;
|
||||
end case;
|
||||
|
||||
if(BGACK_030_INT='0')then
|
||||
--switch amiga bus on for DMA-Cycles
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;
|
||||
elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then
|
||||
AMIGA_BUS_ENABLE_INT <= '1' ;
|
||||
end if;
|
||||
|
||||
--dma stuff
|
||||
--as can only be done if we know the uds/lds!
|
||||
if(BGACK_030_INT='0' and AS_000='0' and (UDS_000='0' or LDS_000='0'))then
|
||||
|
||||
--set AS_000
|
||||
if( CLK_030='1') then
|
||||
AS_000_DMA <= '0'; --sampled on rising edges!
|
||||
RW_000_DMA <= RW_000;
|
||||
elsif(AS_000_DMA = '0' and CLK_030='0')then
|
||||
CLK_030_H <= '1';
|
||||
end if;
|
||||
|
||||
if(RW_000='1') then
|
||||
DS_000_DMA <=AS_000_DMA;
|
||||
elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then
|
||||
DS_000_DMA <=AS_000_DMA; -- write: one clock delayed!
|
||||
end if;
|
||||
-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
|
||||
if(UDS_000='0' and LDS_000='0') then
|
||||
SIZE_DMA <= "10"; --16bit
|
||||
else
|
||||
SIZE_DMA <= "01"; --8 bit
|
||||
end if;
|
||||
|
||||
--now calculate the offset:
|
||||
--if uds is set low, a0 is so too.
|
||||
--if only lds is set a1 is high
|
||||
--therefore a1 = uds
|
||||
--great! life is simple here!
|
||||
A0_DMA <= UDS_000;
|
||||
|
||||
--A1 is set by the amiga side
|
||||
else
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "11";
|
||||
A0_DMA <= '0';
|
||||
RW_000_DMA <= '1';
|
||||
CLK_030_H <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process state_machine;
|
||||
|
||||
CLK_PRE_66 <= (not CLK_CNT_N(0) and CLK_CNT_P(0)) or
|
||||
(CLK_CNT_N(1) and CLK_CNT_P(1));
|
||||
|
||||
process_33_clk:process(RST, CLK_PRE_66)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_OUT_PRE_33 <= '0';
|
||||
elsif(rising_edge(CLK_PRE_66)) then
|
||||
CLK_OUT_PRE_33 <= not CLK_OUT_PRE_33;
|
||||
end if;
|
||||
end process process_33_clk;
|
||||
AMIGA_BUS_ENABLE_LOW <= CLK_OUT_PRE_33;
|
||||
|
||||
|
||||
|
||||
--output clock assignment
|
||||
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||
CLK_EXP <= CLK_OUT_INT;
|
||||
--CLK_DIV_OUT <= CLK_OUT_PRE_33;
|
||||
--CLK_EXP <= CLK_OUT_PRE_33;
|
||||
AVEC_EXP <= CLK_000_PE;
|
||||
AMIGA_BUS_ENABLE <= AMIGA_BUS_ENABLE_INT;
|
||||
--dma stuff
|
||||
DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
DSACK1;
|
||||
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
AS_000_DMA;
|
||||
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
DS_000_DMA;
|
||||
A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
A0_DMA;
|
||||
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
SIZE_DMA;
|
||||
|
||||
--fpu
|
||||
FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1'
|
||||
else '1';
|
||||
|
||||
--if no copro is installed:
|
||||
--BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1'
|
||||
-- else 'Z';
|
||||
BERR <= 'Z';
|
||||
|
||||
|
||||
|
||||
--cache inhibit: For now: disable
|
||||
CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030 ='0' ELSE
|
||||
--'1' WHEN A(31 downto 20) = x"002" ELSE
|
||||
--'1' WHEN A(31 downto 20) = x"004" ELSE
|
||||
'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE = '0' ELSE
|
||||
'0';
|
||||
|
||||
--bus buffers
|
||||
AMIGA_BUS_DATA_DIR <= '1' WHEN (RW='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
|
||||
'0' WHEN (RW='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
|
||||
'1' WHEN (RW='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
|
||||
'0' WHEN (RW='0' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
|
||||
'0'; --Point towarts TK
|
||||
--AMIGA_BUS_ENABLE_LOW <= CLK_OUT_NE; --for now: allways off
|
||||
|
||||
--e and VMA
|
||||
E <= cpu_est(3);
|
||||
VMA <= VMA_INT;
|
||||
|
||||
|
||||
--AVEC
|
||||
AVEC <= '1';
|
||||
|
||||
--as and uds/lds
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
AS_000_INT;
|
||||
RW_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
RW_000_INT;
|
||||
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
'1' when DS_000_ENABLE ='0' else -- datastrobe not ready jet
|
||||
UDS_000_INT;
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
'1' when DS_000_ENABLE ='0' else -- datastrobe not ready jet
|
||||
LDS_000_INT;
|
||||
|
||||
--dsack
|
||||
DSACK1 <= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle
|
||||
DSACK1_INT;
|
||||
--rw
|
||||
RW <= 'Z' when BGACK_030_INT ='1' else
|
||||
RW_000_DMA;
|
||||
|
||||
BGACK_030 <= BGACK_030_INT;
|
||||
end Behavioral;
|
||||
|
|
@ -1,425 +0,0 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity BUS68030 is
|
||||
|
||||
port(
|
||||
AS_030: inout std_logic ;
|
||||
AS_000: inout std_logic ;
|
||||
DS_030: inout std_logic ;
|
||||
UDS_000: inout std_logic;
|
||||
LDS_000: inout std_logic;
|
||||
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||
A: inout std_logic_vector ( 31 downto 0 );
|
||||
CPU_SPACE: in std_logic ;
|
||||
-- BERR: inout std_logic ; --error: this is connected to a global input pin :(
|
||||
BG_030: in std_logic ;
|
||||
BG_000: out std_logic ;
|
||||
BGACK_030: out std_logic ;
|
||||
BGACK_000: in std_logic ;
|
||||
CLK_030: in std_logic ;
|
||||
CLK_000: in std_logic ;
|
||||
CLK_OSZI: in std_logic ;
|
||||
CLK_DIV_OUT: out std_logic ;
|
||||
CLK_EXP: out std_logic ;
|
||||
FPU_CS: out std_logic ;
|
||||
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||
IPL: in std_logic_vector ( 2 downto 0 );
|
||||
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||
DTACK: inout std_logic ;
|
||||
AVEC: out std_logic ;
|
||||
-- AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||
E: out std_logic ;
|
||||
VPA: in std_logic ;
|
||||
VMA: out std_logic ;
|
||||
RST: in std_logic ;
|
||||
RESET: out std_logic ;
|
||||
RW: in std_logic ;
|
||||
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||
FC: in std_logic_vector ( 1 downto 0 );
|
||||
AMIGA_BUS_ENABLE: out std_logic ;
|
||||
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||
CIIN: out std_logic
|
||||
);
|
||||
end BUS68030;
|
||||
|
||||
architecture Behavioral of BUS68030 is
|
||||
|
||||
|
||||
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||
|
||||
constant E1 : ESTATE := "0110";
|
||||
constant E2 : ESTATE := "0111";
|
||||
constant E3 : ESTATE := "0100";
|
||||
constant E4 : ESTATE := "0101";
|
||||
constant E5 : ESTATE := "0010";
|
||||
constant E6 : ESTATE := "0011";
|
||||
constant E7 : ESTATE := "1010";
|
||||
constant E8 : ESTATE := "1011";
|
||||
constant E9 : ESTATE := "1100";
|
||||
constant E10 : ESTATE := "1111";
|
||||
-- Illegal states
|
||||
constant E20 : ESTATE := "0000";
|
||||
constant E4a : ESTATE := "0001";
|
||||
constant E21 : ESTATE := "1000";
|
||||
constant E22 : ESTATE := "1001";
|
||||
constant E23 : ESTATE := "1101";
|
||||
constant E24 : ESTATE := "1110";
|
||||
|
||||
signal cpu_est : ESTATE := E20;
|
||||
|
||||
subtype AMIGA_STATE is std_logic_vector(1 downto 0);
|
||||
|
||||
constant IDLE : AMIGA_STATE := "00";
|
||||
constant AS_SET : AMIGA_STATE := "01";
|
||||
constant DATA_FETCH : AMIGA_STATE := "10";
|
||||
constant END_CYCLE : AMIGA_STATE := "11";
|
||||
|
||||
signal SM_AMIGA : AMIGA_STATE;
|
||||
signal SM_AMIGA_LAST : AMIGA_STATE;
|
||||
|
||||
|
||||
|
||||
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
signal ZorroII:STD_LOGIC:= '0';
|
||||
signal AS_000_INT:STD_LOGIC:= '1';
|
||||
signal AS_000_INT_D:STD_LOGIC:= '1';
|
||||
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||
signal DTACK_INT:STD_LOGIC:= '1';
|
||||
signal DTACK_SYNC:STD_LOGIC:= '1';
|
||||
signal DTACK_SYNC_D:STD_LOGIC:= '1';
|
||||
signal DTACK_SYNC_DD:STD_LOGIC:= '1';
|
||||
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||
signal E_INT: STD_LOGIC:='1';
|
||||
signal VPA_SYNC: STD_LOGIC:='1';
|
||||
signal VMA_INT: STD_LOGIC:='1';
|
||||
signal VMA_INT_D: STD_LOGIC:='1';
|
||||
signal UDS_000_INT: STD_LOGIC:='1';
|
||||
signal LDS_000_INT: STD_LOGIC:='1';
|
||||
signal UDS_LOGIC: STD_LOGIC:='1';
|
||||
signal LDS_LOGIC: STD_LOGIC:='1';
|
||||
--signal AS_030_delay: STD_LOGIC:='1';
|
||||
signal AS_AMIGA_ENABLE: STD_LOGIC:='1';
|
||||
--signal DS_030_INT: STD_LOGIC:='Z';
|
||||
--signal A_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
--signal SIZE_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||
signal CLK_000_D: STD_LOGIC := '1';
|
||||
|
||||
begin
|
||||
|
||||
--clk generation : up to now just half the clock
|
||||
cpu_clk: process(CLK_OSZI)
|
||||
begin
|
||||
if(rising_edge(CLK_OSZI)) then
|
||||
|
||||
if(CLK_CNT="11") then
|
||||
CLK_OUT_INT <= not CLK_OUT_INT;
|
||||
CLK_CNT <= "00";
|
||||
else
|
||||
CLK_CNT <= CLK_CNT+1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process cpu_clk;
|
||||
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||
CLK_EXP <= CLK_OUT_INT;
|
||||
|
||||
|
||||
clk_delay: process(CLK_OSZI)
|
||||
begin
|
||||
if(rising_edge(CLK_OSZI)) then
|
||||
CLK_000_D <= CLK_000;
|
||||
end if;
|
||||
|
||||
end process clk_delay;
|
||||
|
||||
--ZORROII (Amiga) space?
|
||||
ZorroII <= '1' when (A(31 downto 24)= x"00") else '0'; -- 24-bit addres space.
|
||||
|
||||
--BG_ACK is simple:
|
||||
BGACK_030_gen: process (CLK_000,BGACK_000) begin
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif rising_edge(CLK_000) then
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
end process BGACK_030_gen;
|
||||
BGACK_030 <= BGACK_030_INT;
|
||||
|
||||
--DTACK
|
||||
DTACK <= 'Z' when BGACK_030_INT ='1' else
|
||||
DTACK_DMA;
|
||||
DTACK_DMA <= '0' when AS_000_INT ='0' AND DSACK(1) ='0' else
|
||||
'1';
|
||||
|
||||
--CO-Processor Chip select
|
||||
FPU_CS_INT <= '0' when FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='0'
|
||||
else '1';
|
||||
FPU_CS <= FPU_CS_INT;
|
||||
|
||||
--if no copro is installed:
|
||||
-- BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||
|
||||
--reset buffer
|
||||
RESET <= RST;
|
||||
|
||||
--cache inhibit: For now: disable
|
||||
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||
'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||
'0';
|
||||
|
||||
--bus buffers
|
||||
AMIGA_BUS_ENABLE <= '0'; --for now: allways on
|
||||
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||
|
||||
|
||||
-- vma and e clock
|
||||
e_clk: process (CLK_000)
|
||||
begin
|
||||
if falling_edge(CLK_000) then
|
||||
-- next state.
|
||||
case (cpu_est) is
|
||||
when E1 => cpu_est <= E2 ;
|
||||
when E2 => cpu_est <= E3 ;
|
||||
when E3 => cpu_est <= E4;
|
||||
when E4 => cpu_est <= E5 ;
|
||||
when E5 => cpu_est <= E6 ;
|
||||
when E6 => cpu_est <= E7 ;
|
||||
when E7 => cpu_est <= E8 ;
|
||||
when E8 => cpu_est <= E9 ;
|
||||
when E9 => cpu_est <= E10;
|
||||
when E10 => cpu_est <= E1 ;
|
||||
-- Illegal states
|
||||
when E4a => cpu_est <= E5 ;
|
||||
when E20 => cpu_est <= E10;
|
||||
when E21 => cpu_est <= E10;
|
||||
when E22 => cpu_est <= E9 ;
|
||||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end process e_clk;
|
||||
|
||||
vma_gen: process (CLK_000,AS_030) begin
|
||||
--if(AS_030='1') then
|
||||
-- VMA_INT <= '1';
|
||||
-- VPA_SYNC <= '1';
|
||||
--els
|
||||
if falling_edge(CLK_000) then
|
||||
VPA_SYNC <= VPA;
|
||||
if(cpu_est = E3 AND VPA = '0' AND SM_AMIGA = AS_SET) then
|
||||
VMA_INT <= '0'; -- low active !
|
||||
end if;
|
||||
if(cpu_est = E10) then
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process vma_gen;
|
||||
|
||||
vma_delay: process(CLK_030)
|
||||
begin
|
||||
if(rising_edge(CLK_030)) then
|
||||
VMA_INT_D<=VMA_INT;
|
||||
end if;
|
||||
end process vma_delay;
|
||||
|
||||
E_INT <= cpu_est(3);
|
||||
E <= E_INT;
|
||||
VMA <= VMA_INT;-- AND VMA_INT_D;
|
||||
|
||||
|
||||
--AVEC
|
||||
--AVEC <= '0' WHEN VMA='1' AND cpu_est = E10 --
|
||||
-- ELSE '1';
|
||||
AVEC <= '1';
|
||||
|
||||
--IPL: Buffer interrupts for a CPU-Cycle to avoid fake interupts
|
||||
ipl_amiga: process(CLK_000)
|
||||
begin
|
||||
if(rising_edge(CLK_000)) then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
end process ipl_amiga;
|
||||
|
||||
--BG
|
||||
bg_amiga: process(CLK_030,BG_030)
|
||||
begin
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif(falling_edge(CLK_030)) then
|
||||
if(SM_AMIGA = IDLE and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
else
|
||||
BG_000 <='1';
|
||||
end if;
|
||||
end if;
|
||||
end process bg_amiga;
|
||||
|
||||
|
||||
|
||||
--as uds/lds generation
|
||||
UDS_LOGIC <= '0' WHEN DS_030 = '0' AND A(0)='0' ELSE '1';
|
||||
LDS_LOGIC <= '0' WHEN DS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1') ELSE '1';
|
||||
|
||||
as_amiga: process(AS_030, CLK_030)
|
||||
begin
|
||||
--if(AS_030 = '1') then --Read-modify-write cycles do not deassert AS in between but DS does!
|
||||
-- AS_000_INT <= '1';
|
||||
--els
|
||||
if(rising_edge(CLK_030)) then --as is sampled at rising edge on a 68020/030
|
||||
case (SM_AMIGA) is
|
||||
when IDLE =>
|
||||
if( AS_030 = '0' -- obviously as must be low
|
||||
AND CPU_SPACE = '0' -- expansion board not in action
|
||||
AND SM_AMIGA = IDLE -- last cycle completed
|
||||
AND AS_AMIGA_ENABLE = '1' --indicator ready
|
||||
AND CLK_000 = '1' --AND CLK_000_D = '1' -- as is sampled at falling edge on a 68000/010 thus it is set during high CLK_000
|
||||
) then
|
||||
AS_000_INT <= '0';
|
||||
if (RW='1')then -- read: immediate datastrobe!
|
||||
UDS_000_INT <= UDS_LOGIC;
|
||||
LDS_000_INT <= LDS_LOGIC;
|
||||
end if;
|
||||
end if;
|
||||
when AS_SET =>
|
||||
if( CLK_000 = '1'
|
||||
AND DS_030 = '0'
|
||||
AND RW='0'
|
||||
) then
|
||||
UDS_000_INT <= UDS_LOGIC;
|
||||
LDS_000_INT <= LDS_LOGIC;
|
||||
end if;
|
||||
when DATA_FETCH => --here the data is written/read
|
||||
if(AS_030 ='1') then
|
||||
AS_000_INT <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
when END_CYCLE => -- internal DTACK is high here. end cycle!
|
||||
if(AS_030 ='1') then
|
||||
AS_000_INT <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end process as_amiga;
|
||||
|
||||
|
||||
--helper signal for a delayed version of AS_000
|
||||
as_pe_amiga: process(AS_030, CLK_000)
|
||||
begin
|
||||
if(AS_030 ='1') then
|
||||
AS_000_INT_D <= '1';
|
||||
elsif(rising_edge(CLK_000)) then -- positive edge delayed AS_000
|
||||
AS_000_INT_D <= AS_000_INT;
|
||||
end if;
|
||||
end process as_pe_amiga;
|
||||
|
||||
|
||||
--state machine for amiga-cycle
|
||||
sm_amiga: process(RST, CLK_000)
|
||||
begin
|
||||
if(RST='0') then
|
||||
SM_AMIGA <= IDLE;
|
||||
DTACK_INT<= '1';
|
||||
elsif(falling_edge(CLK_000)) then
|
||||
case (SM_AMIGA) is
|
||||
when IDLE =>
|
||||
if(AS_000_INT='0') then
|
||||
SM_AMIGA <= AS_SET;
|
||||
end if;
|
||||
when AS_SET =>
|
||||
if(VPA = '1' AND DTACK='0') then
|
||||
DTACK_INT<= '0';
|
||||
SM_AMIGA <= DATA_FETCH ;
|
||||
elsif(E8=cpu_est AND VPA_SYNC='0' AND VMA_INT='0') then --vpa/vma cycle ends on e10 but we have two clocks after this state!
|
||||
DTACK_INT<= '0';
|
||||
SM_AMIGA <= DATA_FETCH ;
|
||||
end if;
|
||||
when DATA_FETCH => --here the data is written/read
|
||||
SM_AMIGA <= END_CYCLE;
|
||||
when END_CYCLE => -- internal DTACK is high here. end cycle!
|
||||
DTACK_INT<= '1';
|
||||
SM_AMIGA <= IDLE ;
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end process sm_amiga;
|
||||
|
||||
--positive edge deleyed statemachine
|
||||
state_amiga_pe: process(CLK_000)
|
||||
begin
|
||||
if(rising_edge(CLK_000)) then --as is sampled at rising edge on a 68020/030
|
||||
SM_AMIGA_LAST <= SM_AMIGA;
|
||||
end if;
|
||||
end process state_amiga_pe;
|
||||
|
||||
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
AS_000_INT;
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
UDS_000_INT;
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
LDS_000_INT;
|
||||
--dsack generation
|
||||
dtack_sync: process(CLK_030)
|
||||
begin
|
||||
if(rising_edge(CLK_030)) then
|
||||
DTACK_SYNC <= DTACK; --for the AMIGA state machine
|
||||
DTACK_SYNC_D <= DTACK_SYNC;
|
||||
DTACK_SYNC_DD <= DTACK_SYNC_D;
|
||||
end if;
|
||||
end process dtack_sync;
|
||||
|
||||
--dsack generation
|
||||
dsack_CPU: process(DS_030,CLK_030)
|
||||
begin
|
||||
if(AS_030 ='1') then --Read-modify-write cycles do not deassert AS in between but DS does!
|
||||
DSACK_INT<="11";
|
||||
AS_AMIGA_ENABLE <= '0';
|
||||
elsif(falling_edge(CLK_030)) then
|
||||
if(SM_AMIGA = IDLE)then
|
||||
--this is a indicator, that we have been in idle state
|
||||
--this avoids that an "old" DTACK is used a second time in a new memory cycle
|
||||
AS_AMIGA_ENABLE <= '1';
|
||||
elsif(SM_AMIGA_LAST = DATA_FETCH AND AS_AMIGA_ENABLE = '1') then
|
||||
DSACK_INT<="01";
|
||||
AS_AMIGA_ENABLE <= '0';
|
||||
elsif(SM_AMIGA=END_CYCLE) then --Read-modify-write cycles do not deassert AS in between!
|
||||
DSACK_INT<="11";
|
||||
end if;
|
||||
end if;
|
||||
end process dsack_CPU;
|
||||
|
||||
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||
DSACK_INT;
|
||||
|
||||
-- signal assignment
|
||||
--DS_030 <= "ZZ";
|
||||
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- DS_030_INT;
|
||||
|
||||
--A(1) <= 'Z';
|
||||
--A(0) <= 'Z';
|
||||
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- A_INT;
|
||||
|
||||
--SIZE <= "ZZ";
|
||||
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- SIZE_INT;
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -1,387 +0,0 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity BUS68030 is
|
||||
|
||||
port(
|
||||
AS_030: inout std_logic ;
|
||||
AS_000: inout std_logic ;
|
||||
-- DS_030: inout std_logic ;
|
||||
UDS_000: inout std_logic;
|
||||
LDS_000: inout std_logic;
|
||||
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||
A: inout std_logic_vector ( 31 downto 0 );
|
||||
CPU_SPACE: in std_logic ;
|
||||
-- BERR: inout std_logic ; --error: this is connected to a global input pin :(
|
||||
BG_030: in std_logic ;
|
||||
BG_000: out std_logic ;
|
||||
BGACK_030: out std_logic ;
|
||||
BGACK_000: in std_logic ;
|
||||
CLK_030: in std_logic ;
|
||||
CLK_000: in std_logic ;
|
||||
CLK_OSZI: in std_logic ;
|
||||
CLK_DIV_OUT: out std_logic ;
|
||||
CLK_EXP: out std_logic ;
|
||||
FPU_CS: out std_logic ;
|
||||
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||
IPL: in std_logic_vector ( 2 downto 0 );
|
||||
DSACK: inout std_logic_vector ( 1 downto 0 );
|
||||
DTACK: inout std_logic ;
|
||||
AVEC: out std_logic ;
|
||||
-- AVEC_EXP: inout std_logic ; --this is a "free pin"
|
||||
E: out std_logic ;
|
||||
VPA: in std_logic ;
|
||||
VMA: out std_logic ;
|
||||
RST: in std_logic ;
|
||||
RESET: out std_logic ;
|
||||
RW: in std_logic ;
|
||||
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||
FC: in std_logic_vector ( 1 downto 0 );
|
||||
AMIGA_BUS_ENABLE: out std_logic ;
|
||||
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||
CIIN: out std_logic
|
||||
);
|
||||
end BUS68030;
|
||||
|
||||
architecture Behavioral of BUS68030 is
|
||||
|
||||
|
||||
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||
|
||||
constant E1 : ESTATE := "0110";
|
||||
constant E2 : ESTATE := "0111";
|
||||
constant E3 : ESTATE := "0100";
|
||||
constant E4 : ESTATE := "0101";
|
||||
constant E5 : ESTATE := "0010";
|
||||
constant E6 : ESTATE := "0011";
|
||||
constant E7 : ESTATE := "1010";
|
||||
constant E8 : ESTATE := "1011";
|
||||
constant E9 : ESTATE := "1100";
|
||||
constant E10 : ESTATE := "1111";
|
||||
-- Illegal states
|
||||
constant E20 : ESTATE := "0000";
|
||||
constant E4a : ESTATE := "0001";
|
||||
constant E21 : ESTATE := "1000";
|
||||
constant E22 : ESTATE := "1001";
|
||||
constant E23 : ESTATE := "1101";
|
||||
constant E24 : ESTATE := "1110";
|
||||
|
||||
signal cpu_est : ESTATE := E20;
|
||||
|
||||
subtype AMIGA_STATE is std_logic_vector(1 downto 0);
|
||||
|
||||
constant IDLE : AMIGA_STATE := "00";
|
||||
constant AS_SET : AMIGA_STATE := "01";
|
||||
constant DATA_FETCH : AMIGA_STATE := "10";
|
||||
constant END_CYCLE : AMIGA_STATE := "11";
|
||||
|
||||
signal SM_AMIGA : AMIGA_STATE;
|
||||
signal SM_AMIGA_LAST : AMIGA_STATE;
|
||||
|
||||
|
||||
|
||||
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
signal ZorroII:STD_LOGIC:= '0';
|
||||
signal AS_000_INT:STD_LOGIC:= '1';
|
||||
signal AS_000_INT_D:STD_LOGIC:= '1';
|
||||
signal BGACK_030_INT:STD_LOGIC:= '1';
|
||||
signal DTACK_DMA:STD_LOGIC:= '1';
|
||||
signal DTACK_INT:STD_LOGIC:= '1';
|
||||
signal DTACK_SYNC:STD_LOGIC:= '1';
|
||||
signal DTACK_SYNC_D:STD_LOGIC:= '1';
|
||||
signal DTACK_SYNC_DD:STD_LOGIC:= '1';
|
||||
signal FPU_CS_INT:STD_LOGIC:= '1';
|
||||
signal E_INT: STD_LOGIC:='1';
|
||||
signal VPA_SYNC: STD_LOGIC:='1';
|
||||
signal VMA_INT: STD_LOGIC:='1';
|
||||
signal VMA_INT_D: STD_LOGIC:='1';
|
||||
signal UDS_000_INT: STD_LOGIC:='1';
|
||||
signal LDS_000_INT: STD_LOGIC:='1';
|
||||
signal UDS_LOGIC: STD_LOGIC:='1';
|
||||
signal LDS_LOGIC: STD_LOGIC:='1';
|
||||
--signal AS_030_delay: STD_LOGIC:='1';
|
||||
signal SM_AMIGA_ENABLE: STD_LOGIC:='1';
|
||||
--signal DS_030_INT: STD_LOGIC:='Z';
|
||||
--signal A_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
--signal SIZE_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_OUT_INT: STD_LOGIC:='1';
|
||||
signal CLK_000_D: STD_LOGIC := '1';
|
||||
|
||||
begin
|
||||
|
||||
--clk generation : up to now just half the clock
|
||||
cpu_clk: process(CLK_OSZI)
|
||||
begin
|
||||
if(rising_edge(CLK_OSZI)) then
|
||||
|
||||
if(CLK_CNT="01") then
|
||||
CLK_OUT_INT <= not CLK_OUT_INT;
|
||||
CLK_CNT <= "00";
|
||||
else
|
||||
CLK_CNT <= CLK_CNT+1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process cpu_clk;
|
||||
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||
CLK_EXP <= CLK_OUT_INT;
|
||||
|
||||
|
||||
clk_delay: process(CLK_030)
|
||||
begin
|
||||
if(rising_edge(CLK_030)) then
|
||||
CLK_000_D <= CLK_000;
|
||||
end if;
|
||||
|
||||
end process clk_delay;
|
||||
|
||||
--ZORROII (Amiga) space?
|
||||
ZorroII <= '1' when (A(31 downto 24)= x"00") else '0'; -- 24-bit addres space.
|
||||
|
||||
--BG_ACK is simple:
|
||||
BGACK_030_gen: process (CLK_000,BGACK_000) begin
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif rising_edge(CLK_000) then
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
end process BGACK_030_gen;
|
||||
BGACK_030 <= BGACK_030_INT;
|
||||
|
||||
--DTACK
|
||||
DTACK <= 'Z' when BGACK_030_INT ='1' else
|
||||
DTACK_DMA;
|
||||
DTACK_DMA <= '0' when AS_000_INT ='0' AND DSACK(1) ='0' else
|
||||
'1';
|
||||
|
||||
--CO-Processor Chip select
|
||||
FPU_CS_INT <= '0' when FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='0'
|
||||
else '1';
|
||||
FPU_CS <= FPU_CS_INT;
|
||||
|
||||
--if no copro is installed:
|
||||
-- BERR <= 'Z' when FPU_CS_INT ='1' else '0';
|
||||
|
||||
--reset buffer
|
||||
RESET <= RST;
|
||||
|
||||
--cache inhibit: For now: disable
|
||||
CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
|
||||
'1' WHEN A(31 downto 16) = x"00E0" ELSE
|
||||
'0';
|
||||
|
||||
--bus buffers
|
||||
AMIGA_BUS_ENABLE <= '0'; --for now: allways on
|
||||
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
|
||||
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
|
||||
|
||||
|
||||
-- vma and e clock
|
||||
e_clk: process (CLK_000)
|
||||
begin
|
||||
if rising_edge(CLK_000) then
|
||||
-- next state.
|
||||
case (cpu_est) is
|
||||
when E1 => cpu_est <= E2 ;
|
||||
when E2 => cpu_est <= E3 ;
|
||||
when E3 => cpu_est <= E4;
|
||||
when E4 => cpu_est <= E5 ;
|
||||
when E5 => cpu_est <= E6 ;
|
||||
when E6 => cpu_est <= E7 ;
|
||||
when E7 => cpu_est <= E8 ;
|
||||
when E8 => cpu_est <= E9 ;
|
||||
when E9 => cpu_est <= E10;
|
||||
when E10 => cpu_est <= E1 ;
|
||||
-- Illegal states
|
||||
when E4a => cpu_est <= E5 ;
|
||||
when E20 => cpu_est <= E10;
|
||||
when E21 => cpu_est <= E10;
|
||||
when E22 => cpu_est <= E9 ;
|
||||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end process e_clk;
|
||||
|
||||
vma_gen: process (CLK_000,AS_030) begin
|
||||
if(AS_030='1') then
|
||||
VMA_INT <= '1';
|
||||
VPA_SYNC <= '1';
|
||||
elsif falling_edge(CLK_000) then
|
||||
VPA_SYNC <= VPA;
|
||||
if(cpu_est = E3 AND VPA_SYNC = '0' AND AS_000_INT = '0') then
|
||||
VMA_INT <= '0'; -- low active !
|
||||
end if;
|
||||
if(cpu_est = E10) then
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process vma_gen;
|
||||
|
||||
vma_delay: process(CLK_030)
|
||||
begin
|
||||
if(rising_edge(CLK_030)) then
|
||||
VMA_INT_D<=VMA_INT;
|
||||
end if;
|
||||
end process vma_delay;
|
||||
|
||||
E_INT <= cpu_est(3);
|
||||
E <= E_INT;
|
||||
VMA <= VMA_INT AND VMA_INT_D;
|
||||
|
||||
|
||||
--AVEC
|
||||
--AVEC <= '0' WHEN VMA='1' AND cpu_est = E10 --
|
||||
-- ELSE '1';
|
||||
AVEC <= '1';
|
||||
|
||||
--IPL: Buffer interrupts for a CPU-Cycle to avoid fake interupts
|
||||
ipl_amiga: process(CLK_000)
|
||||
begin
|
||||
if(rising_edge(CLK_000)) then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
end process ipl_amiga;
|
||||
|
||||
--BG
|
||||
bg_amiga: process(CLK_030,BG_030)
|
||||
begin
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif(falling_edge(CLK_030)) then
|
||||
if(SM_AMIGA = IDLE and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
else
|
||||
BG_000 <='1';
|
||||
end if;
|
||||
end if;
|
||||
end process bg_amiga;
|
||||
|
||||
|
||||
|
||||
--as uds/lds generation
|
||||
UDS_LOGIC <= '0' WHEN AS_030 = '0' AND A(0)='0' ELSE '1';
|
||||
LDS_LOGIC <= '0' WHEN AS_030 = '0' AND (A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1') ELSE '1';
|
||||
|
||||
|
||||
--state machine for amiga-cycle
|
||||
sm_amiga: process(RST, CLK_030)
|
||||
begin
|
||||
if(RST='0') then
|
||||
SM_AMIGA <= IDLE;
|
||||
DTACK_INT <= '1';
|
||||
DSACK_INT <="11";
|
||||
UDS_000_INT <='1';
|
||||
LDS_000_INT <='1';
|
||||
AS_000_INT <='1';
|
||||
SM_AMIGA_ENABLE <='0';
|
||||
elsif(rising_edge(CLK_030)) then
|
||||
case (SM_AMIGA) is
|
||||
when IDLE =>
|
||||
if(CLK_000 ='0') then
|
||||
SM_AMIGA_ENABLE<='1';
|
||||
end if;
|
||||
if ( AS_030 = '0' -- obviously as must be low
|
||||
AND CPU_SPACE = '0' -- expansion board not in action
|
||||
AND CLK_000 = '1' --AND CLK_000_D = '1' -- as is sampled at falling edge on a 68000/010 thus it is set during high CLK_000
|
||||
AND SM_AMIGA_ENABLE = '1'
|
||||
) then
|
||||
AS_000_INT <= '0';
|
||||
if (RW='1') then --read: set udl/lds
|
||||
UDS_000_INT <= UDS_LOGIC;
|
||||
LDS_000_INT <= LDS_LOGIC;
|
||||
end if;
|
||||
SM_AMIGA_ENABLE <='0';
|
||||
SM_AMIGA <= AS_SET;
|
||||
else
|
||||
DSACK_INT<="11";
|
||||
UDS_000_INT <='1';
|
||||
LDS_000_INT <='1';
|
||||
AS_000_INT <='1';
|
||||
end if;
|
||||
when AS_SET =>
|
||||
if(CLK_000 ='0') then
|
||||
SM_AMIGA_ENABLE<='1';
|
||||
end if;
|
||||
if ( CLK_000 = '1' and SM_AMIGA_ENABLE='1' ) then
|
||||
UDS_000_INT <= UDS_LOGIC;
|
||||
LDS_000_INT <= LDS_LOGIC;
|
||||
if(VPA_SYNC = '1' AND DTACK='0') then
|
||||
DTACK_INT<= '0';
|
||||
SM_AMIGA_ENABLE <='0';
|
||||
SM_AMIGA <= DATA_FETCH ;
|
||||
elsif(E10=cpu_est AND VPA_SYNC='0' AND VMA_INT='0') then --vpa/vma cycle
|
||||
DTACK_INT<= '0';
|
||||
SM_AMIGA_ENABLE <='0';
|
||||
SM_AMIGA <= DATA_FETCH ;
|
||||
end if;
|
||||
end if;
|
||||
when DATA_FETCH => --here the data is written/read
|
||||
DSACK_INT<="01";
|
||||
if(CLK_000_D ='0') then
|
||||
SM_AMIGA_ENABLE<='1';
|
||||
end if;
|
||||
if(AS_030 ='1') then
|
||||
DSACK_INT<="11";
|
||||
UDS_000_INT <='1';
|
||||
LDS_000_INT <='1';
|
||||
AS_000_INT <='1';
|
||||
end if;
|
||||
if( CLK_000 = '1' AND SM_AMIGA_ENABLE = '1')then
|
||||
SM_AMIGA_ENABLE <='0';
|
||||
SM_AMIGA <= END_CYCLE;
|
||||
end if;
|
||||
when END_CYCLE => -- internal DTACK is high here. end cycle!
|
||||
if(CLK_000 ='0') then
|
||||
SM_AMIGA_ENABLE<='1';
|
||||
end if;
|
||||
if(AS_030 ='1') then
|
||||
DSACK_INT<="11";
|
||||
UDS_000_INT <='1';
|
||||
LDS_000_INT <='1';
|
||||
AS_000_INT <='1';
|
||||
end if;
|
||||
if ( CLK_000 = '1' and SM_AMIGA_ENABLE <='1' ) then
|
||||
SM_AMIGA_ENABLE <='0';
|
||||
SM_AMIGA <= IDLE ;
|
||||
end if;
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end process sm_amiga;
|
||||
|
||||
|
||||
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
AS_000_INT;
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
UDS_000_INT;
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
LDS_000_INT;
|
||||
|
||||
DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
|
||||
DSACK_INT;
|
||||
|
||||
-- signal assignment
|
||||
--DS_030 <= "ZZ";
|
||||
--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- DS_030_INT;
|
||||
|
||||
--A(1) <= 'Z';
|
||||
--A(0) <= 'Z';
|
||||
--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- A_INT;
|
||||
|
||||
--SIZE <= "ZZ";
|
||||
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
|
||||
-- SIZE_INT;
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -1,578 +0,0 @@
|
|||
-- Copyright: Matthias Heinrichs 2014
|
||||
-- Free for non-comercial use
|
||||
-- No warranty just for fun
|
||||
-- If you want to earn money with this code, ask me first!
|
||||
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity BUS68030 is
|
||||
|
||||
port(
|
||||
AS_030: inout std_logic ;
|
||||
AS_000: inout std_logic ;
|
||||
RW_000: inout std_logic ;
|
||||
DS_030: inout std_logic ;
|
||||
UDS_000: inout std_logic;
|
||||
LDS_000: inout std_logic;
|
||||
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||
A: in std_logic_vector ( 31 downto 16 );
|
||||
A0: inout std_logic;
|
||||
nEXP_SPACE: in std_logic ;
|
||||
BERR: inout std_logic ;
|
||||
BG_030: in std_logic ;
|
||||
BG_000: out std_logic ;
|
||||
BGACK_030: out std_logic ;
|
||||
BGACK_000: in std_logic ;
|
||||
CLK_030: in std_logic ;
|
||||
CLK_000: in std_logic ;
|
||||
CLK_OSZI: in std_logic ;
|
||||
CLK_DIV_OUT: out std_logic ;
|
||||
CLK_EXP: out std_logic ;
|
||||
FPU_CS: out std_logic ;
|
||||
FPU_SENSE: in std_logic ;
|
||||
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||
IPL: in std_logic_vector ( 2 downto 0 );
|
||||
DSACK1: inout std_logic;
|
||||
DTACK: inout std_logic ;
|
||||
AVEC: out std_logic ;
|
||||
E: out std_logic ;
|
||||
VPA: in std_logic ;
|
||||
VMA: out std_logic ;
|
||||
RST: in std_logic ;
|
||||
RESET: out std_logic ;
|
||||
RW: inout std_logic ;
|
||||
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||
FC: in std_logic_vector ( 1 downto 0 );
|
||||
AMIGA_ADDR_ENABLE: out std_logic ;
|
||||
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||
AMIGA_BUS_ENABLE_HIGH: out std_logic;
|
||||
CIIN: out std_logic
|
||||
);
|
||||
end BUS68030;
|
||||
|
||||
architecture Behavioral of BUS68030 is
|
||||
|
||||
|
||||
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||
|
||||
constant E1 : ESTATE := "0110";
|
||||
constant E2 : ESTATE := "0111";
|
||||
constant E3 : ESTATE := "0100";
|
||||
constant E4 : ESTATE := "0101";
|
||||
constant E5 : ESTATE := "0010";
|
||||
constant E6 : ESTATE := "0011";
|
||||
constant E7 : ESTATE := "1010";
|
||||
constant E8 : ESTATE := "1011";
|
||||
constant E9 : ESTATE := "1100";
|
||||
constant E10 : ESTATE := "1111";
|
||||
-- Illegal states
|
||||
constant E20 : ESTATE := "0000";
|
||||
constant E4a : ESTATE := "0001";
|
||||
constant E21 : ESTATE := "1000";
|
||||
constant E22 : ESTATE := "1001";
|
||||
constant E23 : ESTATE := "1101";
|
||||
constant E24 : ESTATE := "1110";
|
||||
|
||||
signal cpu_est : ESTATE;
|
||||
|
||||
subtype AMIGA_STATE is std_logic_vector(2 downto 0);
|
||||
|
||||
constant IDLE_P : AMIGA_STATE := "000";
|
||||
constant IDLE_N : AMIGA_STATE := "001";
|
||||
constant AS_SET_P : AMIGA_STATE := "010";
|
||||
constant AS_SET_N : AMIGA_STATE := "011";
|
||||
constant SAMPLE_DTACK_P: AMIGA_STATE := "100";
|
||||
constant DATA_FETCH_N: AMIGA_STATE := "101";
|
||||
constant DATA_FETCH_P : AMIGA_STATE := "110";
|
||||
constant END_CYCLE_N : AMIGA_STATE := "111";
|
||||
|
||||
signal SM_AMIGA : AMIGA_STATE;
|
||||
|
||||
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
signal AS_000_INT:STD_LOGIC := '1';
|
||||
signal RW_000_INT:STD_LOGIC := '1';
|
||||
signal AMIGA_BUS_ENABLE_INT:STD_LOGIC := '1';
|
||||
signal AS_030_D0:STD_LOGIC := '1';
|
||||
signal DS_030_D0:STD_LOGIC := '1';
|
||||
signal AS_030_000_SYNC:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT_D:STD_LOGIC := '1';
|
||||
signal AS_000_DMA:STD_LOGIC := '1';
|
||||
signal DS_000_DMA:STD_LOGIC := '1';
|
||||
signal RW_000_DMA:STD_LOGIC := '1';
|
||||
signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||
signal A0_DMA: STD_LOGIC := '1';
|
||||
signal VMA_INT: STD_LOGIC := '1';
|
||||
signal VPA_D: STD_LOGIC := '1';
|
||||
signal UDS_000_INT: STD_LOGIC := '1';
|
||||
signal LDS_000_INT: STD_LOGIC := '1';
|
||||
signal DS_000_ENABLE: STD_LOGIC := '0';
|
||||
signal DSACK1_INT: STD_LOGIC := '1';
|
||||
signal CLK_CNT_P: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_CNT_N: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
|
||||
signal CLK_OUT_PRE_50: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_50_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_25: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_33: STD_LOGIC := '1';
|
||||
signal CLK_PRE_66:STD_LOGIC := '0';
|
||||
signal CLK_OUT_PRE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_NE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_INT: STD_LOGIC := '1';
|
||||
signal CLK_030_H: STD_LOGIC := '1';
|
||||
signal CLK_000_D0: STD_LOGIC := '1';
|
||||
signal CLK_000_D1: STD_LOGIC := '1';
|
||||
signal CLK_000_D2: STD_LOGIC := '1';
|
||||
signal CLK_000_D3: STD_LOGIC := '1';
|
||||
signal CLK_000_D4: STD_LOGIC := '1';
|
||||
signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
|
||||
signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
|
||||
signal CLK_000_PE: STD_LOGIC := '0';
|
||||
signal CLK_000_NE: STD_LOGIC := '0';
|
||||
signal CLK_000_E_ADVANCE: STD_LOGIC := '0';
|
||||
signal DTACK_D0: STD_LOGIC := '1';
|
||||
|
||||
begin
|
||||
|
||||
|
||||
--the clocks
|
||||
neg_clk: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_CNT_N <= "10";
|
||||
elsif(falling_edge(CLK_OSZI)) then
|
||||
if(CLK_CNT_N = "10") then
|
||||
CLK_CNT_N <= "00";
|
||||
else
|
||||
CLK_CNT_N <= CLK_CNT_N+1;
|
||||
end if;
|
||||
end if;
|
||||
end process neg_clk;
|
||||
--the state machine
|
||||
state_machine: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_CNT_P <= "00";
|
||||
RESET <= '0';
|
||||
CLK_OUT_PRE_50 <= '0';
|
||||
CLK_OUT_PRE_50_D <= '0';
|
||||
--CLK_OUT_PRE_33 <= '0';
|
||||
CLK_OUT_PRE_25 <= '0';
|
||||
CLK_OUT_PRE <= '0';
|
||||
CLK_OUT_PRE_D <= '0';
|
||||
CLK_OUT_NE <= '0';
|
||||
CLK_OUT_INT <= '0';
|
||||
cpu_est <= E20;
|
||||
CLK_000_D0 <= '1';
|
||||
CLK_000_D1 <= '1';
|
||||
CLK_000_D2 <= '1';
|
||||
CLK_000_D3 <= '1';
|
||||
CLK_000_D4 <= '1';
|
||||
VPA_D <= '1';
|
||||
DTACK_D0 <= '1';
|
||||
SM_AMIGA <= IDLE_P;
|
||||
AS_000_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
RW_000_DMA <= '1';
|
||||
AS_030_000_SYNC <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
CLK_REF <= "00";
|
||||
VMA_INT <= '1';
|
||||
BG_000 <= '1';
|
||||
BGACK_030_INT <= '1';
|
||||
BGACK_030_INT_D <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
IPL_030 <= "111";
|
||||
CLK_000_P_SYNC <= "0000000000000";
|
||||
CLK_000_N_SYNC <= "0000000000000";
|
||||
CLK_000_PE <= '0';
|
||||
CLK_000_NE <= '0';
|
||||
CLK_000_E_ADVANCE <= '0';
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "11";
|
||||
A0_DMA <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
AS_030_D0 <= '1';
|
||||
DS_030_D0 <= '1';
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
--reset buffer
|
||||
RESET <= '1';
|
||||
|
||||
--clk generation :
|
||||
|
||||
CLK_OUT_PRE_50 <= not CLK_OUT_PRE_50;
|
||||
CLK_OUT_PRE_50_D<= CLK_OUT_PRE_50;
|
||||
if(CLK_CNT_P = "10") then
|
||||
CLK_CNT_P <= "00";
|
||||
else
|
||||
CLK_CNT_P <= CLK_CNT_P+1;
|
||||
end if;
|
||||
|
||||
--if(CLK_CNT_P ="00" or CLK_CNT_N ="00")then --33MHz Clock
|
||||
-- CLK_OUT_PRE_33 <= '0';
|
||||
--else
|
||||
-- CLK_OUT_PRE_33 <= '1';
|
||||
--end if;
|
||||
|
||||
if(CLK_OUT_PRE_50='1' and CLK_OUT_PRE_50_D='0')then
|
||||
CLK_OUT_PRE_25 <= not CLK_OUT_PRE_25;
|
||||
end if;
|
||||
|
||||
--here the clock is selected
|
||||
CLK_OUT_PRE <= CLK_OUT_PRE_25;
|
||||
CLK_OUT_PRE_D <= CLK_OUT_PRE;
|
||||
|
||||
--a negative edge is comming next cycle
|
||||
if(CLK_OUT_PRE_D='1' and CLK_OUT_PRE='0' )then
|
||||
CLK_OUT_NE <= '1';
|
||||
else
|
||||
CLK_OUT_NE <= '0';
|
||||
end if;
|
||||
-- the external clock to the processor is generated here
|
||||
CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
|
||||
--delayed Clocks and signals for edge detection
|
||||
CLK_000_D0 <= CLK_000;
|
||||
CLK_000_D1 <= CLK_000_D0;
|
||||
CLK_000_D2 <= CLK_000_D1;
|
||||
CLK_000_D3 <= CLK_000_D2;
|
||||
CLK_000_D4 <= CLK_000_D3;
|
||||
|
||||
--shift registers for edge detection
|
||||
CLK_000_P_SYNC( 12 downto 1 ) <= CLK_000_P_SYNC( 11 downto 0 );
|
||||
CLK_000_P_SYNC(0) <= CLK_000_D0 AND NOT CLK_000_D1;
|
||||
CLK_000_N_SYNC( 12 downto 1 ) <= CLK_000_N_SYNC( 11 downto 0 );
|
||||
CLK_000_N_SYNC(0) <= NOT CLK_000_D0 AND CLK_000_D1;
|
||||
|
||||
-- values are determined empiracally for 7.09 MHz Clock
|
||||
-- since the clock is not symmetrically these values differ!
|
||||
CLK_000_PE <= CLK_000_P_SYNC(9);
|
||||
CLK_000_NE <= CLK_000_N_SYNC(11);
|
||||
CLK_000_E_ADVANCE <= CLK_000_NE;
|
||||
DTACK_D0 <= DTACK;
|
||||
VPA_D <= VPA;
|
||||
|
||||
--now: 68000 state machine and signals
|
||||
|
||||
-- e-clock is changed on the FALLING edge!
|
||||
|
||||
if(CLK_000_E_ADVANCE = '1' ) then
|
||||
case (cpu_est) is
|
||||
when E1 => cpu_est <= E2 ;
|
||||
when E2 => cpu_est <= E3 ;
|
||||
when E3 => cpu_est <= E4;
|
||||
when E4 => cpu_est <= E5 ;
|
||||
when E5 => cpu_est <= E6 ;
|
||||
when E6 => cpu_est <= E7 ;
|
||||
when E7 => cpu_est <= E8 ;
|
||||
when E8 => cpu_est <= E9 ;
|
||||
when E9 => cpu_est <= E10;
|
||||
when E10 => cpu_est <= E1 ;
|
||||
-- Illegal states
|
||||
when E4a => cpu_est <= E5 ;
|
||||
when E20 => cpu_est <= E10;
|
||||
when E21 => cpu_est <= E10;
|
||||
when E22 => cpu_est <= E9 ;
|
||||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
AS_030_D0 <= AS_030;
|
||||
DS_030_D0 <= DS_030;
|
||||
|
||||
|
||||
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif ( BGACK_000='1'
|
||||
AND CLK_000_PE='1'
|
||||
--AND CLK_000_D1='0' and CLK_000_D0='1'
|
||||
) then -- BGACK_000 is high here!
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
BGACK_030_INT_D <= BGACK_030_INT;
|
||||
|
||||
|
||||
|
||||
--bus grant only in idle state
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
|
||||
and nEXP_SPACE = '1' and AS_030_D0='1'
|
||||
and CLK_000_D0='1'
|
||||
--and CLK_000_D0='1' AND CLK_000_D1='0'
|
||||
) then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
--interrupt buffering to avoid ghost interrupts
|
||||
--if(CLK_000_NE='1')then
|
||||
if(CLK_000_D0='0' and CLK_000_D1='1')then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
|
||||
-- as030-sampling and FPU-Select
|
||||
|
||||
|
||||
if(AS_030_D0 ='1' or BERR='0') then -- "async" reset of various signals
|
||||
AS_030_000_SYNC <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
AS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||
AS_030_D0 = '0' AND --as set
|
||||
BGACK_000='1' AND --no dma -cycle
|
||||
NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
|
||||
nEXP_SPACE ='1' and --not an expansion space cycle
|
||||
SM_AMIGA = IDLE_P --last amiga cycle terminated
|
||||
) then
|
||||
AS_030_000_SYNC <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
-- VMA generation
|
||||
if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
VMA_INT <= '0';
|
||||
--elsif(CLK_000_PE='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert
|
||||
|
||||
end if;
|
||||
|
||||
--uds/lds precalculation
|
||||
if (DS_030_D0 = '0') then --DS: set udl/lds
|
||||
if(A0='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
--Amiga statemachine
|
||||
|
||||
if(BERR='0')then --"async" reset on errors
|
||||
SM_AMIGA<=IDLE_P;
|
||||
end if;
|
||||
|
||||
case (SM_AMIGA) is
|
||||
when IDLE_P => --68000:S0 wait for a falling edge
|
||||
|
||||
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0')then
|
||||
if(nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
|
||||
SM_AMIGA<=IDLE_N; --go to s1
|
||||
end if;
|
||||
end if;
|
||||
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
||||
--if(CLK_000_PE='1')then --go to s2
|
||||
if(CLK_000_D0='1')then --go to s2
|
||||
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||
AS_000_INT <= '0';
|
||||
RW_000_INT <= RW;
|
||||
if (RW='1' ) then --read: set udl/lds
|
||||
DS_000_ENABLE <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
|
||||
if(CLK_000_NE='1')then --go to s3
|
||||
--if(CLK_000_D0='0')then --go to s3
|
||||
SM_AMIGA<=AS_SET_N;
|
||||
end if;
|
||||
when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
|
||||
|
||||
if(CLK_000_PE='1')then --go to s4
|
||||
--if(CLK_000_D0='1')then --go to s4
|
||||
DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
|
||||
-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
|
||||
SM_AMIGA <= SAMPLE_DTACK_P;
|
||||
end if;
|
||||
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
|
||||
if( CLK_000_NE='1' and --falling edge
|
||||
--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
|
||||
((VPA = '1' AND DTACK='0') OR --DTACK end cycle
|
||||
(VPA='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
|
||||
)then --go to s5
|
||||
SM_AMIGA<=DATA_FETCH_N;
|
||||
end if;
|
||||
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||
if(CLK_000_PE = '1')then --go to s6
|
||||
--if(CLK_000_D0='1')then --go to s6
|
||||
SM_AMIGA<=DATA_FETCH_P;
|
||||
end if;
|
||||
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
|
||||
if( (CLK_000_N_SYNC( 5)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
|
||||
(CLK_000_N_SYNC( 6)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
|
||||
DSACK1_INT <='0';
|
||||
end if;
|
||||
--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
-- DSACK1_INT <='0';
|
||||
--end if;
|
||||
if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
|
||||
SM_AMIGA<=END_CYCLE_N;
|
||||
end if;
|
||||
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
|
||||
if(CLK_000_PE='1')then --go to s0
|
||||
--if(CLK_000_D0='1')then --go to s0
|
||||
SM_AMIGA<=IDLE_P;
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
end case;
|
||||
|
||||
if(BGACK_030_INT='0')then
|
||||
--switch amiga bus on for DMA-Cycles
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;
|
||||
elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then
|
||||
AMIGA_BUS_ENABLE_INT <= '1' ;
|
||||
end if;
|
||||
|
||||
--dma stuff
|
||||
--as can only be done if we know the uds/lds!
|
||||
if(BGACK_030_INT='0' and AS_000='0' and (UDS_000='0' or LDS_000='0'))then
|
||||
|
||||
--set AS_000
|
||||
if( CLK_030='1') then
|
||||
AS_000_DMA <= '0'; --sampled on rising edges!
|
||||
RW_000_DMA <= RW_000;
|
||||
elsif(AS_000_DMA = '0' and CLK_030='0')then
|
||||
CLK_030_H <= '1';
|
||||
end if;
|
||||
|
||||
if(RW_000='1') then
|
||||
DS_000_DMA <=AS_000_DMA;
|
||||
elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then
|
||||
DS_000_DMA <=AS_000_DMA; -- write: one clock delayed!
|
||||
end if;
|
||||
-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
|
||||
if(UDS_000='0' and LDS_000='0') then
|
||||
SIZE_DMA <= "10"; --16bit
|
||||
else
|
||||
SIZE_DMA <= "01"; --8 bit
|
||||
end if;
|
||||
|
||||
--now calculate the offset:
|
||||
--if uds is set low, a0 is so too.
|
||||
--if only lds is set a1 is high
|
||||
--therefore a1 = uds
|
||||
--great! life is simple here!
|
||||
A0_DMA <= UDS_000;
|
||||
|
||||
--A1 is set by the amiga side
|
||||
else
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "11";
|
||||
A0_DMA <= '0';
|
||||
RW_000_DMA <= '1';
|
||||
CLK_030_H <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process state_machine;
|
||||
|
||||
CLK_PRE_66 <= (not CLK_CNT_N(0) and CLK_CNT_P(0)) or
|
||||
(CLK_CNT_N(1) and CLK_CNT_P(1));
|
||||
|
||||
process_33_clk:process(RST, CLK_PRE_66)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
CLK_OUT_PRE_33 <= '0';
|
||||
elsif(rising_edge(CLK_PRE_66)) then
|
||||
CLK_OUT_PRE_33 <= not CLK_OUT_PRE_33;
|
||||
end if;
|
||||
end process process_33_clk;
|
||||
|
||||
|
||||
|
||||
--output clock assignment
|
||||
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||
CLK_EXP <= CLK_OUT_INT;
|
||||
|
||||
-- bus drivers
|
||||
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
|
||||
AMIGA_BUS_ENABLE_HIGH <= AMIGA_BUS_ENABLE_INT;
|
||||
AMIGA_BUS_ENABLE_LOW <= '1';
|
||||
AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
|
||||
'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
|
||||
'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
|
||||
'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
|
||||
'0'; --Point towarts TK
|
||||
|
||||
|
||||
--dma stuff
|
||||
DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
DSACK1;
|
||||
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
AS_000_DMA;
|
||||
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
DS_000_DMA;
|
||||
A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
A0_DMA;
|
||||
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
|
||||
SIZE_DMA;
|
||||
|
||||
--fpu
|
||||
FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0'
|
||||
else '1';
|
||||
|
||||
--if no copro is installed:
|
||||
BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1'
|
||||
else 'Z';
|
||||
--BERR <= 'Z';
|
||||
|
||||
|
||||
|
||||
--cache inhibit: Tristate for expansion (it decides) and off for the Amiga
|
||||
CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
|
||||
'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE = '0' ELSE --Tristate for expansion (it decides)
|
||||
'0'; --off for the Amiga
|
||||
|
||||
|
||||
--e and VMA
|
||||
E <= cpu_est(3);
|
||||
VMA <= VMA_INT;
|
||||
|
||||
|
||||
--AVEC
|
||||
AVEC <= '1';
|
||||
|
||||
--as and uds/lds
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
AS_000_INT;
|
||||
RW_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
RW_000_INT;
|
||||
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
'1' when DS_000_ENABLE ='0' else -- datastrobe not ready jet
|
||||
UDS_000_INT;
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
'1' when DS_000_ENABLE ='0' else -- datastrobe not ready jet
|
||||
LDS_000_INT;
|
||||
|
||||
--dsack
|
||||
DSACK1 <= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle
|
||||
DSACK1_INT;
|
||||
--rw
|
||||
RW <= 'Z' when BGACK_030_INT ='1' else
|
||||
RW_000_DMA;
|
||||
|
||||
BGACK_030 <= BGACK_030_INT;
|
||||
end Behavioral;
|
||||
|
|
@ -145,9 +145,6 @@ signal RESET_DLY: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000";
|
|||
|
||||
begin
|
||||
|
||||
|
||||
|
||||
|
||||
--pos edge clock
|
||||
pos_clk: process(CLK_OSZI)
|
||||
begin
|
||||
|
|
@ -215,7 +212,7 @@ begin
|
|||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
cpu_est <= E10;
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
|
|
@ -380,13 +377,13 @@ begin
|
|||
if(CLK_000_PE='1')then --go to s2
|
||||
--if(CLK_000_D0='1')then --go to s2
|
||||
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||
AS_000_INT <= '0';
|
||||
RW_000_INT <= RW;
|
||||
if (RW='1' ) then --read: set udl/lds
|
||||
DS_000_ENABLE <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
|
||||
RW_000_INT <= RW;
|
||||
AS_000_INT <= '0';
|
||||
if (RW='1' ) then --read: set udl/lds
|
||||
DS_000_ENABLE <= '1';
|
||||
end if;
|
||||
if(CLK_000_NE='1')then --go to s3
|
||||
--if(CLK_000_D0='0')then --go to s3
|
||||
SM_AMIGA<=AS_SET_N;
|
||||
|
|
@ -395,11 +392,11 @@ begin
|
|||
|
||||
if(CLK_000_PE='1')then --go to s4
|
||||
--if(CLK_000_D0='1')then --go to s4
|
||||
DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
|
||||
-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
|
||||
SM_AMIGA <= SAMPLE_DTACK_P;
|
||||
end if;
|
||||
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
|
||||
DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
|
||||
if( CLK_000_NE='1' and --falling edge
|
||||
--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
|
||||
((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
|
||||
|
|
@ -494,7 +491,7 @@ begin
|
|||
|
||||
-- bus drivers
|
||||
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
|
||||
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' ELSE
|
||||
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P) ELSE
|
||||
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
|
||||
'1';
|
||||
AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE
|
||||
|
|
|
|||
|
|
@ -1,4 +1,10 @@
|
|||
[STRATEGY-LIST]
|
||||
<<<<<<< HEAD
|
||||
Normal=True, 1412327082
|
||||
=======
|
||||
Normal=True, 1385910337
|
||||
[TOUCHED-REPORT]
|
||||
Design.tt4File=1410033670
|
||||
>>>>>>> parent of a42d9d7... More stability in constraints
|
||||
[synthesis-type]
|
||||
tool=Synplify
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
MAIN_WINDOW_POSITION=0,185,1920,1200
|
||||
LEFT_PANE_WIDTH=634
|
||||
CHILD_FRAME_STATE=Maximal
|
||||
CHILD_WINDOW_SIZE=1920,789
|
||||
CHILD_WINDOW_SIZE=1920,790
|
||||
CHILD_WINDOW_POS=-8,-30
|
||||
[GUI SETTING]
|
||||
Remember_Setting=1
|
||||
|
|
@ -18,7 +18,7 @@ Sort_Type=0
|
|||
Sort_Direction=0
|
||||
Skip_Next_Pin=0
|
||||
[Pin Attributes]
|
||||
sort_column_-1=Slewrate
|
||||
sort_column_-1=Pin
|
||||
Type=42,no
|
||||
Signal/Group Name=209,no
|
||||
Group Members=111,no
|
||||
|
|
@ -40,9 +40,9 @@ State=43,no
|
|||
Constraint Name=162,no
|
||||
Constraint Value=115,no
|
||||
[OPT WINDOWS]
|
||||
MAIN_WINDOW_POSITION=-32000,-32000,-31840,-31973
|
||||
MAIN_WINDOW_POSITION=0,0,1928,1168
|
||||
CHILD_FRAME_STATE=Maximal
|
||||
CHILD_WINDOW_SIZE=1907,934
|
||||
CHILD_WINDOW_SIZE=1928,942
|
||||
CHILD_WINDOW_POS=-8,-30
|
||||
[OPT GUI SETTING]
|
||||
Remember_Setting=1
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
|
|||
|
||||
[Revision]
|
||||
Parent = m4a5.lci;
|
||||
DATE = 10/02/2014;
|
||||
TIME = 23:53:03;
|
||||
DATE = 09/06/2014;
|
||||
TIME = 22:01:10;
|
||||
Source_Format = Pure_VHDL;
|
||||
Synthesis = Synplify;
|
||||
|
||||
|
|
@ -69,6 +69,7 @@ IPL_030_1_ = Pin, 7, -, B, -;
|
|||
IPL_030_2_ = Pin, 9, -, B, -;
|
||||
LDS_000 = Pin, 31, -, D, -;
|
||||
UDS_000 = Pin, 32, -, D, -;
|
||||
VMA = Pin, 35, -, D, -;
|
||||
DTACK = Pin, 30, -, D, -;
|
||||
RESET = Pin, 3, -, B, -;
|
||||
AMIGA_BUS_DATA_DIR = Pin, 48, -, E, -;
|
||||
|
|
@ -97,7 +98,6 @@ AMIGA_BUS_ENABLE_HIGH = Pin, 34, -, D, -;
|
|||
A_23_ = Pin, 85, -, H, -;
|
||||
FPU_SENSE = Pin, 91, -, A, -;
|
||||
A1 = Pin, 60, -, F, -;
|
||||
VMA = Pin, 35, -, D, -;
|
||||
|
||||
[Group Assignments]
|
||||
layer = OFF;
|
||||
|
|
@ -129,11 +129,8 @@ layer = OFF;
|
|||
Default = UP;
|
||||
|
||||
[Slewrate]
|
||||
SLOW = E, VMA;
|
||||
FAST = AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH,
|
||||
AVEC, BG_000, LDS_000, UDS_000, DTACK, RW_000, AS_000, CLK_DIV_OUT, CLK_EXP,
|
||||
FPU_CS, AS_030, RW, SIZE_1_, SIZE_0_, BGACK_030, IPL_030_0_, IPL_030_1_,
|
||||
IPL_030_2_, RESET, CIIN, DS_030, BERR, A0, DSACK1;
|
||||
FAST = CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
|
||||
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
|
||||
Default = Slow;
|
||||
|
||||
[Region]
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
|
|||
|
||||
[Revision]
|
||||
Parent = m4a5.lci;
|
||||
DATE = 10/02/2014;
|
||||
TIME = 23:53:03;
|
||||
DATE = 09/06/2014;
|
||||
TIME = 22:01:10;
|
||||
Source_Format = Pure_VHDL;
|
||||
Synthesis = Synplify;
|
||||
|
||||
|
|
@ -69,6 +69,7 @@ IPL_030_1_ = Pin, 7, -, B, -;
|
|||
IPL_030_2_ = Pin, 9, -, B, -;
|
||||
LDS_000 = Pin, 31, -, D, -;
|
||||
UDS_000 = Pin, 32, -, D, -;
|
||||
VMA = Pin, 35, -, D, -;
|
||||
DTACK = Pin, 30, -, D, -;
|
||||
RESET = Pin, 3, -, B, -;
|
||||
AMIGA_BUS_DATA_DIR = Pin, 48, -, E, -;
|
||||
|
|
@ -97,7 +98,6 @@ AMIGA_BUS_ENABLE_HIGH = Pin, 34, -, D, -;
|
|||
A_23_ = Pin, 85, -, H, -;
|
||||
FPU_SENSE = Pin, 91, -, A, -;
|
||||
A1 = Pin, 60, -, F, -;
|
||||
VMA = Pin, 35, -, D, -;
|
||||
|
||||
[Group Assignments]
|
||||
layer = OFF;
|
||||
|
|
@ -129,11 +129,8 @@ layer = OFF;
|
|||
Default = UP;
|
||||
|
||||
[Slewrate]
|
||||
SLOW = E, VMA;
|
||||
FAST = AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH,
|
||||
AVEC, BG_000, LDS_000, UDS_000, DTACK, RW_000, AS_000, CLK_DIV_OUT, CLK_EXP,
|
||||
FPU_CS, AS_030, RW, SIZE_1_, SIZE_0_, BGACK_030, IPL_030_0_, IPL_030_1_,
|
||||
IPL_030_2_, RESET, CIIN, DS_030, BERR, A0, DSACK1;
|
||||
FAST = CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
|
||||
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
|
||||
Default = Slow;
|
||||
|
||||
[Region]
|
||||
|
|
|
|||
2732
Logic/68030_TK.tcl
2732
Logic/68030_TK.tcl
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
// Signal Name Cross Reference File
|
||||
// ispLEVER Classic 1.7.00.05.28.13
|
||||
|
||||
// Design '68030_tk' created Fri Oct 10 22:40:03 2014
|
||||
// Design '68030_tk' created Thu Oct 16 21:59:11 2014
|
||||
|
||||
|
||||
// LEGEND: '>' Functional Block Port Separator
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
|
||||
GROUP MACH_SEG_A DS_030 RN_DS_030 inst_CLK_030_H inst_LDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_UDS_000_INT AVEC CLK_000_N_SYNC_11_
|
||||
CLK_000_P_SYNC_2_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_8_
|
||||
GROUP MACH_SEG_B RESET RN_RESET IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_
|
||||
IPL_030_2_ RN_IPL_030_2_ RESET_DLY_7_ RESET_DLY_6_ inst_nEXP_SPACE_D0
|
||||
CLK_EXP CLK_000_P_SYNC_1_ CLK_000_P_SYNC_4_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_5_
|
||||
|
||||
GROUP MACH_SEG_C SM_AMIGA_6_ inst_DS_000_ENABLE inst_AS_000_INT SM_AMIGA_4_
|
||||
SM_AMIGA_1_ SM_AMIGA_5_ AMIGA_BUS_ENABLE_LOW sm_amiga_ns_0_3_0__n
|
||||
inst_CLK_000_PE CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_
|
||||
|
||||
GROUP MACH_SEG_D AMIGA_ADDR_ENABLE RN_AMIGA_ADDR_ENABLE VMA RN_VMA BG_000
|
||||
RN_BG_000 inst_DTACK_D0 LDS_000 UDS_000 DTACK AMIGA_BUS_ENABLE_HIGH
|
||||
cpu_est_1_ cpu_est_2_ cpu_est_0_ inst_CLK_000_D0 CLK_000_N_SYNC_4_
|
||||
inst_CLK_000_NE_D0
|
||||
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 CLK_000_P_SYNC_0_
|
||||
CLK_000_N_SYNC_0_ inst_CLK_000_NE CLK_000_N_SYNC_9_ inst_CLK_000_D1
|
||||
|
||||
GROUP MACH_SEG_F SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_7_ RESET_DLY_4_ RESET_DLY_3_
|
||||
RESET_DLY_2_ RESET_DLY_1_ RESET_DLY_0_ SM_AMIGA_0_ inst_VPA_D CLK_000_P_SYNC_8_
|
||||
CLK_000_N_SYNC_7_ CLK_OUT_PRE_Dreg inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE
|
||||
|
||||
GROUP MACH_SEG_G RW RN_RW A0 RESET_DLY_5_ inst_AS_000_DMA SIZE_DMA_1_ SIZE_DMA_0_
|
||||
E RN_E SIZE_0_ CLK_DIV_OUT CLK_000_P_SYNC_9_ CLK_000_P_SYNC_3_ CLK_000_N_SYNC_1_
|
||||
CLK_000_N_SYNC_3_
|
||||
GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030
|
||||
inst_AS_030_000_SYNC inst_DS_030_D0 inst_AS_030_D0 inst_BGACK_030_INT_D
|
||||
FPU_CS SIZE_1_ AS_030 CLK_000_N_SYNC_10_
|
||||
|
|
@ -1 +1 @@
|
|||
<LATTICE_ENCRYPTED_BLIF>31403<4 3 MM6_Y
|
||||
<LATTICE_ENCRYPTED_BLIF>147:<15po'Cb
|
||||
|
|
@ -1,254 +0,0 @@
|
|||
[DEVICE]
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = No;
|
||||
Pin_MC_1to1 = No;
|
||||
EN_PinReserve_IO = Yes;
|
||||
EN_PinReserve_BIDIR = Yes;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
DATE = 10/10/14;
|
||||
TIME = 22:40:09;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
Pin_Block = No;
|
||||
Pin_Macrocell_Block = No;
|
||||
Routing = No;
|
||||
|
||||
[GLOBAL CONSTRAINTS]
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_GLB_Input_Percent = 100;
|
||||
Max_Seg_In_Percent = 100;
|
||||
Logic_Reduction = Yes;
|
||||
XOR_Synthesis = Yes;
|
||||
DT_Synthesis = No;
|
||||
Node_Collapse = Yes;
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = Yes;
|
||||
Clock_Optimize = No;
|
||||
In_Reg_Optimize = Yes;
|
||||
Balanced_Partitioning = Yes;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode = 0;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[LOCATION ASSIGNMENTS]
|
||||
Layer = OFF;
|
||||
A_27_ = pin,16,-,C,-;
|
||||
A_26_ = pin,17,-,C,-;
|
||||
SIZE_1_ = pin,79,-,H,-;
|
||||
A_25_ = pin,18,-,C,-;
|
||||
A_24_ = pin,19,-,C,-;
|
||||
A_31_ = pin,4,-,B,-;
|
||||
A_23_ = pin,85,-,H,-;
|
||||
A_22_ = pin,84,-,H,-;
|
||||
A_21_ = pin,94,-,A,-;
|
||||
A_20_ = pin,93,-,A,-;
|
||||
IPL_2_ = pin,68,-,G,-;
|
||||
A_19_ = pin,97,-,A,-;
|
||||
A_18_ = pin,95,-,A,-;
|
||||
FC_1_ = pin,58,-,F,-;
|
||||
A_17_ = pin,59,-,F,-;
|
||||
AS_030 = pin,82,-,H,-;
|
||||
A_16_ = pin,96,-,A,-;
|
||||
AS_000 = pin,42,-,E,-;
|
||||
IPL_1_ = pin,56,-,F,-;
|
||||
UDS_000 = pin,32,-,D,-;
|
||||
IPL_0_ = pin,67,-,G,-;
|
||||
LDS_000 = pin,31,-,D,-;
|
||||
FC_0_ = pin,57,-,F,-;
|
||||
A1 = pin,60,-,F,-;
|
||||
nEXP_SPACE = pin,14,-,-,-;
|
||||
BERR = pin,41,-,E,-;
|
||||
BG_030 = pin,21,-,C,-;
|
||||
BGACK_000 = pin,28,-,D,-;
|
||||
CLK_030 = pin,64,-,-,-;
|
||||
CLK_000 = pin,11,-,-,-;
|
||||
CLK_OSZI = pin,61,-,-,-;
|
||||
CLK_DIV_OUT = pin,65,-,G,-;
|
||||
CLK_EXP = pin,10,-,B,-;
|
||||
FPU_CS = pin,78,-,H,-;
|
||||
FPU_SENSE = pin,91,-,A,-;
|
||||
DTACK = pin,30,-,D,-;
|
||||
AVEC = pin,92,-,A,-;
|
||||
VPA = pin,36,-,-,-;
|
||||
RST = pin,86,-,-,-;
|
||||
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
|
||||
CIIN = pin,47,-,E,-;
|
||||
SIZE_0_ = pin,70,-,G,-;
|
||||
A_30_ = pin,5,-,B,-;
|
||||
A_29_ = pin,6,-,B,-;
|
||||
A_28_ = pin,15,-,C,-;
|
||||
IPL_030_2_ = pin,9,-,B,-;
|
||||
IPL_030_1_ = pin,7,-,B,-;
|
||||
RW_000 = pin,80,-,H,-;
|
||||
IPL_030_0_ = pin,8,-,B,-;
|
||||
DS_030 = pin,98,-,A,-;
|
||||
A0 = pin,69,-,G,-;
|
||||
BG_000 = pin,29,-,D,-;
|
||||
BGACK_030 = pin,83,-,H,-;
|
||||
DSACK1 = pin,81,-,H,-;
|
||||
E = pin,66,-,G,-;
|
||||
VMA = pin,35,-,D,-;
|
||||
RESET = pin,3,-,B,-;
|
||||
RW = pin,71,-,G,-;
|
||||
AMIGA_ADDR_ENABLE = pin,33,-,D,-;
|
||||
cpu_est_0_ = node,-,-,D,6;
|
||||
cpu_est_1_ = node,-,-,D,13;
|
||||
inst_AS_000_INT = node,-,-,C,9;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,A,13;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,A,9;
|
||||
inst_AS_030_D0 = node,-,-,H,9;
|
||||
inst_nEXP_SPACE_D0 = node,-,-,B,5;
|
||||
inst_DS_030_D0 = node,-,-,H,10;
|
||||
inst_AS_030_000_SYNC = node,-,-,H,13;
|
||||
inst_BGACK_030_INT_D = node,-,-,H,6;
|
||||
inst_AS_000_DMA = node,-,-,G,5;
|
||||
SIZE_DMA_0_ = node,-,-,G,2;
|
||||
SIZE_DMA_1_ = node,-,-,G,9;
|
||||
inst_VPA_D = node,-,-,F,10;
|
||||
inst_UDS_000_INT = node,-,-,A,12;
|
||||
inst_LDS_000_INT = node,-,-,A,8;
|
||||
inst_DTACK_D0 = node,-,-,D,7;
|
||||
RESET_DLY_7_ = node,-,-,B,14;
|
||||
inst_CLK_OUT_PRE_50 = node,-,-,F,11;
|
||||
inst_CLK_000_D1 = node,-,-,E,5;
|
||||
inst_CLK_000_D0 = node,-,-,D,14;
|
||||
sm_amiga_ns_0_3_0__n = node,-,-,C,13;
|
||||
SM_AMIGA_7_ = node,-,-,F,0;
|
||||
inst_CLK_OUT_PRE = node,-,-,F,7;
|
||||
inst_CLK_000_PE = node,-,-,C,4;
|
||||
CLK_000_P_SYNC_9_ = node,-,-,G,3;
|
||||
inst_CLK_000_NE = node,-,-,E,8;
|
||||
CLK_000_N_SYNC_11_ = node,-,-,A,10;
|
||||
cpu_est_2_ = node,-,-,D,2;
|
||||
inst_CLK_000_NE_D0 = node,-,-,D,10;
|
||||
SM_AMIGA_6_ = node,-,-,C,12;
|
||||
SM_AMIGA_4_ = node,-,-,C,5;
|
||||
SM_AMIGA_0_ = node,-,-,F,4;
|
||||
inst_CLK_030_H = node,-,-,A,5;
|
||||
CLK_000_P_SYNC_0_ = node,-,-,E,6;
|
||||
CLK_000_P_SYNC_1_ = node,-,-,B,10;
|
||||
CLK_000_P_SYNC_2_ = node,-,-,A,6;
|
||||
CLK_000_P_SYNC_3_ = node,-,-,G,14;
|
||||
CLK_000_P_SYNC_4_ = node,-,-,B,6;
|
||||
CLK_000_P_SYNC_5_ = node,-,-,C,14;
|
||||
CLK_000_P_SYNC_6_ = node,-,-,C,10;
|
||||
CLK_000_P_SYNC_7_ = node,-,-,C,6;
|
||||
CLK_000_P_SYNC_8_ = node,-,-,F,3;
|
||||
CLK_000_N_SYNC_0_ = node,-,-,E,2;
|
||||
CLK_000_N_SYNC_1_ = node,-,-,G,10;
|
||||
CLK_000_N_SYNC_2_ = node,-,-,B,2;
|
||||
CLK_000_N_SYNC_3_ = node,-,-,G,6;
|
||||
CLK_000_N_SYNC_4_ = node,-,-,D,3;
|
||||
CLK_000_N_SYNC_5_ = node,-,-,B,13;
|
||||
CLK_000_N_SYNC_6_ = node,-,-,A,2;
|
||||
CLK_000_N_SYNC_7_ = node,-,-,F,14;
|
||||
CLK_000_N_SYNC_8_ = node,-,-,A,1;
|
||||
CLK_000_N_SYNC_9_ = node,-,-,E,13;
|
||||
CLK_000_N_SYNC_10_ = node,-,-,H,2;
|
||||
RESET_DLY_0_ = node,-,-,F,13;
|
||||
RESET_DLY_1_ = node,-,-,F,9;
|
||||
RESET_DLY_2_ = node,-,-,F,5;
|
||||
RESET_DLY_3_ = node,-,-,F,1;
|
||||
RESET_DLY_4_ = node,-,-,F,12;
|
||||
RESET_DLY_5_ = node,-,-,G,13;
|
||||
RESET_DLY_6_ = node,-,-,B,9;
|
||||
inst_DS_000_ENABLE = node,-,-,C,1;
|
||||
SM_AMIGA_1_ = node,-,-,C,8;
|
||||
SM_AMIGA_5_ = node,-,-,C,2;
|
||||
SM_AMIGA_3_ = node,-,-,F,2;
|
||||
SM_AMIGA_2_ = node,-,-,F,6;
|
||||
CLK_OUT_PRE_Dreg = node,-,-,F,8;
|
||||
CIIN_0 = node,-,-,E,9;
|
||||
|
||||
[GROUP ASSIGNMENTS]
|
||||
Layer = OFF;
|
||||
|
||||
[RESOURCE RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[SLEWRATE]
|
||||
Default = SLOW;
|
||||
FAST = AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH,AVEC,BG_000,LDS_000,UDS_000,DTACK,RW_000,AS_000,CLK_DIV_OUT,CLK_EXP,FPU_CS,AS_030,RW,SIZE_1_,SIZE_0_,BGACK_030,IPL_030_0_,IPL_030_1_,IPL_030_2_,RESET,CIIN,DS_030,BERR,A0,DSACK1;
|
||||
|
||||
[PULLUP]
|
||||
Default = Up;
|
||||
|
||||
[NETLIST/DELAY FORMAT]
|
||||
Delay_File = SDF;
|
||||
Netlist = VHDL;
|
||||
|
||||
[OSM BYPASS]
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
Fitter_Options = Yes;
|
||||
Pinout_Diagram = No;
|
||||
Pinout_Listing = Yes;
|
||||
Detailed_Block_Segment_Summary = Yes;
|
||||
Input_Signal_List = Yes;
|
||||
Output_Signal_List = Yes;
|
||||
Bidir_Signal_List = Yes;
|
||||
Node_Signal_List = Yes;
|
||||
Signal_Fanout_List = Yes;
|
||||
Block_Segment_Fanin_List = Yes;
|
||||
Postfit_Eqn = Yes;
|
||||
Prefit_Eqn = Yes;
|
||||
Page_Break = Yes;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low,High;
|
||||
Default = High;
|
||||
Low = H,G,F,E,D,C,B,A;
|
||||
Type = GLB;
|
||||
|
||||
[SOURCE CONSTRAINT OPTION]
|
||||
|
||||
[TIMING ANALYZER]
|
||||
Last_source=;
|
||||
Last_source_type=Fmax;
|
||||
|
||||
|
|
@ -1,166 +0,0 @@
|
|||
|--------------------------------------------|
|
||||
|- ispLEVER Fitter Report File -|
|
||||
|- Version 1.7.00.05.28.13 -|
|
||||
|- (c)Copyright, Lattice Semiconductor 2002 -|
|
||||
|--------------------------------------------|
|
||||
|
||||
|
||||
; Source file 68030_tk.tt4
|
||||
; FITTER-generated Placements.
|
||||
; DEVICE mach447a
|
||||
; DATE Fri Oct 10 22:40:09 2014
|
||||
|
||||
|
||||
Pin 16 A_27_
|
||||
Pin 17 A_26_
|
||||
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 271
|
||||
Pin 18 A_25_
|
||||
Pin 19 A_24_
|
||||
Pin 4 A_31_
|
||||
Pin 85 A_23_
|
||||
Pin 84 A_22_
|
||||
Pin 94 A_21_
|
||||
Pin 93 A_20_
|
||||
Pin 68 IPL_2_
|
||||
Pin 97 A_19_
|
||||
Pin 95 A_18_
|
||||
Pin 58 FC_1_
|
||||
Pin 59 A_17_
|
||||
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
|
||||
Pin 96 A_16_
|
||||
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
|
||||
Pin 56 IPL_1_
|
||||
Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185
|
||||
Pin 67 IPL_0_
|
||||
Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
|
||||
Pin 57 FC_0_
|
||||
Pin 60 A1
|
||||
Pin 14 nEXP_SPACE
|
||||
Pin 41 BERR Comb ; S6=1 S9=1 Pair 197
|
||||
Pin 21 BG_030
|
||||
Pin 28 BGACK_000
|
||||
Pin 64 CLK_030
|
||||
Pin 11 CLK_000
|
||||
Pin 61 CLK_OSZI
|
||||
Pin 65 CLK_DIV_OUT Comb ; S6=1 S9=1 Pair 247
|
||||
Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 127
|
||||
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 277
|
||||
Pin 91 FPU_SENSE
|
||||
Pin 30 DTACK Comb ; S6=1 S9=1 Pair 173
|
||||
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
|
||||
Pin 36 VPA
|
||||
Pin 86 RST
|
||||
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199
|
||||
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149
|
||||
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 187
|
||||
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
|
||||
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
|
||||
Pin 5 A_30_
|
||||
Pin 6 A_29_
|
||||
Pin 15 A_28_
|
||||
Pin 9 IPL_030_2_ Reg ; S6=0 S9=1 Pair 131
|
||||
Pin 7 IPL_030_1_ Reg ; S6=0 S9=1 Pair 143
|
||||
Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269
|
||||
Pin 8 IPL_030_0_ Reg ; S6=0 S9=1 Pair 137
|
||||
Pin 98 DS_030 Reg ; S6=1 S9=1 Pair 101
|
||||
Pin 69 A0 Reg ; S6=1 S9=1 Pair 257
|
||||
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
|
||||
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
|
||||
Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 287
|
||||
Pin 66 E Reg ; S6=1 S9=1 Pair 251
|
||||
Pin 35 VMA Reg ; S6=1 S9=1 Pair 179
|
||||
Pin 3 RESET Reg ; S6=1 S9=1 Pair 125
|
||||
Pin 71 RW Reg ; S6=1 S9=1 Pair 245
|
||||
Pin 33 AMIGA_ADDR_ENABLE Reg ; S6=1 S9=1 Pair 181
|
||||
Node 271 RN_SIZE_1_ Comb ; S6=1 S9=1
|
||||
Node 281 RN_AS_030 Comb ; S6=1 S9=1
|
||||
Node 203 RN_AS_000 Comb ; S6=1 S9=1
|
||||
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
|
||||
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
|
||||
Node 197 RN_BERR Comb ; S6=1 S9=1
|
||||
Node 173 RN_DTACK Comb ; S6=1 S9=1
|
||||
Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1
|
||||
Node 131 RN_IPL_030_2_ Reg ; S6=0 S9=1
|
||||
Node 143 RN_IPL_030_1_ Reg ; S6=0 S9=1
|
||||
Node 269 RN_RW_000 Reg ; S6=1 S9=1
|
||||
Node 137 RN_IPL_030_0_ Reg ; S6=0 S9=1
|
||||
Node 101 RN_DS_030 Reg ; S6=1 S9=1
|
||||
Node 257 RN_A0 Reg ; S6=1 S9=1
|
||||
Node 175 RN_BG_000 Reg ; S6=1 S9=1
|
||||
Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
|
||||
Node 287 RN_DSACK1 Reg ; S6=1 S9=1
|
||||
Node 251 RN_E Reg ; S6=1 S9=1
|
||||
Node 179 RN_VMA Reg ; S6=1 S9=1
|
||||
Node 125 RN_RESET Reg ; S6=1 S9=1
|
||||
Node 245 RN_RW Reg ; S6=1 S9=1
|
||||
Node 181 RN_AMIGA_ADDR_ENABLE Reg ; S6=1 S9=1
|
||||
Node 182 cpu_est_0_ Reg ; S6=1 S9=1
|
||||
Node 193 cpu_est_1_ Reg ; S6=1 S9=1
|
||||
Node 163 inst_AS_000_INT Reg ; S6=0 S9=1
|
||||
Node 121 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
|
||||
Node 115 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
|
||||
Node 283 inst_AS_030_D0 Reg ; S6=1 S9=1
|
||||
Node 133 inst_nEXP_SPACE_D0 Reg ; S6=0 S9=1
|
||||
Node 284 inst_DS_030_D0 Reg ; S6=1 S9=1
|
||||
Node 289 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
|
||||
Node 278 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
|
||||
Node 253 inst_AS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 248 SIZE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 259 SIZE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 236 inst_VPA_D Reg ; S6=0 S9=1
|
||||
Node 119 inst_UDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 113 inst_LDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 184 inst_DTACK_D0 Reg ; S6=1 S9=1
|
||||
Node 146 RESET_DLY_7_ Reg ; S6=1 S9=1
|
||||
Node 238 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
|
||||
Node 205 inst_CLK_000_D1 Reg ; S6=1 S9=1
|
||||
Node 194 inst_CLK_000_D0 Reg ; S6=1 S9=1
|
||||
Node 169 sm_amiga_ns_0_3_0__n Comb ; S6=1 S9=1
|
||||
Node 221 SM_AMIGA_7_ Reg ; S6=0 S9=1
|
||||
Node 232 inst_CLK_OUT_PRE Reg ; S6=1 S9=1
|
||||
Node 155 inst_CLK_000_PE Reg ; S6=1 S9=1
|
||||
Node 250 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 209 inst_CLK_000_NE Reg ; S6=1 S9=1
|
||||
Node 116 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1
|
||||
Node 176 cpu_est_2_ Reg ; S6=1 S9=1
|
||||
Node 188 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1
|
||||
Node 167 SM_AMIGA_6_ Reg ; S6=1 S9=1
|
||||
Node 157 SM_AMIGA_4_ Reg ; S6=1 S9=1
|
||||
Node 227 SM_AMIGA_0_ Reg ; S6=1 S9=1
|
||||
Node 109 inst_CLK_030_H Reg ; S6=0 S9=1
|
||||
Node 206 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 140 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 110 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 266 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 134 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 170 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 164 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 158 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 226 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 200 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 260 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 128 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 254 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 178 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 145 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 104 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 242 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 103 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 217 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 272 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1
|
||||
Node 241 RESET_DLY_0_ Reg ; S6=1 S9=1
|
||||
Node 235 RESET_DLY_1_ Reg ; S6=1 S9=1
|
||||
Node 229 RESET_DLY_2_ Reg ; S6=1 S9=1
|
||||
Node 223 RESET_DLY_3_ Reg ; S6=1 S9=1
|
||||
Node 239 RESET_DLY_4_ Reg ; S6=1 S9=1
|
||||
Node 265 RESET_DLY_5_ Reg ; S6=0 S9=1
|
||||
Node 139 RESET_DLY_6_ Reg ; S6=1 S9=1
|
||||
Node 151 inst_DS_000_ENABLE Reg ; S6=1 S9=1
|
||||
Node 161 SM_AMIGA_1_ Reg ; S6=1 S9=1
|
||||
Node 152 SM_AMIGA_5_ Reg ; S6=1 S9=1
|
||||
Node 224 SM_AMIGA_3_ Reg ; S6=1 S9=1
|
||||
Node 230 SM_AMIGA_2_ Reg ; S6=1 S9=1
|
||||
Node 233 CLK_OUT_PRE_Dreg Reg ; S6=1 S9=1
|
||||
Node 211 CIIN_0 Comb ; S6=1 S9=1
|
||||
; Unused Pins & Nodes
|
||||
; -> None Found.
|
||||
1981
Logic/68030_tk.prd
1981
Logic/68030_tk.prd
File diff suppressed because it is too large
Load Diff
1978
Logic/68030_tk.rpt
1978
Logic/68030_tk.rpt
File diff suppressed because it is too large
Load Diff
|
|
@ -1,2 +0,0 @@
|
|||
Part Number: M4A5-128/64-10VC
|
||||
Need not generate svf file according to the constraints, exit
|
||||
|
|
@ -1,136 +0,0 @@
|
|||
|
||||
|
||||
Design Name = 68030_tk.tt4
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
|
||||
*******************
|
||||
* TIMING ANALYSIS *
|
||||
*******************
|
||||
|
||||
Timing Analysis KEY:
|
||||
One unit of delay time is equivalent to one pass
|
||||
through the Central Switch Matrix.
|
||||
.. Delay ( in this column ) not applicable to the indicated signal.
|
||||
TSU, Set-Up Time ( 0 for input-paired signals ),
|
||||
represents the number of switch matrix passes between
|
||||
an input pin and a register setup before clock.
|
||||
TSU is reported on the register.
|
||||
TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ),
|
||||
represents the number of switch matrix passes between
|
||||
a clocked register and an output pin.
|
||||
TCO is reported on the register.
|
||||
TPD, Propagation Delay Time ( calculated only for combinatorial eqns.),
|
||||
represents the number of switch matrix passes between
|
||||
an input pin and an output pin.
|
||||
TPD is reported on the output pin.
|
||||
TCR, Clocked Output-to-Register Time,
|
||||
represents the number of switch matrix passes between
|
||||
a clocked register and the register it drives ( before clock ).
|
||||
TCR is reported on the driving register.
|
||||
|
||||
TSU TCO TPD TCR
|
||||
#passes #passes #passes #passes
|
||||
SIGNAL NAME min max min max min max min max
|
||||
AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. ..
|
||||
DS_030 1 2 0 0 .. .. 1 1
|
||||
RN_DS_030 1 2 0 0 .. .. 1 1
|
||||
A0 1 2 0 0 .. .. .. ..
|
||||
RW 1 2 0 0 .. .. 1 1
|
||||
RN_RW 1 2 0 0 .. .. 1 1
|
||||
inst_AS_000_INT 1 1 1 2 .. .. 2 2
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 2 1 1 .. .. .. ..
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW 1 2 1 1 .. .. .. ..
|
||||
inst_nEXP_SPACE_D0 1 1 1 1 .. .. 1 2
|
||||
inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2
|
||||
inst_AS_000_DMA 1 2 .. .. .. .. 1 1
|
||||
SIZE_DMA_0_ 1 2 1 1 .. .. 2 2
|
||||
SIZE_DMA_1_ 1 2 1 1 .. .. 2 2
|
||||
inst_UDS_000_INT 1 1 1 1 .. .. 2 2
|
||||
inst_LDS_000_INT 1 1 1 1 .. .. 2 2
|
||||
inst_DTACK_D0 1 2 .. .. .. .. 1 1
|
||||
inst_CLK_000_D1 .. .. .. .. .. .. 1 2
|
||||
inst_CLK_000_D0 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_7_ 1 2 .. .. .. .. 1 1
|
||||
inst_CLK_000_PE .. .. .. .. .. .. 1 2
|
||||
inst_CLK_000_NE .. .. .. .. .. .. 1 2
|
||||
SM_AMIGA_6_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_4_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_0_ 1 1 .. .. .. .. 1 2
|
||||
inst_CLK_030_H 1 2 .. .. .. .. 1 1
|
||||
inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
|
||||
SM_AMIGA_1_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_5_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_3_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_2_ 1 1 .. .. .. .. 1 2
|
||||
AS_000 .. .. .. .. 1 1 .. ..
|
||||
UDS_000 .. .. .. .. 1 1 .. ..
|
||||
LDS_000 .. .. .. .. 1 1 .. ..
|
||||
FPU_CS .. .. .. .. 1 1 .. ..
|
||||
DTACK .. .. .. .. 1 1 .. ..
|
||||
CIIN .. .. .. .. 1 1 .. ..
|
||||
IPL_030_2_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_2_ 1 1 0 0 .. .. 1 1
|
||||
IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
RW_000 1 1 0 0 .. .. 1 1
|
||||
RN_RW_000 1 1 0 0 .. .. 1 1
|
||||
IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
BG_000 1 1 0 0 .. .. 1 1
|
||||
RN_BG_000 1 1 0 0 .. .. 1 1
|
||||
BGACK_030 1 1 0 1 .. .. 1 1
|
||||
RN_BGACK_030 1 1 0 1 .. .. 1 1
|
||||
DSACK1 1 1 0 0 .. .. 1 1
|
||||
RN_DSACK1 1 1 0 0 .. .. 1 1
|
||||
E .. .. 0 0 .. .. 1 1
|
||||
RN_E .. .. 0 0 .. .. 1 1
|
||||
VMA .. .. 0 0 .. .. 1 1
|
||||
RN_VMA .. .. 0 0 .. .. 1 1
|
||||
RESET .. .. 0 0 .. .. 1 1
|
||||
RN_RESET .. .. 0 0 .. .. 1 1
|
||||
AMIGA_ADDR_ENABLE .. .. 0 0 .. .. 1 1
|
||||
RN_AMIGA_ADDR_ENABLE .. .. 0 0 .. .. 1 1
|
||||
cpu_est_0_ .. .. .. .. .. .. 1 1
|
||||
cpu_est_1_ .. .. .. .. .. .. 1 1
|
||||
inst_AS_030_D0 1 1 1 1 .. .. 1 1
|
||||
inst_DS_030_D0 1 1 .. .. .. .. 1 1
|
||||
inst_BGACK_030_INT_D .. .. .. .. .. .. 1 1
|
||||
inst_VPA_D 1 1 .. .. .. .. 1 1
|
||||
RESET_DLY_7_ .. .. .. .. .. .. 1 1
|
||||
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
|
||||
sm_amiga_ns_0_3_0__n .. .. .. .. 1 1 .. ..
|
||||
inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1
|
||||
cpu_est_2_ .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_0_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_1_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_2_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_3_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_4_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_4_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_5_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_6_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_0_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_1_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_2_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_3_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_4_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_5_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_6_ .. .. .. .. .. .. 1 1
|
||||
CLK_OUT_PRE_Dreg .. .. 1 1 .. .. 1 1
|
||||
CIIN_0 .. .. .. .. 1 1 .. ..
|
||||
|
|
@ -1,269 +0,0 @@
|
|||
[DEVICE]
|
||||
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = NO;
|
||||
Pin_MC_1to1 = NO;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 10/10/14;
|
||||
TIME = 22:40:09;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
|
||||
Pin_Assignments = NO;
|
||||
Pin_Keep_Block = NO;
|
||||
Pin_Keep_Segment = NO;
|
||||
Group_Assignments = NO;
|
||||
Macrocell_Assignments = NO;
|
||||
Macrocell_Keep_Block = NO;
|
||||
Macrocell_Keep_Segment = NO;
|
||||
Pin_Reservation = NO;
|
||||
Timing_Constraints = NO;
|
||||
Block_Reservation = NO;
|
||||
Segment_Reservation = NO;
|
||||
Ignore_Source_Location = NO;
|
||||
Ignore_Source_Optimization = NO;
|
||||
Ignore_Source_Timing = NO;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
|
||||
Pin_Assignments = NO;
|
||||
Pin_Keep_Block = NO;
|
||||
Pin_Keep_Segment = NO;
|
||||
Group_Assignments = NO;
|
||||
Macrocell_Assignments = NO;
|
||||
Macrocell_Keep_Block = NO;
|
||||
Macrocell_Keep_Segment = NO;
|
||||
Pin_Reservation = NO;
|
||||
Timing_Constraints = NO;
|
||||
Block_Reservation = NO;
|
||||
Segment_Reservation = NO;
|
||||
Ignore_Source_Location = NO;
|
||||
Ignore_Source_Optimization = NO;
|
||||
Ignore_Source_Timing = NO;
|
||||
|
||||
[BACKANNOTATE NETLIST]
|
||||
|
||||
Netlist = VHDL;
|
||||
Delay_File = SDF;
|
||||
Generic_VCC = ;
|
||||
Generic_GND = ;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
|
||||
Pin_Assignment = NO;
|
||||
Pin_Block = NO;
|
||||
Pin_Macrocell_Block = NO;
|
||||
Routing = NO;
|
||||
|
||||
[GLOBAL PROJECT OPTIMIZATION]
|
||||
|
||||
Balanced_Partitioning = YES;
|
||||
Spread_Placement = YES;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_Inter_Seg_Percent = 100;
|
||||
Max_Seg_In_Percent = 100;
|
||||
Max_Blk_In_Percent = 100;
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
|
||||
Fitter_Options = YES;
|
||||
Pinout_Diagram = NO;
|
||||
Pinout_Listing = YES;
|
||||
Detailed_Block_Segment_Summary = YES;
|
||||
Input_Signal_List = YES;
|
||||
Output_Signal_List = YES;
|
||||
Bidir_Signal_List = YES;
|
||||
Node_Signal_List = YES;
|
||||
Signal_Fanout_List = YES;
|
||||
Block_Segment_Fanin_List = YES;
|
||||
Prefit_Eqn = YES;
|
||||
Postfit_Eqn = YES;
|
||||
Page_Break = YES;
|
||||
|
||||
[OPTIMIZATION OPTIONS]
|
||||
|
||||
Logic_Reduction = YES;
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
XOR_Synthesis = YES;
|
||||
Node_Collapse = Yes;
|
||||
DT_Synthesis = No;
|
||||
|
||||
[FITTER GLOBAL OPTIONS]
|
||||
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = YES;
|
||||
In_Reg_Optimize = YES;
|
||||
Clock_Optimize = NO;
|
||||
Conf_Unused_IOs = OUT_LOW;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low, High;
|
||||
Default = High;
|
||||
Low = 8, H, G, F, E, D, C, B, A;
|
||||
Type = GLB;
|
||||
|
||||
[HARDWARE DEVICE OPTIONS]
|
||||
Zero_Hold_Time = Yes;
|
||||
Signature_Word = 0;
|
||||
Pull_up = Yes;
|
||||
Out_Slew_Rate = SLOW, FAST, 28, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, AMIGA_ADDR_ENABLE,
|
||||
AMIGA_BUS_ENABLE_HIGH, AVEC, BG_000, LDS_000, UDS_000, DTACK, RW_000, AS_000,
|
||||
CLK_DIV_OUT, CLK_EXP, FPU_CS, AS_030, RW, SIZE_1_, SIZE_0_, BGACK_030,
|
||||
IPL_030_0_, IPL_030_1_, IPL_030_2_, RESET, CIIN, DS_030, BERR, A0, DSACK1;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[PIN RESERVATIONS]
|
||||
layer = OFF;
|
||||
|
||||
[LOCATION ASSIGNMENT]
|
||||
|
||||
Layer = OFF;
|
||||
A_27_ = INPUT,16, C,-;
|
||||
A_26_ = INPUT,17, C,-;
|
||||
SIZE_1_ = BIDIR,79, H,-;
|
||||
A_25_ = INPUT,18, C,-;
|
||||
A_24_ = INPUT,19, C,-;
|
||||
A_31_ = INPUT,4, B,-;
|
||||
A_23_ = INPUT,85, H,-;
|
||||
A_22_ = INPUT,84, H,-;
|
||||
A_21_ = INPUT,94, A,-;
|
||||
A_20_ = INPUT,93, A,-;
|
||||
IPL_2_ = INPUT,68, G,-;
|
||||
A_19_ = INPUT,97, A,-;
|
||||
A_18_ = INPUT,95, A,-;
|
||||
FC_1_ = INPUT,58, F,-;
|
||||
A_17_ = INPUT,59, F,-;
|
||||
AS_030 = BIDIR,82, H,-;
|
||||
A_16_ = INPUT,96, A,-;
|
||||
AS_000 = BIDIR,42, E,-;
|
||||
IPL_1_ = INPUT,56, F,-;
|
||||
UDS_000 = BIDIR,32, D,-;
|
||||
IPL_0_ = INPUT,67, G,-;
|
||||
LDS_000 = BIDIR,31, D,-;
|
||||
FC_0_ = INPUT,57, F,-;
|
||||
A1 = INPUT,60, F,-;
|
||||
nEXP_SPACE = INPUT,14,-,-;
|
||||
BERR = BIDIR,41, E,-;
|
||||
BG_030 = INPUT,21, C,-;
|
||||
BGACK_000 = INPUT,28, D,-;
|
||||
CLK_030 = INPUT,64,-,-;
|
||||
CLK_000 = INPUT,11,-,-;
|
||||
CLK_OSZI = INPUT,61,-,-;
|
||||
CLK_DIV_OUT = OUTPUT,65, G,-;
|
||||
CLK_EXP = OUTPUT,10, B,-;
|
||||
FPU_CS = OUTPUT,78, H,-;
|
||||
FPU_SENSE = INPUT,91, A,-;
|
||||
DTACK = BIDIR,30, D,-;
|
||||
AVEC = OUTPUT,92, A,-;
|
||||
VPA = INPUT,36,-,-;
|
||||
RST = INPUT,86,-,-;
|
||||
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
|
||||
CIIN = OUTPUT,47, E,-;
|
||||
SIZE_0_ = BIDIR,70, G,-;
|
||||
A_30_ = INPUT,5, B,-;
|
||||
A_29_ = INPUT,6, B,-;
|
||||
A_28_ = INPUT,15, C,-;
|
||||
IPL_030_2_ = OUTPUT,9, B,-;
|
||||
IPL_030_1_ = OUTPUT,7, B,-;
|
||||
RW_000 = BIDIR,80, H,-;
|
||||
IPL_030_0_ = OUTPUT,8, B,-;
|
||||
DS_030 = BIDIR,98, A,-;
|
||||
A0 = BIDIR,69, G,-;
|
||||
BG_000 = OUTPUT,29, D,-;
|
||||
BGACK_030 = OUTPUT,83, H,-;
|
||||
DSACK1 = BIDIR,81, H,-;
|
||||
E = OUTPUT,66, G,-;
|
||||
VMA = OUTPUT,35, D,-;
|
||||
RESET = OUTPUT,3, B,-;
|
||||
RW = BIDIR,71, G,-;
|
||||
AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
|
||||
cpu_est_0_ = NODE,6, D,-;
|
||||
cpu_est_1_ = NODE,13, D,-;
|
||||
inst_AS_000_INT = NODE,9, C,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,13, A,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,9, A,-;
|
||||
inst_AS_030_D0 = NODE,9, H,-;
|
||||
inst_nEXP_SPACE_D0 = NODE,5, B,-;
|
||||
inst_DS_030_D0 = NODE,10, H,-;
|
||||
inst_AS_030_000_SYNC = NODE,13, H,-;
|
||||
inst_BGACK_030_INT_D = NODE,6, H,-;
|
||||
inst_AS_000_DMA = NODE,5, G,-;
|
||||
SIZE_DMA_0_ = NODE,2, G,-;
|
||||
SIZE_DMA_1_ = NODE,9, G,-;
|
||||
inst_VPA_D = NODE,10, F,-;
|
||||
inst_UDS_000_INT = NODE,12, A,-;
|
||||
inst_LDS_000_INT = NODE,8, A,-;
|
||||
inst_DTACK_D0 = NODE,7, D,-;
|
||||
RESET_DLY_7_ = NODE,14, B,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,11, F,-;
|
||||
inst_CLK_000_D1 = NODE,5, E,-;
|
||||
inst_CLK_000_D0 = NODE,14, D,-;
|
||||
sm_amiga_ns_0_3_0__n = NODE,13, C,-;
|
||||
SM_AMIGA_7_ = NODE,0, F,-;
|
||||
inst_CLK_OUT_PRE = NODE,7, F,-;
|
||||
inst_CLK_000_PE = NODE,4, C,-;
|
||||
CLK_000_P_SYNC_9_ = NODE,3, G,-;
|
||||
inst_CLK_000_NE = NODE,8, E,-;
|
||||
CLK_000_N_SYNC_11_ = NODE,10, A,-;
|
||||
cpu_est_2_ = NODE,2, D,-;
|
||||
inst_CLK_000_NE_D0 = NODE,10, D,-;
|
||||
SM_AMIGA_6_ = NODE,12, C,-;
|
||||
SM_AMIGA_4_ = NODE,5, C,-;
|
||||
SM_AMIGA_0_ = NODE,4, F,-;
|
||||
inst_CLK_030_H = NODE,5, A,-;
|
||||
CLK_000_P_SYNC_0_ = NODE,6, E,-;
|
||||
CLK_000_P_SYNC_1_ = NODE,10, B,-;
|
||||
CLK_000_P_SYNC_2_ = NODE,6, A,-;
|
||||
CLK_000_P_SYNC_3_ = NODE,14, G,-;
|
||||
CLK_000_P_SYNC_4_ = NODE,6, B,-;
|
||||
CLK_000_P_SYNC_5_ = NODE,14, C,-;
|
||||
CLK_000_P_SYNC_6_ = NODE,10, C,-;
|
||||
CLK_000_P_SYNC_7_ = NODE,6, C,-;
|
||||
CLK_000_P_SYNC_8_ = NODE,3, F,-;
|
||||
CLK_000_N_SYNC_0_ = NODE,2, E,-;
|
||||
CLK_000_N_SYNC_1_ = NODE,10, G,-;
|
||||
CLK_000_N_SYNC_2_ = NODE,2, B,-;
|
||||
CLK_000_N_SYNC_3_ = NODE,6, G,-;
|
||||
CLK_000_N_SYNC_4_ = NODE,3, D,-;
|
||||
CLK_000_N_SYNC_5_ = NODE,13, B,-;
|
||||
CLK_000_N_SYNC_6_ = NODE,2, A,-;
|
||||
CLK_000_N_SYNC_7_ = NODE,14, F,-;
|
||||
CLK_000_N_SYNC_8_ = NODE,1, A,-;
|
||||
CLK_000_N_SYNC_9_ = NODE,13, E,-;
|
||||
CLK_000_N_SYNC_10_ = NODE,2, H,-;
|
||||
RESET_DLY_0_ = NODE,13, F,-;
|
||||
RESET_DLY_1_ = NODE,9, F,-;
|
||||
RESET_DLY_2_ = NODE,5, F,-;
|
||||
RESET_DLY_3_ = NODE,1, F,-;
|
||||
RESET_DLY_4_ = NODE,12, F,-;
|
||||
RESET_DLY_5_ = NODE,13, G,-;
|
||||
RESET_DLY_6_ = NODE,9, B,-;
|
||||
inst_DS_000_ENABLE = NODE,1, C,-;
|
||||
SM_AMIGA_1_ = NODE,8, C,-;
|
||||
SM_AMIGA_5_ = NODE,2, C,-;
|
||||
SM_AMIGA_3_ = NODE,2, F,-;
|
||||
SM_AMIGA_2_ = NODE,6, F,-;
|
||||
CLK_OUT_PRE_Dreg = NODE,8, F,-;
|
||||
CIIN_0 = NODE,9, E,-;
|
||||
|
|
@ -1,219 +0,0 @@
|
|||
[DEVICE]
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = No;
|
||||
Pin_MC_1to1 = No;
|
||||
EN_PinReserve_IO = Yes;
|
||||
EN_PinReserve_BIDIR = Yes;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
DATE = 10/02/2014;
|
||||
TIME = 23:53:03;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
Pin_Block = No;
|
||||
Pin_Macrocell_Block = No;
|
||||
Routing = No;
|
||||
|
||||
[GLOBAL PROJECT OPTIMIZATION]
|
||||
Balanced_Partitioning = Yes;
|
||||
Spread_Placement = Yes;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_Blk_In_Percent = 100;
|
||||
|
||||
[OPTIMIZATION OPTIONS]
|
||||
Logic_Reduction = Yes;
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
XOR_Synthesis = Yes;
|
||||
EN_XOR_Synthesis = Yes;
|
||||
XOR_Gate = Yes;
|
||||
Node_Collapse = Yes;
|
||||
Keep_XOR = Yes;
|
||||
DT_Synthesis = No;
|
||||
Clock_PTerm = Min;
|
||||
Reset_PTerm = On;
|
||||
Preset_PTerm = On;
|
||||
Clock_Enable_PTerm = On;
|
||||
Output_Enable_PTerm = On;
|
||||
EN_DT_Synthesis = Yes;
|
||||
Cluster_PTerm = 5;
|
||||
FF_inv = No;
|
||||
EN_Use_CE = No;
|
||||
Use_CE = No;
|
||||
Use_Internal_COM_FB = Yes;
|
||||
EN_use_Internal_COM_FB = Yes;
|
||||
Set_Reset_Swap = No;
|
||||
EN_Set_Reset_Swap = No;
|
||||
Density = No;
|
||||
DeMorgan = Yes;
|
||||
T_FF = Yes;
|
||||
Max_Symbols = 32;
|
||||
|
||||
[FITTER GLOBAL OPTIONS]
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = Yes;
|
||||
EN_Set_Reset_Dont_Care = Yes;
|
||||
In_Reg_Optimize = Yes;
|
||||
EN_In_Reg_Optimize = No;
|
||||
Clock_Optimize = No;
|
||||
Global_Clock_As_Pterm = No;
|
||||
Show_Iterations = No;
|
||||
Routing_Attempts = 2;
|
||||
Conf_Unused_IOs = Out_Low;
|
||||
|
||||
[HARDWARE DEVICE OPTIONS]
|
||||
Zero_Hold_Time = Yes;
|
||||
Signature_Word = 0;
|
||||
Pull_up = Yes;
|
||||
Out_Slew_Rate = SLOW,FAST,28,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH,AVEC,BG_000,LDS_000,UDS_000,DTACK,RW_000,AS_000,CLK_DIV_OUT,CLK_EXP,FPU_CS,AS_030,RW,SIZE_1_,SIZE_0_,BGACK_030,IPL_030_0_,IPL_030_1_,IPL_030_2_,RESET,CIIN,DS_030,BERR,A0,DSACK1;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[PIN RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[LOCATION ASSIGNMENT]
|
||||
Layer = OFF;
|
||||
AS_030 = input,82,H,-;
|
||||
A_16_ = input,96,A,-;
|
||||
A_17_ = input,59,F,-;
|
||||
A_18_ = input,95,A,-;
|
||||
A_19_ = input,97,A,-;
|
||||
BGACK_000 = input,28,D,-;
|
||||
BG_030 = input,21,C,-;
|
||||
CLK_000 = input,11,-,-;
|
||||
CLK_030 = input,64,-,-;
|
||||
CLK_OSZI = input,61,-,-;
|
||||
FC_0_ = input,57,F,-;
|
||||
FC_1_ = input,58,F,-;
|
||||
IPL_0_ = input,67,G,-;
|
||||
IPL_1_ = input,56,F,-;
|
||||
IPL_2_ = input,68,G,-;
|
||||
RST = input,86,-,-;
|
||||
RW = input,71,G,-;
|
||||
SIZE_1_ = input,79,H,-;
|
||||
SIZE_0_ = input,70,G,-;
|
||||
VPA = input,36,-,-;
|
||||
AVEC = input,92,A,-;
|
||||
BGACK_030 = input,83,H,-;
|
||||
BG_000 = input,29,D,-;
|
||||
CLK_DIV_OUT = input,65,G,-;
|
||||
CLK_EXP = input,10,B,-;
|
||||
E = input,66,G,-;
|
||||
FPU_CS = input,78,H,-;
|
||||
IPL_030_0_ = input,8,B,-;
|
||||
IPL_030_1_ = input,7,B,-;
|
||||
IPL_030_2_ = input,9,B,-;
|
||||
LDS_000 = input,31,D,-;
|
||||
UDS_000 = input,32,D,-;
|
||||
DTACK = input,30,D,-;
|
||||
RESET = input,3,B,-;
|
||||
AMIGA_BUS_DATA_DIR = input,48,E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = input,20,C,-;
|
||||
CIIN = input,47,E,-;
|
||||
A_20_ = input,93,A,-;
|
||||
A_21_ = input,94,A,-;
|
||||
A_22_ = input,84,H,-;
|
||||
A_24_ = input,19,C,-;
|
||||
A_25_ = input,18,C,-;
|
||||
A_26_ = input,17,C,-;
|
||||
A_27_ = input,16,C,-;
|
||||
A_28_ = input,15,C,-;
|
||||
A_29_ = input,6,B,-;
|
||||
A_30_ = input,5,B,-;
|
||||
A_31_ = input,4,B,-;
|
||||
DS_030 = input,98,A,-;
|
||||
BERR = input,41,E,-;
|
||||
nEXP_SPACE = input,14,-,-;
|
||||
A0 = input,69,G,-;
|
||||
DSACK1 = input,81,H,-;
|
||||
RW_000 = input,80,H,-;
|
||||
AS_000 = input,42,E,-;
|
||||
AMIGA_ADDR_ENABLE = input,33,D,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = input,34,D,-;
|
||||
A_23_ = input,85,H,-;
|
||||
FPU_SENSE = input,91,A,-;
|
||||
A1 = input,60,F,-;
|
||||
VMA = input,35,D,-;
|
||||
|
||||
[GROUP ASSIGNMENT]
|
||||
Layer = OFF;
|
||||
|
||||
[SPACE RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[BACKANNOTATE NETLIST]
|
||||
Delay_File = SDF;
|
||||
Netlist = VHDL;
|
||||
VCC_GND = Cell;
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
Fitter_Options = Yes;
|
||||
Pinout_Diagram = No;
|
||||
Pinout_Listing = Yes;
|
||||
Detailed_Block_Segment_Summary = Yes;
|
||||
Input_Signal_List = Yes;
|
||||
Output_Signal_List = Yes;
|
||||
Bidir_Signal_List = Yes;
|
||||
Node_Signal_List = Yes;
|
||||
Signal_Fanout_List = Yes;
|
||||
Block_Segment_Fanin_List = Yes;
|
||||
Postfit_Eqn = Yes;
|
||||
Page_Break = Yes;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low,High;
|
||||
Default = High;
|
||||
Low = 8,H,G,F,E,D,C,B,A;
|
||||
Type = GLB;
|
||||
|
||||
[SOURCE CONSTRAINT OPTION]
|
||||
Import_source_constraint = Yes;
|
||||
Disable_warning_message = No;
|
||||
|
||||
[TIMING ANALYZER]
|
||||
Last_source=;
|
||||
Last_source_type=Fmax;
|
||||
|
||||
[INPUT REGISTERS]
|
||||
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
Signal Name Cross Reference File
|
||||
|
||||
ispLEVER Classic 1.7.00.05.28.13
|
||||
|
||||
Design '68030_tk' created Fri Oct 10 22:40:03 2014
|
||||
|
||||
|
||||
LEGEND: '>' Functional Block Port Separator
|
||||
'/' Hierarchy Path Separator
|
||||
'@' Automatically Generated Node
|
||||
|
||||
|
||||
Short Name Hierarchical Name
|
||||
---------- -----------------
|
||||
|
||||
*** Shortened names not required for this design. ***
|
||||
3753
Logic/BUS68030.edi
3753
Logic/BUS68030.edi
File diff suppressed because it is too large
Load Diff
|
|
@ -1,61 +0,0 @@
|
|||
AS_030 b
|
||||
AS_000 b
|
||||
RW_000 b
|
||||
DS_030 b
|
||||
UDS_000 b
|
||||
LDS_000 b
|
||||
SIZE[1] b
|
||||
SIZE[0] b
|
||||
A[31] i
|
||||
A[30] i
|
||||
A[29] i
|
||||
A[28] i
|
||||
A[27] i
|
||||
A[26] i
|
||||
A[25] i
|
||||
A[24] i
|
||||
A[23] i
|
||||
A[22] i
|
||||
A[21] i
|
||||
A[20] i
|
||||
A[19] i
|
||||
A[18] i
|
||||
A[17] i
|
||||
A[16] i
|
||||
A0 b
|
||||
A1 i
|
||||
nEXP_SPACE i
|
||||
BERR b
|
||||
BG_030 i
|
||||
BG_000 o
|
||||
BGACK_030 o
|
||||
BGACK_000 i
|
||||
CLK_030 i
|
||||
CLK_000 i
|
||||
CLK_OSZI i
|
||||
CLK_DIV_OUT o
|
||||
CLK_EXP o
|
||||
FPU_CS o
|
||||
FPU_SENSE i
|
||||
IPL_030[2] o
|
||||
IPL_030[1] o
|
||||
IPL_030[0] o
|
||||
IPL[2] i
|
||||
IPL[1] i
|
||||
IPL[0] i
|
||||
DSACK1 b
|
||||
DTACK b
|
||||
AVEC o
|
||||
E o
|
||||
VPA i
|
||||
VMA o
|
||||
RST i
|
||||
RESET o
|
||||
RW b
|
||||
FC[1] i
|
||||
FC[0] i
|
||||
AMIGA_ADDR_ENABLE o
|
||||
AMIGA_BUS_DATA_DIR o
|
||||
AMIGA_BUS_ENABLE_LOW o
|
||||
AMIGA_BUS_ENABLE_HIGH o
|
||||
CIIN o
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
||||
#-- Written on Fri Oct 10 22:39:56 2014
|
||||
#-- Written on Thu Oct 16 21:59:04 2014
|
||||
|
||||
|
||||
#device options
|
||||
|
|
|
|||
|
|
@ -19,8 +19,8 @@
|
|||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
|
||||
<FileTime>10/05/14 21:32:45</FileTime>
|
||||
<JedecChecksum>0x4FC8</JedecChecksum>
|
||||
<FileTime>10/16/14 21:59:16</FileTime>
|
||||
<JedecChecksum>0xC45A</JedecChecksum>
|
||||
<Operation>Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Fri Oct 10 22:39:57 2014
|
||||
#Thu Oct 16 21:59:04 2014
|
||||
|
||||
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
|
||||
@N|Running in 64-bit mode
|
||||
|
|
@ -18,7 +18,6 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
|
|||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:22|Signal clk_out_pre_33_d is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:8:127:17|Signal clk_pre_66 is undriven
|
||||
|
|
@ -47,7 +46,7 @@ State machine has 8 reachable states with original encodings of:
|
|||
111
|
||||
@END
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Oct 10 22:39:57 2014
|
||||
# Thu Oct 16 21:59:04 2014
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -66,7 +65,7 @@ original code -> new code
|
|||
101 -> 00100000
|
||||
110 -> 01000000
|
||||
111 -> 10000000
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":199:4:199:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":196:4:196:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
|
||||
|
|
@ -78,10 +77,10 @@ BI_DIR 13 uses
|
|||
IBUF 31 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 1 use
|
||||
AND2 228 uses
|
||||
INV 189 uses
|
||||
AND2 238 uses
|
||||
INV 181 uses
|
||||
OR2 22 uses
|
||||
XOR2 9 uses
|
||||
OR2 21 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
@ -91,6 +90,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Oct 10 22:39:58 2014
|
||||
# Thu Oct 16 21:59:06 2014
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version G-2012.09LC-SP1
|
||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
||||
#-- Written on Fri Oct 10 22:39:56 2014
|
||||
#-- Written on Thu Oct 16 21:59:04 2014
|
||||
|
||||
|
||||
#project files
|
||||
|
|
|
|||
|
|
@ -1,39 +0,0 @@
|
|||
ABEL5DEV=C:\Program Files (x86)\ispLever\ispcpld\lib5
|
||||
DIOEDA_ABEL5DEV=C:\Program Files (x86)\ispLever\ispcpld\lib5
|
||||
DIOEDA_ActiveHDL=C:\Program Files (x86)\ispLever\active-hdl\BIN
|
||||
DIOEDA_ActiveHDLPath=C:\Program Files (x86)\ispLever\active-hdl\BIN
|
||||
DIOEDA_AppNotes=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
DIOEDA_Bin=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
DIOEDA_Config=C:\Program Files (x86)\ispLever\ispcpld\config
|
||||
DIOEDA_CONTEXT=ispLEVER CLASSIC
|
||||
DIOEDA_DSPPATH=C:\Program Files (x86)\ispLever\ispLeverDSP
|
||||
DIOEDA_EPICPATH=C:\Program Files (x86)\ispLever\ispfpga\bin\nt
|
||||
DIOEDA_Examples=C:\Program Files (x86)\ispLever\examples
|
||||
DIOEDA_FPGABinPath=C:\Program Files (x86)\ispLever\ispfpga\bin\nt
|
||||
DIOEDA_FPGAPath=C:\Program Files (x86)\ispLever\ispfpga
|
||||
DIOEDA_HDLExplorer=C:\Program Files (x86)\ispLever\hdle\win32
|
||||
DIOEDA_INI=C:\lsc_env
|
||||
DIOEDA_ispVM=C:\Program Files (x86)\ispLever\ispvmsystem
|
||||
DIOEDA_ispVMSystem=C:\Program Files (x86)\ispLever\ispvmsystem
|
||||
DIOEDA_License=C:\Program Files (x86)\ispLever\license
|
||||
DIOEDA_MachPath=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
DIOEDA_Manuals=C:\Program Files (x86)\ispLever\ispcpld\manuals
|
||||
DIOEDA_ModelSim=C:\Program Files (x86)\ispLever\modelsim\win32loem
|
||||
DIOEDA_ModelsimPath=C:\Program Files (x86)\ispLever\modelsim\win32loem
|
||||
DIOEDA_PDSPath=C:\Program Files (x86)\ispLever\ispcomp
|
||||
DIOEDA_Precision=C:\isptools\precision
|
||||
DIOEDA_PrecisionPath=C:\isptools\precision
|
||||
DIOEDA_ProductName=ispLEVER
|
||||
DIOEDA_ProductPrefix=SYN
|
||||
DIOEDA_ProductTitle=ispLEVER
|
||||
DIOEDA_ProductType=1.7.00.05.28.13_LS_HDL_BASE_PC_N
|
||||
DIOEDA_ProductVersion=1.7.00.05
|
||||
DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 1.7
|
||||
DIOEDA_Root=C:\Program Files (x86)\ispLever\ispcpld
|
||||
DIOEDA_Spectrum=C:\isptools\spectrum
|
||||
DIOEDA_SpectrumPath=C:\isptools\spectrum
|
||||
DIOEDA_Synplify=C:\Program Files (x86)\ispLever\synpbase
|
||||
DIOEDA_SynplifyPath=C:\Program Files (x86)\ispLever\synpbase
|
||||
DIOEDA_Tutorial=C:\Program Files (x86)\ispLever\ispcpld\tutorial
|
||||
DIOPRODUCT=ispLEVER
|
||||
PATH=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
|
|
@ -12,7 +12,7 @@ original code -> new code
|
|||
101 -> 00100000
|
||||
110 -> 01000000
|
||||
111 -> 10000000
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":199:4:199:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":196:4:196:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
|
||||
|
|
@ -24,10 +24,10 @@ BI_DIR 13 uses
|
|||
IBUF 31 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 1 use
|
||||
AND2 228 uses
|
||||
INV 189 uses
|
||||
AND2 238 uses
|
||||
INV 181 uses
|
||||
OR2 22 uses
|
||||
XOR2 9 uses
|
||||
OR2 21 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
@ -37,6 +37,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Oct 10 22:39:58 2014
|
||||
# Thu Oct 16 21:59:06 2014
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
@E: CG103 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:68:498:71|Expecting expression
|
||||
@E: CD493 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":494:67:494:67|character '~' is not allowed
|
||||
@E|Parse errors encountered - exiting
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>14</data>
|
||||
<data>13</data>
|
||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Errors">
|
||||
|
|
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<data>-</data>
|
||||
</info>
|
||||
<info name="Date &Time">
|
||||
<data type="timestamp">1412973597</data>
|
||||
<data type="timestamp">1413489544</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
@ -1,4 +1,3 @@
|
|||
@W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:22|Signal clk_out_pre_33_d is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:8:127:17|Signal clk_pre_66 is undriven
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":199:4:199:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":196:4:196:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
<data>96MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1412973598</data>
|
||||
<data type="timestamp">1413489546</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
Synopsys, Inc.
|
||||
Version G-2012.09LC-SP1
|
||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||
Written on Fri Oct 10 22:39:57 2014
|
||||
Written on Thu Oct 16 21:59:04 2014
|
||||
|
||||
|
||||
-->
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412973591
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1413489533
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412973591
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1413489533
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,5 +1,4 @@
|
|||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:22|Signal clk_out_pre_33_d is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:8:127:17|Signal clk_pre_66 is undriven
|
||||
|
|
|
|||
Loading…
Reference in New Issue