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68030tk
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Better timing & Resetfix

This commit is contained in:
MHeinrichs 2016-11-30 23:10:23 +01:00
parent e79ab9bae7
commit 1152df45a6
53 changed files with 31409 additions and 13868 deletions
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73
Logic/68030-68000-bus.vhd
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@ -100,6 +100,7 @@ signal SM_AMIGA : SM_68000;
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal AS_000_INT:STD_LOGIC := '1';
signal AS_000_D0:STD_LOGIC := '1';
signal RW_000_INT:STD_LOGIC := '1';
signal AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC := '1';
signal AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC := '1';
@ -137,7 +138,8 @@ signal DTACK_D0: STD_LOGIC := '1';
signal RESET_OUT: STD_LOGIC := '0';
signal CLK_030_D0: STD_LOGIC := '0';
signal RST_DLY: STD_LOGIC_VECTOR ( 2 downto 0 ) := "000";
signal CLK_030_PE: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
signal AMIGA_DS: STD_LOGIC := '1';
begin
CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1);
@ -166,7 +168,7 @@ begin
-- the external clock to the processor is generated here
CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
CLK_OUT_EXP_INT <= CLK_OUT_PRE_50;
CLK_OUT_EXP_INT <= CLK_OUT_PRE_D;
--delayed Clocks and signals for edge detection
CLK_000_D(0) <= CLK_000;
CLK_000_D(DS_SAMPLE downto 1) <= CLK_000_D((DS_SAMPLE-1) downto 0);
@ -217,10 +219,12 @@ begin
AS_030_D0 <= '1';
nEXP_SPACE_D0 <= '1';
DS_030_D0 <= '1';
CLK_030_H <= '0';
CYCLE_DMA <= "00";
RST_DLY <= "000";
RESET_OUT <= '0';
AS_000_D0 <='1';
AMIGA_DS <='1';
CLK_030_PE <= "00";
else
if(CLK_000_NE='1')then
@ -246,7 +250,7 @@ begin
BGACK_030_INT <= '0';
--BGACK_030_INT_PRE<= '0';
elsif ( BGACK_000='1'
AND CLK_000_PE='1'
AND CLK_000_NE='1'
AND AS_000 = '1' --the amiga AS can be still active while bgack is deasserted, so wait for this signal too!
) then -- BGACK_000 is high here!
--BGACK_030_INT_PRE<= '1';
@ -269,7 +273,7 @@ begin
--interrupt buffering to avoid ghost interrupts
IPL_D0<=IPL;
if(IPL = IPL_D0 and CLK_000_PE = '1')then
if(IPL = IPL_D0) then --and CLK_000_PE = '1')then
IPL_030<=IPL;
end if;
@ -374,10 +378,20 @@ begin
end case;
--dma stuff
AS_000_D0 <=AS_000;
if(UDS_000='0' or LDS_000='0') then
AMIGA_DS <='0';
else
AMIGA_DS <='1';
end if;
if(BGACK_030_INT='0')then
--set some signals NOT linked to AS_000='0'
RW_000_DMA <= RW_000;
-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
if(UDS_000='0' and LDS_000='0') then
SIZE_DMA <= "10"; --16bit
else
@ -389,6 +403,7 @@ begin
--therefore a1 = uds
--great! life is simple here!
A0_DMA <= UDS_000;
--A0_DMA <= '0';
--A1 is set by the amiga side
--here we determine the upper or lower half of the databus
AMIGA_BUS_ENABLE_DMA_HIGH <= A(1);
@ -403,8 +418,8 @@ begin
end if;
if(BGACK_030_INT='0' and AS_000='0')then
-- an 68000-memory cycle is three positive edges long!
if(CLK_000_PE='1')then
-- an 68000-memory cycle is three negative edges long!
if(CLK_000_NE='1' and CYCLE_DMA<"11")then
CYCLE_DMA <= CYCLE_DMA+1;
end if;
else
@ -412,33 +427,33 @@ begin
end if;
--as can only be done if we know the uds/lds!
if( BGACK_030_INT='0'
and AS_000='0'
and(UDS_000='0' or LDS_000='0')
if( CYCLE_DMA >"00"
and AS_000 = '0'
and AMIGA_DS ='0'
and (
CYCLE_DMA ="01"
or CYCLE_DMA ="10"
)
CYCLE_DMA < "11"
or RW_000 = '1')
)then
--set AS_000
if( CLK_030='1') then
AS_000_DMA <= '0'; --sampled on rising edges!
if( not(CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1')) then --sampled on rising edges, so we can set AS only if the next clock is not rising!!
AS_000_DMA <= '0';
if(RW_000='1') then
DS_000_DMA <='0';
end if;
end if;
if( CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1' and CLK_030_PE <"11" and AS_000_DMA = '0') then --sample rising edges
CLK_030_PE <= CLK_030_PE+1;
end if;
--delayed clock for write cycle
if(AS_000_DMA = '0' and CLK_030='0')then
CLK_030_H <= '1';
end if;
if(RW_000='1') then
DS_000_DMA <='0';
elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then
DS_000_DMA <=AS_000_DMA; -- write: one clock delayed!
if(RW_000='0' and CLK_030_PE="01" and CLK_030='1')then
DS_000_DMA <= '0'; -- write: one clock delayed!
end if;
else
CLK_030_PE <= "00";
AS_000_DMA <= '1';
DS_000_DMA <= '1';
CLK_030_H <= '0';
end if;
end if;
@ -452,8 +467,8 @@ begin
--CLK_EXP <= CLK_030;
RESET <= 'Z' when RESET_OUT ='1' else '0';
RESET <= 'Z';
--RESET <= 'Z' when RESET_OUT ='1' else '0';
--RST <= '0' when RESET_OUT_AMIGA = '1' else 'Z';
--RESET <= RESET_OUT;
@ -474,7 +489,7 @@ begin
--dma stuff
DTACK <= 'Z'; --DTACK will be generated by GARY!
DTACK <= 'Z' when AS_000_DMA='1' else '0'; --DTACK will be generated by GARY!
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else
'0' when AS_000_DMA ='0' and AS_000 ='0' else
@ -485,7 +500,7 @@ begin
A(0) <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' --tristate on CPU-Cycle
else A0_DMA; --drive on DMA-Cycle
A(1) <= 'Z';
AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else x"00";
AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR RESET = '0' else x"00";
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else
SIZE_DMA;
--rw

10232
Logic/68030_TK.tcl
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2823
Logic/68030_tk.bl2
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1007
Logic/68030_tk.bl3
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2
Logic/68030_tk.crf
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@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 2.0.00.17.20.15
// Design '68030_tk' created Wed Oct 26 22:26:25 2016
// Design '68030_tk' created Fri Nov 18 19:32:36 2016
// LEGEND: '>' Functional Block Port Separator

350
Logic/68030_tk.eq3
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@ -2,7 +2,7 @@
Copyright(C), 1992-2015, Lattice Semiconductor Corp.
All Rights Reserved.
Design bus68030 created Wed Oct 26 22:26:25 2016
Design bus68030 created Fri Nov 18 19:32:36 2016
P-Terms Fan-in Fan-out Type Name (attributes)
@ -21,6 +21,15 @@ Design bus68030 created Wed Oct 26 22:26:25 2016
1 2 1 Pin LDS_000.OE
0 0 1 Pin BERR
1 9 1 Pin BERR.OE
1 1 1 Pin CLK_DIV_OUT
1 1 1 Pin CLK_EXP
1 9 1 Pin FPU_CS-
1 2 1 Pin DSACK1-
1 1 1 Pin DSACK1.OE
0 0 1 Pin DTACK
1 1 1 Pin DTACK.OE
1 0 1 Pin AVEC
2 3 1 Pin E
0 0 1 Pin AHIGH_30_
1 3 1 Pin AHIGH_30_.OE
0 0 1 Pin AHIGH_29_
@ -31,54 +40,45 @@ Design bus68030 created Wed Oct 26 22:26:25 2016
1 3 1 Pin AHIGH_27_.OE
0 0 1 Pin AHIGH_26_
1 3 1 Pin AHIGH_26_.OE
1 1 1 Pin CLK_DIV_OUT.D
1 1 1 Pin CLK_DIV_OUT.C
0 0 1 Pin AHIGH_25_
1 3 1 Pin AHIGH_25_.OE
0 0 1 Pin AMIGA_ADDR_ENABLE
0 0 1 Pin AHIGH_24_
1 3 1 Pin AHIGH_24_.OE
1 9 1 Pin FPU_CS-
1 2 1 Pin DSACK1-
1 1 1 Pin DSACK1.OE
1 0 1 Pin AVEC
2 3 1 Pin E
0 0 1 Pin RESET
1 1 1 Pin RESET.OE
0 0 1 Pin AMIGA_ADDR_ENABLE
2 4 1 Pin AMIGA_BUS_DATA_DIR
1 2 1 Pin AMIGA_BUS_ENABLE_LOW-
2 4 1 Pin AMIGA_BUS_ENABLE_HIGH-
1 13 1 Pin CIIN
1 1 1 Pin CIIN.OE
1 3 1 Pin A_0_.OE
3 5 1 Pin A_0_.D
1 1 1 Pin A_0_.C
1 2 1 Pin SIZE_1_.OE
3 6 1 Pin SIZE_1_.D
1 1 1 Pin SIZE_1_.C
9 10 1 Pin IPL_030_2_.T
10 8 1 Pin IPL_030_1_.D-
1 1 1 Pin IPL_030_1_.C
10 8 1 Pin IPL_030_0_.D-
1 1 1 Pin IPL_030_0_.C
10 8 1 Pin IPL_030_2_.D-
1 1 1 Pin IPL_030_2_.C
1 2 1 Pin RW_000.OE
4 8 1 Pin RW_000.D-
1 1 1 Pin RW_000.C
2 6 1 Pin BG_000.D-
1 1 1 Pin BG_000.C
3 6 1 Pin BGACK_030.D
1 1 1 Pin BGACK_030.C
1 2 1 Pin SIZE_0_.OE
3 6 1 Pin SIZE_0_.D-
1 1 1 Pin SIZE_0_.C
3 6 1 Pin BGACK_030.D
1 1 1 Pin BGACK_030.C
1 1 1 Pin CLK_EXP.D
1 1 1 Pin CLK_EXP.C
3 9 1 Pin VMA.T
1 1 1 Pin VMA.C
1 2 1 Pin RW.OE
2 5 1 Pin RW.D-
1 1 1 Pin RW.C
1 3 1 Pin A_0_.OE
3 5 1 Pin A_0_.D
1 1 1 Pin A_0_.C
9 10 1 Pin IPL_030_1_.T
1 1 1 Pin IPL_030_1_.C
9 10 1 Pin IPL_030_0_.T
1 1 1 Pin IPL_030_0_.C
4 5 1 Node cpu_est_1_.D
1 1 1 Node cpu_est_1_.C
1 1 1 NodeX1 cpu_est_2_.D.X1
1 4 1 NodeX2 cpu_est_2_.D.X2
1 1 1 Node cpu_est_2_.C
@ -86,8 +86,6 @@ Design bus68030 created Wed Oct 26 22:26:25 2016
1 1 1 Node cpu_est_3_.C
3 3 1 Node cpu_est_0_.D
1 1 1 Node cpu_est_0_.C
4 5 1 Node cpu_est_1_.D
1 1 1 Node cpu_est_1_.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
@ -98,14 +96,10 @@ Design bus68030 created Wed Oct 26 22:26:25 2016
1 1 1 Node inst_AS_030_000_SYNC.C
1 2 1 Node inst_BGACK_030_INT_D.D-
1 1 1 Node inst_BGACK_030_INT_D.C
7 9 1 Node inst_AS_000_DMA.D
6 9 1 Node inst_AS_000_DMA.D
1 1 1 Node inst_AS_000_DMA.C
9 12 1 Node inst_DS_000_DMA.D
1 1 1 Node inst_DS_000_DMA.C
3 6 1 Node CYCLE_DMA_0_.D
1 1 1 Node CYCLE_DMA_0_.C
4 7 1 Node CYCLE_DMA_1_.D
1 1 1 Node CYCLE_DMA_1_.C
1 2 1 Node inst_VPA_D.D-
1 1 1 Node inst_VPA_D.C
1 1 1 Node CLK_000_D_3_.D
@ -114,6 +108,10 @@ Design bus68030 created Wed Oct 26 22:26:25 2016
1 1 1 Node inst_DTACK_D0.C
2 7 1 Node inst_RESET_OUT.D
1 1 1 Node inst_RESET_OUT.C
6 11 1 Node CLK_030_PE_1_.D
1 1 1 Node CLK_030_PE_1_.C
2 3 1 Node inst_AMIGA_DS.D
1 1 1 Node inst_AMIGA_DS.C
1 1 1 Node CLK_000_D_1_.D
1 1 1 Node CLK_000_D_1_.C
1 1 1 Node CLK_000_D_0_.D
@ -146,6 +144,12 @@ Design bus68030 created Wed Oct 26 22:26:25 2016
1 1 1 Node SM_AMIGA_1_.C
3 5 1 Node SM_AMIGA_0_.D
1 1 1 Node SM_AMIGA_0_.C
4 7 1 Node CYCLE_DMA_0_.D
1 1 1 Node CYCLE_DMA_0_.C
2 7 1 Node CYCLE_DMA_1_.D
1 1 1 Node CYCLE_DMA_1_.C
9 11 1 Node CLK_030_PE_0_.D-
1 1 1 Node CLK_030_PE_0_.C
4 6 1 Node RST_DLY_0_.D
1 1 1 Node RST_DLY_0_.C
2 6 1 NodeX1 RST_DLY_1_.D.X1
@ -153,8 +157,6 @@ Design bus68030 created Wed Oct 26 22:26:25 2016
1 1 1 Node RST_DLY_1_.C
2 6 1 Node RST_DLY_2_.D
1 1 1 Node RST_DLY_2_.C
8 10 1 Node inst_CLK_030_H.D
1 1 1 Node inst_CLK_030_H.C
2 6 1 Node inst_DSACK1_INT.D-
1 1 1 Node inst_DSACK1_INT.C
2 6 1 Node inst_AS_000_INT.D-
@ -168,11 +170,13 @@ Design bus68030 created Wed Oct 26 22:26:25 2016
3 9 1 NodeX1 SM_AMIGA_i_7_.T.X1
1 9 1 NodeX2 SM_AMIGA_i_7_.T.X2
1 1 1 Node SM_AMIGA_i_7_.C
1 1 1 Node CLK_OUT_INTreg.D
1 1 1 Node CLK_OUT_INTreg.C
2 14 1 Node CIIN_0
=========
269 P-Term Total: 269
281 P-Term Total: 281
Total Pins: 61
Total Nodes: 44
Total Nodes: 47
Average P-Term/Output: 2
@ -180,7 +184,7 @@ Equations:
AHIGH_31_ = (0);
AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_31_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q);
!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
@ -206,37 +210,9 @@ BERR = (0);
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
AHIGH_30_ = (0);
CLK_DIV_OUT = (CLK_OUT_INTreg.Q);
AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_29_ = (0);
AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_28_ = (0);
AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_27_ = (0);
AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_26_ = (0);
AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
CLK_DIV_OUT.C = (CLK_OSZI);
AHIGH_25_ = (0);
AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_24_ = (0);
AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
CLK_EXP = (CLK_OUT_INTreg.Q);
!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
@ -244,17 +220,45 @@ AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
DSACK1.OE = (nEXP_SPACE);
DTACK = (0);
DTACK.OE = (!inst_AS_000_DMA.Q);
AVEC = (1);
E = (cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_1_.Q
# !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_1_.Q);
E = (!cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q
# cpu_est_1_.Q & cpu_est_2_.Q & !cpu_est_3_.Q);
RESET = (0);
AHIGH_30_ = (0);
RESET.OE = (!inst_RESET_OUT.Q);
AHIGH_30_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q);
AHIGH_29_ = (0);
AHIGH_29_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q);
AHIGH_28_ = (0);
AHIGH_28_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q);
AHIGH_27_ = (0);
AHIGH_27_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q);
AHIGH_26_ = (0);
AHIGH_26_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q);
AHIGH_25_ = (0);
AHIGH_25_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q);
AMIGA_ADDR_ENABLE = (0);
AHIGH_24_ = (0);
AHIGH_24_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q);
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
# !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN);
@ -267,6 +271,14 @@ CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030
CIIN.OE = (CIIN_0);
A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
A_0_.D = (!RST
# !BGACK_030.Q & UDS_000.PIN
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & A_0_.Q);
A_0_.C = (CLK_OSZI);
SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q);
SIZE_1_.D = (!RST
@ -275,15 +287,42 @@ SIZE_1_.D = (!RST
SIZE_1_.C = (CLK_OSZI);
IPL_030_2_.T = (!RST & !IPL_030_2_.Q
# IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q
# IPL_2_ & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q
# IPL_2_ & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q
# IPL_2_ & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q
# !IPL_2_ & RST & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q);
!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
# RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q
# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q
# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q
# IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
IPL_030_1_.C = (CLK_OSZI);
!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q
# RST & !IPL_D0_0_.Q & !IPL_030_0_.Q
# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q
# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q
# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q
# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q
# IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
IPL_030_0_.C = (CLK_OSZI);
!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
# RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q
# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q
# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q
# !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
IPL_030_2_.C = (CLK_OSZI);
@ -301,6 +340,12 @@ RW_000.C = (CLK_OSZI);
BG_000.C = (CLK_OSZI);
BGACK_030.D = (!RST
# BGACK_000 & BGACK_030.Q
# BGACK_000 & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & AS_000.PIN);
BGACK_030.C = (CLK_OSZI);
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q);
!SIZE_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q
@ -309,19 +354,9 @@ SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q);
SIZE_0_.C = (CLK_OSZI);
BGACK_030.D = (!RST
# BGACK_000 & BGACK_030.Q
# BGACK_000 & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & AS_000.PIN);
BGACK_030.C = (CLK_OSZI);
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
CLK_EXP.C = (CLK_OSZI);
VMA.T = (!RST & !VMA.Q
# !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q
# RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
# !VMA.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q
# RST & VMA.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
VMA.C = (CLK_OSZI);
@ -332,48 +367,23 @@ RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
RW.C = (CLK_OSZI);
A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
cpu_est_1_.D = (cpu_est_1_.Q & !cpu_est_0_.Q
# cpu_est_1_.Q & !CLK_000_D_1_.Q
# cpu_est_1_.Q & CLK_000_D_0_.Q
# !cpu_est_1_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
A_0_.D = (!RST
# !BGACK_030.Q & UDS_000.PIN
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & A_0_.Q);
A_0_.C = (CLK_OSZI);
IPL_030_1_.T = (!RST & !IPL_030_1_.Q
# IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_1_.Q
# IPL_2_ & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_1_.Q
# !IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_1_.Q
# !IPL_2_ & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_1_.Q
# IPL_2_ & RST & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_1_.Q
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_1_.Q
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_1_.Q
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_1_.Q);
IPL_030_1_.C = (CLK_OSZI);
IPL_030_0_.T = (!RST & !IPL_030_0_.Q
# IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_0_.Q
# IPL_2_ & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_0_.Q
# !IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_0_.Q
# !IPL_2_ & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_0_.Q
# IPL_2_ & RST & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_0_.Q
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_0_.Q
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_0_.Q
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_0_.Q);
IPL_030_0_.C = (CLK_OSZI);
cpu_est_1_.C = (CLK_OSZI);
cpu_est_2_.D.X1 = (cpu_est_2_.Q);
cpu_est_2_.D.X2 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
cpu_est_2_.D.X2 = (cpu_est_1_.Q & cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
cpu_est_2_.C = (CLK_OSZI);
cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q
# cpu_est_3_.Q & CLK_000_D_0_.Q
# !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q
# cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
# cpu_est_1_.Q & cpu_est_2_.Q & cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
cpu_est_3_.C = (CLK_OSZI);
@ -383,13 +393,6 @@ cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q
cpu_est_0_.C = (CLK_OSZI);
cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q
# cpu_est_1_.Q & !CLK_000_D_1_.Q
# cpu_est_1_.Q & CLK_000_D_0_.Q
# !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
cpu_est_1_.C = (CLK_OSZI);
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q
# RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q & inst_BGACK_030_INT_D.Q);
@ -419,40 +422,26 @@ inst_AS_030_000_SYNC.C = (CLK_OSZI);
inst_BGACK_030_INT_D.C = (CLK_OSZI);
inst_AS_000_DMA.D = (!RST
# BGACK_030.Q
# inst_AMIGA_DS.Q
# AS_000.PIN
# !CLK_030 & inst_AS_000_DMA.Q
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
# UDS_000.PIN & LDS_000.PIN);
# inst_AS_000_DMA.Q & inst_CLK_OUT_PRE_D.Q & !CLK_OUT_INTreg.Q
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN);
inst_AS_000_DMA.C = (CLK_OSZI);
inst_DS_000_DMA.D = (!RST
# BGACK_030.Q
# inst_AMIGA_DS.Q
# AS_000.PIN
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
# UDS_000.PIN & LDS_000.PIN
# !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN
# inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN
# CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN);
# inst_DS_000_DMA.Q & CLK_030_PE_1_.Q & !RW_000.PIN
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN
# inst_DS_000_DMA.Q & !CLK_030_PE_0_.Q & !RW_000.PIN
# inst_DS_000_DMA.Q & inst_CLK_OUT_PRE_D.Q & !CLK_OUT_INTreg.Q & RW_000.PIN);
inst_DS_000_DMA.C = (CLK_OSZI);
CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & CLK_000_D_1_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CLK_000_D_0_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !AS_000.PIN);
CYCLE_DMA_0_.C = (CLK_OSZI);
CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & CLK_000_D_1_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !CLK_000_D_0_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !AS_000.PIN);
CYCLE_DMA_1_.C = (CLK_OSZI);
!inst_VPA_D.D = (!VPA & RST);
inst_VPA_D.C = (CLK_OSZI);
@ -461,7 +450,7 @@ CLK_000_D_3_.D = (CLK_000_D_2_.Q);
CLK_000_D_3_.C = (CLK_OSZI);
!inst_DTACK_D0.D = (!DTACK & RST);
!inst_DTACK_D0.D = (RST & !DTACK.PIN);
inst_DTACK_D0.C = (CLK_OSZI);
@ -470,6 +459,20 @@ inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q
inst_RESET_OUT.C = (CLK_OSZI);
CLK_030_PE_1_.D = (RST & CLK_030_PE_1_.Q & !inst_AMIGA_DS.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
# RST & CLK_030_PE_1_.Q & !inst_AMIGA_DS.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN
# RST & CLK_030_PE_1_.Q & !inst_AMIGA_DS.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & RW_000.PIN
# RST & !inst_AS_000_DMA.Q & !inst_AMIGA_DS.Q & inst_CLK_OUT_PRE_D.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q & !AS_000.PIN
# RST & !inst_AS_000_DMA.Q & !inst_AMIGA_DS.Q & inst_CLK_OUT_PRE_D.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q & !AS_000.PIN
# RST & !inst_AS_000_DMA.Q & !inst_AMIGA_DS.Q & inst_CLK_OUT_PRE_D.Q & CYCLE_DMA_1_.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q & !AS_000.PIN & RW_000.PIN);
CLK_030_PE_1_.C = (CLK_OSZI);
inst_AMIGA_DS.D = (!RST
# UDS_000.PIN & LDS_000.PIN);
inst_AMIGA_DS.C = (CLK_OSZI);
CLK_000_D_1_.D = (CLK_000_D_0_.Q);
CLK_000_D_1_.C = (CLK_OSZI);
@ -547,6 +550,30 @@ SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q
SM_AMIGA_0_.C = (CLK_OSZI);
CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CLK_000_D_1_.Q & CYCLE_DMA_0_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CLK_000_D_0_.Q & CYCLE_DMA_0_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !CYCLE_DMA_0_.Q & !AS_000.PIN);
CYCLE_DMA_0_.C = (CLK_OSZI);
CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & CYCLE_DMA_0_.Q & !AS_000.PIN);
CYCLE_DMA_1_.C = (CLK_OSZI);
!CLK_030_PE_0_.D = (!RST
# inst_AMIGA_DS.Q
# AS_000.PIN
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
# inst_AS_000_DMA.Q & !CLK_030_PE_0_.Q
# !inst_CLK_OUT_PRE_D.Q & !CLK_030_PE_0_.Q
# !CLK_030_PE_0_.Q & CLK_OUT_INTreg.Q
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN
# !inst_AS_000_DMA.Q & !CLK_030_PE_1_.Q & inst_CLK_OUT_PRE_D.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q);
CLK_030_PE_0_.C = (CLK_OSZI);
RST_DLY_0_.D = (RST & !CLK_000_D_1_.Q & RST_DLY_0_.Q
# RST & CLK_000_D_0_.Q & RST_DLY_0_.Q
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !RST_DLY_0_.Q
@ -566,17 +593,6 @@ RST_DLY_2_.D = (RST & RST_DLY_2_.Q
RST_DLY_2_.C = (CLK_OSZI);
inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
# RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN);
inst_CLK_030_H.C = (CLK_OSZI);
!inst_DSACK1_INT.D = (RST & !inst_DSACK1_INT.Q & !AS_030.PIN
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q);
@ -597,7 +613,7 @@ SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
# CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
# inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
# !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
# !VMA.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
SM_AMIGA_3_.C = (CLK_OSZI);
@ -605,7 +621,7 @@ SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q
# RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
# RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
# RST & !VMA.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
SM_AMIGA_2_.C = (CLK_OSZI);
@ -617,6 +633,10 @@ SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_
SM_AMIGA_i_7_.C = (CLK_OSZI);
CLK_OUT_INTreg.D = (inst_CLK_OUT_PRE_D.Q);
CLK_OUT_INTreg.C = (CLK_OSZI);
CIIN_0 = (nEXP_SPACE
# A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);

219
Logic/68030_tk.fti
View File

@ -11,9 +11,9 @@ DATA LOCATION AHIGH_28_:C_0_15 // IO
DATA LOCATION AHIGH_29_:B_8_6 // IO
DATA LOCATION AHIGH_30_:B_0_5 // IO
DATA LOCATION AHIGH_31_:B_12_4 // IO
DATA LOCATION AMIGA_ADDR_ENABLE:D_5_33 // OUT
DATA LOCATION AMIGA_ADDR_ENABLE:D_9_33 // OUT
DATA LOCATION AMIGA_BUS_DATA_DIR:E_1_48 // OUT
DATA LOCATION AMIGA_BUS_ENABLE_HIGH:D_4_34 // OUT
DATA LOCATION AMIGA_BUS_ENABLE_HIGH:D_5_34 // OUT
DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_1_20 // OUT
DATA LOCATION AS_000:E_4_42 // IO
DATA LOCATION AS_030:H_8_82 // IO
@ -34,22 +34,25 @@ DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030}
DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000}
DATA LOCATION BG_030:C_*_21 // INP
DATA LOCATION CIIN:E_12_47 // OUT
DATA LOCATION CIIN_0:E_9 // NOD
DATA LOCATION CIIN_0:E_5 // NOD
DATA LOCATION CLK_000:*_*_11 // INP
DATA LOCATION CLK_000_D_0_:C_9 // NOD
DATA LOCATION CLK_000_D_0_:D_13 // NOD
DATA LOCATION CLK_000_D_1_:H_5 // NOD
DATA LOCATION CLK_000_D_2_:H_6 // NOD
DATA LOCATION CLK_000_D_3_:D_10 // NOD
DATA LOCATION CLK_000_D_4_:B_10 // NOD
DATA LOCATION CLK_000_D_3_:F_13 // NOD
DATA LOCATION CLK_000_D_4_:C_14 // NOD
DATA LOCATION CLK_030:*_*_64 // INP
DATA LOCATION CLK_030_PE_0_:A_9 // NOD
DATA LOCATION CLK_030_PE_1_:A_2 // NOD
DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT
DATA LOCATION CLK_EXP:B_1_10 // OUT
DATA LOCATION CLK_OSZI:*_*_61 // Cin
DATA LOCATION CYCLE_DMA_0_:A_10 // NOD
DATA LOCATION CYCLE_DMA_1_:A_6 // NOD
DATA LOCATION CLK_OUT_INTreg:D_10 // NOD
DATA LOCATION CYCLE_DMA_0_:A_6 // NOD
DATA LOCATION CYCLE_DMA_1_:A_10 // NOD
DATA LOCATION DSACK1:H_9_81 // OUT
DATA LOCATION DS_030:A_0_98 // OUT
DATA LOCATION DTACK:D_*_30 // INP
DATA LOCATION DTACK:D_0_30 // IO
DATA LOCATION E:G_4_66 // OUT
DATA LOCATION FC_0_:F_*_57 // INP
DATA LOCATION FC_1_:F_*_58 // INP
@ -61,11 +64,11 @@ DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_}
DATA LOCATION IPL_0_:G_*_67 // INP
DATA LOCATION IPL_1_:F_*_56 // INP
DATA LOCATION IPL_2_:G_*_68 // INP
DATA LOCATION IPL_D0_0_:G_14 // NOD
DATA LOCATION IPL_D0_1_:D_14 // NOD
DATA LOCATION IPL_D0_2_:B_14 // NOD
DATA LOCATION IPL_D0_0_:B_10 // NOD
DATA LOCATION IPL_D0_1_:B_6 // NOD
DATA LOCATION IPL_D0_2_:B_2 // NOD
DATA LOCATION LDS_000:D_12_31 // IO
DATA LOCATION RESET:B_2_3 // OUT
DATA LOCATION RESET:B_*_3 // INP
DATA LOCATION RN_A_0_:G_8 // NOD {A_0_}
DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030}
DATA LOCATION RN_BG_000:D_1 // NOD {BG_000}
@ -76,48 +79,48 @@ DATA LOCATION RN_RW:G_0 // NOD {RW}
DATA LOCATION RN_RW_000:H_0 // NOD {RW_000}
DATA LOCATION RN_SIZE_0_:G_12 // NOD {SIZE_0_}
DATA LOCATION RN_SIZE_1_:H_12 // NOD {SIZE_1_}
DATA LOCATION RN_VMA:D_0 // NOD {VMA}
DATA LOCATION RN_VMA:D_4 // NOD {VMA}
DATA LOCATION RST:*_*_86 // INP
DATA LOCATION RST_DLY_0_:G_2 // NOD
DATA LOCATION RST_DLY_1_:G_10 // NOD
DATA LOCATION RST_DLY_2_:G_6 // NOD
DATA LOCATION RST_DLY_0_:G_6 // NOD
DATA LOCATION RST_DLY_1_:G_14 // NOD
DATA LOCATION RST_DLY_2_:G_10 // NOD
DATA LOCATION RW:G_0_71 // IO {RN_RW}
DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000}
DATA LOCATION SIZE_0_:G_12_70 // IO {RN_SIZE_0_}
DATA LOCATION SIZE_1_:H_12_79 // IO {RN_SIZE_1_}
DATA LOCATION SM_AMIGA_0_:H_13 // NOD
DATA LOCATION SM_AMIGA_1_:F_4 // NOD
DATA LOCATION SM_AMIGA_2_:A_5 // NOD
DATA LOCATION SM_AMIGA_3_:D_13 // NOD
DATA LOCATION SM_AMIGA_4_:D_2 // NOD
DATA LOCATION SM_AMIGA_5_:C_6 // NOD
DATA LOCATION SM_AMIGA_6_:C_13 // NOD
DATA LOCATION SM_AMIGA_i_7_:C_2 // NOD
DATA LOCATION SM_AMIGA_0_:A_12 // NOD
DATA LOCATION SM_AMIGA_1_:F_8 // NOD
DATA LOCATION SM_AMIGA_2_:C_9 // NOD
DATA LOCATION SM_AMIGA_3_:C_6 // NOD
DATA LOCATION SM_AMIGA_4_:A_1 // NOD
DATA LOCATION SM_AMIGA_5_:G_13 // NOD
DATA LOCATION SM_AMIGA_6_:F_0 // NOD
DATA LOCATION SM_AMIGA_i_7_:F_4 // NOD
DATA LOCATION UDS_000:D_8_32 // IO
DATA LOCATION VMA:D_0_35 // IO {RN_VMA}
DATA LOCATION VMA:D_4_35 // IO {RN_VMA}
DATA LOCATION VPA:*_*_36 // INP
DATA LOCATION cpu_est_0_:G_9 // NOD
DATA LOCATION cpu_est_1_:A_8 // NOD
DATA LOCATION cpu_est_2_:A_12 // NOD
DATA LOCATION cpu_est_3_:D_9 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:C_14 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:F_1 // NOD
DATA LOCATION inst_AS_000_DMA:A_1 // NOD
DATA LOCATION inst_AS_000_INT:C_10 // NOD
DATA LOCATION inst_AS_030_000_SYNC:F_0 // NOD
DATA LOCATION inst_AS_030_D0:E_5 // NOD
DATA LOCATION inst_BGACK_030_INT_D:E_8 // NOD
DATA LOCATION inst_CLK_030_H:A_2 // NOD
DATA LOCATION inst_CLK_OUT_PRE_50:G_13 // NOD
DATA LOCATION inst_CLK_OUT_PRE_D:D_6 // NOD
DATA LOCATION inst_DSACK1_INT:H_2 // NOD
DATA LOCATION cpu_est_1_:D_6 // NOD
DATA LOCATION cpu_est_2_:D_14 // NOD
DATA LOCATION cpu_est_3_:D_2 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:F_9 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:F_5 // NOD
DATA LOCATION inst_AMIGA_DS:C_10 // NOD
DATA LOCATION inst_AS_000_DMA:A_8 // NOD
DATA LOCATION inst_AS_000_INT:C_2 // NOD
DATA LOCATION inst_AS_030_000_SYNC:B_13 // NOD
DATA LOCATION inst_AS_030_D0:H_2 // NOD
DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD
DATA LOCATION inst_CLK_OUT_PRE_50:G_2 // NOD
DATA LOCATION inst_CLK_OUT_PRE_D:E_8 // NOD
DATA LOCATION inst_DSACK1_INT:A_5 // NOD
DATA LOCATION inst_DS_000_DMA:A_13 // NOD
DATA LOCATION inst_DS_000_ENABLE:B_13 // NOD
DATA LOCATION inst_DTACK_D0:B_6 // NOD
DATA LOCATION inst_LDS_000_INT:F_8 // NOD
DATA LOCATION inst_DS_000_ENABLE:C_13 // NOD
DATA LOCATION inst_DTACK_D0:B_14 // NOD
DATA LOCATION inst_LDS_000_INT:F_12 // NOD
DATA LOCATION inst_RESET_OUT:G_5 // NOD
DATA LOCATION inst_UDS_000_INT:F_12 // NOD
DATA LOCATION inst_VPA_D:A_9 // NOD
DATA LOCATION inst_UDS_000_INT:F_1 // NOD
DATA LOCATION inst_VPA_D:F_2 // NOD
DATA LOCATION nEXP_SPACE:*_*_14 // INP
DATA IO_DIR AHIGH_24_:BI
DATA IO_DIR AHIGH_25_:BI
@ -157,7 +160,7 @@ DATA IO_DIR CLK_EXP:OUT
DATA IO_DIR CLK_OSZI:IN
DATA IO_DIR DSACK1:OUT
DATA IO_DIR DS_030:OUT
DATA IO_DIR DTACK:IN
DATA IO_DIR DTACK:BI
DATA IO_DIR E:OUT
DATA IO_DIR FC_0_:IN
DATA IO_DIR FC_1_:IN
@ -170,7 +173,7 @@ DATA IO_DIR IPL_0_:IN
DATA IO_DIR IPL_1_:IN
DATA IO_DIR IPL_2_:IN
DATA IO_DIR LDS_000:BI
DATA IO_DIR RESET:OUT
DATA IO_DIR RESET:IN
DATA IO_DIR RST:IN
DATA IO_DIR RW:BI
DATA IO_DIR RW_000:BI
@ -183,8 +186,16 @@ DATA IO_DIR nEXP_SPACE:IN
DATA GLB_CLOCK CLK_OSZI
DATA PW_LEVEL AHIGH_31_:1
DATA SLEW AHIGH_31_:0
DATA PW_LEVEL IPL_1_:1
DATA SLEW IPL_1_:1
DATA PW_LEVEL IPL_0_:1
DATA SLEW IPL_0_:1
DATA PW_LEVEL A_DECODE_23_:1
DATA SLEW A_DECODE_23_:1
DATA PW_LEVEL FC_0_:1
DATA SLEW FC_0_:1
DATA PW_LEVEL A_1_:1
DATA SLEW A_1_:1
DATA PW_LEVEL IPL_2_:1
DATA SLEW IPL_2_:1
DATA PW_LEVEL FC_1_:1
@ -204,107 +215,99 @@ DATA PW_LEVEL BERR:1
DATA SLEW BERR:0
DATA PW_LEVEL BG_030:1
DATA SLEW BG_030:1
DATA PW_LEVEL AHIGH_30_:1
DATA SLEW AHIGH_30_:0
DATA PW_LEVEL BGACK_000:1
DATA SLEW BGACK_000:1
DATA PW_LEVEL AHIGH_29_:1
DATA SLEW AHIGH_29_:0
DATA SLEW CLK_030:1
DATA PW_LEVEL AHIGH_28_:1
DATA SLEW AHIGH_28_:0
DATA SLEW CLK_000:1
DATA PW_LEVEL AHIGH_27_:1
DATA SLEW AHIGH_27_:0
DATA SLEW CLK_OSZI:1
DATA PW_LEVEL AHIGH_26_:1
DATA SLEW AHIGH_26_:0
DATA PW_LEVEL CLK_DIV_OUT:1
DATA SLEW CLK_DIV_OUT:0
DATA PW_LEVEL AHIGH_25_:1
DATA SLEW AHIGH_25_:0
DATA PW_LEVEL AHIGH_24_:1
DATA SLEW AHIGH_24_:0
DATA PW_LEVEL CLK_EXP:1
DATA SLEW CLK_EXP:0
DATA PW_LEVEL FPU_CS:1
DATA SLEW FPU_CS:0
DATA PW_LEVEL A_DECODE_22_:1
DATA SLEW A_DECODE_22_:1
DATA PW_LEVEL FPU_SENSE:1
DATA SLEW FPU_SENSE:1
DATA PW_LEVEL A_DECODE_21_:1
DATA SLEW A_DECODE_21_:1
DATA PW_LEVEL DSACK1:1
DATA SLEW DSACK1:0
DATA PW_LEVEL A_DECODE_20_:1
DATA SLEW A_DECODE_20_:1
DATA PW_LEVEL DTACK:1
DATA SLEW DTACK:1
DATA PW_LEVEL A_DECODE_19_:1
DATA SLEW A_DECODE_19_:1
DATA PW_LEVEL AVEC:1
DATA SLEW AVEC:0
DATA PW_LEVEL A_DECODE_18_:1
DATA SLEW A_DECODE_18_:1
DATA PW_LEVEL E:1
DATA SLEW E:0
DATA PW_LEVEL A_DECODE_17_:1
DATA SLEW A_DECODE_17_:1
DATA PW_LEVEL AHIGH_30_:1
DATA SLEW AHIGH_30_:0
DATA SLEW VPA:1
DATA PW_LEVEL A_DECODE_16_:1
DATA SLEW A_DECODE_16_:1
DATA PW_LEVEL AHIGH_29_:1
DATA SLEW AHIGH_29_:0
DATA PW_LEVEL AHIGH_28_:1
DATA SLEW AHIGH_28_:0
DATA SLEW RST:1
DATA PW_LEVEL AHIGH_27_:1
DATA SLEW AHIGH_27_:0
DATA PW_LEVEL RESET:1
DATA SLEW RESET:0
DATA PW_LEVEL AHIGH_26_:1
DATA SLEW AHIGH_26_:0
DATA PW_LEVEL AHIGH_25_:1
DATA SLEW AHIGH_25_:0
DATA PW_LEVEL AMIGA_ADDR_ENABLE:1
DATA SLEW AMIGA_ADDR_ENABLE:0
DATA PW_LEVEL AHIGH_24_:1
DATA SLEW AHIGH_24_:0
DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1
DATA SLEW AMIGA_BUS_DATA_DIR:0
DATA PW_LEVEL A_DECODE_22_:1
DATA SLEW A_DECODE_22_:1
DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:1
DATA SLEW AMIGA_BUS_ENABLE_LOW:0
DATA PW_LEVEL A_DECODE_21_:1
DATA SLEW A_DECODE_21_:1
DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1
DATA SLEW AMIGA_BUS_ENABLE_HIGH:0
DATA PW_LEVEL A_DECODE_20_:1
DATA SLEW A_DECODE_20_:1
DATA PW_LEVEL CIIN:1
DATA SLEW CIIN:0
DATA PW_LEVEL IPL_1_:1
DATA SLEW IPL_1_:1
DATA PW_LEVEL IPL_0_:1
DATA SLEW IPL_0_:1
DATA PW_LEVEL FC_0_:1
DATA SLEW FC_0_:1
DATA PW_LEVEL A_1_:1
DATA SLEW A_1_:1
DATA PW_LEVEL A_DECODE_19_:1
DATA SLEW A_DECODE_19_:1
DATA PW_LEVEL A_DECODE_18_:1
DATA SLEW A_DECODE_18_:1
DATA PW_LEVEL A_DECODE_17_:1
DATA SLEW A_DECODE_17_:1
DATA PW_LEVEL A_DECODE_16_:1
DATA SLEW A_DECODE_16_:1
DATA PW_LEVEL A_0_:1
DATA SLEW A_0_:0
DATA PW_LEVEL SIZE_1_:1
DATA SLEW SIZE_1_:0
DATA PW_LEVEL IPL_030_1_:1
DATA SLEW IPL_030_1_:0
DATA PW_LEVEL IPL_030_0_:1
DATA SLEW IPL_030_0_:0
DATA PW_LEVEL IPL_030_2_:1
DATA SLEW IPL_030_2_:0
DATA PW_LEVEL RW_000:1
DATA SLEW RW_000:0
DATA PW_LEVEL BG_000:1
DATA SLEW BG_000:0
DATA PW_LEVEL SIZE_0_:1
DATA SLEW SIZE_0_:0
DATA PW_LEVEL BGACK_030:1
DATA SLEW BGACK_030:0
DATA PW_LEVEL CLK_EXP:1
DATA SLEW CLK_EXP:0
DATA PW_LEVEL SIZE_0_:1
DATA SLEW SIZE_0_:0
DATA PW_LEVEL VMA:1
DATA SLEW VMA:0
DATA PW_LEVEL RW:1
DATA SLEW RW:0
DATA PW_LEVEL A_0_:1
DATA SLEW A_0_:0
DATA PW_LEVEL IPL_030_1_:1
DATA SLEW IPL_030_1_:0
DATA PW_LEVEL IPL_030_0_:1
DATA SLEW IPL_030_0_:0
DATA PW_LEVEL cpu_est_1_:1
DATA SLEW cpu_est_1_:1
DATA PW_LEVEL cpu_est_2_:1
DATA SLEW cpu_est_2_:1
DATA PW_LEVEL cpu_est_3_:1
DATA SLEW cpu_est_3_:1
DATA PW_LEVEL cpu_est_0_:1
DATA SLEW cpu_est_0_:1
DATA PW_LEVEL cpu_est_1_:1
DATA SLEW cpu_est_1_:1
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1
@ -319,10 +322,6 @@ DATA PW_LEVEL inst_AS_000_DMA:1
DATA SLEW inst_AS_000_DMA:1
DATA PW_LEVEL inst_DS_000_DMA:1
DATA SLEW inst_DS_000_DMA:1
DATA PW_LEVEL CYCLE_DMA_0_:1
DATA SLEW CYCLE_DMA_0_:1
DATA PW_LEVEL CYCLE_DMA_1_:1
DATA SLEW CYCLE_DMA_1_:1
DATA PW_LEVEL inst_VPA_D:1
DATA SLEW inst_VPA_D:1
DATA PW_LEVEL CLK_000_D_3_:1
@ -331,6 +330,10 @@ DATA PW_LEVEL inst_DTACK_D0:1
DATA SLEW inst_DTACK_D0:1
DATA PW_LEVEL inst_RESET_OUT:1
DATA SLEW inst_RESET_OUT:1
DATA PW_LEVEL CLK_030_PE_1_:1
DATA SLEW CLK_030_PE_1_:1
DATA PW_LEVEL inst_AMIGA_DS:1
DATA SLEW inst_AMIGA_DS:1
DATA PW_LEVEL CLK_000_D_1_:1
DATA SLEW CLK_000_D_1_:1
DATA PW_LEVEL CLK_000_D_0_:1
@ -363,14 +366,18 @@ DATA PW_LEVEL SM_AMIGA_1_:1
DATA SLEW SM_AMIGA_1_:1
DATA PW_LEVEL SM_AMIGA_0_:1
DATA SLEW SM_AMIGA_0_:1
DATA PW_LEVEL CYCLE_DMA_0_:1
DATA SLEW CYCLE_DMA_0_:1
DATA PW_LEVEL CYCLE_DMA_1_:1
DATA SLEW CYCLE_DMA_1_:1
DATA PW_LEVEL CLK_030_PE_0_:1
DATA SLEW CLK_030_PE_0_:1
DATA PW_LEVEL RST_DLY_0_:1
DATA SLEW RST_DLY_0_:1
DATA PW_LEVEL RST_DLY_1_:1
DATA SLEW RST_DLY_1_:1
DATA PW_LEVEL RST_DLY_2_:1
DATA SLEW RST_DLY_2_:1
DATA PW_LEVEL inst_CLK_030_H:1
DATA SLEW inst_CLK_030_H:1
DATA PW_LEVEL inst_DSACK1_INT:1
DATA SLEW inst_DSACK1_INT:1
DATA PW_LEVEL inst_AS_000_INT:1
@ -383,17 +390,19 @@ DATA PW_LEVEL SM_AMIGA_2_:1
DATA SLEW SM_AMIGA_2_:1
DATA PW_LEVEL SM_AMIGA_i_7_:1
DATA SLEW SM_AMIGA_i_7_:1
DATA PW_LEVEL CLK_OUT_INTreg:1
DATA SLEW CLK_OUT_INTreg:1
DATA PW_LEVEL CIIN_0:1
DATA SLEW CIIN_0:1
DATA PW_LEVEL RN_A_0_:1
DATA PW_LEVEL RN_SIZE_1_:1
DATA PW_LEVEL RN_IPL_030_1_:1
DATA PW_LEVEL RN_IPL_030_0_:1
DATA PW_LEVEL RN_IPL_030_2_:1
DATA PW_LEVEL RN_RW_000:1
DATA PW_LEVEL RN_BG_000:1
DATA PW_LEVEL RN_SIZE_0_:1
DATA PW_LEVEL RN_BGACK_030:1
DATA PW_LEVEL RN_SIZE_0_:1
DATA PW_LEVEL RN_VMA:1
DATA PW_LEVEL RN_RW:1
DATA PW_LEVEL RN_A_0_:1
DATA PW_LEVEL RN_IPL_030_1_:1
DATA PW_LEVEL RN_IPL_030_0_:1
END

31
Logic/68030_tk.grp
View File

@ -1,23 +1,24 @@
GROUP MACH_SEG_A DS_030 AVEC SM_AMIGA_2_ inst_DS_000_DMA inst_CLK_030_H
inst_AS_000_DMA CYCLE_DMA_1_ CYCLE_DMA_0_ cpu_est_2_ cpu_est_1_ inst_VPA_D
GROUP MACH_SEG_A DS_030 AVEC inst_DS_000_DMA CLK_030_PE_1_ CLK_030_PE_0_
inst_AS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT SM_AMIGA_4_
SM_AMIGA_0_
GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP RESET inst_DS_000_ENABLE
inst_DTACK_D0 IPL_D0_2_ CLK_000_D_4_
RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP inst_AS_030_000_SYNC
inst_DTACK_D0 IPL_D0_0_ IPL_D0_1_ IPL_D0_2_
GROUP MACH_SEG_C AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AMIGA_BUS_ENABLE_LOW
SM_AMIGA_i_7_ SM_AMIGA_6_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_HIGH
SM_AMIGA_5_ CLK_000_D_0_
SM_AMIGA_2_ SM_AMIGA_3_ inst_DS_000_ENABLE inst_AS_000_INT inst_AMIGA_DS
CLK_000_D_4_
GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 AMIGA_BUS_ENABLE_HIGH LDS_000
UDS_000 AMIGA_ADDR_ENABLE SM_AMIGA_3_ cpu_est_3_ SM_AMIGA_4_ IPL_D0_1_
CLK_000_D_3_ inst_CLK_OUT_PRE_D
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 inst_AS_030_D0
inst_BGACK_030_INT_D
GROUP MACH_SEG_F inst_AS_030_000_SYNC inst_LDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW
SM_AMIGA_1_ inst_UDS_000_INT
UDS_000 DTACK AMIGA_ADDR_ENABLE cpu_est_3_ cpu_est_1_ cpu_est_2_
CLK_000_D_0_ CLK_OUT_INTreg
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 inst_CLK_OUT_PRE_D
GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_6_ inst_LDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_AMIGA_BUS_ENABLE_DMA_LOW SM_AMIGA_1_ inst_UDS_000_INT inst_VPA_D
CLK_000_D_3_
GROUP MACH_SEG_G SIZE_0_ RN_SIZE_0_ A_0_ RN_A_0_ RW RN_RW E CLK_DIV_OUT
inst_RESET_OUT RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ cpu_est_0_ IPL_D0_0_
inst_RESET_OUT RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ SM_AMIGA_5_ cpu_est_0_
inst_CLK_OUT_PRE_50
GROUP MACH_SEG_H RW_000 RN_RW_000 FPU_CS SIZE_1_ RN_SIZE_1_ BGACK_030 RN_BGACK_030
AS_030 DSACK1 inst_DSACK1_INT SM_AMIGA_0_ CLK_000_D_2_ CLK_000_D_1_
AS_030 DSACK1 inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_D_2_ CLK_000_D_1_

2
Logic/68030_tk.ipr
View File

@ -1 +1 @@
<LATTICE_ENCRYPTED_BLIF>5970501@qV_IP
<LATTICE_ENCRYPTED_BLIF>64;0=1?P_reM=E>

955
Logic/68030_tk.jed
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File diff suppressed because it is too large Load Diff

131
Logic/68030_tk.lco
View File

@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = 68030_tk.tt4;
DATE = 10/26/16;
TIME = 22:26:30;
DATE = 11/18/16;
TIME = 19:32:41;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;
@ -77,7 +77,11 @@ Usercode_Format = Hex;
[LOCATION ASSIGNMENTS]
Layer = OFF;
AHIGH_31_ = pin,4,-,B,-;
IPL_1_ = pin,56,-,F,-;
IPL_0_ = pin,67,-,G,-;
A_DECODE_23_ = pin,85,-,H,-;
FC_0_ = pin,57,-,F,-;
A_1_ = pin,60,-,F,-;
IPL_2_ = pin,68,-,G,-;
FC_1_ = pin,58,-,F,-;
AS_030 = pin,82,-,H,-;
@ -88,99 +92,98 @@ LDS_000 = pin,31,-,D,-;
nEXP_SPACE = pin,14,-,-,-;
BERR = pin,41,-,E,-;
BG_030 = pin,21,-,C,-;
AHIGH_30_ = pin,5,-,B,-;
BGACK_000 = pin,28,-,D,-;
AHIGH_29_ = pin,6,-,B,-;
CLK_030 = pin,64,-,-,-;
AHIGH_28_ = pin,15,-,C,-;
CLK_000 = pin,11,-,-,-;
AHIGH_27_ = pin,16,-,C,-;
CLK_OSZI = pin,61,-,-,-;
AHIGH_26_ = pin,17,-,C,-;
CLK_DIV_OUT = pin,65,-,G,-;
AHIGH_25_ = pin,18,-,C,-;
AHIGH_24_ = pin,19,-,C,-;
CLK_EXP = pin,10,-,B,-;
FPU_CS = pin,78,-,H,-;
A_DECODE_22_ = pin,84,-,H,-;
FPU_SENSE = pin,91,-,A,-;
A_DECODE_21_ = pin,94,-,A,-;
DSACK1 = pin,81,-,H,-;
A_DECODE_20_ = pin,93,-,A,-;
DTACK = pin,30,-,D,-;
A_DECODE_19_ = pin,97,-,A,-;
AVEC = pin,92,-,A,-;
A_DECODE_18_ = pin,95,-,A,-;
E = pin,66,-,G,-;
A_DECODE_17_ = pin,59,-,F,-;
AHIGH_30_ = pin,5,-,B,-;
VPA = pin,36,-,-,-;
A_DECODE_16_ = pin,96,-,A,-;
AHIGH_29_ = pin,6,-,B,-;
AHIGH_28_ = pin,15,-,C,-;
RST = pin,86,-,-,-;
AHIGH_27_ = pin,16,-,C,-;
RESET = pin,3,-,B,-;
AHIGH_26_ = pin,17,-,C,-;
AHIGH_25_ = pin,18,-,C,-;
AMIGA_ADDR_ENABLE = pin,33,-,D,-;
AHIGH_24_ = pin,19,-,C,-;
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
A_DECODE_22_ = pin,84,-,H,-;
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
A_DECODE_21_ = pin,94,-,A,-;
AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
A_DECODE_20_ = pin,93,-,A,-;
CIIN = pin,47,-,E,-;
IPL_1_ = pin,56,-,F,-;
IPL_0_ = pin,67,-,G,-;
FC_0_ = pin,57,-,F,-;
A_1_ = pin,60,-,F,-;
A_DECODE_19_ = pin,97,-,A,-;
A_DECODE_18_ = pin,95,-,A,-;
A_DECODE_17_ = pin,59,-,F,-;
A_DECODE_16_ = pin,96,-,A,-;
A_0_ = pin,69,-,G,-;
SIZE_1_ = pin,79,-,H,-;
IPL_030_1_ = pin,7,-,B,-;
IPL_030_0_ = pin,8,-,B,-;
IPL_030_2_ = pin,9,-,B,-;
RW_000 = pin,80,-,H,-;
BG_000 = pin,29,-,D,-;
SIZE_0_ = pin,70,-,G,-;
BGACK_030 = pin,83,-,H,-;
CLK_EXP = pin,10,-,B,-;
SIZE_0_ = pin,70,-,G,-;
VMA = pin,35,-,D,-;
RW = pin,71,-,G,-;
A_0_ = pin,69,-,G,-;
IPL_030_1_ = pin,7,-,B,-;
IPL_030_0_ = pin,8,-,B,-;
cpu_est_2_ = node,-,-,A,12;
cpu_est_3_ = node,-,-,D,9;
cpu_est_1_ = node,-,-,D,6;
cpu_est_2_ = node,-,-,D,14;
cpu_est_3_ = node,-,-,D,2;
cpu_est_0_ = node,-,-,G,9;
cpu_est_1_ = node,-,-,A,8;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,C,14;
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,F,1;
inst_AS_030_D0 = node,-,-,E,5;
inst_AS_030_000_SYNC = node,-,-,F,0;
inst_BGACK_030_INT_D = node,-,-,E,8;
inst_AS_000_DMA = node,-,-,A,1;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,F,9;
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,F,5;
inst_AS_030_D0 = node,-,-,H,2;
inst_AS_030_000_SYNC = node,-,-,B,13;
inst_BGACK_030_INT_D = node,-,-,H,13;
inst_AS_000_DMA = node,-,-,A,8;
inst_DS_000_DMA = node,-,-,A,13;
CYCLE_DMA_0_ = node,-,-,A,10;
CYCLE_DMA_1_ = node,-,-,A,6;
inst_VPA_D = node,-,-,A,9;
CLK_000_D_3_ = node,-,-,D,10;
inst_DTACK_D0 = node,-,-,B,6;
inst_VPA_D = node,-,-,F,2;
CLK_000_D_3_ = node,-,-,F,13;
inst_DTACK_D0 = node,-,-,B,14;
inst_RESET_OUT = node,-,-,G,5;
CLK_030_PE_1_ = node,-,-,A,2;
inst_AMIGA_DS = node,-,-,C,10;
CLK_000_D_1_ = node,-,-,H,5;
CLK_000_D_0_ = node,-,-,C,9;
inst_CLK_OUT_PRE_50 = node,-,-,G,13;
inst_CLK_OUT_PRE_D = node,-,-,D,6;
IPL_D0_0_ = node,-,-,G,14;
IPL_D0_1_ = node,-,-,D,14;
IPL_D0_2_ = node,-,-,B,14;
CLK_000_D_0_ = node,-,-,D,13;
inst_CLK_OUT_PRE_50 = node,-,-,G,2;
inst_CLK_OUT_PRE_D = node,-,-,E,8;
IPL_D0_0_ = node,-,-,B,10;
IPL_D0_1_ = node,-,-,B,6;
IPL_D0_2_ = node,-,-,B,2;
CLK_000_D_2_ = node,-,-,H,6;
CLK_000_D_4_ = node,-,-,B,10;
inst_LDS_000_INT = node,-,-,F,8;
inst_DS_000_ENABLE = node,-,-,B,13;
inst_UDS_000_INT = node,-,-,F,12;
SM_AMIGA_6_ = node,-,-,C,13;
SM_AMIGA_4_ = node,-,-,D,2;
SM_AMIGA_1_ = node,-,-,F,4;
SM_AMIGA_0_ = node,-,-,H,13;
RST_DLY_0_ = node,-,-,G,2;
RST_DLY_1_ = node,-,-,G,10;
RST_DLY_2_ = node,-,-,G,6;
inst_CLK_030_H = node,-,-,A,2;
inst_DSACK1_INT = node,-,-,H,2;
inst_AS_000_INT = node,-,-,C,10;
SM_AMIGA_5_ = node,-,-,C,6;
SM_AMIGA_3_ = node,-,-,D,13;
SM_AMIGA_2_ = node,-,-,A,5;
SM_AMIGA_i_7_ = node,-,-,C,2;
CIIN_0 = node,-,-,E,9;
CLK_000_D_4_ = node,-,-,C,14;
inst_LDS_000_INT = node,-,-,F,12;
inst_DS_000_ENABLE = node,-,-,C,13;
inst_UDS_000_INT = node,-,-,F,1;
SM_AMIGA_6_ = node,-,-,F,0;
SM_AMIGA_4_ = node,-,-,A,1;
SM_AMIGA_1_ = node,-,-,F,8;
SM_AMIGA_0_ = node,-,-,A,12;
CYCLE_DMA_0_ = node,-,-,A,6;
CYCLE_DMA_1_ = node,-,-,A,10;
CLK_030_PE_0_ = node,-,-,A,9;
RST_DLY_0_ = node,-,-,G,6;
RST_DLY_1_ = node,-,-,G,14;
RST_DLY_2_ = node,-,-,G,10;
inst_DSACK1_INT = node,-,-,A,5;
inst_AS_000_INT = node,-,-,C,2;
SM_AMIGA_5_ = node,-,-,G,13;
SM_AMIGA_3_ = node,-,-,C,6;
SM_AMIGA_2_ = node,-,-,C,9;
SM_AMIGA_i_7_ = node,-,-,F,4;
CLK_OUT_INTreg = node,-,-,D,10;
CIIN_0 = node,-,-,E,5;
[GROUP ASSIGNMENTS]
Layer = OFF;

6701
Logic/68030_tk.out
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152
Logic/68030_tk.plc
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@ -8,11 +8,15 @@
; Source file 68030_tk.tt4
; FITTER-generated Placements.
; DEVICE mach447a
; DATE Wed Oct 26 22:26:30 2016
; DATE Fri Nov 18 19:32:41 2016
Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143
Pin 56 IPL_1_
Pin 67 IPL_0_
Pin 85 A_DECODE_23_
Pin 57 FC_0_
Pin 60 A_1_
Pin 68 IPL_2_
Pin 58 FC_1_
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
@ -23,61 +27,58 @@ Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
Pin 14 nEXP_SPACE
Pin 41 BERR Comb ; S6=1 S9=1 Pair 197
Pin 21 BG_030
Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125
Pin 28 BGACK_000
Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137
Pin 64 CLK_030
Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149
Pin 11 CLK_000
Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 157
Pin 61 CLK_OSZI
Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 155
Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247
Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167
Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161
Pin 65 CLK_DIV_OUT Comb ; S6=1 S9=1 Pair 247
Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 127
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271
Pin 84 A_DECODE_22_
Pin 91 FPU_SENSE
Pin 94 A_DECODE_21_
Pin 81 DSACK1 Comb ; S6=1 S9=1 Pair 283
Pin 93 A_DECODE_20_
Pin 30 DTACK
Pin 97 A_DECODE_19_
Pin 30 DTACK Comb ; S6=1 S9=1 Pair 173
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
Pin 95 A_DECODE_18_
Pin 66 E Comb ; S6=1 S9=1 Pair 251
Pin 59 A_DECODE_17_
Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125
Pin 36 VPA
Pin 96 A_DECODE_16_
Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137
Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149
Pin 86 RST
Pin 3 RESET Comb ; S6=1 S9=1 Pair 128
Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181
Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 157
Pin 3 RESET
Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 155
Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167
Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 187
Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199
Pin 84 A_DECODE_22_
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179
Pin 94 A_DECODE_21_
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 181
Pin 93 A_DECODE_20_
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
Pin 56 IPL_1_
Pin 67 IPL_0_
Pin 57 FC_0_
Pin 60 A_1_
Pin 97 A_DECODE_19_
Pin 95 A_DECODE_18_
Pin 59 A_DECODE_17_
Pin 96 A_DECODE_16_
Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257
Pin 79 SIZE_1_ Reg ; S6=1 S9=1 Pair 287
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133
Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131
Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
Pin 70 SIZE_0_ Reg ; S6=1 S9=1 Pair 263
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 127
Pin 35 VMA Reg ; S6=1 S9=1 Pair 173
Pin 70 SIZE_0_ Reg ; S6=1 S9=1 Pair 263
Pin 35 VMA Reg ; S6=1 S9=1 Pair 179
Pin 71 RW Reg ; S6=1 S9=1 Pair 245
Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133
Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1
Node 281 RN_AS_030 Comb ; S6=1 S9=1
Node 203 RN_AS_000 Comb ; S6=1 S9=1
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
Node 197 RN_BERR Comb ; S6=1 S9=1
Node 173 RN_DTACK Comb ; S6=1 S9=1
Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1
Node 137 RN_AHIGH_29_ Comb ; S6=1 S9=1
Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1
@ -85,60 +86,63 @@ Node 157 RN_AHIGH_27_ Comb ; S6=1 S9=1
Node 155 RN_AHIGH_26_ Comb ; S6=1 S9=1
Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1
Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1
Node 257 RN_A_0_ Reg ; S6=1 S9=1
Node 287 RN_SIZE_1_ Reg ; S6=1 S9=1
Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1
Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1
Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1
Node 269 RN_RW_000 Reg ; S6=1 S9=1
Node 175 RN_BG_000 Reg ; S6=1 S9=1
Node 263 RN_SIZE_0_ Reg ; S6=1 S9=1
Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
Node 173 RN_VMA Reg ; S6=1 S9=1
Node 263 RN_SIZE_0_ Reg ; S6=1 S9=1
Node 179 RN_VMA Reg ; S6=1 S9=1
Node 245 RN_RW Reg ; S6=1 S9=1
Node 257 RN_A_0_ Reg ; S6=1 S9=1
Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1
Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1
Node 119 cpu_est_2_ Reg ; S6=1 S9=1
Node 187 cpu_est_3_ Reg ; S6=1 S9=1
Node 182 cpu_est_1_ Reg ; S6=1 S9=1
Node 194 cpu_est_2_ Reg ; S6=1 S9=1
Node 176 cpu_est_3_ Reg ; S6=1 S9=1
Node 259 cpu_est_0_ Reg ; S6=1 S9=1
Node 113 cpu_est_1_ Reg ; S6=1 S9=1
Node 170 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
Node 223 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
Node 205 inst_AS_030_D0 Reg ; S6=1 S9=1
Node 221 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
Node 209 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
Node 103 inst_AS_000_DMA Reg ; S6=1 S9=1
Node 235 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
Node 229 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
Node 272 inst_AS_030_D0 Reg ; S6=1 S9=1
Node 145 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
Node 113 inst_AS_000_DMA Reg ; S6=1 S9=1
Node 121 inst_DS_000_DMA Reg ; S6=1 S9=1
Node 116 CYCLE_DMA_0_ Reg ; S6=1 S9=1
Node 110 CYCLE_DMA_1_ Reg ; S6=1 S9=1
Node 115 inst_VPA_D Reg ; S6=1 S9=1
Node 188 CLK_000_D_3_ Reg ; S6=1 S9=1
Node 134 inst_DTACK_D0 Reg ; S6=1 S9=1
Node 224 inst_VPA_D Reg ; S6=1 S9=1
Node 241 CLK_000_D_3_ Reg ; S6=1 S9=1
Node 146 inst_DTACK_D0 Reg ; S6=1 S9=1
Node 253 inst_RESET_OUT Reg ; S6=1 S9=1
Node 104 CLK_030_PE_1_ Reg ; S6=1 S9=1
Node 164 inst_AMIGA_DS Reg ; S6=1 S9=1
Node 277 CLK_000_D_1_ Reg ; S6=1 S9=1
Node 163 CLK_000_D_0_ Reg ; S6=1 S9=1
Node 265 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
Node 182 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
Node 266 IPL_D0_0_ Reg ; S6=1 S9=1
Node 194 IPL_D0_1_ Reg ; S6=1 S9=1
Node 146 IPL_D0_2_ Reg ; S6=1 S9=1
Node 193 CLK_000_D_0_ Reg ; S6=1 S9=1
Node 248 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
Node 209 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
Node 140 IPL_D0_0_ Reg ; S6=1 S9=1
Node 134 IPL_D0_1_ Reg ; S6=1 S9=1
Node 128 IPL_D0_2_ Reg ; S6=1 S9=1
Node 278 CLK_000_D_2_ Reg ; S6=1 S9=1
Node 140 CLK_000_D_4_ Reg ; S6=1 S9=1
Node 233 inst_LDS_000_INT Reg ; S6=1 S9=1
Node 145 inst_DS_000_ENABLE Reg ; S6=1 S9=1
Node 239 inst_UDS_000_INT Reg ; S6=1 S9=1
Node 169 SM_AMIGA_6_ Reg ; S6=1 S9=1
Node 176 SM_AMIGA_4_ Reg ; S6=1 S9=1
Node 227 SM_AMIGA_1_ Reg ; S6=1 S9=1
Node 289 SM_AMIGA_0_ Reg ; S6=1 S9=1
Node 248 RST_DLY_0_ Reg ; S6=1 S9=1
Node 260 RST_DLY_1_ Reg ; S6=1 S9=1
Node 254 RST_DLY_2_ Reg ; S6=1 S9=1
Node 104 inst_CLK_030_H Reg ; S6=1 S9=1
Node 272 inst_DSACK1_INT Reg ; S6=1 S9=1
Node 164 inst_AS_000_INT Reg ; S6=1 S9=1
Node 158 SM_AMIGA_5_ Reg ; S6=1 S9=1
Node 193 SM_AMIGA_3_ Reg ; S6=1 S9=1
Node 109 SM_AMIGA_2_ Reg ; S6=1 S9=1
Node 152 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
Node 211 CIIN_0 Comb ; S6=1 S9=1
Node 170 CLK_000_D_4_ Reg ; S6=1 S9=1
Node 239 inst_LDS_000_INT Reg ; S6=1 S9=1
Node 169 inst_DS_000_ENABLE Reg ; S6=1 S9=1
Node 223 inst_UDS_000_INT Reg ; S6=1 S9=1
Node 221 SM_AMIGA_6_ Reg ; S6=1 S9=1
Node 103 SM_AMIGA_4_ Reg ; S6=1 S9=1
Node 233 SM_AMIGA_1_ Reg ; S6=1 S9=1
Node 119 SM_AMIGA_0_ Reg ; S6=1 S9=1
Node 110 CYCLE_DMA_0_ Reg ; S6=1 S9=1
Node 116 CYCLE_DMA_1_ Reg ; S6=1 S9=1
Node 115 CLK_030_PE_0_ Reg ; S6=1 S9=1
Node 254 RST_DLY_0_ Reg ; S6=1 S9=1
Node 266 RST_DLY_1_ Reg ; S6=1 S9=1
Node 260 RST_DLY_2_ Reg ; S6=1 S9=1
Node 109 inst_DSACK1_INT Reg ; S6=1 S9=1
Node 152 inst_AS_000_INT Reg ; S6=1 S9=1
Node 265 SM_AMIGA_5_ Reg ; S6=1 S9=1
Node 158 SM_AMIGA_3_ Reg ; S6=1 S9=1
Node 163 SM_AMIGA_2_ Reg ; S6=1 S9=1
Node 227 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
Node 188 CLK_OUT_INTreg Reg ; S6=1 S9=1
Node 205 CIIN_0 Comb ; S6=1 S9=1
; Unused Pins & Nodes
; -> None Found.

1069
Logic/68030_tk.prd
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Logic/68030_tk.rpt
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23
Logic/68030_tk.tal
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@ -44,18 +44,25 @@ AMIGA_BUS_ENABLE_HIGH .. .. .. .. 1 2 .. ..
inst_AS_030_D0 1 2 1 1 .. .. 1 1
inst_AS_030_000_SYNC 1 2 1 1 .. .. 1 1
inst_DS_000_DMA 1 2 1 1 .. .. .. ..
CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1
CYCLE_DMA_1_ 1 2 .. .. .. .. 1 1
CLK_030_PE_1_ 1 2 .. .. .. .. 1 1
inst_LDS_000_INT 1 1 1 1 .. .. 2 2
inst_DS_000_ENABLE 1 2 1 1 .. .. 2 2
inst_UDS_000_INT 1 1 1 1 .. .. 2 2
inst_CLK_030_H 1 2 .. .. .. .. 1 1
CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1
CYCLE_DMA_1_ 1 2 .. .. .. .. 1 1
CLK_030_PE_0_ 1 2 .. .. .. .. 1 1
inst_DSACK1_INT 1 2 1 1 .. .. .. ..
AS_030 .. .. .. .. 1 1 .. ..
AS_000 .. .. .. .. 1 1 .. ..
CIIN .. .. .. .. 1 1 .. ..
A_0_ 1 1 0 0 .. .. 1 1
RN_A_0_ 1 1 0 0 .. .. 1 1
SIZE_1_ 1 1 0 0 .. .. 1 1
RN_SIZE_1_ 1 1 0 0 .. .. 1 1
IPL_030_1_ 1 1 0 0 .. .. 1 1
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
IPL_030_0_ 1 1 0 0 .. .. 1 1
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
IPL_030_2_ 1 1 0 0 .. .. 1 1
RN_IPL_030_2_ 1 1 0 0 .. .. 1 1
RW_000 1 1 0 0 .. .. 1 1
@ -68,16 +75,10 @@ inst_UDS_000_INT 1 1 1 1 .. .. 2 2
RN_VMA 1 1 0 0 .. .. 1 1
RW 1 1 0 0 .. .. 1 1
RN_RW 1 1 0 0 .. .. 1 1
A_0_ 1 1 0 0 .. .. 1 1
RN_A_0_ 1 1 0 0 .. .. 1 1
IPL_030_1_ 1 1 0 0 .. .. 1 1
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
IPL_030_0_ 1 1 0 0 .. .. 1 1
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
cpu_est_1_ .. .. 1 1 .. .. 1 1
cpu_est_2_ .. .. 1 1 .. .. 1 1
cpu_est_3_ .. .. 1 1 .. .. 1 1
cpu_est_0_ .. .. .. .. .. .. 1 1
cpu_est_1_ .. .. 1 1 .. .. 1 1
inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. ..
inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. ..
inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1
@ -85,6 +86,7 @@ inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1
CLK_000_D_3_ .. .. .. .. .. .. 1 1
inst_DTACK_D0 1 1 .. .. .. .. 1 1
inst_RESET_OUT 1 1 .. .. .. .. .. ..
inst_AMIGA_DS 1 1 .. .. .. .. 1 1
CLK_000_D_1_ .. .. .. .. .. .. 1 1
CLK_000_D_0_ 1 1 .. .. .. .. 1 1
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
@ -105,4 +107,5 @@ inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1
SM_AMIGA_3_ 1 1 .. .. .. .. 1 1
SM_AMIGA_2_ 1 1 .. .. .. .. 1 1
SM_AMIGA_i_7_ 1 1 .. .. .. .. 1 1
CLK_OUT_INTreg .. .. 1 1 .. .. 1 1
CIIN_0 .. .. .. .. 1 1 .. ..

1005
Logic/68030_tk.tt2
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1005
Logic/68030_tk.tt3
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478
Logic/68030_tk.tt4
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@ -1,259 +1,265 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Oct 26 22:26:25 2016
#$ DATE Fri Nov 18 19:32:36 2016
#$ MODULE BUS68030
#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000
LDS_000 nEXP_SPACE BERR BG_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_
CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ AHIGH_24_ FPU_CS
A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC
A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET AMIGA_ADDR_ENABLE
AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_
FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 SIZE_0_ BGACK_030 CLK_EXP VMA RW
A_0_ IPL_030_1_ IPL_030_0_
#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_
#$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030
AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000
CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E AHIGH_30_ VPA
AHIGH_29_ AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ AHIGH_25_ AMIGA_ADDR_ENABLE
AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_
AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_
A_DECODE_16_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ IPL_030_2_ RW_000 BG_000
BGACK_030 SIZE_0_ VMA RW
#$ NODES 47 cpu_est_1_ cpu_est_2_ cpu_est_3_ cpu_est_0_
inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT
inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ inst_AMIGA_DS
CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_
IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT
inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_
SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT
inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ RST_DLY_0_ RST_DLY_1_
RST_DLY_2_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_
SM_AMIGA_i_7_ CLK_OUT_INTreg CIIN_0
.type f
.i 97
.o 162
.i 101
.o 166
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
CLK_OSZI FPU_SENSE VPA RST RESET A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q
BGACK_030.Q VMA.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q
inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q
inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_3_.Q
inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q
inst_DS_000_DMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q
CLK_030_PE_1_.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q
inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
CLK_000_D_2_.Q CLK_000_D_4_.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q
inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q
SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q
inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q
SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q
AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
SIZE_0_.Q SIZE_1_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q CLK_030_PE_0_.Q RW_000.Q RW.Q
RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_DSACK1_INT.Q
inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q
BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN
AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN
AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN DTACK.PIN RW.PIN
CIIN_0
.ob AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE
UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE AHIGH_30_ AHIGH_30_.OE
AHIGH_29_ AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_
AHIGH_26_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AHIGH_25_ AHIGH_25_.OE AHIGH_24_
AHIGH_24_.OE FPU_CS% DSACK1% DSACK1.OE AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE
UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_EXP FPU_CS%
DSACK1% DSACK1.OE DTACK DTACK.OE AVEC E AHIGH_30_ AHIGH_30_.OE AHIGH_29_
AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_
AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AMIGA_ADDR_ENABLE AHIGH_24_ AHIGH_24_.OE
AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH% CIIN CIIN.OE
SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_2_.T IPL_030_2_.C RW_000.D% RW_000.C
RW_000.OE BG_000.D% BG_000.C SIZE_0_.D% SIZE_0_.C SIZE_0_.OE BGACK_030.D
BGACK_030.C CLK_EXP.D CLK_EXP.C VMA.T VMA.C RW.D% RW.C RW.OE A_0_.D A_0_.C
A_0_.OE IPL_030_1_.T IPL_030_1_.C IPL_030_0_.T IPL_030_0_.C cpu_est_2_.D.X1
cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C
cpu_est_1_.D cpu_est_1_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D%
A_0_.D A_0_.C A_0_.OE SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_1_.D% IPL_030_1_.C
IPL_030_0_.D% IPL_030_0_.C IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C
RW_000.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C SIZE_0_.D% SIZE_0_.C
SIZE_0_.OE VMA.T VMA.C RW.D% RW.C RW.OE cpu_est_1_.D cpu_est_1_.C
cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C
cpu_est_0_.D cpu_est_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D%
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D%
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C
inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D%
inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D
inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C
inst_VPA_D.D% inst_VPA_D.C CLK_000_D_3_.D CLK_000_D_3_.C inst_DTACK_D0.D%
inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C CLK_000_D_1_.D CLK_000_D_1_.C
CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D%
IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C
CLK_000_D_4_.D CLK_000_D_4_.C inst_LDS_000_INT.D inst_LDS_000_INT.C
inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_UDS_000_INT.D% inst_UDS_000_INT.C
SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_1_.D
SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C RST_DLY_0_.D RST_DLY_0_.C
RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C
inst_CLK_030_H.D inst_CLK_030_H.C inst_DSACK1_INT.D% inst_DSACK1_INT.C
inst_AS_000_INT.D% inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T
SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.T.X1 SM_AMIGA_i_7_.T.X2
SM_AMIGA_i_7_.C CIIN_0
.phase 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 185
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inst_DS_000_DMA.C inst_VPA_D.D% inst_VPA_D.C CLK_000_D_3_.D CLK_000_D_3_.C
inst_DTACK_D0.D% inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C
CLK_030_PE_1_.D CLK_030_PE_1_.C inst_AMIGA_DS.D inst_AMIGA_DS.C CLK_000_D_1_.D
CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D
inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D%
IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D
CLK_000_D_2_.C CLK_000_D_4_.D CLK_000_D_4_.C inst_LDS_000_INT.D
inst_LDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_UDS_000_INT.D%
inst_UDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C CYCLE_DMA_0_.D
CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C CLK_030_PE_0_.D% CLK_030_PE_0_.C
RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C
RST_DLY_2_.D RST_DLY_2_.C inst_DSACK1_INT.D% inst_DSACK1_INT.C inst_AS_000_INT.D%
inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C
SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.T.X1 SM_AMIGA_i_7_.T.X2
SM_AMIGA_i_7_.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C CIIN_0
.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 187
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.end

478
Logic/68030_tk.tte
View File

@ -1,259 +1,265 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Oct 26 22:26:25 2016
#$ DATE Fri Nov 18 19:32:36 2016
#$ MODULE BUS68030
#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000
LDS_000 nEXP_SPACE BERR BG_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_
CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ AHIGH_24_ FPU_CS
A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC
A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET AMIGA_ADDR_ENABLE
AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_
FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 SIZE_0_ BGACK_030 CLK_EXP VMA RW
A_0_ IPL_030_1_ IPL_030_0_
#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_
#$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030
AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000
CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E AHIGH_30_ VPA
AHIGH_29_ AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ AHIGH_25_ AMIGA_ADDR_ENABLE
AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_
AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_
A_DECODE_16_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ IPL_030_2_ RW_000 BG_000
BGACK_030 SIZE_0_ VMA RW
#$ NODES 47 cpu_est_1_ cpu_est_2_ cpu_est_3_ cpu_est_0_
inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT
inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ inst_AMIGA_DS
CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_
IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT
inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_
SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT
inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ RST_DLY_0_ RST_DLY_1_
RST_DLY_2_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_
SM_AMIGA_i_7_ CLK_OUT_INTreg CIIN_0
.type f
.i 97
.o 162
.i 101
.o 166
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
CLK_OSZI FPU_SENSE VPA RST RESET A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q
BGACK_030.Q VMA.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q
inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q
inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_3_.Q
inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q
inst_DS_000_DMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q
CLK_030_PE_1_.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q
inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
CLK_000_D_2_.Q CLK_000_D_4_.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q
inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q
SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q
inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q
SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q
AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
SIZE_0_.Q SIZE_1_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q CLK_030_PE_0_.Q RW_000.Q RW.Q
RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_DSACK1_INT.Q
inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q
BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN
AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN
AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN DTACK.PIN RW.PIN
CIIN_0
.ob AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE
UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE AHIGH_30_ AHIGH_30_.OE
AHIGH_29_ AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_
AHIGH_26_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AHIGH_25_ AHIGH_25_.OE AHIGH_24_
AHIGH_24_.OE FPU_CS- DSACK1- DSACK1.OE AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE
UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_EXP FPU_CS-
DSACK1- DSACK1.OE DTACK DTACK.OE AVEC E AHIGH_30_ AHIGH_30_.OE AHIGH_29_
AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_
AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AMIGA_ADDR_ENABLE AHIGH_24_ AHIGH_24_.OE
AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH- CIIN CIIN.OE
SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_2_.T IPL_030_2_.C RW_000.D- RW_000.C
RW_000.OE BG_000.D- BG_000.C SIZE_0_.D- SIZE_0_.C SIZE_0_.OE BGACK_030.D
BGACK_030.C CLK_EXP.D CLK_EXP.C VMA.T VMA.C RW.D- RW.C RW.OE A_0_.D A_0_.C
A_0_.OE IPL_030_1_.T IPL_030_1_.C IPL_030_0_.T IPL_030_0_.C cpu_est_2_.D.X1
cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C
cpu_est_1_.D cpu_est_1_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
A_0_.D A_0_.C A_0_.OE SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_1_.D- IPL_030_1_.C
IPL_030_0_.D- IPL_030_0_.C IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C
RW_000.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C SIZE_0_.D- SIZE_0_.C
SIZE_0_.OE VMA.T VMA.C RW.D- RW.C RW.OE cpu_est_1_.D cpu_est_1_.C
cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C
cpu_est_0_.D cpu_est_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C
inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D-
inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D
inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C
inst_VPA_D.D- inst_VPA_D.C CLK_000_D_3_.D CLK_000_D_3_.C inst_DTACK_D0.D-
inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C CLK_000_D_1_.D CLK_000_D_1_.C
CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D-
IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C
CLK_000_D_4_.D CLK_000_D_4_.C inst_LDS_000_INT.D inst_LDS_000_INT.C
inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_UDS_000_INT.D- inst_UDS_000_INT.C
SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_1_.D
SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C RST_DLY_0_.D RST_DLY_0_.C
RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C
inst_CLK_030_H.D inst_CLK_030_H.C inst_DSACK1_INT.D- inst_DSACK1_INT.C
inst_AS_000_INT.D- inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T
SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.T.X1 SM_AMIGA_i_7_.T.X2
SM_AMIGA_i_7_.C CIIN_0
.phase 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 185
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------------1-------------------------------------------------------0---------0------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000
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-------------------------00100---------0---10--------------------------1------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
---------------------------------------1-0-10--------------------------1------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
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------------0------------------------------------------------------------1----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
------------1------------------------------01-------------1--------------1----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
---1--------1--------------------0------0----------1---------------------0----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
---1--------1--------------------0------0--01------1------1--------------0----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
inst_DS_000_DMA.C inst_VPA_D.D- inst_VPA_D.C CLK_000_D_3_.D CLK_000_D_3_.C
inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C
CLK_030_PE_1_.D CLK_030_PE_1_.C inst_AMIGA_DS.D inst_AMIGA_DS.C CLK_000_D_1_.D
CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D
inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D-
IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D
CLK_000_D_2_.C CLK_000_D_4_.D CLK_000_D_4_.C inst_LDS_000_INT.D
inst_LDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_UDS_000_INT.D-
inst_UDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C CYCLE_DMA_0_.D
CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C CLK_030_PE_0_.D- CLK_030_PE_0_.C
RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C
RST_DLY_2_.D RST_DLY_2_.C inst_DSACK1_INT.D- inst_DSACK1_INT.C inst_AS_000_INT.D-
inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C
SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.T.X1 SM_AMIGA_i_7_.T.X2
SM_AMIGA_i_7_.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C CIIN_0
.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 187
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.end

73
Logic/68030_tk.vcl
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 10/26/16;
TIME = 22:26:30;
DATE = 11/18/16;
TIME = 19:32:40;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@ -147,10 +147,11 @@ AS_000 = OUTPUT,42,4,-;
UDS_000 = OUTPUT,32,3,-;
LDS_000 = OUTPUT,31,3,-;
RW = BIDIR,71,6,-;
BERR = OUTPUT,41,4,-;
SIZE_1_ = BIDIR,79,7,-;
SIZE_0_ = BIDIR,70,6,-;
A_0_ = BIDIR,69,6,-;
BERR = OUTPUT,41,4,-;
DTACK = OUTPUT,30,3,-;
AHIGH_24_ = OUTPUT,19,2,-;
AHIGH_25_ = OUTPUT,18,2,-;
AHIGH_26_ = OUTPUT,17,2,-;
@ -177,60 +178,62 @@ CIIN = OUTPUT,47,4,-;
AMIGA_ADDR_ENABLE = OUTPUT,33,3,-;
AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
CLK_EXP = OUTPUT,10,1,-;
RESET = OUTPUT,3,1,-;
RN_BGACK_030 = NODE,-1,7,-;
inst_RESET_OUT = NODE,*,6,-;
CLK_000_D_0_ = NODE,*,2,-;
CLK_000_D_0_ = NODE,*,3,-;
CLK_000_D_1_ = NODE,*,7,-;
SM_AMIGA_6_ = NODE,*,2,-;
inst_BGACK_030_INT_D = NODE,*,4,-;
inst_AS_030_000_SYNC = NODE,*,5,-;
cpu_est_1_ = NODE,*,0,-;
cpu_est_3_ = NODE,*,3,-;
SM_AMIGA_i_7_ = NODE,*,2,-;
cpu_est_0_ = NODE,*,6,-;
inst_AS_030_D0 = NODE,*,4,-;
cpu_est_2_ = NODE,*,0,-;
inst_RESET_OUT = NODE,*,6,-;
SM_AMIGA_6_ = NODE,*,5,-;
inst_BGACK_030_INT_D = NODE,*,7,-;
inst_AS_030_000_SYNC = NODE,*,1,-;
inst_AS_000_DMA = NODE,*,0,-;
SM_AMIGA_2_ = NODE,*,0,-;
SM_AMIGA_3_ = NODE,*,3,-;
cpu_est_3_ = NODE,*,3,-;
cpu_est_1_ = NODE,*,3,-;
SM_AMIGA_i_7_ = NODE,*,5,-;
SM_AMIGA_0_ = NODE,*,0,-;
cpu_est_0_ = NODE,*,6,-;
CLK_OUT_INTreg = NODE,*,3,-;
inst_AS_030_D0 = NODE,*,7,-;
cpu_est_2_ = NODE,*,3,-;
SM_AMIGA_2_ = NODE,*,2,-;
RN_VMA = NODE,-1,3,-;
SM_AMIGA_5_ = NODE,*,2,-;
SM_AMIGA_0_ = NODE,*,7,-;
SM_AMIGA_5_ = NODE,*,6,-;
SM_AMIGA_1_ = NODE,*,5,-;
SM_AMIGA_4_ = NODE,*,3,-;
inst_DS_000_ENABLE = NODE,*,1,-;
SM_AMIGA_4_ = NODE,*,0,-;
inst_DS_000_ENABLE = NODE,*,2,-;
inst_LDS_000_INT = NODE,*,5,-;
inst_AS_000_INT = NODE,*,2,-;
inst_DSACK1_INT = NODE,*,0,-;
inst_UDS_000_INT = NODE,*,5,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,5,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,2,-;
inst_CLK_OUT_PRE_D = NODE,*,3,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,5,-;
inst_CLK_OUT_PRE_D = NODE,*,4,-;
inst_CLK_OUT_PRE_50 = NODE,*,6,-;
inst_DTACK_D0 = NODE,*,1,-;
CLK_000_D_3_ = NODE,*,3,-;
inst_VPA_D = NODE,*,0,-;
CLK_000_D_3_ = NODE,*,5,-;
inst_VPA_D = NODE,*,5,-;
RN_IPL_030_2_ = NODE,-1,1,-;
RN_IPL_030_0_ = NODE,-1,1,-;
RN_IPL_030_1_ = NODE,-1,1,-;
RN_IPL_030_2_ = NODE,-1,1,-;
CLK_030_PE_0_ = NODE,*,0,-;
inst_DS_000_DMA = NODE,*,0,-;
inst_CLK_030_H = NODE,*,0,-;
CLK_030_PE_1_ = NODE,*,0,-;
SM_AMIGA_3_ = NODE,*,2,-;
RN_RW_000 = NODE,-1,7,-;
RST_DLY_0_ = NODE,*,6,-;
CYCLE_DMA_1_ = NODE,*,0,-;
RN_A_0_ = NODE,-1,6,-;
CYCLE_DMA_0_ = NODE,*,0,-;
RN_SIZE_0_ = NODE,-1,6,-;
RN_SIZE_1_ = NODE,-1,7,-;
CYCLE_DMA_0_ = NODE,*,0,-;
RN_A_0_ = NODE,-1,6,-;
RN_RW = NODE,-1,6,-;
RN_BG_000 = NODE,-1,3,-;
CIIN_0 = NODE,*,4,-;
inst_DSACK1_INT = NODE,*,7,-;
RST_DLY_2_ = NODE,*,6,-;
RST_DLY_1_ = NODE,*,6,-;
CLK_000_D_4_ = NODE,*,1,-;
CYCLE_DMA_1_ = NODE,*,0,-;
inst_AMIGA_DS = NODE,*,2,-;
CLK_000_D_4_ = NODE,*,2,-;
CLK_000_D_2_ = NODE,*,7,-;
IPL_D0_2_ = NODE,*,1,-;
IPL_D0_1_ = NODE,*,3,-;
IPL_D0_0_ = NODE,*,6,-;
IPL_D0_1_ = NODE,*,1,-;
IPL_D0_0_ = NODE,*,1,-;
inst_DTACK_D0 = NODE,*,1,-;
CLK_OSZI = INPUT,61,-,-;

135
Logic/68030_tk.vco
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 10/26/16;
TIME = 22:26:30;
DATE = 11/18/16;
TIME = 19:32:41;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@ -142,7 +142,11 @@ layer = OFF;
Layer = OFF;
AHIGH_31_ = BIDIR,4, B,-;
IPL_1_ = INPUT,56, F,-;
IPL_0_ = INPUT,67, G,-;
A_DECODE_23_ = INPUT,85, H,-;
FC_0_ = INPUT,57, F,-;
A_1_ = INPUT,60, F,-;
IPL_2_ = INPUT,68, G,-;
FC_1_ = INPUT,58, F,-;
AS_030 = BIDIR,82, H,-;
@ -153,96 +157,95 @@ LDS_000 = BIDIR,31, D,-;
nEXP_SPACE = INPUT,14,-,-;
BERR = BIDIR,41, E,-;
BG_030 = INPUT,21, C,-;
AHIGH_30_ = BIDIR,5, B,-;
BGACK_000 = INPUT,28, D,-;
AHIGH_29_ = BIDIR,6, B,-;
CLK_030 = INPUT,64,-,-;
AHIGH_28_ = BIDIR,15, C,-;
CLK_000 = INPUT,11,-,-;
AHIGH_27_ = BIDIR,16, C,-;
CLK_OSZI = INPUT,61,-,-;
AHIGH_26_ = BIDIR,17, C,-;
CLK_DIV_OUT = OUTPUT,65, G,-;
AHIGH_25_ = BIDIR,18, C,-;
AHIGH_24_ = BIDIR,19, C,-;
CLK_EXP = OUTPUT,10, B,-;
FPU_CS = OUTPUT,78, H,-;
A_DECODE_22_ = INPUT,84, H,-;
FPU_SENSE = INPUT,91, A,-;
A_DECODE_21_ = INPUT,94, A,-;
DSACK1 = OUTPUT,81, H,-;
A_DECODE_20_ = INPUT,93, A,-;
DTACK = INPUT,30, D,-;
A_DECODE_19_ = INPUT,97, A,-;
DTACK = BIDIR,30, D,-;
AVEC = OUTPUT,92, A,-;
A_DECODE_18_ = INPUT,95, A,-;
E = OUTPUT,66, G,-;
A_DECODE_17_ = INPUT,59, F,-;
AHIGH_30_ = BIDIR,5, B,-;
VPA = INPUT,36,-,-;
A_DECODE_16_ = INPUT,96, A,-;
AHIGH_29_ = BIDIR,6, B,-;
AHIGH_28_ = BIDIR,15, C,-;
RST = INPUT,86,-,-;
RESET = OUTPUT,3, B,-;
AHIGH_27_ = BIDIR,16, C,-;
RESET = INPUT,3, B,-;
AHIGH_26_ = BIDIR,17, C,-;
AHIGH_25_ = BIDIR,18, C,-;
AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
AHIGH_24_ = BIDIR,19, C,-;
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
A_DECODE_22_ = INPUT,84, H,-;
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
A_DECODE_21_ = INPUT,94, A,-;
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
A_DECODE_20_ = INPUT,93, A,-;
CIIN = OUTPUT,47, E,-;
IPL_1_ = INPUT,56, F,-;
IPL_0_ = INPUT,67, G,-;
FC_0_ = INPUT,57, F,-;
A_1_ = INPUT,60, F,-;
A_DECODE_19_ = INPUT,97, A,-;
A_DECODE_18_ = INPUT,95, A,-;
A_DECODE_17_ = INPUT,59, F,-;
A_DECODE_16_ = INPUT,96, A,-;
A_0_ = BIDIR,69, G,-;
SIZE_1_ = BIDIR,79, H,-;
IPL_030_1_ = OUTPUT,7, B,-;
IPL_030_0_ = OUTPUT,8, B,-;
IPL_030_2_ = OUTPUT,9, B,-;
RW_000 = BIDIR,80, H,-;
BG_000 = OUTPUT,29, D,-;
SIZE_0_ = BIDIR,70, G,-;
BGACK_030 = OUTPUT,83, H,-;
CLK_EXP = OUTPUT,10, B,-;
SIZE_0_ = BIDIR,70, G,-;
VMA = OUTPUT,35, D,-;
RW = BIDIR,71, G,-;
A_0_ = BIDIR,69, G,-;
IPL_030_1_ = OUTPUT,7, B,-;
IPL_030_0_ = OUTPUT,8, B,-;
cpu_est_2_ = NODE,12, A,-;
cpu_est_3_ = NODE,9, D,-;
cpu_est_1_ = NODE,6, D,-;
cpu_est_2_ = NODE,14, D,-;
cpu_est_3_ = NODE,2, D,-;
cpu_est_0_ = NODE,9, G,-;
cpu_est_1_ = NODE,8, A,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,14, C,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,1, F,-;
inst_AS_030_D0 = NODE,5, E,-;
inst_AS_030_000_SYNC = NODE,0, F,-;
inst_BGACK_030_INT_D = NODE,8, E,-;
inst_AS_000_DMA = NODE,1, A,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,9, F,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,5, F,-;
inst_AS_030_D0 = NODE,2, H,-;
inst_AS_030_000_SYNC = NODE,13, B,-;
inst_BGACK_030_INT_D = NODE,13, H,-;
inst_AS_000_DMA = NODE,8, A,-;
inst_DS_000_DMA = NODE,13, A,-;
CYCLE_DMA_0_ = NODE,10, A,-;
CYCLE_DMA_1_ = NODE,6, A,-;
inst_VPA_D = NODE,9, A,-;
CLK_000_D_3_ = NODE,10, D,-;
inst_DTACK_D0 = NODE,6, B,-;
inst_VPA_D = NODE,2, F,-;
CLK_000_D_3_ = NODE,13, F,-;
inst_DTACK_D0 = NODE,14, B,-;
inst_RESET_OUT = NODE,5, G,-;
CLK_030_PE_1_ = NODE,2, A,-;
inst_AMIGA_DS = NODE,10, C,-;
CLK_000_D_1_ = NODE,5, H,-;
CLK_000_D_0_ = NODE,9, C,-;
inst_CLK_OUT_PRE_50 = NODE,13, G,-;
inst_CLK_OUT_PRE_D = NODE,6, D,-;
IPL_D0_0_ = NODE,14, G,-;
IPL_D0_1_ = NODE,14, D,-;
IPL_D0_2_ = NODE,14, B,-;
CLK_000_D_0_ = NODE,13, D,-;
inst_CLK_OUT_PRE_50 = NODE,2, G,-;
inst_CLK_OUT_PRE_D = NODE,8, E,-;
IPL_D0_0_ = NODE,10, B,-;
IPL_D0_1_ = NODE,6, B,-;
IPL_D0_2_ = NODE,2, B,-;
CLK_000_D_2_ = NODE,6, H,-;
CLK_000_D_4_ = NODE,10, B,-;
inst_LDS_000_INT = NODE,8, F,-;
inst_DS_000_ENABLE = NODE,13, B,-;
inst_UDS_000_INT = NODE,12, F,-;
SM_AMIGA_6_ = NODE,13, C,-;
SM_AMIGA_4_ = NODE,2, D,-;
SM_AMIGA_1_ = NODE,4, F,-;
SM_AMIGA_0_ = NODE,13, H,-;
RST_DLY_0_ = NODE,2, G,-;
RST_DLY_1_ = NODE,10, G,-;
RST_DLY_2_ = NODE,6, G,-;
inst_CLK_030_H = NODE,2, A,-;
inst_DSACK1_INT = NODE,2, H,-;
inst_AS_000_INT = NODE,10, C,-;
SM_AMIGA_5_ = NODE,6, C,-;
SM_AMIGA_3_ = NODE,13, D,-;
SM_AMIGA_2_ = NODE,5, A,-;
SM_AMIGA_i_7_ = NODE,2, C,-;
CIIN_0 = NODE,9, E,-;
CLK_000_D_4_ = NODE,14, C,-;
inst_LDS_000_INT = NODE,12, F,-;
inst_DS_000_ENABLE = NODE,13, C,-;
inst_UDS_000_INT = NODE,1, F,-;
SM_AMIGA_6_ = NODE,0, F,-;
SM_AMIGA_4_ = NODE,1, A,-;
SM_AMIGA_1_ = NODE,8, F,-;
SM_AMIGA_0_ = NODE,12, A,-;
CYCLE_DMA_0_ = NODE,6, A,-;
CYCLE_DMA_1_ = NODE,10, A,-;
CLK_030_PE_0_ = NODE,9, A,-;
RST_DLY_0_ = NODE,6, G,-;
RST_DLY_1_ = NODE,14, G,-;
RST_DLY_2_ = NODE,10, G,-;
inst_DSACK1_INT = NODE,5, A,-;
inst_AS_000_INT = NODE,2, C,-;
SM_AMIGA_5_ = NODE,13, G,-;
SM_AMIGA_3_ = NODE,6, C,-;
SM_AMIGA_2_ = NODE,9, C,-;
SM_AMIGA_i_7_ = NODE,4, F,-;
CLK_OUT_INTreg = NODE,10, D,-;
CIIN_0 = NODE,5, E,-;

2
Logic/68030_tk.xrf
View File

@ -2,7 +2,7 @@ Signal Name Cross Reference File
ispLEVER Classic 2.0.00.17.20.15
Design '68030_tk' created Wed Oct 26 22:26:25 2016
Design '68030_tk' created Fri Nov 18 19:32:36 2016
LEGEND: '>' Functional Block Port Separator

3018
Logic/BUS68030.bl0
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2823
Logic/BUS68030.bl1
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4909
Logic/BUS68030.edi
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20
Logic/BUS68030.fse
View File

@ -1,20 +1,20 @@
fsm_encoding {7131381311} onehot
fsm_encoding {7132381321} onehot
fsm_state_encoding {7131381311} idle_p {00000000}
fsm_state_encoding {7132381321} idle_p {00000000}
fsm_state_encoding {7131381311} idle_n {00000011}
fsm_state_encoding {7132381321} idle_n {00000011}
fsm_state_encoding {7131381311} as_set_p {00000101}
fsm_state_encoding {7132381321} as_set_p {00000101}
fsm_state_encoding {7131381311} as_set_n {00001001}
fsm_state_encoding {7132381321} as_set_n {00001001}
fsm_state_encoding {7131381311} sample_dtack_p {00010001}
fsm_state_encoding {7132381321} sample_dtack_p {00010001}
fsm_state_encoding {7131381311} data_fetch_n {00100001}
fsm_state_encoding {7132381321} data_fetch_n {00100001}
fsm_state_encoding {7131381311} data_fetch_p {01000001}
fsm_state_encoding {7132381321} data_fetch_p {01000001}
fsm_state_encoding {7131381311} end_cycle_n {10000001}
fsm_state_encoding {7132381321} end_cycle_n {10000001}
fsm_registers {7131381311} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}
fsm_registers {7132381321} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}

2
Logic/BUS68030.prj
View File

@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic\BUS68030.prj
#-- Written on Wed Oct 26 22:25:56 2016
#-- Written on Fri Nov 18 19:32:22 2016
#device options

5268
Logic/BUS68030.srm
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46
Logic/BUS68030.srr
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@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Wed Oct 26 22:26:19 2016
#Fri Nov 18 19:32:29 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
@ -20,16 +20,18 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vh
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:7:133:15|Signal clk_030_h is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":126:36:126:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register AS_000_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":156:2:156:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -40,14 +42,14 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 26 22:26:19 2016
# Fri Nov 18 19:32:29 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -57,7 +59,7 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 26 22:26:20 2016
# Fri Nov 18 19:32:31 2016
###########################################################]
Map & Optimize Report
@ -66,7 +68,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
@N:"c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:"c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -81,15 +83,15 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFF 55 uses
BI_DIR 18 uses
BUFTH 4 uses
DFF 57 uses
BI_DIR 19 uses
BUFTH 3 uses
IBUF 38 uses
OBUF 15 uses
AND2 269 uses
INV 238 uses
OR2 22 uses
XOR2 5 uses
AND2 277 uses
INV 236 uses
OR2 23 uses
XOR2 8 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
@ -99,6 +101,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 26 22:26:20 2016
# Fri Nov 18 19:32:31 2016
###########################################################]

BIN
Logic/BUS68030.srs
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Binary file not shown.

909
Logic/bus68030.exf
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28
Logic/bus68030.srf
View File

@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Wed Oct 26 22:26:19 2016
#Fri Nov 18 19:32:29 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
@ -20,16 +20,18 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vh
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:7:133:15|Signal clk_030_h is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":126:36:126:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register AS_000_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":156:2:156:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -40,14 +42,14 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 26 22:26:19 2016
# Fri Nov 18 19:32:29 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -57,6 +59,6 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 26 22:26:20 2016
# Fri Nov 18 19:32:31 2016
###########################################################]

4
Logic/dm/BUS68030_comp.xdm
View File

@ -27,8 +27,8 @@ SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
/>SqS<R"M=3ONsEDVHCP"R=""(/S>
SR<qM3="lkF8DHCVDRC"P(=""
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.6"
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j66n."
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjjjjj/j">S
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=jj3jjjjj"
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjn46./6">S
S<MqR=s"FHHo_M_#0FRV"P&="J0kF;1AzndUjjk&JF"0;/S>
SR<qM3="FosHhCNl"=RP"k&JFA0;zU1nj&djJ0kF;>"/
/S<7>CV

2
Logic/run_options.txt
View File

@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version I-2014.03LC
#-- Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\run_options.txt
#-- Written on Wed Oct 26 22:26:19 2016
#-- Written on Fri Nov 18 19:32:29 2016
#project files

2
Logic/synlog/BUS68030_multi_srs_gen.srr
View File

@ -5,6 +5,6 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 26 22:26:20 2016
# Fri Nov 18 19:32:31 2016
###########################################################]

18
Logic/synlog/bus68030_fpga_mapper.srr
View File

@ -2,7 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
@N:"c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:"c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -17,15 +17,15 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFF 55 uses
BI_DIR 18 uses
BUFTH 4 uses
DFF 57 uses
BI_DIR 19 uses
BUFTH 3 uses
IBUF 38 uses
OBUF 15 uses
AND2 269 uses
INV 238 uses
OR2 22 uses
XOR2 5 uses
AND2 277 uses
INV 236 uses
OR2 23 uses
XOR2 8 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
@ -35,6 +35,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 26 22:26:20 2016
# Fri Nov 18 19:32:31 2016
###########################################################]

4
Logic/synlog/report/BUS68030_compiler_errors.txt
View File

@ -1,3 +1,3 @@
@E: CD371 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":176:6:176:38|No matching overload for "and"
@E: CD676 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":176:6:176:38|Can't implement expression (no function signature?)
@E: CG119 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":428:6:428:9|Expecting closing )
@E|Parse errors encountered - exiting

4
Logic/synlog/report/BUS68030_compiler_notes.txt
View File

@ -4,6 +4,6 @@
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Trying to extract state machine for register SM_AMIGA
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Trying to extract state machine for register cpu_est

4
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
<report_link name="more"><data>C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>9</data>
<data>11</data>
<report_link name="more"><data>C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1477513579</data>
<data type="timestamp">1479493949</data>
</info>
</job_info>
</job_run_status>

18
Logic/synlog/report/BUS68030_compiler_warnings.txt
View File

@ -1,10 +1,12 @@
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":126:36:126:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:7:133:15|Signal clk_030_h is undriven
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register AS_000_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":156:2:156:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
@W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused

2
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>105MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1477513580</data>
<data type="timestamp">1479493951</data>
</info>
</job_info>
</job_run_status>

68
Logic/syntmp/BUS68030_srr.htm
View File

@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1477513579>
<!@TC:1479493949>
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: E:\ispLEVER_Classic2_0\synpbase
#OS: Windows 7 6.2
@ -8,30 +8,32 @@
#Implementation: logic
<a name=compilerReport1>$ Start of Compile</a>
#Wed Oct 26 22:26:19 2016
#Fri Nov 18 19:32:29 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1477513579> | Running in 64-bit mode
@N: : <!@TM:1479493949> | Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1477513579> | Setting time resolution to ns
@N: : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1477513579> | Top entity is set to BUS68030.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1479493949> | Setting time resolution to ns
@N: : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1479493949> | Top entity is set to BUS68030.
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1477513579> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1477513579> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1477513579> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:128:7:128:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(128)</a><!@TM:1477513579> | Signal clk_out_pre is undriven </font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1479493949> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1479493949> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1479493949> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:129:7:129:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1479493949> | Signal clk_out_pre is undriven </font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:133:7:133:16:@W:CD638:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1479493949> | Signal clk_030_h is undriven </font>
Post processing for work.bus68030.behavioral
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Pruning register nEXP_SPACE_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Pruning register BGACK_030_INT_PRE_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1477513579> | Pruning register CLK_OUT_EXP_INT_1 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:126:36:126:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1477513579> | Pruning register CLK_OUT_PRE_25_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:154:2:154:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(154)</a><!@TM:1477513579> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Trying to extract state machine for register SM_AMIGA
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Pruning register AS_000_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Pruning register nEXP_SPACE_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Pruning register BGACK_030_INT_PRE_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1479493949> | Pruning register CLK_OUT_EXP_INT_1 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:127:36:127:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1479493949> | Pruning register CLK_OUT_PRE_25_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:156:2:156:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(156)</a><!@TM:1479493949> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -42,24 +44,24 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1477513579> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1479493949> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 26 22:26:19 2016
# Fri Nov 18 19:32:29 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1477513580> | Running in 64-bit mode
@N: : <!@TM:1479493951> | Running in 64-bit mode
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 26 22:26:20 2016
# Fri Nov 18 19:32:31 2016
###########################################################]
Map & Optimize Report
@ -67,8 +69,8 @@ Map & Optimize Report
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1477513580> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N::@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513580> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1479493951> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@N::@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493951> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -83,25 +85,25 @@ original code -> new code
<a name=resourceUsage3>Resource Usage Report</a>
Simple gate primitives:
DFF 55 uses
BI_DIR 18 uses
BUFTH 4 uses
DFF 57 uses
BI_DIR 19 uses
BUFTH 3 uses
IBUF 38 uses
OBUF 15 uses
AND2 269 uses
INV 238 uses
OR2 22 uses
XOR2 5 uses
AND2 277 uses
INV 236 uses
OR2 23 uses
XOR2 8 uses
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1477513580> | Timing Report not generated for this device, please use place and route tools for timing analysis.
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1479493951> | Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 26 22:26:20 2016
# Fri Nov 18 19:32:31 2016
###########################################################]

2
Logic/syntmp/BUS68030_toc.htm
View File

@ -16,7 +16,7 @@
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
<ul rel="open" >
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\stdout.log" target="srrFrame" title="">Session Log (22:25 26-Oct)</a>
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\stdout.log" target="srrFrame" title="">Session Log (19:32 18-Nov)</a>
<ul ></ul></li> </ul>
</li>
</ul>

2
Logic/syntmp/run_option.xml
View File

@ -3,7 +3,7 @@
Synopsys, Inc.
Version I-2014.03LC
Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\run_option.xml
Written on Wed Oct 26 22:26:19 2016
Written on Fri Nov 18 19:32:29 2016
-->

8
Logic/syntmp/statusReport.html
View File

@ -33,12 +33,12 @@
<tr>
<td class="optionTitle">Compile Input</td><td>Complete</td>
<td>8</td>
<td>9</td>
<td>11</td>
<td>0</td>
<td>-</td>
<td>0m:00s</td>
<td>-</td>
<td><font size="-1">26.10.2016</font><br/><font size="-2">22:26:19</font></td>
<td><font size="-1">18.11.2016</font><br/><font size="-2">19:32:29</font></td>
</tr>
<tr>
@ -49,12 +49,12 @@
<td>0m:00s</td>
<td>0m:00s</td>
<td>105MB</td>
<td><font size="-1">26.10.2016</font><br/><font size="-2">22:26:20</font></td>
<td><font size="-1">18.11.2016</font><br/><font size="-2">19:32:31</font></td>
</tr>
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">26.10.2016</font><br/><font size="-2">22:26:20</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:01s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">18.11.2016</font><br/><font size="-2">19:32:31</font></td> </tbody>
</table>
</td></tr></table></body>
</html>

20
Logic/synwork/BUS68030_comp.fdep
View File

@ -1,15 +1,15 @@
#defaultlanguage:vhdl
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\bin64\\c_vhdl.exe":1401224104
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\location.map":1310457374
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1477513553
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\bin64\\c_vhdl.exe":1401220504
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\location.map":1310453774
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std1164.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\numeric.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401220368
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401220122
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1479493940
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

20
Logic/synwork/BUS68030_comp.fdeporig
View File

@ -1,15 +1,15 @@
#defaultlanguage:vhdl
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\bin64\\c_vhdl.exe":1401224104
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\location.map":1310457374
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1477513553
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\bin64\\c_vhdl.exe":1401220504
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\location.map":1310453774
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\std1164.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\numeric.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401220368
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401220122
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1479493940
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_comp.srs
View File

Binary file not shown.

22
Logic/synwork/BUS68030_comp.tlg
View File

@ -1,16 +1,18 @@
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:7:133:15|Signal clk_030_h is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":126:36:126:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register AS_000_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":156:2:156:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -21,5 +23,5 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused

BIN
Logic/synwork/BUS68030_mult.srs
View File

Binary file not shown.

BIN
Logic/synwork/BUS68030_mult_srs/skeleton.srs
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Binary file not shown.

BIN
Logic/synwork/BUS68030_s.srs
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Binary file not shown.