mirror of https://github.com/kr239/68030tk.git
Cleaned up BRD-Files
This commit is contained in:
MHeinrichs
parent
cb8dfae058
commit
ae77c5fb85
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@ -278,7 +278,7 @@ begin
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-- as030-sampling and FPU-Select
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if(AS_030_D0 ='1' or BERR='0') then -- "async" reset of various signals
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if(AS_030_D0 ='1') then -- "async" reset of various signals
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AS_030_000_SYNC <= '1';
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DSACK1_INT <= '1';
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AS_000_INT <= '1';
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@ -320,14 +320,14 @@ begin
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--Amiga statemachine
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if(BERR='0')then --"async" reset on errors
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SM_AMIGA<=IDLE_P;
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end if;
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--if(BERR='0')then --"async" reset on errors
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-- SM_AMIGA<=IDLE_P;
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--end if;
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case (SM_AMIGA) is
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when IDLE_P => --68000:S0 wait for a falling edge
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RW_000_INT <= '1';
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if( CLK_000_D(0)='0' and CLK_000_D(1)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
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if( CLK_000_D(1)='0' and CLK_000_D(2)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
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SM_AMIGA<=IDLE_N; --go to s1
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end if;
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when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
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@ -353,6 +353,7 @@ begin
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when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
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if( CLK_000_NE='1' and --falling edge
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((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
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(VPA_D = '1' AND BERR='0') OR --Bus error
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(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
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)then --go to s5
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SM_AMIGA<=DATA_FETCH_N;
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@ -1,4 +1,4 @@
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[synthesis-type]
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tool=Synplify
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[STRATEGY-LIST]
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Normal=True, 1412327082
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[synthesis-type]
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tool=Synplify
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2226
Logic/68030_TK.tcl
2226
Logic/68030_TK.tcl
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2765
Logic/68030_tk.bl2
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Logic/68030_tk.bl2
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@ -1,19 +1,19 @@
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#$ TOOL ispLEVER Classic 2.0.00.17.20.15
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#$ DATE Thu Aug 25 22:27:51 2016
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#$ DATE Wed Sep 14 23:54:26 2016
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#$ MODULE 68030_tk
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#$ PINS 61 AHIGH_30_ AHIGH_29_ SIZE_1_ AHIGH_28_ AHIGH_27_ AHIGH_31_ AHIGH_26_ \
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# AHIGH_25_ A_DECODE_23_ AHIGH_24_ A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ IPL_030_2_ \
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# A_DECODE_19_ A_DECODE_18_ IPL_2_ A_DECODE_17_ A_DECODE_16_ FC_1_ AS_030 AS_000 RW_000 \
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#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \
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# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \
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# A_0_ CLK_OSZI IPL_030_1_ CLK_DIV_OUT IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE \
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# FC_0_ DSACK1 A_1_ DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR \
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# AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_
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#$ NODES 54 inst_BGACK_030_INTreg un10_ciin_i inst_VMA_INTreg cpu_est_0_ \
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# cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW \
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# inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA \
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# inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D \
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# inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 \
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# inst_CLK_OUT_PRE_25 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ \
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# SIZE_0_ CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ CLK_EXP AHIGH_28_ FPU_CS AHIGH_27_ \
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# FPU_SENSE AHIGH_26_ DSACK1 AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ \
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# VPA A_DECODE_20_ VMA A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ RW A_DECODE_16_ \
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# AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH \
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# CIIN A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_
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#$ NODES 54 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_2_ cpu_est_3_ cpu_est_0_ \
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# cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 \
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# inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \
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# CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D CLK_000_D_1_ \
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# inst_DTACK_D0 inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 \
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# inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ \
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# inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg inst_LDS_000_INT \
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# inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ \
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# inst_RW_000_INT inst_RW_000_DMA RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_A0_DMA \
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@ -25,41 +25,42 @@ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
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DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \
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A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \
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A_DECODE_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF \
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inst_BGACK_030_INTreg.BLIF un10_ciin_i.BLIF inst_VMA_INTreg.BLIF \
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cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
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inst_AS_000_INT.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
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inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF \
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cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \
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inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
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inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \
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inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF \
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SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF \
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CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_CLK_OUT_PRE_50.BLIF \
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SIZE_DMA_1_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF inst_DTACK_D0.BLIF \
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inst_RESET_OUT.BLIF CLK_000_D_0_.BLIF inst_CLK_OUT_PRE_50.BLIF \
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inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF \
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IPL_D0_2_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF \
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inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF \
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SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \
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inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
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RST_DLY_2_.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF SM_AMIGA_5_.BLIF \
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SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF \
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CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF \
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IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \
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UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \
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AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF \
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AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF \
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A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
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IPL_D0_2_.BLIF CLK_000_D_2_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \
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inst_DSACK1_INTreg.BLIF inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF \
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inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF \
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SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF RST_DLY_0_.BLIF \
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RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF \
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SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF \
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BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF \
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IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
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RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
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SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \
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AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \
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AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
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.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
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AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
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AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_1_.D SM_AMIGA_1_.C \
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SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \
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IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \
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IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \
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SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \
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SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C \
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CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
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SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.C \
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cpu_est_3_.D cpu_est_3_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.D \
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RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \
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CYCLE_DMA_0_.D CYCLE_DMA_0_.C inst_AS_000_DMA.D inst_AS_000_DMA.C \
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inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D \
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inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \
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AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.C SM_AMIGA_2_.D \
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SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \
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IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \
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IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \
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IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.D \
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SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C \
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CLK_000_D_2_.D CLK_000_D_2_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \
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CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \
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cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.C cpu_est_3_.D \
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cpu_est_3_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \
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CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C inst_RW_000_INT.D \
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inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
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inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \
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inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D \
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inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \
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inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D \
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inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \
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@ -67,45 +68,59 @@ inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C BG_000DFFreg.D BG_000DFFreg.C \
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inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \
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inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \
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inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
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inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
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inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_DMA.D inst_RW_000_DMA.C \
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inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \
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inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D \
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inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \
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inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
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SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ \
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AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ \
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un10_ciin_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \
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SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \
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AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \
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DSACK1.OE RESET.OE CIIN.OE cpu_est_2_.D.X1 cpu_est_2_.D.X2 RST_DLY_1_.D.X1 \
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RST_DLY_1_.D.X2 inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 \
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SM_AMIGA_3_.D.X2 SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2
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inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D \
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inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
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CLK_OUT_INTreg.D CLK_OUT_INTreg.C SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 \
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UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \
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AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \
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LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE \
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AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE \
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BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE cpu_est_2_.D.X1 \
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cpu_est_2_.D.X2 RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 inst_CLK_030_H.D.X1 \
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inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 SM_AMIGA_i_7_.D.X1 \
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SM_AMIGA_i_7_.D.X2
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.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
|
||||
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \
|
||||
inst_DTACK_D0.BLIF CLK_000_D_0_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
|
||||
BERR.PIN.BLIF SM_AMIGA_2_.D
|
||||
10010001-01-- 1
|
||||
1-----11001-- 1
|
||||
1-----11-01-0 1
|
||||
1--------0-1- 1
|
||||
1------1---1- 1
|
||||
------1-1--01 0
|
||||
-----10----0- 0
|
||||
----1-0----0- 0
|
||||
---0--0----0- 0
|
||||
--1---0----0- 0
|
||||
-1----0----0- 0
|
||||
-------0-1--- 0
|
||||
----------00- 0
|
||||
---------1-0- 0
|
||||
-------0---0- 0
|
||||
0------------ 0
|
||||
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \
|
||||
SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D
|
||||
101-1- 1
|
||||
1-11-1 1
|
||||
10-1-1 1
|
||||
---00- 0
|
||||
--00-- 0
|
||||
-1-0-- 0
|
||||
-10--- 0
|
||||
----00 0
|
||||
0----- 0
|
||||
--0--0 0
|
||||
-1---0 0
|
||||
SM_AMIGA_2_.BLIF SM_AMIGA_1_.D
|
||||
101-1 1
|
||||
1-110 1
|
||||
10-10 1
|
||||
-10-- 0
|
||||
---00 0
|
||||
0---- 0
|
||||
--0-1 0
|
||||
-1--1 0
|
||||
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \
|
||||
SM_AMIGA_0_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D
|
||||
1101-- 1
|
||||
1-0-11 1
|
||||
11--11 1
|
||||
---00- 0
|
||||
--1-0- 0
|
||||
-0--0- 0
|
||||
-01--- 0
|
||||
---0-0 0
|
||||
0----- 0
|
||||
--1--0 0
|
||||
-0---0 0
|
||||
SM_AMIGA_0_.BLIF SM_AMIGA_0_.D
|
||||
1101- 1
|
||||
1-0-1 1
|
||||
11--1 1
|
||||
-01-- 0
|
||||
0---- 0
|
||||
---00 0
|
||||
--1-0 0
|
||||
-0--0 0
|
||||
.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
|
||||
IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D
|
||||
0-01100- 1
|
||||
|
|
@ -188,73 +203,49 @@ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D
|
|||
-0 1
|
||||
01 0
|
||||
.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF \
|
||||
CLK_000_D_0_.BLIF CLK_000_D_2_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF \
|
||||
SM_AMIGA_6_.D
|
||||
11010-0- 1
|
||||
-1--0111 1
|
||||
-1-1-111 1
|
||||
-----01- 0
|
||||
---01--- 0
|
||||
1100-100 1
|
||||
-1--0-1- 1
|
||||
-1-1--1- 1
|
||||
---01-1- 0
|
||||
-----00- 0
|
||||
---1--0- 0
|
||||
--1---0- 0
|
||||
0-----0- 0
|
||||
----1-0- 0
|
||||
---0--0- 0
|
||||
------10 0
|
||||
-0------ 0
|
||||
------01 0
|
||||
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \
|
||||
SM_AMIGA_5_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
|
||||
1011-- 1
|
||||
1-1-11 1
|
||||
10--11 1
|
||||
---00- 0
|
||||
--0-0- 0
|
||||
-1--0- 0
|
||||
-10--- 0
|
||||
---0-0 0
|
||||
0----- 0
|
||||
--0--0 0
|
||||
-1---0 0
|
||||
SM_AMIGA_5_.BLIF SM_AMIGA_5_.D
|
||||
1011- 1
|
||||
1-1-1 1
|
||||
10--1 1
|
||||
-10-- 0
|
||||
0---- 0
|
||||
---00 0
|
||||
--0-0 0
|
||||
-1--0 0
|
||||
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF \
|
||||
SM_AMIGA_5_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D
|
||||
110-1- 1
|
||||
1-01-1 1
|
||||
11-1-1 1
|
||||
---00- 0
|
||||
--10-- 0
|
||||
-0-0-- 0
|
||||
-01--- 0
|
||||
----00 0
|
||||
SM_AMIGA_5_.BLIF SM_AMIGA_4_.D
|
||||
1-01- 1
|
||||
11-1- 1
|
||||
110-1 1
|
||||
-01-- 0
|
||||
--10- 0
|
||||
-0-0- 0
|
||||
0---- 0
|
||||
---00 0
|
||||
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D
|
||||
100010 1
|
||||
101-00 1
|
||||
1011-0 1
|
||||
--101- 0
|
||||
--0-0- 0
|
||||
--01-- 0
|
||||
-1---- 0
|
||||
0----- 0
|
||||
--1--0 0
|
||||
-0---0 0
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
||||
cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
|
||||
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
|
||||
BERR.PIN.BLIF SM_AMIGA_2_.D
|
||||
1000010-101-- 1
|
||||
1-----10101-- 1
|
||||
1--------0-11 1
|
||||
1-------1--11 1
|
||||
------11---0- 0
|
||||
-----00----0- 0
|
||||
----1-0----0- 0
|
||||
---1--0----0- 0
|
||||
--1---0----0- 0
|
||||
-1----0----0- 0
|
||||
------11----0 0
|
||||
--------01--- 0
|
||||
-----00-----0 0
|
||||
----1-0-----0 0
|
||||
---1--0-----0 0
|
||||
--1---0-----0 0
|
||||
-1----0-----0 0
|
||||
----------00- 0
|
||||
---------1-0- 0
|
||||
--------0--0- 0
|
||||
----------0-0 0
|
||||
0------------ 0
|
||||
---------1--0 0
|
||||
--------0---0 0
|
||||
-----1 0
|
||||
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
|
||||
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D
|
||||
1010010 1
|
||||
|
|
@ -293,28 +284,29 @@ SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D
|
|||
110 0
|
||||
00- 0
|
||||
0-1 0
|
||||
.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_3_.BLIF CLK_000_D_1_.BLIF \
|
||||
.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF cpu_est_1_.D
|
||||
10010 1
|
||||
01--- 1
|
||||
-1-0- 1
|
||||
-1--1 1
|
||||
-01-- 0
|
||||
11-10 0
|
||||
-0-0- 0
|
||||
00--- 0
|
||||
-0--1 0
|
||||
.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
|
||||
01010 1
|
||||
-01-- 1
|
||||
--10- 1
|
||||
--1-1 1
|
||||
1-0-- 0
|
||||
-1110 0
|
||||
--00- 0
|
||||
-00-- 0
|
||||
--0-1 0
|
||||
.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
||||
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D
|
||||
111-10 1
|
||||
0--1-- 1
|
||||
---10- 1
|
||||
---1-1 1
|
||||
1-1110 1
|
||||
010--- 1
|
||||
-1--0- 1
|
||||
-1---1 1
|
||||
--1010 0
|
||||
-00--- 0
|
||||
1-0-10 0
|
||||
10--10 0
|
||||
---00- 0
|
||||
0--0-- 0
|
||||
---0-1 0
|
||||
0-1-10 0
|
||||
-0--0- 0
|
||||
-0---1 0
|
||||
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \
|
||||
RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_0_.D
|
||||
1--111 1
|
||||
|
|
@ -335,17 +327,56 @@ RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_2_.D
|
|||
---0-0 0
|
||||
--1--0 0
|
||||
-0---0 0
|
||||
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D
|
||||
100010 1
|
||||
101-00 1
|
||||
1011-0 1
|
||||
--101- 0
|
||||
--0-0- 0
|
||||
--01-- 0
|
||||
-1---- 0
|
||||
0----- 0
|
||||
-----1 0
|
||||
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \
|
||||
SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF \
|
||||
inst_RW_000_INT.D
|
||||
-01-1--- 1
|
||||
-011---1 1
|
||||
---0-1-- 1
|
||||
--0--1-- 1
|
||||
-1---1-- 1
|
||||
------0- 1
|
||||
0------- 1
|
||||
10110-10 0
|
||||
1--0001- 0
|
||||
1-0--01- 0
|
||||
11---01- 0
|
||||
.names FC_1_.BLIF nEXP_SPACE.BLIF RST.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \
|
||||
A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
|
||||
inst_AS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
|
||||
SM_AMIGA_i_7_.BLIF inst_AS_030_000_SYNC.D
|
||||
1--00101--1-- 1
|
||||
----------10- 1
|
||||
--------0-1-- 1
|
||||
-0--------1-- 1
|
||||
----------1-1 1
|
||||
---------1--- 1
|
||||
--0---------- 1
|
||||
-11----010-10 0
|
||||
-11---1-10-10 0
|
||||
-11--0--10-10 0
|
||||
-11-1---10-10 0
|
||||
-111----10-10 0
|
||||
011-----10-10 0
|
||||
--1------00-- 0
|
||||
.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
|
||||
SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D
|
||||
--1100 1
|
||||
-10--- 1
|
||||
0----- 1
|
||||
100--- 0
|
||||
1-1-1- 0
|
||||
1-10-- 0
|
||||
1-1--1 0
|
||||
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
|
||||
1--011 1
|
||||
1-1--- 1
|
||||
-0---- 1
|
||||
-10-0- 0
|
||||
-101-- 0
|
||||
01---- 0
|
||||
-10--0 0
|
||||
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
||||
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
|
||||
LDS_000.PIN.BLIF inst_AS_000_DMA.D
|
||||
|
|
@ -364,53 +395,6 @@ LDS_000.PIN.BLIF inst_AS_000_DMA.D
|
|||
110-100-0 0
|
||||
-100010-0 0
|
||||
110-010-0 0
|
||||
.names FC_1_.BLIF nEXP_SPACE.BLIF RST.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \
|
||||
A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
|
||||
inst_AS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
|
||||
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D
|
||||
1--00101--1--- 1
|
||||
----------1-1- 1
|
||||
----------10-- 1
|
||||
--------0-1--- 1
|
||||
-0--------1--- 1
|
||||
---------1---- 1
|
||||
--0----------- 1
|
||||
-------------0 1
|
||||
-11----010-101 0
|
||||
-11---1-10-101 0
|
||||
-11--0--10-101 0
|
||||
-11-1---10-101 0
|
||||
-111----10-101 0
|
||||
011-----10-101 0
|
||||
--1------00--1 0
|
||||
.names RST.BLIF inst_AS_000_INT.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF BERR.PIN.BLIF inst_AS_000_INT.D
|
||||
--1--0- 1
|
||||
-1---0- 1
|
||||
--1-0-- 1
|
||||
-1--0-- 1
|
||||
--11--- 1
|
||||
-1-1--- 1
|
||||
0------ 1
|
||||
-----00 1
|
||||
----0-0 1
|
||||
---1--0 1
|
||||
1--011- 0
|
||||
100---1 0
|
||||
.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
|
||||
inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D
|
||||
----10- 1
|
||||
---11-- 1
|
||||
--0-1-- 1
|
||||
-1---0- 1
|
||||
-1-1--- 1
|
||||
-10---- 1
|
||||
0------ 1
|
||||
-----00 1
|
||||
---1--0 1
|
||||
--0---0 1
|
||||
1-10-1- 0
|
||||
10--0-1 0
|
||||
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
||||
inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \
|
||||
AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
|
||||
|
|
@ -452,42 +436,38 @@ inst_DS_000_DMA.D
|
|||
1- 1
|
||||
-0 1
|
||||
01 0
|
||||
.names RST.BLIF inst_RESET_OUT.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
|
||||
.names RST.BLIF CLK_000_D_1_.BLIF inst_RESET_OUT.BLIF CLK_000_D_0_.BLIF \
|
||||
RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D
|
||||
1-10111 1
|
||||
11----- 1
|
||||
11-0111 1
|
||||
1-1---- 1
|
||||
0------ 0
|
||||
-0---0- 0
|
||||
-0--0-- 0
|
||||
-0-1--- 0
|
||||
--0--0- 0
|
||||
--0-0-- 0
|
||||
--01--- 0
|
||||
-00---- 0
|
||||
-0----0 0
|
||||
--0---0 0
|
||||
.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
|
||||
inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF BERR.PIN.BLIF \
|
||||
RW.PIN.BLIF inst_DS_000_ENABLE.D
|
||||
10--1--1- 1
|
||||
1-01--1-- 1
|
||||
1-01-1--1 1
|
||||
-----000- 0
|
||||
----000-- 0
|
||||
-1---00-- 0
|
||||
------000 0
|
||||
---0---0- 0
|
||||
--1----0- 0
|
||||
----0-0-0 0
|
||||
-1----0-0 0
|
||||
---00---- 0
|
||||
--1-0---- 0
|
||||
-1-0----- 0
|
||||
-11------ 0
|
||||
0-------- 0
|
||||
inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF RW.PIN.BLIF \
|
||||
inst_DS_000_ENABLE.D
|
||||
1-01--1- 1
|
||||
1-01-1-1 1
|
||||
10--1--- 1
|
||||
----000- 0
|
||||
-1---00- 0
|
||||
----0-00 0
|
||||
-1----00 0
|
||||
---00--- 0
|
||||
--1-0--- 0
|
||||
-1-0---- 0
|
||||
-11----- 0
|
||||
0------- 0
|
||||
.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \
|
||||
CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
|
||||
--0--- 1
|
||||
-1---- 1
|
||||
----01 1
|
||||
---0-1 1
|
||||
0----1 1
|
||||
--0--- 1
|
||||
-1---- 1
|
||||
10111- 0
|
||||
-01--0 0
|
||||
.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
||||
|
|
@ -522,24 +502,46 @@ inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D
|
|||
11-0- 0
|
||||
110-- 0
|
||||
10--0 0
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
||||
cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \
|
||||
.names RST.BLIF inst_AS_000_INT.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INT.D
|
||||
--1-0- 1
|
||||
-1--0- 1
|
||||
--11-- 1
|
||||
-1-1-- 1
|
||||
0----- 1
|
||||
--1--0 1
|
||||
-1---0 1
|
||||
1--011 0
|
||||
100--- 0
|
||||
.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
|
||||
inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF inst_DSACK1_INTreg.D
|
||||
---11- 1
|
||||
--0-1- 1
|
||||
-1-1-- 1
|
||||
-10--- 1
|
||||
0----- 1
|
||||
----10 1
|
||||
-1---0 1
|
||||
1-10-1 0
|
||||
10--0- 0
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
|
||||
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF inst_VMA_INTreg.D
|
||||
--0000-01 1
|
||||
-1----1-- 1
|
||||
-1---1--- 1
|
||||
-1--1---- 1
|
||||
-1-1----- 1
|
||||
-11------ 1
|
||||
0-------- 1
|
||||
-1-----0- 1
|
||||
-1-0----- 1
|
||||
-10------ 1
|
||||
-1---0--- 1
|
||||
-1--0---- 1
|
||||
-1------1 1
|
||||
1-1100010 0
|
||||
10---1--- 0
|
||||
10--1---- 0
|
||||
10-----1- 0
|
||||
1-0011010 0
|
||||
10-1----- 0
|
||||
101------ 0
|
||||
10-----1- 0
|
||||
10---1--- 0
|
||||
10--1---- 0
|
||||
10------0 0
|
||||
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
||||
inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
|
||||
|
|
@ -549,38 +551,6 @@ inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
|
|||
-0--1 1
|
||||
1110- 0
|
||||
10--0 0
|
||||
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \
|
||||
SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF \
|
||||
inst_RW_000_INT.D
|
||||
-01-1--- 1
|
||||
-011---1 1
|
||||
---0-1-- 1
|
||||
--0--1-- 1
|
||||
-1---1-- 1
|
||||
------0- 1
|
||||
0------- 1
|
||||
10110-10 0
|
||||
1--0001- 0
|
||||
1-0--01- 0
|
||||
11---01- 0
|
||||
.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
|
||||
SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D
|
||||
--1100 1
|
||||
-10--- 1
|
||||
0----- 1
|
||||
100--- 0
|
||||
1-1-1- 0
|
||||
1-10-- 0
|
||||
1-1--1 0
|
||||
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
|
||||
1--011 1
|
||||
1-1--- 1
|
||||
-0---- 1
|
||||
-10-0- 0
|
||||
-101-- 0
|
||||
01---- 0
|
||||
-10--0 0
|
||||
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
|
||||
0- 1
|
||||
-1 1
|
||||
|
|
@ -588,24 +558,6 @@ CLK_000_D_0_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
|
|||
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
|
||||
0 1
|
||||
1 0
|
||||
.names A_DECODE_23_.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \
|
||||
inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \
|
||||
AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \
|
||||
AHIGH_31_.PIN.BLIF un10_ciin_i
|
||||
-----------1- 1
|
||||
----------1-- 1
|
||||
---------1--- 1
|
||||
--------1---- 1
|
||||
-------1----- 1
|
||||
------1------ 1
|
||||
-----1------- 1
|
||||
----1-------- 1
|
||||
---0--------- 1
|
||||
--0---------- 1
|
||||
-0----------- 1
|
||||
0------------ 1
|
||||
------------1 1
|
||||
1111000000000 0
|
||||
.names IPL_030DFF_2_reg.BLIF IPL_030_2_
|
||||
1 1
|
||||
0 0
|
||||
|
|
@ -643,12 +595,12 @@ AS_030.PIN.BLIF FPU_CS
|
|||
0 0
|
||||
.names AVEC
|
||||
1
|
||||
.names cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF E
|
||||
110 1
|
||||
001 1
|
||||
.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_1_.BLIF E
|
||||
010 1
|
||||
101 1
|
||||
-00 0
|
||||
1-1 0
|
||||
01- 0
|
||||
0-1 0
|
||||
11- 0
|
||||
.names inst_VMA_INTreg.BLIF VMA
|
||||
1 1
|
||||
0 0
|
||||
|
|
@ -699,6 +651,12 @@ AHIGH_31_.PIN.BLIF CIIN
|
|||
.names IPL_030DFF_0_reg.BLIF IPL_030_0_
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
|
||||
1 1
|
||||
0 0
|
||||
|
|
@ -735,10 +693,13 @@ AHIGH_31_.PIN.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
|
||||
.names CLK_000_D_1_.BLIF CLK_000_D_2_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
|
||||
.names CLK_OSZI.BLIF CLK_000_D_2_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CYCLE_DMA_0_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CYCLE_DMA_1_.C
|
||||
|
|
@ -783,19 +744,19 @@ AHIGH_31_.PIN.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF CLK_000_D_1_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CYCLE_DMA_0_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
|
||||
.names CLK_OSZI.BLIF inst_RW_000_INT.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_AS_000_INT.C
|
||||
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_DSACK1_INTreg.C
|
||||
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_DS_000_DMA.C
|
||||
|
|
@ -842,21 +803,18 @@ AHIGH_31_.PIN.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF inst_A0_DMA.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_AS_000_INT.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_DSACK1_INTreg.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_VMA_INTreg.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_RW_000_DMA.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_RW_000_INT.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
|
||||
1 1
|
||||
0 0
|
||||
|
|
@ -1038,18 +996,33 @@ DS_030.OE
|
|||
.names inst_RESET_OUT.BLIF RESET.OE
|
||||
0 1
|
||||
1 0
|
||||
.names nEXP_SPACE.BLIF un10_ciin_i.BLIF CIIN.OE
|
||||
1- 1
|
||||
-0 1
|
||||
01 0
|
||||
.names A_DECODE_23_.BLIF nEXP_SPACE.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \
|
||||
A_DECODE_20_.BLIF inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \
|
||||
AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \
|
||||
AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF CIIN.OE
|
||||
1-111000000000 1
|
||||
-1------------ 1
|
||||
-0----------1- 0
|
||||
-0---------1-- 0
|
||||
-0--------1--- 0
|
||||
-0-------1---- 0
|
||||
-0------1----- 0
|
||||
-0-----1------ 0
|
||||
-0----1------- 0
|
||||
-0---1-------- 0
|
||||
-0--0--------- 0
|
||||
-0-0---------- 0
|
||||
-00----------- 0
|
||||
00------------ 0
|
||||
-0-----------1 0
|
||||
.names cpu_est_2_.BLIF cpu_est_2_.D.X1
|
||||
1 1
|
||||
0 0
|
||||
.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF CLK_000_D_1_.BLIF \
|
||||
.names cpu_est_2_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF cpu_est_2_.D.X2
|
||||
11-10 1
|
||||
0---- 0
|
||||
-1110 1
|
||||
-0--- 0
|
||||
--0-- 0
|
||||
---0- 0
|
||||
----1 0
|
||||
.names RST_DLY_1_.BLIF RST_DLY_1_.D.X1
|
||||
|
|
@ -1091,78 +1064,46 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2
|
|||
0--010-00- 0
|
||||
0--001-0-0 0
|
||||
0--010-0-0 0
|
||||
.names RST.BLIF SM_AMIGA_3_.BLIF BERR.PIN.BLIF SM_AMIGA_3_.D.X1
|
||||
111 1
|
||||
0-- 0
|
||||
-0- 0
|
||||
--0 0
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
||||
cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
|
||||
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
|
||||
BERR.PIN.BLIF SM_AMIGA_3_.D.X2
|
||||
1-------0110- 1
|
||||
1-------011-0 1
|
||||
1000010-10-11 1
|
||||
1-----1010-11 1
|
||||
0------------ 0
|
||||
--------11--- 0
|
||||
--------00--- 0
|
||||
--------0-0-- 0
|
||||
--------1--0- 0
|
||||
--------1---0 0
|
||||
-1----0-1---- 0
|
||||
--1---0-1---- 0
|
||||
---1--0-1---- 0
|
||||
----1-0-1---- 0
|
||||
-----00-1---- 0
|
||||
------111---- 0
|
||||
--------0--11 0
|
||||
.names RST.BLIF BERR.PIN.BLIF SM_AMIGA_i_7_.D.X1
|
||||
.names RST.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D.X1
|
||||
11 1
|
||||
0- 0
|
||||
-0 0
|
||||
.names nEXP_SPACE.BLIF RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \
|
||||
cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF inst_AS_030_000_SYNC.BLIF \
|
||||
inst_VPA_D.BLIF inst_DTACK_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
|
||||
SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \
|
||||
SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
|
||||
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \
|
||||
inst_DTACK_D0.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
|
||||
BERR.PIN.BLIF SM_AMIGA_3_.D.X2
|
||||
1------0-110- 1
|
||||
10010001-0-1- 1
|
||||
1-----1100-1- 1
|
||||
1-----11-0-10 1
|
||||
0------------ 0
|
||||
-------1-1--- 0
|
||||
-------0-0--- 0
|
||||
-------0--0-- 0
|
||||
-------0---1- 0
|
||||
-------1---0- 0
|
||||
-1----01----- 0
|
||||
--1---01----- 0
|
||||
---0--01----- 0
|
||||
----1-01----- 0
|
||||
-----101----- 0
|
||||
------111---1 0
|
||||
.names RST.BLIF SM_AMIGA_i_7_.BLIF SM_AMIGA_i_7_.D.X1
|
||||
11 1
|
||||
0- 0
|
||||
-0 0
|
||||
.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_1_.BLIF \
|
||||
CLK_000_D_0_.BLIF CLK_000_D_2_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_i_7_.BLIF \
|
||||
SM_AMIGA_i_7_.D.X2
|
||||
-1--------011------0 1
|
||||
-1--------01-1-----0 1
|
||||
-1--------01------10 1
|
||||
-1--------10--1----0 1
|
||||
-1--------10----1--0 1
|
||||
11-----0--1000-0-000 1
|
||||
-100001-0-10-----1-0 1
|
||||
-1------1010-----1-0 1
|
||||
-1--------01000-0001 1
|
||||
01----------00000001 1
|
||||
-1-----1----00000001 1
|
||||
-1--------0-00000001 1
|
||||
-1---------100000001 1
|
||||
-0------------------ 0
|
||||
------------1------1 0
|
||||
-------------1-----1 0
|
||||
--------------1----1 0
|
||||
----------------1--1 0
|
||||
-----------------1-1 0
|
||||
------------------11 0
|
||||
----------1----1---1 0
|
||||
-----------0---1---1 0
|
||||
----------11-------0 0
|
||||
----------00-------0 0
|
||||
----------1-1-0-00-- 0
|
||||
----------1--10-00-- 0
|
||||
----------1---0100-- 0
|
||||
----------1---0-001- 0
|
||||
1------0--10-------1 0
|
||||
----------0-00----00 0
|
||||
--1-----0-1---0-01-- 0
|
||||
---1----0-1---0-01-- 0
|
||||
----1---0-1---0-01-- 0
|
||||
-----1--0-1---0-01-- 0
|
||||
------0-0-1---0-01-- 0
|
||||
--------111---0-01-- 0
|
||||
0---------1---0-00-0 0
|
||||
-------1--1---0-00-0 0
|
||||
110001-0 1
|
||||
1100-100 1
|
||||
-1-01-11 1
|
||||
-0------ 0
|
||||
---1---- 0
|
||||
----0--1 0
|
||||
------01 0
|
||||
0------0 0
|
||||
--1----0 0
|
||||
-----0-0 0
|
||||
----1-10 0
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
// Signal Name Cross Reference File
|
||||
// ispLEVER Classic 2.0.00.17.20.15
|
||||
|
||||
// Design '68030_tk' created Thu Aug 25 22:27:51 2016
|
||||
// Design '68030_tk' created Wed Sep 14 23:54:26 2016
|
||||
|
||||
|
||||
// LEGEND: '>' Functional Block Port Separator
|
||||
|
|
|
|||
|
|
@ -2,29 +2,15 @@
|
|||
Copyright(C), 1992-2015, Lattice Semiconductor Corp.
|
||||
All Rights Reserved.
|
||||
|
||||
Design bus68030 created Thu Aug 25 22:27:51 2016
|
||||
Design bus68030 created Wed Sep 14 23:54:26 2016
|
||||
|
||||
|
||||
P-Terms Fan-in Fan-out Type Name (attributes)
|
||||
--------- ------ ------- ---- -----------------
|
||||
0 0 1 Pin AHIGH_30_
|
||||
1 3 1 Pin AHIGH_30_.OE
|
||||
0 0 1 Pin AHIGH_29_
|
||||
1 3 1 Pin AHIGH_29_.OE
|
||||
1 2 1 Pin SIZE_1_
|
||||
1 2 1 Pin SIZE_1_.OE
|
||||
0 0 1 Pin AHIGH_28_
|
||||
1 3 1 Pin AHIGH_28_.OE
|
||||
0 0 1 Pin AHIGH_27_
|
||||
1 3 1 Pin AHIGH_27_.OE
|
||||
0 0 1 Pin AHIGH_31_
|
||||
1 3 1 Pin AHIGH_31_.OE
|
||||
0 0 1 Pin AHIGH_26_
|
||||
1 3 1 Pin AHIGH_26_.OE
|
||||
0 0 1 Pin AHIGH_25_
|
||||
1 3 1 Pin AHIGH_25_.OE
|
||||
0 0 1 Pin AHIGH_24_
|
||||
1 3 1 Pin AHIGH_24_.OE
|
||||
1 2 1 Pin AS_030-
|
||||
1 3 1 Pin AS_030.OE
|
||||
1 2 1 Pin AS_000-
|
||||
|
|
@ -37,9 +23,25 @@ Design bus68030 created Thu Aug 25 22:27:51 2016
|
|||
1 2 1 Pin LDS_000.OE
|
||||
0 0 1 Pin BERR
|
||||
1 9 1 Pin BERR.OE
|
||||
1 2 1 Pin SIZE_0_
|
||||
1 2 1 Pin SIZE_0_.OE
|
||||
0 0 1 Pin AHIGH_30_
|
||||
1 3 1 Pin AHIGH_30_.OE
|
||||
1 1 1 Pin CLK_DIV_OUT.D
|
||||
1 1 1 Pin CLK_DIV_OUT.C
|
||||
0 0 1 Pin AHIGH_29_
|
||||
1 3 1 Pin AHIGH_29_.OE
|
||||
0 0 1 Pin AHIGH_28_
|
||||
1 3 1 Pin AHIGH_28_.OE
|
||||
1 9 1 Pin FPU_CS-
|
||||
0 0 1 Pin AHIGH_27_
|
||||
1 3 1 Pin AHIGH_27_.OE
|
||||
0 0 1 Pin AHIGH_26_
|
||||
1 3 1 Pin AHIGH_26_.OE
|
||||
0 0 1 Pin AHIGH_25_
|
||||
1 3 1 Pin AHIGH_25_.OE
|
||||
0 0 1 Pin AHIGH_24_
|
||||
1 3 1 Pin AHIGH_24_.OE
|
||||
1 0 1 Pin AVEC
|
||||
2 3 1 Pin E
|
||||
0 0 1 Pin RESET
|
||||
|
|
@ -50,8 +52,6 @@ Design bus68030 created Thu Aug 25 22:27:51 2016
|
|||
2 3 1 Pin AMIGA_BUS_ENABLE_HIGH
|
||||
1 13 1 Pin CIIN
|
||||
1 1 1 Pin CIIN.OE
|
||||
1 2 1 Pin SIZE_0_
|
||||
1 2 1 Pin SIZE_0_.OE
|
||||
10 8 1 Pin IPL_030_2_.D-
|
||||
1 1 1 Pin IPL_030_2_.C
|
||||
1 2 1 Pin RW_000.OE
|
||||
|
|
@ -61,6 +61,16 @@ Design bus68030 created Thu Aug 25 22:27:51 2016
|
|||
1 1 1 Pin BG_000.C
|
||||
3 6 1 Pin BGACK_030.D
|
||||
1 1 1 Pin BGACK_030.C
|
||||
1 1 1 Pin CLK_EXP.D
|
||||
1 1 1 Pin CLK_EXP.C
|
||||
1 1 1 Pin DSACK1.OE
|
||||
2 6 1 Pin DSACK1.D-
|
||||
1 1 1 Pin DSACK1.C
|
||||
3 9 1 Pin VMA.T
|
||||
1 1 1 Pin VMA.C
|
||||
1 2 1 Pin RW.OE
|
||||
2 5 1 Pin RW.D-
|
||||
1 1 1 Pin RW.C
|
||||
1 3 1 Pin A_0_.OE
|
||||
3 5 1 Pin A_0_.D
|
||||
1 1 1 Pin A_0_.C
|
||||
|
|
@ -68,33 +78,22 @@ Design bus68030 created Thu Aug 25 22:27:51 2016
|
|||
1 1 1 Pin IPL_030_1_.C
|
||||
10 8 1 Pin IPL_030_0_.D-
|
||||
1 1 1 Pin IPL_030_0_.C
|
||||
1 1 1 Pin CLK_EXP.D
|
||||
1 1 1 Pin CLK_EXP.C
|
||||
1 1 1 Pin DSACK1.OE
|
||||
2 7 1 Pin DSACK1.D-
|
||||
1 1 1 Pin DSACK1.C
|
||||
3 9 1 Pin VMA.T
|
||||
1 1 1 Pin VMA.C
|
||||
1 2 1 Pin RW.OE
|
||||
2 5 1 Pin RW.D-
|
||||
1 1 1 Pin RW.C
|
||||
1 13 1 Node un10_ciin_i-
|
||||
1 1 1 NodeX1 cpu_est_2_.D.X1
|
||||
1 4 1 NodeX2 cpu_est_2_.D.X2
|
||||
1 1 1 Node cpu_est_2_.C
|
||||
4 6 1 Node cpu_est_3_.D
|
||||
1 1 1 Node cpu_est_3_.C
|
||||
3 3 1 Node cpu_est_0_.D
|
||||
1 1 1 Node cpu_est_0_.C
|
||||
4 5 1 Node cpu_est_1_.D
|
||||
1 1 1 Node cpu_est_1_.C
|
||||
1 4 1 NodeX1 cpu_est_2_.D.X1
|
||||
1 1 1 NodeX2 cpu_est_2_.D.X2
|
||||
1 1 1 Node cpu_est_2_.C
|
||||
4 6 1 Node cpu_est_3_.D
|
||||
1 1 1 Node cpu_est_3_.C
|
||||
2 7 1 Node inst_AS_000_INT.D-
|
||||
2 6 1 Node inst_AS_000_INT.D-
|
||||
1 1 1 Node inst_AS_000_INT.C
|
||||
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
|
||||
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C
|
||||
1 2 1 Node inst_AS_030_D0.D-
|
||||
1 1 1 Node inst_AS_030_D0.C
|
||||
7 14 1 Node inst_AS_030_000_SYNC.D-
|
||||
7 13 1 Node inst_AS_030_000_SYNC.D
|
||||
1 1 1 Node inst_AS_030_000_SYNC.C
|
||||
1 2 1 Node inst_BGACK_030_INT_D.D-
|
||||
1 1 1 Node inst_BGACK_030_INT_D.C
|
||||
|
|
@ -112,12 +111,12 @@ Design bus68030 created Thu Aug 25 22:27:51 2016
|
|||
1 1 1 Node SIZE_DMA_1_.C
|
||||
1 2 1 Node inst_VPA_D.D-
|
||||
1 1 1 Node inst_VPA_D.C
|
||||
1 1 1 Node CLK_000_D_1_.D
|
||||
1 1 1 Node CLK_000_D_1_.C
|
||||
1 2 1 Node inst_DTACK_D0.D-
|
||||
1 1 1 Node inst_DTACK_D0.C
|
||||
2 7 1 Node inst_RESET_OUT.D
|
||||
1 1 1 Node inst_RESET_OUT.C
|
||||
1 1 1 Node CLK_000_D_1_.D
|
||||
1 1 1 Node CLK_000_D_1_.C
|
||||
1 1 1 Node CLK_000_D_0_.D
|
||||
1 1 1 Node CLK_000_D_0_.C
|
||||
1 1 1 Node inst_CLK_OUT_PRE_50.D
|
||||
|
|
@ -132,21 +131,23 @@ Design bus68030 created Thu Aug 25 22:27:51 2016
|
|||
1 1 1 Node IPL_D0_1_.C
|
||||
1 2 1 Node IPL_D0_2_.D-
|
||||
1 1 1 Node IPL_D0_2_.C
|
||||
1 1 1 Node CLK_000_D_2_.D
|
||||
1 1 1 Node CLK_000_D_2_.C
|
||||
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
|
||||
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
|
||||
3 6 1 Node inst_LDS_000_INT.D
|
||||
1 1 1 Node inst_LDS_000_INT.C
|
||||
3 9 1 Node inst_DS_000_ENABLE.D
|
||||
3 8 1 Node inst_DS_000_ENABLE.D
|
||||
1 1 1 Node inst_DS_000_ENABLE.C
|
||||
2 4 1 Node inst_UDS_000_INT.D-
|
||||
1 1 1 Node inst_UDS_000_INT.C
|
||||
3 8 1 Node SM_AMIGA_6_.D
|
||||
1 1 1 Node SM_AMIGA_6_.C
|
||||
3 6 1 Node SM_AMIGA_4_.D
|
||||
3 5 1 Node SM_AMIGA_4_.D
|
||||
1 1 1 Node SM_AMIGA_4_.C
|
||||
3 6 1 Node SM_AMIGA_1_.D
|
||||
3 5 1 Node SM_AMIGA_1_.D
|
||||
1 1 1 Node SM_AMIGA_1_.C
|
||||
3 6 1 Node SM_AMIGA_0_.D
|
||||
3 5 1 Node SM_AMIGA_0_.D
|
||||
1 1 1 Node SM_AMIGA_0_.C
|
||||
4 6 1 Node RST_DLY_0_.D
|
||||
1 1 1 Node RST_DLY_0_.C
|
||||
|
|
@ -157,19 +158,18 @@ Design bus68030 created Thu Aug 25 22:27:51 2016
|
|||
1 1 1 Node RST_DLY_2_.C
|
||||
8 10 1 Node inst_CLK_030_H.D
|
||||
1 1 1 Node inst_CLK_030_H.C
|
||||
3 6 1 Node SM_AMIGA_5_.D
|
||||
3 5 1 Node SM_AMIGA_5_.D
|
||||
1 1 1 Node SM_AMIGA_5_.C
|
||||
4 13 1 NodeX1 SM_AMIGA_3_.D.X1
|
||||
1 3 1 NodeX2 SM_AMIGA_3_.D.X2
|
||||
5 13 1 Node SM_AMIGA_3_.T
|
||||
1 1 1 Node SM_AMIGA_3_.C
|
||||
4 13 1 Node SM_AMIGA_2_.D
|
||||
5 13 1 Node SM_AMIGA_2_.D
|
||||
1 1 1 Node SM_AMIGA_2_.C
|
||||
13 20 1 NodeX1 SM_AMIGA_i_7_.D.X1
|
||||
1 2 1 NodeX2 SM_AMIGA_i_7_.D.X2
|
||||
3 8 1 NodeX1 SM_AMIGA_i_7_.D.X1
|
||||
1 5 1 NodeX2 SM_AMIGA_i_7_.D.X2
|
||||
1 1 1 Node SM_AMIGA_i_7_.C
|
||||
1 2 1 Node CIIN_0-
|
||||
2 14 1 Node CIIN_0
|
||||
=========
|
||||
279 P-Term Total: 279
|
||||
272 P-Term Total: 272
|
||||
Total Pins: 61
|
||||
Total Nodes: 44
|
||||
Average P-Term/Output: 2
|
||||
|
|
@ -177,42 +177,14 @@ Design bus68030 created Thu Aug 25 22:27:51 2016
|
|||
|
||||
Equations:
|
||||
|
||||
AHIGH_30_ = (0);
|
||||
|
||||
AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AHIGH_29_ = (0);
|
||||
|
||||
AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
|
||||
|
||||
SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q);
|
||||
|
||||
AHIGH_28_ = (0);
|
||||
|
||||
AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AHIGH_27_ = (0);
|
||||
|
||||
AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AHIGH_31_ = (0);
|
||||
|
||||
AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AHIGH_26_ = (0);
|
||||
|
||||
AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AHIGH_25_ = (0);
|
||||
|
||||
AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AHIGH_24_ = (0);
|
||||
|
||||
AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
|
||||
|
||||
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
|
@ -237,16 +209,48 @@ BERR = (0);
|
|||
|
||||
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
|
||||
|
||||
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
|
||||
|
||||
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q);
|
||||
|
||||
AHIGH_30_ = (0);
|
||||
|
||||
AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
|
||||
|
||||
CLK_DIV_OUT.C = (CLK_OSZI);
|
||||
|
||||
AHIGH_29_ = (0);
|
||||
|
||||
AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AHIGH_28_ = (0);
|
||||
|
||||
AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
|
||||
|
||||
AHIGH_27_ = (0);
|
||||
|
||||
AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AHIGH_26_ = (0);
|
||||
|
||||
AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AHIGH_25_ = (0);
|
||||
|
||||
AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AHIGH_24_ = (0);
|
||||
|
||||
AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
AVEC = (1);
|
||||
|
||||
E = (!cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q
|
||||
# cpu_est_1_.Q & cpu_est_2_.Q & !cpu_est_3_.Q);
|
||||
E = (cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_1_.Q
|
||||
# !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_1_.Q);
|
||||
|
||||
RESET = (0);
|
||||
|
||||
|
|
@ -266,10 +270,6 @@ CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030
|
|||
|
||||
CIIN.OE = (CIIN_0);
|
||||
|
||||
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
|
||||
|
||||
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q);
|
||||
|
||||
!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
|
||||
# RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
|
||||
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
|
||||
|
|
@ -303,6 +303,30 @@ BGACK_030.D = (!RST
|
|||
|
||||
BGACK_030.C = (CLK_OSZI);
|
||||
|
||||
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
|
||||
|
||||
CLK_EXP.C = (CLK_OSZI);
|
||||
|
||||
DSACK1.OE = (nEXP_SPACE);
|
||||
|
||||
!DSACK1.D = (RST & !inst_AS_030_D0.Q & !DSACK1.Q
|
||||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q);
|
||||
|
||||
DSACK1.C = (CLK_OSZI);
|
||||
|
||||
VMA.T = (!RST & !VMA.Q
|
||||
# !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q
|
||||
# RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||||
|
||||
VMA.C = (CLK_OSZI);
|
||||
|
||||
RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
|
||||
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
|
||||
|
||||
RW.C = (CLK_OSZI);
|
||||
|
||||
A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
A_0_.D = (!RST
|
||||
|
|
@ -337,31 +361,18 @@ IPL_030_1_.C = (CLK_OSZI);
|
|||
|
||||
IPL_030_0_.C = (CLK_OSZI);
|
||||
|
||||
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
|
||||
cpu_est_2_.D.X1 = (cpu_est_2_.Q);
|
||||
|
||||
CLK_EXP.C = (CLK_OSZI);
|
||||
cpu_est_2_.D.X2 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||||
|
||||
DSACK1.OE = (nEXP_SPACE);
|
||||
cpu_est_2_.C = (CLK_OSZI);
|
||||
|
||||
!DSACK1.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
|
||||
# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);
|
||||
cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q
|
||||
# cpu_est_3_.Q & CLK_000_D_0_.Q
|
||||
# !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q
|
||||
# cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||||
|
||||
DSACK1.C = (CLK_OSZI);
|
||||
|
||||
VMA.T = (!RST & !VMA.Q
|
||||
# !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q
|
||||
# RST & VMA.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||||
|
||||
VMA.C = (CLK_OSZI);
|
||||
|
||||
RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
|
||||
|
||||
!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
|
||||
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
|
||||
|
||||
RW.C = (CLK_OSZI);
|
||||
|
||||
!un10_ciin_i = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
|
||||
cpu_est_3_.C = (CLK_OSZI);
|
||||
|
||||
cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q
|
||||
# cpu_est_0_.Q & CLK_000_D_0_.Q
|
||||
|
|
@ -372,25 +383,12 @@ cpu_est_0_.C = (CLK_OSZI);
|
|||
cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q
|
||||
# cpu_est_1_.Q & !CLK_000_D_1_.Q
|
||||
# cpu_est_1_.Q & CLK_000_D_0_.Q
|
||||
# cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_3_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||||
# !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||||
|
||||
cpu_est_1_.C = (CLK_OSZI);
|
||||
|
||||
cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||||
|
||||
cpu_est_2_.D.X2 = (cpu_est_2_.Q);
|
||||
|
||||
cpu_est_2_.C = (CLK_OSZI);
|
||||
|
||||
cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q
|
||||
# cpu_est_3_.Q & !CLK_000_D_1_.Q
|
||||
# cpu_est_3_.Q & CLK_000_D_0_.Q
|
||||
# cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||||
|
||||
cpu_est_3_.C = (CLK_OSZI);
|
||||
|
||||
!inst_AS_000_INT.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q
|
||||
# RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
|
||||
!inst_AS_000_INT.D = (RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q
|
||||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q);
|
||||
|
||||
inst_AS_000_INT.C = (CLK_OSZI);
|
||||
|
||||
|
|
@ -403,13 +401,13 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
|
|||
|
||||
inst_AS_030_D0.C = (CLK_OSZI);
|
||||
|
||||
!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN
|
||||
# !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);
|
||||
inst_AS_030_000_SYNC.D = (!RST
|
||||
# inst_AS_030_D0.Q
|
||||
# !nEXP_SPACE & inst_AS_030_000_SYNC.Q
|
||||
# !BGACK_030.Q & inst_AS_030_000_SYNC.Q
|
||||
# inst_AS_030_000_SYNC.Q & !inst_BGACK_030_INT_D.Q
|
||||
# inst_AS_030_000_SYNC.Q & SM_AMIGA_i_7_.Q
|
||||
# FC_1_ & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & inst_AS_030_000_SYNC.Q);
|
||||
|
||||
inst_AS_030_000_SYNC.C = (CLK_OSZI);
|
||||
|
||||
|
|
@ -468,6 +466,10 @@ SIZE_DMA_1_.C = (CLK_OSZI);
|
|||
|
||||
inst_VPA_D.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_D_1_.D = (CLK_000_D_0_.Q);
|
||||
|
||||
CLK_000_D_1_.C = (CLK_OSZI);
|
||||
|
||||
!inst_DTACK_D0.D = (!DTACK & RST);
|
||||
|
||||
inst_DTACK_D0.C = (CLK_OSZI);
|
||||
|
|
@ -477,10 +479,6 @@ inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q
|
|||
|
||||
inst_RESET_OUT.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_D_1_.D = (CLK_000_D_0_.Q);
|
||||
|
||||
CLK_000_D_1_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_D_0_.D = (CLK_000);
|
||||
|
||||
CLK_000_D_0_.C = (CLK_OSZI);
|
||||
|
|
@ -510,6 +508,10 @@ IPL_D0_1_.C = (CLK_OSZI);
|
|||
|
||||
IPL_D0_2_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_D_2_.D = (CLK_000_D_1_.Q);
|
||||
|
||||
CLK_000_D_2_.C = (CLK_OSZI);
|
||||
|
||||
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q
|
||||
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
|
||||
|
||||
|
|
@ -521,8 +523,8 @@ inst_LDS_000_INT.D = (!RST
|
|||
|
||||
inst_LDS_000_INT.C = (CLK_OSZI);
|
||||
|
||||
inst_DS_000_ENABLE.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q
|
||||
# RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
|
||||
inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q
|
||||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q
|
||||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN);
|
||||
|
||||
inst_DS_000_ENABLE.C = (CLK_OSZI);
|
||||
|
|
@ -532,27 +534,27 @@ inst_DS_000_ENABLE.C = (CLK_OSZI);
|
|||
|
||||
inst_UDS_000_INT.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q);
|
||||
SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q
|
||||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q
|
||||
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q);
|
||||
|
||||
SM_AMIGA_6_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q
|
||||
# RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q & BERR.PIN
|
||||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_4_.Q & BERR.PIN);
|
||||
SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q
|
||||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_4_.Q
|
||||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q);
|
||||
|
||||
SM_AMIGA_4_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q
|
||||
# RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & BERR.PIN
|
||||
# RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & BERR.PIN);
|
||||
# RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
|
||||
|
||||
SM_AMIGA_1_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
|
||||
# RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q & BERR.PIN
|
||||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q & BERR.PIN);
|
||||
SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q
|
||||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q
|
||||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q);
|
||||
|
||||
SM_AMIGA_0_.C = (CLK_OSZI);
|
||||
|
||||
|
|
@ -586,47 +588,38 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst
|
|||
|
||||
inst_CLK_030_H.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q
|
||||
# RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q & BERR.PIN
|
||||
# RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q & BERR.PIN);
|
||||
SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q
|
||||
# RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q
|
||||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q);
|
||||
|
||||
SM_AMIGA_5_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_3_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
|
||||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN
|
||||
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN
|
||||
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN);
|
||||
|
||||
SM_AMIGA_3_.D.X2 = (RST & SM_AMIGA_3_.Q & BERR.PIN);
|
||||
SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
|
||||
# inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
|
||||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
|
||||
# inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
|
||||
# !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
|
||||
|
||||
SM_AMIGA_3_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q & BERR.PIN
|
||||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q & BERR.PIN
|
||||
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
|
||||
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
|
||||
SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q
|
||||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q
|
||||
# RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
|
||||
# RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
|
||||
# RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
|
||||
|
||||
SM_AMIGA_2_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_i_7_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !BERR.PIN
|
||||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN
|
||||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !BERR.PIN
|
||||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q & !BERR.PIN
|
||||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q & !BERR.PIN
|
||||
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
|
||||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
|
||||
# !nEXP_SPACE & RST & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
|
||||
# RST & inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
|
||||
# RST & !CLK_000_D_1_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
|
||||
# RST & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
|
||||
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
|
||||
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !BERR.PIN);
|
||||
SM_AMIGA_i_7_.D.X1 = (RST & SM_AMIGA_i_7_.Q
|
||||
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & !CLK_000_D_0_.Q & CLK_000_D_2_.Q & !SM_AMIGA_i_7_.Q
|
||||
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q);
|
||||
|
||||
SM_AMIGA_i_7_.D.X2 = (RST & BERR.PIN);
|
||||
SM_AMIGA_i_7_.D.X2 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q);
|
||||
|
||||
SM_AMIGA_i_7_.C = (CLK_OSZI);
|
||||
|
||||
!CIIN_0 = (!nEXP_SPACE & un10_ciin_i);
|
||||
CIIN_0 = (nEXP_SPACE
|
||||
# A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
|
||||
|
||||
|
||||
Reverse-Polarity Equations:
|
||||
|
|
|
|||
|
|
@ -34,16 +34,17 @@ DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030}
|
|||
DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000}
|
||||
DATA LOCATION BG_030:C_*_21 // INP
|
||||
DATA LOCATION CIIN:E_12_47 // OUT
|
||||
DATA LOCATION CIIN_0:G_14 // NOD
|
||||
DATA LOCATION CIIN_0:E_9 // NOD
|
||||
DATA LOCATION CLK_000:*_*_11 // INP
|
||||
DATA LOCATION CLK_000_D_0_:D_9 // NOD
|
||||
DATA LOCATION CLK_000_D_0_:B_13 // NOD
|
||||
DATA LOCATION CLK_000_D_1_:H_5 // NOD
|
||||
DATA LOCATION CLK_000_D_2_:E_13 // NOD
|
||||
DATA LOCATION CLK_030:*_*_64 // INP
|
||||
DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT
|
||||
DATA LOCATION CLK_EXP:B_1_10 // OUT
|
||||
DATA LOCATION CLK_OSZI:*_*_61 // Cin
|
||||
DATA LOCATION CYCLE_DMA_0_:F_1 // NOD
|
||||
DATA LOCATION CYCLE_DMA_1_:F_0 // NOD
|
||||
DATA LOCATION CYCLE_DMA_0_:G_2 // NOD
|
||||
DATA LOCATION CYCLE_DMA_1_:G_5 // NOD
|
||||
DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1}
|
||||
DATA LOCATION DS_030:A_0_98 // OUT
|
||||
DATA LOCATION DTACK:D_*_30 // INP
|
||||
|
|
@ -58,9 +59,9 @@ DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_}
|
|||
DATA LOCATION IPL_0_:G_*_67 // INP
|
||||
DATA LOCATION IPL_1_:F_*_56 // INP
|
||||
DATA LOCATION IPL_2_:G_*_68 // INP
|
||||
DATA LOCATION IPL_D0_0_:B_14 // NOD
|
||||
DATA LOCATION IPL_D0_1_:E_9 // NOD
|
||||
DATA LOCATION IPL_D0_2_:D_10 // NOD
|
||||
DATA LOCATION IPL_D0_0_:C_14 // NOD
|
||||
DATA LOCATION IPL_D0_1_:D_14 // NOD
|
||||
DATA LOCATION IPL_D0_2_:C_10 // NOD
|
||||
DATA LOCATION LDS_000:D_12_31 // IO
|
||||
DATA LOCATION RESET:B_2_3 // OUT
|
||||
DATA LOCATION RN_A_0_:G_8 // NOD {A_0_}
|
||||
|
|
@ -74,50 +75,49 @@ DATA LOCATION RN_RW:G_0 // NOD {RW}
|
|||
DATA LOCATION RN_RW_000:H_0 // NOD {RW_000}
|
||||
DATA LOCATION RN_VMA:D_0 // NOD {VMA}
|
||||
DATA LOCATION RST:*_*_86 // INP
|
||||
DATA LOCATION RST_DLY_0_:C_6 // NOD
|
||||
DATA LOCATION RST_DLY_1_:C_14 // NOD
|
||||
DATA LOCATION RST_DLY_2_:C_10 // NOD
|
||||
DATA LOCATION RST_DLY_0_:A_13 // NOD
|
||||
DATA LOCATION RST_DLY_1_:A_6 // NOD
|
||||
DATA LOCATION RST_DLY_2_:A_2 // NOD
|
||||
DATA LOCATION RW:G_0_71 // IO {RN_RW}
|
||||
DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000}
|
||||
DATA LOCATION SIZE_0_:G_12_70 // IO
|
||||
DATA LOCATION SIZE_1_:H_12_79 // IO
|
||||
DATA LOCATION SIZE_DMA_0_:G_2 // NOD
|
||||
DATA LOCATION SIZE_DMA_1_:G_13 // NOD
|
||||
DATA LOCATION SIZE_DMA_0_:C_2 // NOD
|
||||
DATA LOCATION SIZE_DMA_1_:G_10 // NOD
|
||||
DATA LOCATION SM_AMIGA_0_:H_13 // NOD
|
||||
DATA LOCATION SM_AMIGA_1_:A_1 // NOD
|
||||
DATA LOCATION SM_AMIGA_2_:A_9 // NOD
|
||||
DATA LOCATION SM_AMIGA_3_:A_13 // NOD
|
||||
DATA LOCATION SM_AMIGA_4_:F_4 // NOD
|
||||
DATA LOCATION SM_AMIGA_5_:A_12 // NOD
|
||||
DATA LOCATION SM_AMIGA_6_:C_13 // NOD
|
||||
DATA LOCATION SM_AMIGA_i_7_:A_8 // NOD
|
||||
DATA LOCATION SM_AMIGA_1_:A_12 // NOD
|
||||
DATA LOCATION SM_AMIGA_2_:A_5 // NOD
|
||||
DATA LOCATION SM_AMIGA_3_:A_9 // NOD
|
||||
DATA LOCATION SM_AMIGA_4_:G_13 // NOD
|
||||
DATA LOCATION SM_AMIGA_5_:D_13 // NOD
|
||||
DATA LOCATION SM_AMIGA_6_:B_6 // NOD
|
||||
DATA LOCATION SM_AMIGA_i_7_:B_14 // NOD
|
||||
DATA LOCATION UDS_000:D_8_32 // IO
|
||||
DATA LOCATION VMA:D_0_35 // IO {RN_VMA}
|
||||
DATA LOCATION VPA:*_*_36 // INP
|
||||
DATA LOCATION cpu_est_0_:D_2 // NOD
|
||||
DATA LOCATION cpu_est_1_:G_5 // NOD
|
||||
DATA LOCATION cpu_est_2_:G_9 // NOD
|
||||
DATA LOCATION cpu_est_3_:D_13 // NOD
|
||||
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:G_6 // NOD
|
||||
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:G_10 // NOD
|
||||
DATA LOCATION inst_AS_000_DMA:B_6 // NOD
|
||||
DATA LOCATION inst_AS_000_INT:F_5 // NOD
|
||||
DATA LOCATION inst_AS_030_000_SYNC:C_2 // NOD
|
||||
DATA LOCATION cpu_est_0_:B_10 // NOD
|
||||
DATA LOCATION cpu_est_1_:G_9 // NOD
|
||||
DATA LOCATION cpu_est_2_:G_6 // NOD
|
||||
DATA LOCATION cpu_est_3_:D_9 // NOD
|
||||
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:F_8 // NOD
|
||||
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:F_12 // NOD
|
||||
DATA LOCATION inst_AS_000_DMA:C_9 // NOD
|
||||
DATA LOCATION inst_AS_000_INT:D_2 // NOD
|
||||
DATA LOCATION inst_AS_030_000_SYNC:C_13 // NOD
|
||||
DATA LOCATION inst_AS_030_D0:E_8 // NOD
|
||||
DATA LOCATION inst_BGACK_030_INT_D:E_5 // NOD
|
||||
DATA LOCATION inst_CLK_030_H:B_10 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_25:F_13 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_50:F_2 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_D:F_9 // NOD
|
||||
DATA LOCATION inst_DS_000_DMA:B_13 // NOD
|
||||
DATA LOCATION inst_DS_000_ENABLE:F_8 // NOD
|
||||
DATA LOCATION inst_DTACK_D0:F_6 // NOD
|
||||
DATA LOCATION inst_LDS_000_INT:F_12 // NOD
|
||||
DATA LOCATION inst_RESET_OUT:C_9 // NOD
|
||||
DATA LOCATION inst_UDS_000_INT:D_6 // NOD
|
||||
DATA LOCATION inst_VPA_D:A_5 // NOD
|
||||
DATA LOCATION inst_CLK_030_H:C_6 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_25:G_14 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_50:A_1 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_D:H_2 // NOD
|
||||
DATA LOCATION inst_DS_000_DMA:F_0 // NOD
|
||||
DATA LOCATION inst_DS_000_ENABLE:D_6 // NOD
|
||||
DATA LOCATION inst_DTACK_D0:H_6 // NOD
|
||||
DATA LOCATION inst_LDS_000_INT:F_4 // NOD
|
||||
DATA LOCATION inst_RESET_OUT:A_8 // NOD
|
||||
DATA LOCATION inst_UDS_000_INT:D_10 // NOD
|
||||
DATA LOCATION inst_VPA_D:F_1 // NOD
|
||||
DATA LOCATION nEXP_SPACE:*_*_14 // INP
|
||||
DATA LOCATION un10_ciin_i:E_13 // NOD
|
||||
DATA IO_DIR AHIGH_24_:BI
|
||||
DATA IO_DIR AHIGH_25_:BI
|
||||
DATA IO_DIR AHIGH_26_:BI
|
||||
|
|
@ -180,42 +180,14 @@ DATA IO_DIR VMA:OUT
|
|||
DATA IO_DIR VPA:IN
|
||||
DATA IO_DIR nEXP_SPACE:IN
|
||||
DATA GLB_CLOCK CLK_OSZI
|
||||
DATA PW_LEVEL AHIGH_30_:1
|
||||
DATA SLEW AHIGH_30_:0
|
||||
DATA PW_LEVEL AHIGH_29_:1
|
||||
DATA SLEW AHIGH_29_:0
|
||||
DATA PW_LEVEL SIZE_1_:1
|
||||
DATA SLEW SIZE_1_:0
|
||||
DATA PW_LEVEL AHIGH_28_:1
|
||||
DATA SLEW AHIGH_28_:0
|
||||
DATA PW_LEVEL AHIGH_27_:1
|
||||
DATA SLEW AHIGH_27_:0
|
||||
DATA PW_LEVEL AHIGH_31_:1
|
||||
DATA SLEW AHIGH_31_:0
|
||||
DATA PW_LEVEL AHIGH_26_:1
|
||||
DATA SLEW AHIGH_26_:0
|
||||
DATA PW_LEVEL AHIGH_25_:1
|
||||
DATA SLEW AHIGH_25_:0
|
||||
DATA PW_LEVEL A_DECODE_23_:1
|
||||
DATA SLEW A_DECODE_23_:1
|
||||
DATA PW_LEVEL AHIGH_24_:1
|
||||
DATA SLEW AHIGH_24_:0
|
||||
DATA PW_LEVEL A_DECODE_22_:1
|
||||
DATA SLEW A_DECODE_22_:1
|
||||
DATA PW_LEVEL A_DECODE_21_:1
|
||||
DATA SLEW A_DECODE_21_:1
|
||||
DATA PW_LEVEL A_DECODE_20_:1
|
||||
DATA SLEW A_DECODE_20_:1
|
||||
DATA PW_LEVEL A_DECODE_19_:1
|
||||
DATA SLEW A_DECODE_19_:1
|
||||
DATA PW_LEVEL A_DECODE_18_:1
|
||||
DATA SLEW A_DECODE_18_:1
|
||||
DATA PW_LEVEL IPL_2_:1
|
||||
DATA SLEW IPL_2_:1
|
||||
DATA PW_LEVEL A_DECODE_17_:1
|
||||
DATA SLEW A_DECODE_17_:1
|
||||
DATA PW_LEVEL A_DECODE_16_:1
|
||||
DATA SLEW A_DECODE_16_:1
|
||||
DATA PW_LEVEL FC_1_:1
|
||||
DATA SLEW FC_1_:1
|
||||
DATA PW_LEVEL AS_030:1
|
||||
|
|
@ -237,31 +209,53 @@ DATA PW_LEVEL BGACK_000:1
|
|||
DATA SLEW BGACK_000:1
|
||||
DATA SLEW CLK_030:1
|
||||
DATA SLEW CLK_000:1
|
||||
DATA PW_LEVEL SIZE_0_:1
|
||||
DATA SLEW SIZE_0_:0
|
||||
DATA SLEW CLK_OSZI:1
|
||||
DATA PW_LEVEL AHIGH_30_:1
|
||||
DATA SLEW AHIGH_30_:0
|
||||
DATA PW_LEVEL CLK_DIV_OUT:1
|
||||
DATA SLEW CLK_DIV_OUT:0
|
||||
DATA PW_LEVEL IPL_1_:1
|
||||
DATA SLEW IPL_1_:1
|
||||
DATA PW_LEVEL AHIGH_29_:1
|
||||
DATA SLEW AHIGH_29_:0
|
||||
DATA PW_LEVEL AHIGH_28_:1
|
||||
DATA SLEW AHIGH_28_:0
|
||||
DATA PW_LEVEL FPU_CS:1
|
||||
DATA SLEW FPU_CS:0
|
||||
DATA PW_LEVEL IPL_0_:1
|
||||
DATA SLEW IPL_0_:1
|
||||
DATA PW_LEVEL AHIGH_27_:1
|
||||
DATA SLEW AHIGH_27_:0
|
||||
DATA PW_LEVEL FPU_SENSE:1
|
||||
DATA SLEW FPU_SENSE:1
|
||||
DATA PW_LEVEL FC_0_:1
|
||||
DATA SLEW FC_0_:1
|
||||
DATA PW_LEVEL A_1_:1
|
||||
DATA SLEW A_1_:1
|
||||
DATA PW_LEVEL AHIGH_26_:1
|
||||
DATA SLEW AHIGH_26_:0
|
||||
DATA PW_LEVEL AHIGH_25_:1
|
||||
DATA SLEW AHIGH_25_:0
|
||||
DATA PW_LEVEL DTACK:1
|
||||
DATA SLEW DTACK:1
|
||||
DATA PW_LEVEL AHIGH_24_:1
|
||||
DATA SLEW AHIGH_24_:0
|
||||
DATA PW_LEVEL AVEC:1
|
||||
DATA SLEW AVEC:0
|
||||
DATA PW_LEVEL A_DECODE_22_:1
|
||||
DATA SLEW A_DECODE_22_:1
|
||||
DATA PW_LEVEL E:1
|
||||
DATA SLEW E:0
|
||||
DATA PW_LEVEL A_DECODE_21_:1
|
||||
DATA SLEW A_DECODE_21_:1
|
||||
DATA SLEW VPA:1
|
||||
DATA PW_LEVEL A_DECODE_20_:1
|
||||
DATA SLEW A_DECODE_20_:1
|
||||
DATA PW_LEVEL A_DECODE_19_:1
|
||||
DATA SLEW A_DECODE_19_:1
|
||||
DATA SLEW RST:1
|
||||
DATA PW_LEVEL A_DECODE_18_:1
|
||||
DATA SLEW A_DECODE_18_:1
|
||||
DATA PW_LEVEL RESET:1
|
||||
DATA SLEW RESET:0
|
||||
DATA PW_LEVEL A_DECODE_17_:1
|
||||
DATA SLEW A_DECODE_17_:1
|
||||
DATA PW_LEVEL A_DECODE_16_:1
|
||||
DATA SLEW A_DECODE_16_:1
|
||||
DATA PW_LEVEL AMIGA_ADDR_ENABLE:1
|
||||
DATA SLEW AMIGA_ADDR_ENABLE:0
|
||||
DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1
|
||||
|
|
@ -272,8 +266,14 @@ DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1
|
|||
DATA SLEW AMIGA_BUS_ENABLE_HIGH:0
|
||||
DATA PW_LEVEL CIIN:1
|
||||
DATA SLEW CIIN:0
|
||||
DATA PW_LEVEL SIZE_0_:1
|
||||
DATA SLEW SIZE_0_:0
|
||||
DATA PW_LEVEL IPL_1_:1
|
||||
DATA SLEW IPL_1_:1
|
||||
DATA PW_LEVEL IPL_0_:1
|
||||
DATA SLEW IPL_0_:1
|
||||
DATA PW_LEVEL FC_0_:1
|
||||
DATA SLEW FC_0_:1
|
||||
DATA PW_LEVEL A_1_:1
|
||||
DATA SLEW A_1_:1
|
||||
DATA PW_LEVEL IPL_030_2_:1
|
||||
DATA SLEW IPL_030_2_:0
|
||||
DATA PW_LEVEL RW_000:1
|
||||
|
|
@ -282,12 +282,6 @@ DATA PW_LEVEL BG_000:1
|
|||
DATA SLEW BG_000:0
|
||||
DATA PW_LEVEL BGACK_030:1
|
||||
DATA SLEW BGACK_030:0
|
||||
DATA PW_LEVEL A_0_:1
|
||||
DATA SLEW A_0_:0
|
||||
DATA PW_LEVEL IPL_030_1_:1
|
||||
DATA SLEW IPL_030_1_:0
|
||||
DATA PW_LEVEL IPL_030_0_:1
|
||||
DATA SLEW IPL_030_0_:0
|
||||
DATA PW_LEVEL CLK_EXP:1
|
||||
DATA SLEW CLK_EXP:0
|
||||
DATA PW_LEVEL DSACK1:1
|
||||
|
|
@ -296,16 +290,20 @@ DATA PW_LEVEL VMA:1
|
|||
DATA SLEW VMA:0
|
||||
DATA PW_LEVEL RW:1
|
||||
DATA SLEW RW:0
|
||||
DATA PW_LEVEL un10_ciin_i:1
|
||||
DATA SLEW un10_ciin_i:1
|
||||
DATA PW_LEVEL cpu_est_0_:1
|
||||
DATA SLEW cpu_est_0_:1
|
||||
DATA PW_LEVEL cpu_est_1_:1
|
||||
DATA SLEW cpu_est_1_:1
|
||||
DATA PW_LEVEL A_0_:1
|
||||
DATA SLEW A_0_:0
|
||||
DATA PW_LEVEL IPL_030_1_:1
|
||||
DATA SLEW IPL_030_1_:0
|
||||
DATA PW_LEVEL IPL_030_0_:1
|
||||
DATA SLEW IPL_030_0_:0
|
||||
DATA PW_LEVEL cpu_est_2_:1
|
||||
DATA SLEW cpu_est_2_:1
|
||||
DATA PW_LEVEL cpu_est_3_:1
|
||||
DATA SLEW cpu_est_3_:1
|
||||
DATA PW_LEVEL cpu_est_0_:1
|
||||
DATA SLEW cpu_est_0_:1
|
||||
DATA PW_LEVEL cpu_est_1_:1
|
||||
DATA SLEW cpu_est_1_:1
|
||||
DATA PW_LEVEL inst_AS_000_INT:1
|
||||
DATA SLEW inst_AS_000_INT:1
|
||||
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1
|
||||
|
|
@ -330,12 +328,12 @@ DATA PW_LEVEL SIZE_DMA_1_:1
|
|||
DATA SLEW SIZE_DMA_1_:1
|
||||
DATA PW_LEVEL inst_VPA_D:1
|
||||
DATA SLEW inst_VPA_D:1
|
||||
DATA PW_LEVEL CLK_000_D_1_:1
|
||||
DATA SLEW CLK_000_D_1_:1
|
||||
DATA PW_LEVEL inst_DTACK_D0:1
|
||||
DATA SLEW inst_DTACK_D0:1
|
||||
DATA PW_LEVEL inst_RESET_OUT:1
|
||||
DATA SLEW inst_RESET_OUT:1
|
||||
DATA PW_LEVEL CLK_000_D_1_:1
|
||||
DATA SLEW CLK_000_D_1_:1
|
||||
DATA PW_LEVEL CLK_000_D_0_:1
|
||||
DATA SLEW CLK_000_D_0_:1
|
||||
DATA PW_LEVEL inst_CLK_OUT_PRE_50:1
|
||||
|
|
@ -350,6 +348,8 @@ DATA PW_LEVEL IPL_D0_1_:1
|
|||
DATA SLEW IPL_D0_1_:1
|
||||
DATA PW_LEVEL IPL_D0_2_:1
|
||||
DATA SLEW IPL_D0_2_:1
|
||||
DATA PW_LEVEL CLK_000_D_2_:1
|
||||
DATA SLEW CLK_000_D_2_:1
|
||||
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
|
||||
DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
|
||||
DATA PW_LEVEL inst_LDS_000_INT:1
|
||||
|
|
@ -388,10 +388,10 @@ DATA PW_LEVEL RN_IPL_030_2_:1
|
|||
DATA PW_LEVEL RN_RW_000:1
|
||||
DATA PW_LEVEL RN_BG_000:1
|
||||
DATA PW_LEVEL RN_BGACK_030:1
|
||||
DATA PW_LEVEL RN_A_0_:1
|
||||
DATA PW_LEVEL RN_IPL_030_1_:1
|
||||
DATA PW_LEVEL RN_IPL_030_0_:1
|
||||
DATA PW_LEVEL RN_DSACK1:1
|
||||
DATA PW_LEVEL RN_VMA:1
|
||||
DATA PW_LEVEL RN_RW:1
|
||||
DATA PW_LEVEL RN_A_0_:1
|
||||
DATA PW_LEVEL RN_IPL_030_1_:1
|
||||
DATA PW_LEVEL RN_IPL_030_0_:1
|
||||
END
|
||||
|
|
|
|||
|
|
@ -1,22 +1,22 @@
|
|||
|
||||
GROUP MACH_SEG_A DS_030 AVEC SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_1_
|
||||
SM_AMIGA_5_ inst_VPA_D
|
||||
GROUP MACH_SEG_A DS_030 AVEC SM_AMIGA_2_ SM_AMIGA_3_ inst_RESET_OUT RST_DLY_0_
|
||||
RST_DLY_1_ RST_DLY_2_ SM_AMIGA_1_ inst_CLK_OUT_PRE_50
|
||||
GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
|
||||
RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP RESET inst_DS_000_DMA
|
||||
inst_CLK_030_H inst_AS_000_DMA IPL_D0_0_
|
||||
RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP RESET SM_AMIGA_i_7_
|
||||
SM_AMIGA_6_ cpu_est_0_ CLK_000_D_0_
|
||||
GROUP MACH_SEG_C AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AMIGA_BUS_ENABLE_LOW
|
||||
inst_AS_030_000_SYNC SM_AMIGA_6_ inst_RESET_OUT RST_DLY_0_ RST_DLY_1_
|
||||
RST_DLY_2_
|
||||
inst_AS_030_000_SYNC inst_CLK_030_H inst_AS_000_DMA SIZE_DMA_0_ IPL_D0_0_
|
||||
IPL_D0_2_
|
||||
GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH
|
||||
AMIGA_ADDR_ENABLE cpu_est_3_ inst_UDS_000_INT cpu_est_0_ IPL_D0_2_
|
||||
CLK_000_D_0_
|
||||
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 un10_ciin_i inst_AS_030_D0
|
||||
IPL_D0_1_ inst_BGACK_030_INT_D
|
||||
GROUP MACH_SEG_F inst_DS_000_ENABLE inst_AS_000_INT CYCLE_DMA_1_ inst_LDS_000_INT
|
||||
SM_AMIGA_4_ CYCLE_DMA_0_ inst_CLK_OUT_PRE_25 inst_DTACK_D0 inst_CLK_OUT_PRE_50
|
||||
inst_CLK_OUT_PRE_D
|
||||
GROUP MACH_SEG_G A_0_ RN_A_0_ RW RN_RW SIZE_0_ E CLK_DIV_OUT SIZE_DMA_0_
|
||||
SIZE_DMA_1_ cpu_est_1_ cpu_est_2_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
CIIN_0
|
||||
AMIGA_ADDR_ENABLE inst_DS_000_ENABLE cpu_est_3_ inst_AS_000_INT SM_AMIGA_5_
|
||||
inst_UDS_000_INT IPL_D0_1_
|
||||
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 inst_AS_030_D0
|
||||
inst_BGACK_030_INT_D CLK_000_D_2_
|
||||
GROUP MACH_SEG_F inst_DS_000_DMA inst_LDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_VPA_D
|
||||
GROUP MACH_SEG_G A_0_ RN_A_0_ RW RN_RW SIZE_0_ E CLK_DIV_OUT CYCLE_DMA_1_
|
||||
SIZE_DMA_1_ CYCLE_DMA_0_ cpu_est_2_ cpu_est_1_ SM_AMIGA_4_ inst_CLK_OUT_PRE_25
|
||||
|
||||
GROUP MACH_SEG_H RW_000 RN_RW_000 FPU_CS DSACK1 RN_DSACK1 BGACK_030 RN_BGACK_030
|
||||
AS_030 SIZE_1_ SM_AMIGA_0_ CLK_000_D_1_
|
||||
AS_030 SIZE_1_ SM_AMIGA_0_ inst_DTACK_D0 inst_CLK_OUT_PRE_D CLK_000_D_1_
|
||||
|
||||
|
|
@ -1 +1 @@
|
|||
<LATTICE_ENCRYPTED_BLIF>26:5144]e @1UtR
|
||||
<LATTICE_ENCRYPTED_BLIF>6723==5O39`{ >
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1 +1 @@
|
|||
. BUS68030 68030-68000-bus.vhd c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd
|
||||
. BUS68030 68030-68000-bus.vhd c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd
|
||||
|
|
|
|||
|
|
@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
|
|||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
DATE = 8/25/16;
|
||||
TIME = 22:27:55;
|
||||
DATE = 9/14/16;
|
||||
TIME = 23:54:30;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
|
@ -76,24 +76,10 @@ Usercode_Format = Hex;
|
|||
|
||||
[LOCATION ASSIGNMENTS]
|
||||
Layer = OFF;
|
||||
AHIGH_30_ = pin,5,-,B,-;
|
||||
AHIGH_29_ = pin,6,-,B,-;
|
||||
SIZE_1_ = pin,79,-,H,-;
|
||||
AHIGH_28_ = pin,15,-,C,-;
|
||||
AHIGH_27_ = pin,16,-,C,-;
|
||||
AHIGH_31_ = pin,4,-,B,-;
|
||||
AHIGH_26_ = pin,17,-,C,-;
|
||||
AHIGH_25_ = pin,18,-,C,-;
|
||||
A_DECODE_23_ = pin,85,-,H,-;
|
||||
AHIGH_24_ = pin,19,-,C,-;
|
||||
A_DECODE_22_ = pin,84,-,H,-;
|
||||
A_DECODE_21_ = pin,94,-,A,-;
|
||||
A_DECODE_20_ = pin,93,-,A,-;
|
||||
A_DECODE_19_ = pin,97,-,A,-;
|
||||
A_DECODE_18_ = pin,95,-,A,-;
|
||||
IPL_2_ = pin,68,-,G,-;
|
||||
A_DECODE_17_ = pin,59,-,F,-;
|
||||
A_DECODE_16_ = pin,96,-,A,-;
|
||||
FC_1_ = pin,58,-,F,-;
|
||||
AS_030 = pin,82,-,H,-;
|
||||
AS_000 = pin,42,-,E,-;
|
||||
|
|
@ -106,81 +92,95 @@ BG_030 = pin,21,-,C,-;
|
|||
BGACK_000 = pin,28,-,D,-;
|
||||
CLK_030 = pin,64,-,-,-;
|
||||
CLK_000 = pin,11,-,-,-;
|
||||
SIZE_0_ = pin,70,-,G,-;
|
||||
CLK_OSZI = pin,61,-,-,-;
|
||||
AHIGH_30_ = pin,5,-,B,-;
|
||||
CLK_DIV_OUT = pin,65,-,G,-;
|
||||
IPL_1_ = pin,56,-,F,-;
|
||||
AHIGH_29_ = pin,6,-,B,-;
|
||||
AHIGH_28_ = pin,15,-,C,-;
|
||||
FPU_CS = pin,78,-,H,-;
|
||||
IPL_0_ = pin,67,-,G,-;
|
||||
AHIGH_27_ = pin,16,-,C,-;
|
||||
FPU_SENSE = pin,91,-,A,-;
|
||||
FC_0_ = pin,57,-,F,-;
|
||||
A_1_ = pin,60,-,F,-;
|
||||
AHIGH_26_ = pin,17,-,C,-;
|
||||
AHIGH_25_ = pin,18,-,C,-;
|
||||
DTACK = pin,30,-,D,-;
|
||||
AHIGH_24_ = pin,19,-,C,-;
|
||||
AVEC = pin,92,-,A,-;
|
||||
A_DECODE_22_ = pin,84,-,H,-;
|
||||
E = pin,66,-,G,-;
|
||||
A_DECODE_21_ = pin,94,-,A,-;
|
||||
VPA = pin,36,-,-,-;
|
||||
A_DECODE_20_ = pin,93,-,A,-;
|
||||
A_DECODE_19_ = pin,97,-,A,-;
|
||||
RST = pin,86,-,-,-;
|
||||
A_DECODE_18_ = pin,95,-,A,-;
|
||||
RESET = pin,3,-,B,-;
|
||||
A_DECODE_17_ = pin,59,-,F,-;
|
||||
A_DECODE_16_ = pin,96,-,A,-;
|
||||
AMIGA_ADDR_ENABLE = pin,33,-,D,-;
|
||||
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
|
||||
CIIN = pin,47,-,E,-;
|
||||
SIZE_0_ = pin,70,-,G,-;
|
||||
IPL_1_ = pin,56,-,F,-;
|
||||
IPL_0_ = pin,67,-,G,-;
|
||||
FC_0_ = pin,57,-,F,-;
|
||||
A_1_ = pin,60,-,F,-;
|
||||
IPL_030_2_ = pin,9,-,B,-;
|
||||
RW_000 = pin,80,-,H,-;
|
||||
BG_000 = pin,29,-,D,-;
|
||||
BGACK_030 = pin,83,-,H,-;
|
||||
A_0_ = pin,69,-,G,-;
|
||||
IPL_030_1_ = pin,7,-,B,-;
|
||||
IPL_030_0_ = pin,8,-,B,-;
|
||||
CLK_EXP = pin,10,-,B,-;
|
||||
DSACK1 = pin,81,-,H,-;
|
||||
VMA = pin,35,-,D,-;
|
||||
RW = pin,71,-,G,-;
|
||||
un10_ciin_i = node,-,-,E,13;
|
||||
cpu_est_0_ = node,-,-,D,2;
|
||||
cpu_est_1_ = node,-,-,G,5;
|
||||
cpu_est_2_ = node,-,-,G,9;
|
||||
cpu_est_3_ = node,-,-,D,13;
|
||||
inst_AS_000_INT = node,-,-,F,5;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,G,10;
|
||||
A_0_ = pin,69,-,G,-;
|
||||
IPL_030_1_ = pin,7,-,B,-;
|
||||
IPL_030_0_ = pin,8,-,B,-;
|
||||
cpu_est_2_ = node,-,-,G,6;
|
||||
cpu_est_3_ = node,-,-,D,9;
|
||||
cpu_est_0_ = node,-,-,B,10;
|
||||
cpu_est_1_ = node,-,-,G,9;
|
||||
inst_AS_000_INT = node,-,-,D,2;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,F,12;
|
||||
inst_AS_030_D0 = node,-,-,E,8;
|
||||
inst_AS_030_000_SYNC = node,-,-,C,2;
|
||||
inst_AS_030_000_SYNC = node,-,-,C,13;
|
||||
inst_BGACK_030_INT_D = node,-,-,E,5;
|
||||
inst_AS_000_DMA = node,-,-,B,6;
|
||||
inst_DS_000_DMA = node,-,-,B,13;
|
||||
CYCLE_DMA_0_ = node,-,-,F,1;
|
||||
CYCLE_DMA_1_ = node,-,-,F,0;
|
||||
SIZE_DMA_0_ = node,-,-,G,2;
|
||||
SIZE_DMA_1_ = node,-,-,G,13;
|
||||
inst_VPA_D = node,-,-,A,5;
|
||||
inst_DTACK_D0 = node,-,-,F,6;
|
||||
inst_RESET_OUT = node,-,-,C,9;
|
||||
inst_AS_000_DMA = node,-,-,C,9;
|
||||
inst_DS_000_DMA = node,-,-,F,0;
|
||||
CYCLE_DMA_0_ = node,-,-,G,2;
|
||||
CYCLE_DMA_1_ = node,-,-,G,5;
|
||||
SIZE_DMA_0_ = node,-,-,C,2;
|
||||
SIZE_DMA_1_ = node,-,-,G,10;
|
||||
inst_VPA_D = node,-,-,F,1;
|
||||
CLK_000_D_1_ = node,-,-,H,5;
|
||||
CLK_000_D_0_ = node,-,-,D,9;
|
||||
inst_CLK_OUT_PRE_50 = node,-,-,F,2;
|
||||
inst_CLK_OUT_PRE_25 = node,-,-,F,13;
|
||||
inst_CLK_OUT_PRE_D = node,-,-,F,9;
|
||||
IPL_D0_0_ = node,-,-,B,14;
|
||||
IPL_D0_1_ = node,-,-,E,9;
|
||||
IPL_D0_2_ = node,-,-,D,10;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,G,6;
|
||||
inst_LDS_000_INT = node,-,-,F,12;
|
||||
inst_DS_000_ENABLE = node,-,-,F,8;
|
||||
inst_UDS_000_INT = node,-,-,D,6;
|
||||
SM_AMIGA_6_ = node,-,-,C,13;
|
||||
SM_AMIGA_4_ = node,-,-,F,4;
|
||||
SM_AMIGA_1_ = node,-,-,A,1;
|
||||
inst_DTACK_D0 = node,-,-,H,6;
|
||||
inst_RESET_OUT = node,-,-,A,8;
|
||||
CLK_000_D_0_ = node,-,-,B,13;
|
||||
inst_CLK_OUT_PRE_50 = node,-,-,A,1;
|
||||
inst_CLK_OUT_PRE_25 = node,-,-,G,14;
|
||||
inst_CLK_OUT_PRE_D = node,-,-,H,2;
|
||||
IPL_D0_0_ = node,-,-,C,14;
|
||||
IPL_D0_1_ = node,-,-,D,14;
|
||||
IPL_D0_2_ = node,-,-,C,10;
|
||||
CLK_000_D_2_ = node,-,-,E,13;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,F,8;
|
||||
inst_LDS_000_INT = node,-,-,F,4;
|
||||
inst_DS_000_ENABLE = node,-,-,D,6;
|
||||
inst_UDS_000_INT = node,-,-,D,10;
|
||||
SM_AMIGA_6_ = node,-,-,B,6;
|
||||
SM_AMIGA_4_ = node,-,-,G,13;
|
||||
SM_AMIGA_1_ = node,-,-,A,12;
|
||||
SM_AMIGA_0_ = node,-,-,H,13;
|
||||
RST_DLY_0_ = node,-,-,C,6;
|
||||
RST_DLY_1_ = node,-,-,C,14;
|
||||
RST_DLY_2_ = node,-,-,C,10;
|
||||
inst_CLK_030_H = node,-,-,B,10;
|
||||
SM_AMIGA_5_ = node,-,-,A,12;
|
||||
SM_AMIGA_3_ = node,-,-,A,13;
|
||||
SM_AMIGA_2_ = node,-,-,A,9;
|
||||
SM_AMIGA_i_7_ = node,-,-,A,8;
|
||||
CIIN_0 = node,-,-,G,14;
|
||||
RST_DLY_0_ = node,-,-,A,13;
|
||||
RST_DLY_1_ = node,-,-,A,6;
|
||||
RST_DLY_2_ = node,-,-,A,2;
|
||||
inst_CLK_030_H = node,-,-,C,6;
|
||||
SM_AMIGA_5_ = node,-,-,D,13;
|
||||
SM_AMIGA_3_ = node,-,-,A,9;
|
||||
SM_AMIGA_2_ = node,-,-,A,5;
|
||||
SM_AMIGA_i_7_ = node,-,-,B,14;
|
||||
CIIN_0 = node,-,-,E,9;
|
||||
|
||||
[GROUP ASSIGNMENTS]
|
||||
Layer = OFF;
|
||||
|
|
|
|||
1441
Logic/68030_tk.out
1441
Logic/68030_tk.out
File diff suppressed because it is too large
Load Diff
|
|
@ -8,27 +8,13 @@
|
|||
; Source file 68030_tk.tt4
|
||||
; FITTER-generated Placements.
|
||||
; DEVICE mach447a
|
||||
; DATE Thu Aug 25 22:27:55 2016
|
||||
; DATE Wed Sep 14 23:54:30 2016
|
||||
|
||||
|
||||
Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125
|
||||
Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137
|
||||
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287
|
||||
Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149
|
||||
Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 157
|
||||
Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143
|
||||
Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 155
|
||||
Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167
|
||||
Pin 85 A_DECODE_23_
|
||||
Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161
|
||||
Pin 84 A_DECODE_22_
|
||||
Pin 94 A_DECODE_21_
|
||||
Pin 93 A_DECODE_20_
|
||||
Pin 97 A_DECODE_19_
|
||||
Pin 95 A_DECODE_18_
|
||||
Pin 68 IPL_2_
|
||||
Pin 59 A_DECODE_17_
|
||||
Pin 96 A_DECODE_16_
|
||||
Pin 58 FC_1_
|
||||
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
|
||||
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
|
||||
|
|
@ -41,105 +27,119 @@ Pin 21 BG_030
|
|||
Pin 28 BGACK_000
|
||||
Pin 64 CLK_030
|
||||
Pin 11 CLK_000
|
||||
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
|
||||
Pin 61 CLK_OSZI
|
||||
Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125
|
||||
Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247
|
||||
Pin 56 IPL_1_
|
||||
Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137
|
||||
Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149
|
||||
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271
|
||||
Pin 67 IPL_0_
|
||||
Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 157
|
||||
Pin 91 FPU_SENSE
|
||||
Pin 57 FC_0_
|
||||
Pin 60 A_1_
|
||||
Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 155
|
||||
Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167
|
||||
Pin 30 DTACK
|
||||
Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161
|
||||
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
|
||||
Pin 84 A_DECODE_22_
|
||||
Pin 66 E Comb ; S6=1 S9=1 Pair 251
|
||||
Pin 94 A_DECODE_21_
|
||||
Pin 36 VPA
|
||||
Pin 93 A_DECODE_20_
|
||||
Pin 97 A_DECODE_19_
|
||||
Pin 86 RST
|
||||
Pin 95 A_DECODE_18_
|
||||
Pin 3 RESET Comb ; S6=1 S9=1 Pair 128
|
||||
Pin 59 A_DECODE_17_
|
||||
Pin 96 A_DECODE_16_
|
||||
Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181
|
||||
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199
|
||||
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151
|
||||
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179
|
||||
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
|
||||
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
|
||||
Pin 56 IPL_1_
|
||||
Pin 67 IPL_0_
|
||||
Pin 57 FC_0_
|
||||
Pin 60 A_1_
|
||||
Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131
|
||||
Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269
|
||||
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
|
||||
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
|
||||
Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257
|
||||
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139
|
||||
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133
|
||||
Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 127
|
||||
Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 283
|
||||
Pin 35 VMA Reg ; S6=1 S9=1 Pair 173
|
||||
Pin 71 RW Reg ; S6=1 S9=1 Pair 245
|
||||
Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1
|
||||
Node 137 RN_AHIGH_29_ Comb ; S6=1 S9=1
|
||||
Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257
|
||||
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139
|
||||
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133
|
||||
Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1
|
||||
Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1
|
||||
Node 157 RN_AHIGH_27_ Comb ; S6=1 S9=1
|
||||
Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1
|
||||
Node 155 RN_AHIGH_26_ Comb ; S6=1 S9=1
|
||||
Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1
|
||||
Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1
|
||||
Node 281 RN_AS_030 Comb ; S6=1 S9=1
|
||||
Node 203 RN_AS_000 Comb ; S6=1 S9=1
|
||||
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
|
||||
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
|
||||
Node 197 RN_BERR Comb ; S6=1 S9=1
|
||||
Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1
|
||||
Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1
|
||||
Node 137 RN_AHIGH_29_ Comb ; S6=1 S9=1
|
||||
Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1
|
||||
Node 157 RN_AHIGH_27_ Comb ; S6=1 S9=1
|
||||
Node 155 RN_AHIGH_26_ Comb ; S6=1 S9=1
|
||||
Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1
|
||||
Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1
|
||||
Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1
|
||||
Node 269 RN_RW_000 Reg ; S6=1 S9=1
|
||||
Node 175 RN_BG_000 Reg ; S6=1 S9=1
|
||||
Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
|
||||
Node 257 RN_A_0_ Reg ; S6=1 S9=1
|
||||
Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1
|
||||
Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1
|
||||
Node 283 RN_DSACK1 Reg ; S6=1 S9=1
|
||||
Node 173 RN_VMA Reg ; S6=1 S9=1
|
||||
Node 245 RN_RW Reg ; S6=1 S9=1
|
||||
Node 217 un10_ciin_i Comb ; S6=1 S9=1
|
||||
Node 176 cpu_est_0_ Reg ; S6=1 S9=1
|
||||
Node 253 cpu_est_1_ Reg ; S6=1 S9=1
|
||||
Node 259 cpu_est_2_ Reg ; S6=1 S9=1
|
||||
Node 193 cpu_est_3_ Reg ; S6=1 S9=1
|
||||
Node 229 inst_AS_000_INT Reg ; S6=1 S9=1
|
||||
Node 260 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
|
||||
Node 257 RN_A_0_ Reg ; S6=1 S9=1
|
||||
Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1
|
||||
Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1
|
||||
Node 254 cpu_est_2_ Reg ; S6=1 S9=1
|
||||
Node 187 cpu_est_3_ Reg ; S6=1 S9=1
|
||||
Node 140 cpu_est_0_ Reg ; S6=1 S9=1
|
||||
Node 259 cpu_est_1_ Reg ; S6=1 S9=1
|
||||
Node 176 inst_AS_000_INT Reg ; S6=1 S9=1
|
||||
Node 239 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
|
||||
Node 209 inst_AS_030_D0 Reg ; S6=1 S9=1
|
||||
Node 152 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
|
||||
Node 169 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
|
||||
Node 205 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
|
||||
Node 134 inst_AS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 145 inst_DS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 223 CYCLE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 221 CYCLE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 248 SIZE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 265 SIZE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 109 inst_VPA_D Reg ; S6=1 S9=1
|
||||
Node 230 inst_DTACK_D0 Reg ; S6=1 S9=1
|
||||
Node 163 inst_RESET_OUT Reg ; S6=1 S9=1
|
||||
Node 163 inst_AS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 221 inst_DS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 248 CYCLE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 253 CYCLE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 152 SIZE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 260 SIZE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 223 inst_VPA_D Reg ; S6=1 S9=1
|
||||
Node 277 CLK_000_D_1_ Reg ; S6=1 S9=1
|
||||
Node 187 CLK_000_D_0_ Reg ; S6=1 S9=1
|
||||
Node 224 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
|
||||
Node 241 inst_CLK_OUT_PRE_25 Reg ; S6=1 S9=1
|
||||
Node 235 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
|
||||
Node 146 IPL_D0_0_ Reg ; S6=1 S9=1
|
||||
Node 211 IPL_D0_1_ Reg ; S6=1 S9=1
|
||||
Node 188 IPL_D0_2_ Reg ; S6=1 S9=1
|
||||
Node 254 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
|
||||
Node 239 inst_LDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 233 inst_DS_000_ENABLE Reg ; S6=1 S9=1
|
||||
Node 182 inst_UDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 169 SM_AMIGA_6_ Reg ; S6=1 S9=1
|
||||
Node 227 SM_AMIGA_4_ Reg ; S6=1 S9=1
|
||||
Node 103 SM_AMIGA_1_ Reg ; S6=1 S9=1
|
||||
Node 278 inst_DTACK_D0 Reg ; S6=1 S9=1
|
||||
Node 113 inst_RESET_OUT Reg ; S6=1 S9=1
|
||||
Node 145 CLK_000_D_0_ Reg ; S6=1 S9=1
|
||||
Node 103 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
|
||||
Node 266 inst_CLK_OUT_PRE_25 Reg ; S6=1 S9=1
|
||||
Node 272 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
|
||||
Node 170 IPL_D0_0_ Reg ; S6=1 S9=1
|
||||
Node 194 IPL_D0_1_ Reg ; S6=1 S9=1
|
||||
Node 164 IPL_D0_2_ Reg ; S6=1 S9=1
|
||||
Node 217 CLK_000_D_2_ Reg ; S6=1 S9=1
|
||||
Node 233 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
|
||||
Node 227 inst_LDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 182 inst_DS_000_ENABLE Reg ; S6=1 S9=1
|
||||
Node 188 inst_UDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 134 SM_AMIGA_6_ Reg ; S6=1 S9=1
|
||||
Node 265 SM_AMIGA_4_ Reg ; S6=1 S9=1
|
||||
Node 119 SM_AMIGA_1_ Reg ; S6=1 S9=1
|
||||
Node 289 SM_AMIGA_0_ Reg ; S6=1 S9=1
|
||||
Node 158 RST_DLY_0_ Reg ; S6=1 S9=1
|
||||
Node 170 RST_DLY_1_ Reg ; S6=1 S9=1
|
||||
Node 164 RST_DLY_2_ Reg ; S6=1 S9=1
|
||||
Node 140 inst_CLK_030_H Reg ; S6=1 S9=1
|
||||
Node 119 SM_AMIGA_5_ Reg ; S6=1 S9=1
|
||||
Node 121 SM_AMIGA_3_ Reg ; S6=1 S9=1
|
||||
Node 115 SM_AMIGA_2_ Reg ; S6=1 S9=1
|
||||
Node 113 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
|
||||
Node 266 CIIN_0 Comb ; S6=1 S9=1
|
||||
Node 121 RST_DLY_0_ Reg ; S6=1 S9=1
|
||||
Node 110 RST_DLY_1_ Reg ; S6=1 S9=1
|
||||
Node 104 RST_DLY_2_ Reg ; S6=1 S9=1
|
||||
Node 158 inst_CLK_030_H Reg ; S6=1 S9=1
|
||||
Node 193 SM_AMIGA_5_ Reg ; S6=1 S9=1
|
||||
Node 115 SM_AMIGA_3_ Reg ; S6=1 S9=1
|
||||
Node 109 SM_AMIGA_2_ Reg ; S6=1 S9=1
|
||||
Node 146 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
|
||||
Node 211 CIIN_0 Comb ; S6=1 S9=1
|
||||
; Unused Pins & Nodes
|
||||
; -> None Found.
|
||||
|
|
|
|||
1006
Logic/68030_tk.prd
1006
Logic/68030_tk.prd
File diff suppressed because it is too large
Load Diff
1092
Logic/68030_tk.rpt
1092
Logic/68030_tk.rpt
File diff suppressed because it is too large
Load Diff
|
|
@ -49,7 +49,6 @@ inst_LDS_000_INT 1 1 1 1 .. .. 2 2
|
|||
inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
|
||||
inst_UDS_000_INT 1 1 1 1 .. .. 2 2
|
||||
inst_CLK_030_H 1 2 .. .. .. .. 1 1
|
||||
CIIN_0 .. .. .. .. 1 2 .. ..
|
||||
AS_030 .. .. .. .. 1 1 .. ..
|
||||
AS_000 .. .. .. .. 1 1 .. ..
|
||||
CIIN .. .. .. .. 1 1 .. ..
|
||||
|
|
@ -59,30 +58,29 @@ inst_UDS_000_INT 1 1 1 1 .. .. 2 2
|
|||
RN_RW_000 1 1 0 0 .. .. 1 1
|
||||
BG_000 1 1 0 0 .. .. 1 1
|
||||
RN_BG_000 1 1 0 0 .. .. 1 1
|
||||
A_0_ 1 1 0 0 .. .. 1 1
|
||||
RN_A_0_ 1 1 0 0 .. .. 1 1
|
||||
IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
DSACK1 1 1 0 0 .. .. 1 1
|
||||
RN_DSACK1 1 1 0 0 .. .. 1 1
|
||||
VMA 1 1 0 0 .. .. 1 1
|
||||
RN_VMA 1 1 0 0 .. .. 1 1
|
||||
RW 1 1 0 0 .. .. 1 1
|
||||
RN_RW 1 1 0 0 .. .. 1 1
|
||||
un10_ciin_i .. .. .. .. 1 1 .. ..
|
||||
cpu_est_0_ .. .. .. .. .. .. 1 1
|
||||
cpu_est_1_ .. .. 1 1 .. .. 1 1
|
||||
A_0_ 1 1 0 0 .. .. 1 1
|
||||
RN_A_0_ 1 1 0 0 .. .. 1 1
|
||||
IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
cpu_est_2_ .. .. 1 1 .. .. 1 1
|
||||
cpu_est_3_ .. .. 1 1 .. .. 1 1
|
||||
cpu_est_0_ .. .. .. .. .. .. 1 1
|
||||
cpu_est_1_ .. .. 1 1 .. .. 1 1
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. ..
|
||||
inst_AS_030_000_SYNC 1 1 1 1 .. .. 1 1
|
||||
inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1
|
||||
inst_VPA_D 1 1 .. .. .. .. 1 1
|
||||
CLK_000_D_1_ .. .. .. .. .. .. 1 1
|
||||
inst_DTACK_D0 1 1 .. .. .. .. 1 1
|
||||
inst_RESET_OUT 1 1 .. .. .. .. .. ..
|
||||
CLK_000_D_1_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_D_0_ 1 1 .. .. .. .. 1 1
|
||||
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
|
||||
inst_CLK_OUT_PRE_25 .. .. .. .. .. .. 1 1
|
||||
|
|
@ -90,6 +88,7 @@ inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1
|
|||
IPL_D0_0_ 1 1 .. .. .. .. 1 1
|
||||
IPL_D0_1_ 1 1 .. .. .. .. 1 1
|
||||
IPL_D0_2_ 1 1 .. .. .. .. 1 1
|
||||
CLK_000_D_2_ .. .. .. .. .. .. 1 1
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. ..
|
||||
SM_AMIGA_6_ 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_4_ 1 1 .. .. .. .. 1 1
|
||||
|
|
@ -101,4 +100,5 @@ inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. ..
|
|||
SM_AMIGA_5_ 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_3_ 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_2_ 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_i_7_ 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_i_7_ 1 1 .. .. .. .. 1 1
|
||||
CIIN_0 .. .. .. .. 1 1 .. ..
|
||||
1040
Logic/68030_tk.tt2
1040
Logic/68030_tk.tt2
File diff suppressed because it is too large
Load Diff
1040
Logic/68030_tk.tt3
1040
Logic/68030_tk.tt3
File diff suppressed because it is too large
Load Diff
|
|
@ -1,20 +1,20 @@
|
|||
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
|
||||
#$ DATE Thu Aug 25 22:27:51 2016
|
||||
#$ DATE Wed Sep 14 23:54:26 2016
|
||||
#$ MODULE BUS68030
|
||||
#$ PINS 61 AHIGH_30_ AHIGH_29_ SIZE_1_ AHIGH_28_ AHIGH_27_ AHIGH_31_ AHIGH_26_
|
||||
AHIGH_25_ A_DECODE_23_ AHIGH_24_ A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
|
||||
A_DECODE_19_ A_DECODE_18_ IPL_2_ A_DECODE_17_ A_DECODE_16_ FC_1_ AS_030 AS_000
|
||||
DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
|
||||
CLK_DIV_OUT IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ A_1_ DTACK AVEC E VPA RST RESET
|
||||
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030
|
||||
UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_
|
||||
CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ AHIGH_28_ FPU_CS AHIGH_27_ FPU_SENSE
|
||||
AHIGH_26_ AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ VPA
|
||||
A_DECODE_20_ A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ A_DECODE_16_
|
||||
AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH
|
||||
CIIN SIZE_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ IPL_030_0_
|
||||
CLK_EXP DSACK1 VMA RW
|
||||
#$ NODES 44 un10_ciin_i cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_
|
||||
inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0
|
||||
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
|
||||
CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_DTACK_D0
|
||||
inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25
|
||||
inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1
|
||||
VMA RW A_0_ IPL_030_1_ IPL_030_0_
|
||||
#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC
|
||||
inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_
|
||||
SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D CLK_000_D_1_ inst_DTACK_D0 inst_RESET_OUT
|
||||
CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_CLK_OUT_PRE_D
|
||||
IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_
|
||||
SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H
|
||||
SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
|
||||
|
|
@ -24,13 +24,13 @@
|
|||
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
|
||||
CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
|
||||
A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
|
||||
BGACK_030.Q un10_ciin_i VMA.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q
|
||||
cpu_est_3_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
|
||||
BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q
|
||||
inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
|
||||
inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
|
||||
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
|
||||
inst_VPA_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q
|
||||
inst_VPA_D.Q CLK_000_D_1_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_0_.Q
|
||||
inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q
|
||||
IPL_D0_1_.Q IPL_D0_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
|
||||
IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
|
||||
inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q
|
||||
SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q
|
||||
RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q
|
||||
|
|
@ -38,229 +38,220 @@
|
|||
AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
|
||||
AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN
|
||||
AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
|
||||
.ob AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE SIZE_1_ SIZE_1_.OE AHIGH_28_
|
||||
AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_31_ AHIGH_31_.OE AHIGH_26_
|
||||
AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AS_030% AS_030.OE
|
||||
AS_000% AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR
|
||||
BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS% AVEC E RESET RESET.OE
|
||||
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000%
|
||||
AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE
|
||||
SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AHIGH_29_
|
||||
AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE FPU_CS% AHIGH_27_ AHIGH_27_.OE AHIGH_26_
|
||||
AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AVEC E RESET RESET.OE
|
||||
AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH
|
||||
CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C
|
||||
RW_000.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C A_0_.D A_0_.C A_0_.OE
|
||||
IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C CLK_EXP.D CLK_EXP.C
|
||||
DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% RW.C RW.OE un10_ciin_i%
|
||||
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D.X1
|
||||
cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C inst_AS_000_INT.D%
|
||||
inst_AS_000_INT.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D%
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C
|
||||
inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D%
|
||||
inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D
|
||||
inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C
|
||||
SIZE_DMA_0_.D% SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D%
|
||||
inst_VPA_D.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C
|
||||
CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C
|
||||
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_25.D
|
||||
inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D%
|
||||
IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C
|
||||
CIIN CIIN.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C RW_000.OE BG_000.D%
|
||||
BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D% DSACK1.C
|
||||
DSACK1.OE VMA.T VMA.C RW.D% RW.C RW.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D%
|
||||
IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2
|
||||
cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D
|
||||
cpu_est_1_.C inst_AS_000_INT.D% inst_AS_000_INT.C
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.D% inst_AMIGA_BUS_ENABLE_DMA_LOW.C
|
||||
inst_AS_030_D0.D% inst_AS_030_D0.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C
|
||||
inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C inst_AS_000_DMA.D
|
||||
inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D
|
||||
CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D% SIZE_DMA_0_.C
|
||||
SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C CLK_000_D_1_.D
|
||||
CLK_000_D_1_.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_RESET_OUT.D
|
||||
inst_RESET_OUT.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D
|
||||
inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C
|
||||
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D%
|
||||
IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
|
||||
inst_LDS_000_INT.D inst_LDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C
|
||||
inst_UDS_000_INT.D% inst_UDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D
|
||||
SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C
|
||||
RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C
|
||||
RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_5_.D
|
||||
SM_AMIGA_5_.C SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 SM_AMIGA_3_.C SM_AMIGA_2_.D
|
||||
SM_AMIGA_2_.C SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 SM_AMIGA_i_7_.C CIIN_0%
|
||||
SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C
|
||||
SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 SM_AMIGA_i_7_.C CIIN_0
|
||||
.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
.p 192
|
||||
------------------------------------------------------------------------------------------------ 00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---0--------------------0-------------------1--------------------------------------------------- 01010001010101010101000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------01------------------------------------------------------ 00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---0--------------------0----------------------------------------------------------------------- 00000100000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------0-----------------------------------------0----------------- 00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------0---------------------------------------------0------------------ 00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------1-------------------1--------------------------------------------------- 00000000000000000000010001010000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------0----------------------------------------0----------------- 00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------10-------------------------------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------------------------01--------------------------------------- 00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--1--1---1------0010--1------------------------------------------------------0------------------ 00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------------------1---------------------------------------------- 00000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------1--------------------------------------------------------------------------------------- 00000000000000000000000000000001000000000000001010010101001010101001010001010010101010101010101010101010101010101010101010101010101010101010101001010101001010010
|
||||
--1--1---0------0010--1------------------------------------------------------0------------------ 00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------001----------------------------------------------------------------- 00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------110----------------------------------------------------------------- 00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------0--------------------------------------------------- 00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---0--------------------0-----------------------------------------------------01---------------- 00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------1------------------------------------------------------0---------------- 00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------0-------0--------------------------------------------------------------- 00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------1---------1------------------------------------------------------------- 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------0----------------------------1------------------------------------------ 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
1------------111-----------------0--------------------------------------------------00000000---- 00000000000000000000000000000000000000000100000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
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|
||||
------------1-----------0------------01-----------------------------1---------0-0--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------------1-----------0------------10-----------------------------1---------0-0--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------0-----1-----------0----------0-01---------------------------------------0--0-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------0-----1-----------0----------0-10---------------------------------------0--0-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------------1-----------0------------01-----------------------------1---------0--0-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------------1-----------0------------10-----------------------------1---------0--0-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------------1-----------------------------0--------------------------1-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||
------------1--------------------------------1-----------------------1-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||
------------0---------------------------------------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
-------------------------00100-----------01--0------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
-----------------------------------------110-0------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
------------1-----------------------------0--1-------------1----------0------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
-----------------------------------------11--0------------------------1----------------------0-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
------------1------------00100-----------01--0------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
------------1----------------------------110-0------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
------------1-----------------------------1----------------------------1------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
------------1--------------------------------0-------------------------1------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
------------1----------------------------11--0------------------------1----------------------0-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
------------1-----------------------------------------------------------1----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
|
||||
---1--------1--------------------0--------0---------1--------0----------0----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
|
||||
---1--------1--------------------0--------0--0------1-------------------0----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
|
||||
------------1-----------------------------0--1---------------1----------1----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -1,20 +1,20 @@
|
|||
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
|
||||
#$ DATE Thu Aug 25 22:27:51 2016
|
||||
#$ DATE Wed Sep 14 23:54:26 2016
|
||||
#$ MODULE BUS68030
|
||||
#$ PINS 61 AHIGH_30_ AHIGH_29_ SIZE_1_ AHIGH_28_ AHIGH_27_ AHIGH_31_ AHIGH_26_
|
||||
AHIGH_25_ A_DECODE_23_ AHIGH_24_ A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
|
||||
A_DECODE_19_ A_DECODE_18_ IPL_2_ A_DECODE_17_ A_DECODE_16_ FC_1_ AS_030 AS_000
|
||||
DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
|
||||
CLK_DIV_OUT IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ A_1_ DTACK AVEC E VPA RST RESET
|
||||
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030
|
||||
UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_
|
||||
CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ AHIGH_28_ FPU_CS AHIGH_27_ FPU_SENSE
|
||||
AHIGH_26_ AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ VPA
|
||||
A_DECODE_20_ A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ A_DECODE_16_
|
||||
AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH
|
||||
CIIN SIZE_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ IPL_030_0_
|
||||
CLK_EXP DSACK1 VMA RW
|
||||
#$ NODES 44 un10_ciin_i cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_
|
||||
inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0
|
||||
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
|
||||
CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_DTACK_D0
|
||||
inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25
|
||||
inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1
|
||||
VMA RW A_0_ IPL_030_1_ IPL_030_0_
|
||||
#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC
|
||||
inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_
|
||||
SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D CLK_000_D_1_ inst_DTACK_D0 inst_RESET_OUT
|
||||
CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_CLK_OUT_PRE_D
|
||||
IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_
|
||||
SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H
|
||||
SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
|
||||
|
|
@ -24,13 +24,13 @@
|
|||
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
|
||||
CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
|
||||
A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
|
||||
BGACK_030.Q un10_ciin_i VMA.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q
|
||||
cpu_est_3_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
|
||||
BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q
|
||||
inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
|
||||
inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
|
||||
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
|
||||
inst_VPA_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q
|
||||
inst_VPA_D.Q CLK_000_D_1_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_0_.Q
|
||||
inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q
|
||||
IPL_D0_1_.Q IPL_D0_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
|
||||
IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
|
||||
inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q
|
||||
SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q
|
||||
RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q
|
||||
|
|
@ -38,229 +38,220 @@
|
|||
AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
|
||||
AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN
|
||||
AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
|
||||
.ob AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE SIZE_1_ SIZE_1_.OE AHIGH_28_
|
||||
AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_31_ AHIGH_31_.OE AHIGH_26_
|
||||
AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AS_030- AS_030.OE
|
||||
AS_000- AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR
|
||||
BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS- AVEC E RESET RESET.OE
|
||||
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000-
|
||||
AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE
|
||||
SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AHIGH_29_
|
||||
AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE FPU_CS- AHIGH_27_ AHIGH_27_.OE AHIGH_26_
|
||||
AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AVEC E RESET RESET.OE
|
||||
AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH
|
||||
CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C
|
||||
RW_000.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C A_0_.D A_0_.C A_0_.OE
|
||||
IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C CLK_EXP.D CLK_EXP.C
|
||||
DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE un10_ciin_i-
|
||||
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D.X1
|
||||
cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C inst_AS_000_INT.D-
|
||||
inst_AS_000_INT.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C
|
||||
inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D-
|
||||
inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D
|
||||
inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C
|
||||
SIZE_DMA_0_.D- SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D-
|
||||
inst_VPA_D.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C
|
||||
CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C
|
||||
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_25.D
|
||||
inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D-
|
||||
IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C
|
||||
CIIN CIIN.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C RW_000.OE BG_000.D-
|
||||
BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D- DSACK1.C
|
||||
DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D-
|
||||
IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2
|
||||
cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D
|
||||
cpu_est_1_.C inst_AS_000_INT.D- inst_AS_000_INT.C
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C
|
||||
inst_AS_030_D0.D- inst_AS_030_D0.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C
|
||||
inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C inst_AS_000_DMA.D
|
||||
inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D
|
||||
CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D- SIZE_DMA_0_.C
|
||||
SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C CLK_000_D_1_.D
|
||||
CLK_000_D_1_.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D
|
||||
inst_RESET_OUT.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D
|
||||
inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C
|
||||
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D-
|
||||
IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
|
||||
inst_LDS_000_INT.D inst_LDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C
|
||||
inst_UDS_000_INT.D- inst_UDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D
|
||||
SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C
|
||||
RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C
|
||||
RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_5_.D
|
||||
SM_AMIGA_5_.C SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 SM_AMIGA_3_.C SM_AMIGA_2_.D
|
||||
SM_AMIGA_2_.C SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 SM_AMIGA_i_7_.C CIIN_0-
|
||||
SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C
|
||||
SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 SM_AMIGA_i_7_.C CIIN_0
|
||||
.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
.p 192
|
||||
------------------------------------------------------------------------------------------------ 00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---0--------------------0-------------------1--------------------------------------------------- 01010001010101010101000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------01------------------------------------------------------ 00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---0--------------------0----------------------------------------------------------------------- 00000100000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------0-----------------------------------------0----------------- 00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------0---------------------------------------------0------------------ 00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------1-------------------1--------------------------------------------------- 00000000000000000000010001010000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------0----------------------------------------0----------------- 00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------10-------------------------------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------------------------01--------------------------------------- 00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--1--1---1------0010--1------------------------------------------------------0------------------ 00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------------------1---------------------------------------------- 00000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------1--------------------------------------------------------------------------------------- 00000000000000000000000000000001000000000000001010010101001010101001010001010010101010101010101010101010101010101010101010101010101010101010101001010101001010010
|
||||
--1--1---0------0010--1------------------------------------------------------0------------------ 00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------001----------------------------------------------------------------- 00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------110----------------------------------------------------------------- 00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------0--------------------------------------------------- 00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---0--------------------0-----------------------------------------------------01---------------- 00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------1------------------------------------------------------0---------------- 00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------0-------0--------------------------------------------------------------- 00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------1---------1------------------------------------------------------------- 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------0----------------------------1------------------------------------------ 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
1------------111-----------------0--------------------------------------------------00000000---- 00000000000000000000000000000000000000000100000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------------------------------------------------------------------1 00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------10------------------------------------------------------ 00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0----------1-------11----------------------------110------------------------------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0----------1-------10----------------------------010------------------------------------------- 00000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0----------1-------01----------------------------100------------------------------------------- 00000000000000000000000000000000000000000000010000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0----------1-------00----------------------------000------------------------------------------- 00000000000000000000000000000000000000000000010000000000010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
.p 183
|
||||
---------------------------------------01------------------------------------------------------- 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---0--------------------0----------------------------------------------------------------------- 01000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------------------------------------------------------------------ 00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---0--------------------0-------------------1--------------------------------------------------- 00010100010000000001000101001010101000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------0------------------------------------------0----------------- 00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------0----------------------------------------------0------------------ 00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------1-------------------1--------------------------------------------------- 00000001000101000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------0-----------------------------------------0----------------- 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------10-------------------------------------- 00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------------------------01--------------------------------------- 00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--1--1---1------0010--1------------------------------------------------------0------------------ 00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---------------------------------------10------------------------------------------------------- 00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------------------1----------------------------------------------- 00000000000000000000100000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------1--------------------------------------------------------------------------------------- 00000000000000000000010000000000000000000000001010010101010010100100101001010101010101010101010101010101010101010101010101010101010101010101010100101010101010010
|
||||
--1--1---0------0010--1------------------------------------------------------0------------------ 00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------10-1------------------------------------------------------------------ 00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------01-0------------------------------------------------------------------ 00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------0--------------------------------------------------- 00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---0--------------------0-----------------------------------------------------01---------------- 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------1------------------------------------------------------0---------------- 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------0------0---------------------------------------------------------------- 00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------1--------1-------------------------------------------------------------- 00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------0----------------------------1------------------------------------------ 00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
1------------111----------------0---------------------------------------------------00000000---- 00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||
-----------------------------------------------------------------------------------------------1 00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0----------1-------11---------------------------110-------------------------------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0----------1-------10---------------------------010-------------------------------------------- 00000000000000000000000000000000000000000000010000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0----------1-------01---------------------------100-------------------------------------------- 00000000000000000000000000000000000000000000010000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0----------1-------00---------------------------000-------------------------------------------- 00000000000000000000000000000000000000000000010000000000000000000001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0----------1---------------------------------------------------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1--------0----------------------------1-------------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1--------1----------------------------0-------------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1-------0------------------------------1------------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1-------1------------------------------0------------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1---------------------------------------0-----------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1--------------------------------1----------------0---------1----------------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1---------------------------------0---------------0---------1----------------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1--------0---------------------------1--------------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1--------1---------------------------0--------------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1-------0-----------------------------1-------------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1-------1-----------------------------0-------------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1--------------------------------------0------------------------0------------------- 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1-----------------------------1-------------------0---------1----------------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1--------------------------------0----------------0---------1----------------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1---------------------------------------------0--00---------1----------------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1--------------------------------01-----------1--0----------1---------------------0- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---10-------1--------------------1------------1------------------------------------------------- 00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1-----------------------------0--1------------1--0----------1---------------------0- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---10-------1-------------------1------------1-------------------------------------------------- 00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----0-------1------------------------------------------------------------0---------------------- 00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------0----------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000001010000000000000000000000000000000000001010000000100000000000000000000000001000000000000000000000000000000000
|
||||
------------0----------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000001000000000001000000000000000000000100010100000001000000000000000000000000000100000000000000000000000000000000
|
||||
-----1------------------1----------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----1---------------------------------------01-------------------------------1----------------- 00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------1----------1-------------------------------1---------------------------- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------0-------------------------------------------------------1--------------- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-1----------1-------01----------------------------101------------------------------------------- 00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-1----------1-------00----------------------------001------------------------------------------- 00000000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1-------0------------------------------------------------------0-------------------- 00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1--------0----------------------------1------------------------0-------------------- 00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
-----------------------------------------------0------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000
|
||||
-----------------------------------------------01----------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000
|
||||
-----------------------------------------------10----------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
------------1-----------0-------------01----------------------------1---------0--0-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
------------------------------------------------------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------------------------------11-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000000000000
|
||||
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|
||||
------1----------------------------1--------------------------------1----------0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------1-------------------------------0----------0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1-----------0------------1----1-----------------------------------0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||
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|
||||
------------1-----------0------------1-------0--------------------------------0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1-----------0------------01---------------------------------------0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||
------------1-----------0-------------1---1-----------------------------------0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
------------------------1---------1-----1------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------0-------------------------------------------------------00-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000
|
||||
-----------01----------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
|
||||
---------------------------------------------1-------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||
----------0-1----------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000
|
||||
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|
||||
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|
||||
-------1---------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000
|
||||
----------------------------------------------0------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000
|
||||
----------------------------------------------01------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000
|
||||
----------------------------------------------10------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000
|
||||
-----------------------------------------------1------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000
|
||||
------------1--------0-------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000
|
||||
------------1-------0--------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000
|
||||
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|
||||
------------------------------------------1----------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000
|
||||
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|
||||
------------1-----------1---------1------------------0------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000
|
||||
-------------------------------------------------------1--0------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
|
||||
----------------------------------------------------------1-----------------------10--------0--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
|
||||
------------1-------------------0-----------------------1--------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000
|
||||
------------1-----------------------------0--1-------------1------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000
|
||||
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|
||||
------------1--------------------------------------------00------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000
|
||||
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|
||||
------------1-----------------------------1---------------1------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000
|
||||
------------1--------------------------------0------------1------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000
|
||||
---1--------1--------------------0--------0---------1-----0-------------0----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000
|
||||
------------1-----------------------------1----------------1------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000
|
||||
------------1--------------------------------0-------------1------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000
|
||||
------------1-----------------------------1--0-----------------------1-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000
|
||||
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|
||||
------------1-----------------------------0-----------------1----------0------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000
|
||||
------------1--------------------------------1--------------1----------0------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000
|
||||
------------1-----------------------------1------------------1---------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000
|
||||
------------1--------------------------------0---------------1---------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000
|
||||
------------1-----------------------------0---------------------1------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000
|
||||
------------1--------------------------------1------------------1------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000
|
||||
------------1-----------------------------1--0------------------0------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000
|
||||
------------1---------------------------------------------------111----------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000
|
||||
------------1-----------------------------1--0------------------1-0----------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000
|
||||
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|
||||
------------1----------------------------------------------------1------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000
|
||||
------------1-----------------------------1--0------------------11------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000
|
||||
------------1-----------------------------------------------------1----------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000
|
||||
------0-----1-----------0----------0-01---------------------------------------0-0--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------0-----1-----------0----------0-10---------------------------------------0-0--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------------1-----------0------------01-----------------------------1---------0-0--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------------1-----------0------------10-----------------------------1---------0-0--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------0-----1-----------0----------0-01---------------------------------------0--0-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------0-----1-----------0----------0-10---------------------------------------0--0-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------------1-----------0------------01-----------------------------1---------0--0-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------------1-----------0------------10-----------------------------1---------0--0-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
|
||||
------------1-----------------------------0--------------------------1-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||
------------1--------------------------------1-----------------------1-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
|
||||
------------0---------------------------------------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
-------------------------00100-----------01--0------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
-----------------------------------------110-0------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
------------1-----------------------------0--1-------------1----------0------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
-----------------------------------------11--0------------------------1----------------------0-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
------------1------------00100-----------01--0------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
------------1----------------------------110-0------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
------------1-----------------------------1----------------------------1------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
------------1--------------------------------0-------------------------1------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
------------1----------------------------11--0------------------------1----------------------0-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
------------1-----------------------------------------------------------1----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
|
||||
---1--------1--------------------0--------0---------1--------0----------0----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
|
||||
---1--------1--------------------0--------0--0------1-------------------0----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
|
||||
------------1-----------------------------0--1---------------1----------1----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ Parent = m4a5.lci;
|
|||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 8/25/16;
|
||||
TIME = 22:27:55;
|
||||
DATE = 9/14/16;
|
||||
TIME = 23:54:30;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
|
@ -142,15 +142,15 @@ layer = OFF;
|
|||
|
||||
Layer = OFF
|
||||
AS_000 = OUTPUT,42,4,-;
|
||||
BERR = OUTPUT,41,4,-;
|
||||
RW_000 = BIDIR,80,7,-;
|
||||
UDS_000 = OUTPUT,32,3,-;
|
||||
LDS_000 = OUTPUT,31,3,-;
|
||||
A_0_ = BIDIR,69,6,-;
|
||||
RW = BIDIR,71,6,-;
|
||||
AS_030 = OUTPUT,82,7,-;
|
||||
UDS_000 = OUTPUT,32,3,-;
|
||||
LDS_000 = OUTPUT,31,3,-;
|
||||
SIZE_1_ = OUTPUT,79,7,-;
|
||||
SIZE_0_ = OUTPUT,70,6,-;
|
||||
BERR = OUTPUT,41,4,-;
|
||||
AHIGH_24_ = OUTPUT,19,2,-;
|
||||
AHIGH_25_ = OUTPUT,18,2,-;
|
||||
AHIGH_26_ = OUTPUT,17,2,-;
|
||||
|
|
@ -179,57 +179,57 @@ AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
|
|||
CLK_EXP = OUTPUT,10,1,-;
|
||||
RESET = OUTPUT,3,1,-;
|
||||
RN_BGACK_030 = NODE,-1,7,-;
|
||||
inst_RESET_OUT = NODE,*,2,-;
|
||||
CLK_000_D_0_ = NODE,*,3,-;
|
||||
inst_RESET_OUT = NODE,*,0,-;
|
||||
CLK_000_D_1_ = NODE,*,7,-;
|
||||
SM_AMIGA_6_ = NODE,*,2,-;
|
||||
CLK_000_D_0_ = NODE,*,1,-;
|
||||
SM_AMIGA_6_ = NODE,*,1,-;
|
||||
cpu_est_0_ = NODE,*,1,-;
|
||||
inst_AS_030_D0 = NODE,*,4,-;
|
||||
inst_AS_000_DMA = NODE,*,2,-;
|
||||
inst_AS_030_000_SYNC = NODE,*,2,-;
|
||||
cpu_est_3_ = NODE,*,3,-;
|
||||
CYCLE_DMA_1_ = NODE,*,6,-;
|
||||
cpu_est_1_ = NODE,*,6,-;
|
||||
cpu_est_0_ = NODE,*,3,-;
|
||||
cpu_est_3_ = NODE,*,3,-;
|
||||
SM_AMIGA_i_7_ = NODE,*,1,-;
|
||||
SM_AMIGA_4_ = NODE,*,6,-;
|
||||
SIZE_DMA_0_ = NODE,*,2,-;
|
||||
CYCLE_DMA_0_ = NODE,*,6,-;
|
||||
inst_BGACK_030_INT_D = NODE,*,4,-;
|
||||
cpu_est_2_ = NODE,*,6,-;
|
||||
SM_AMIGA_i_7_ = NODE,*,0,-;
|
||||
inst_DS_000_DMA = NODE,*,1,-;
|
||||
inst_AS_000_DMA = NODE,*,1,-;
|
||||
CYCLE_DMA_1_ = NODE,*,5,-;
|
||||
inst_DS_000_DMA = NODE,*,5,-;
|
||||
inst_CLK_030_H = NODE,*,2,-;
|
||||
RN_VMA = NODE,-1,3,-;
|
||||
SM_AMIGA_5_ = NODE,*,0,-;
|
||||
SM_AMIGA_5_ = NODE,*,3,-;
|
||||
SM_AMIGA_0_ = NODE,*,7,-;
|
||||
SM_AMIGA_1_ = NODE,*,0,-;
|
||||
SM_AMIGA_4_ = NODE,*,5,-;
|
||||
inst_DS_000_ENABLE = NODE,*,5,-;
|
||||
inst_LDS_000_INT = NODE,*,5,-;
|
||||
SIZE_DMA_1_ = NODE,*,6,-;
|
||||
SIZE_DMA_0_ = NODE,*,6,-;
|
||||
CYCLE_DMA_0_ = NODE,*,5,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,6,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,6,-;
|
||||
inst_AS_000_INT = NODE,*,5,-;
|
||||
inst_CLK_OUT_PRE_D = NODE,*,5,-;
|
||||
inst_VPA_D = NODE,*,0,-;
|
||||
inst_BGACK_030_INT_D = NODE,*,4,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,5,-;
|
||||
inst_CLK_OUT_PRE_25 = NODE,*,6,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,5,-;
|
||||
inst_AS_000_INT = NODE,*,3,-;
|
||||
inst_CLK_OUT_PRE_D = NODE,*,7,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,*,0,-;
|
||||
inst_VPA_D = NODE,*,5,-;
|
||||
RN_IPL_030_0_ = NODE,-1,1,-;
|
||||
RN_IPL_030_1_ = NODE,-1,1,-;
|
||||
RN_IPL_030_2_ = NODE,-1,1,-;
|
||||
inst_CLK_030_H = NODE,*,1,-;
|
||||
RN_RW_000 = NODE,-1,7,-;
|
||||
SM_AMIGA_2_ = NODE,*,0,-;
|
||||
SM_AMIGA_3_ = NODE,*,0,-;
|
||||
RST_DLY_0_ = NODE,*,2,-;
|
||||
RN_RW_000 = NODE,-1,7,-;
|
||||
RST_DLY_0_ = NODE,*,0,-;
|
||||
RN_A_0_ = NODE,-1,6,-;
|
||||
inst_DS_000_ENABLE = NODE,*,3,-;
|
||||
RN_RW = NODE,-1,6,-;
|
||||
RN_DSACK1 = NODE,-1,7,-;
|
||||
RN_BG_000 = NODE,-1,3,-;
|
||||
RST_DLY_2_ = NODE,*,2,-;
|
||||
RST_DLY_1_ = NODE,*,2,-;
|
||||
CIIN_0 = NODE,*,4,-;
|
||||
RST_DLY_2_ = NODE,*,0,-;
|
||||
RST_DLY_1_ = NODE,*,0,-;
|
||||
inst_UDS_000_INT = NODE,*,3,-;
|
||||
inst_CLK_OUT_PRE_25 = NODE,*,5,-;
|
||||
CIIN_0 = NODE,*,6,-;
|
||||
IPL_D0_2_ = NODE,*,3,-;
|
||||
IPL_D0_1_ = NODE,*,4,-;
|
||||
IPL_D0_0_ = NODE,*,1,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,*,5,-;
|
||||
inst_DTACK_D0 = NODE,*,5,-;
|
||||
un10_ciin_i = NODE,*,4,-;
|
||||
CLK_000_D_2_ = NODE,*,4,-;
|
||||
IPL_D0_2_ = NODE,*,2,-;
|
||||
IPL_D0_1_ = NODE,*,3,-;
|
||||
IPL_D0_0_ = NODE,*,2,-;
|
||||
inst_DTACK_D0 = NODE,*,7,-;
|
||||
CLK_OSZI = INPUT,61,-,-;
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ Parent = m4a5.lci;
|
|||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 8/25/16;
|
||||
TIME = 22:27:55;
|
||||
DATE = 9/14/16;
|
||||
TIME = 23:54:30;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
|
@ -141,24 +141,10 @@ layer = OFF;
|
|||
[LOCATION ASSIGNMENT]
|
||||
|
||||
Layer = OFF;
|
||||
AHIGH_30_ = BIDIR,5, B,-;
|
||||
AHIGH_29_ = BIDIR,6, B,-;
|
||||
SIZE_1_ = BIDIR,79, H,-;
|
||||
AHIGH_28_ = BIDIR,15, C,-;
|
||||
AHIGH_27_ = BIDIR,16, C,-;
|
||||
AHIGH_31_ = BIDIR,4, B,-;
|
||||
AHIGH_26_ = BIDIR,17, C,-;
|
||||
AHIGH_25_ = BIDIR,18, C,-;
|
||||
A_DECODE_23_ = INPUT,85, H,-;
|
||||
AHIGH_24_ = BIDIR,19, C,-;
|
||||
A_DECODE_22_ = INPUT,84, H,-;
|
||||
A_DECODE_21_ = INPUT,94, A,-;
|
||||
A_DECODE_20_ = INPUT,93, A,-;
|
||||
A_DECODE_19_ = INPUT,97, A,-;
|
||||
A_DECODE_18_ = INPUT,95, A,-;
|
||||
IPL_2_ = INPUT,68, G,-;
|
||||
A_DECODE_17_ = INPUT,59, F,-;
|
||||
A_DECODE_16_ = INPUT,96, A,-;
|
||||
FC_1_ = INPUT,58, F,-;
|
||||
AS_030 = BIDIR,82, H,-;
|
||||
AS_000 = BIDIR,42, E,-;
|
||||
|
|
@ -171,78 +157,92 @@ BG_030 = INPUT,21, C,-;
|
|||
BGACK_000 = INPUT,28, D,-;
|
||||
CLK_030 = INPUT,64,-,-;
|
||||
CLK_000 = INPUT,11,-,-;
|
||||
SIZE_0_ = BIDIR,70, G,-;
|
||||
CLK_OSZI = INPUT,61,-,-;
|
||||
AHIGH_30_ = BIDIR,5, B,-;
|
||||
CLK_DIV_OUT = OUTPUT,65, G,-;
|
||||
IPL_1_ = INPUT,56, F,-;
|
||||
AHIGH_29_ = BIDIR,6, B,-;
|
||||
AHIGH_28_ = BIDIR,15, C,-;
|
||||
FPU_CS = OUTPUT,78, H,-;
|
||||
IPL_0_ = INPUT,67, G,-;
|
||||
AHIGH_27_ = BIDIR,16, C,-;
|
||||
FPU_SENSE = INPUT,91, A,-;
|
||||
FC_0_ = INPUT,57, F,-;
|
||||
A_1_ = INPUT,60, F,-;
|
||||
AHIGH_26_ = BIDIR,17, C,-;
|
||||
AHIGH_25_ = BIDIR,18, C,-;
|
||||
DTACK = INPUT,30, D,-;
|
||||
AHIGH_24_ = BIDIR,19, C,-;
|
||||
AVEC = OUTPUT,92, A,-;
|
||||
A_DECODE_22_ = INPUT,84, H,-;
|
||||
E = OUTPUT,66, G,-;
|
||||
A_DECODE_21_ = INPUT,94, A,-;
|
||||
VPA = INPUT,36,-,-;
|
||||
A_DECODE_20_ = INPUT,93, A,-;
|
||||
A_DECODE_19_ = INPUT,97, A,-;
|
||||
RST = INPUT,86,-,-;
|
||||
A_DECODE_18_ = INPUT,95, A,-;
|
||||
RESET = OUTPUT,3, B,-;
|
||||
A_DECODE_17_ = INPUT,59, F,-;
|
||||
A_DECODE_16_ = INPUT,96, A,-;
|
||||
AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
|
||||
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
|
||||
CIIN = OUTPUT,47, E,-;
|
||||
SIZE_0_ = BIDIR,70, G,-;
|
||||
IPL_1_ = INPUT,56, F,-;
|
||||
IPL_0_ = INPUT,67, G,-;
|
||||
FC_0_ = INPUT,57, F,-;
|
||||
A_1_ = INPUT,60, F,-;
|
||||
IPL_030_2_ = OUTPUT,9, B,-;
|
||||
RW_000 = BIDIR,80, H,-;
|
||||
BG_000 = OUTPUT,29, D,-;
|
||||
BGACK_030 = OUTPUT,83, H,-;
|
||||
A_0_ = BIDIR,69, G,-;
|
||||
IPL_030_1_ = OUTPUT,7, B,-;
|
||||
IPL_030_0_ = OUTPUT,8, B,-;
|
||||
CLK_EXP = OUTPUT,10, B,-;
|
||||
DSACK1 = OUTPUT,81, H,-;
|
||||
VMA = OUTPUT,35, D,-;
|
||||
RW = BIDIR,71, G,-;
|
||||
un10_ciin_i = NODE,13, E,-;
|
||||
cpu_est_0_ = NODE,2, D,-;
|
||||
cpu_est_1_ = NODE,5, G,-;
|
||||
cpu_est_2_ = NODE,9, G,-;
|
||||
cpu_est_3_ = NODE,13, D,-;
|
||||
inst_AS_000_INT = NODE,5, F,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,10, G,-;
|
||||
A_0_ = BIDIR,69, G,-;
|
||||
IPL_030_1_ = OUTPUT,7, B,-;
|
||||
IPL_030_0_ = OUTPUT,8, B,-;
|
||||
cpu_est_2_ = NODE,6, G,-;
|
||||
cpu_est_3_ = NODE,9, D,-;
|
||||
cpu_est_0_ = NODE,10, B,-;
|
||||
cpu_est_1_ = NODE,9, G,-;
|
||||
inst_AS_000_INT = NODE,2, D,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,12, F,-;
|
||||
inst_AS_030_D0 = NODE,8, E,-;
|
||||
inst_AS_030_000_SYNC = NODE,2, C,-;
|
||||
inst_AS_030_000_SYNC = NODE,13, C,-;
|
||||
inst_BGACK_030_INT_D = NODE,5, E,-;
|
||||
inst_AS_000_DMA = NODE,6, B,-;
|
||||
inst_DS_000_DMA = NODE,13, B,-;
|
||||
CYCLE_DMA_0_ = NODE,1, F,-;
|
||||
CYCLE_DMA_1_ = NODE,0, F,-;
|
||||
SIZE_DMA_0_ = NODE,2, G,-;
|
||||
SIZE_DMA_1_ = NODE,13, G,-;
|
||||
inst_VPA_D = NODE,5, A,-;
|
||||
inst_DTACK_D0 = NODE,6, F,-;
|
||||
inst_RESET_OUT = NODE,9, C,-;
|
||||
inst_AS_000_DMA = NODE,9, C,-;
|
||||
inst_DS_000_DMA = NODE,0, F,-;
|
||||
CYCLE_DMA_0_ = NODE,2, G,-;
|
||||
CYCLE_DMA_1_ = NODE,5, G,-;
|
||||
SIZE_DMA_0_ = NODE,2, C,-;
|
||||
SIZE_DMA_1_ = NODE,10, G,-;
|
||||
inst_VPA_D = NODE,1, F,-;
|
||||
CLK_000_D_1_ = NODE,5, H,-;
|
||||
CLK_000_D_0_ = NODE,9, D,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,2, F,-;
|
||||
inst_CLK_OUT_PRE_25 = NODE,13, F,-;
|
||||
inst_CLK_OUT_PRE_D = NODE,9, F,-;
|
||||
IPL_D0_0_ = NODE,14, B,-;
|
||||
IPL_D0_1_ = NODE,9, E,-;
|
||||
IPL_D0_2_ = NODE,10, D,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,6, G,-;
|
||||
inst_LDS_000_INT = NODE,12, F,-;
|
||||
inst_DS_000_ENABLE = NODE,8, F,-;
|
||||
inst_UDS_000_INT = NODE,6, D,-;
|
||||
SM_AMIGA_6_ = NODE,13, C,-;
|
||||
SM_AMIGA_4_ = NODE,4, F,-;
|
||||
SM_AMIGA_1_ = NODE,1, A,-;
|
||||
inst_DTACK_D0 = NODE,6, H,-;
|
||||
inst_RESET_OUT = NODE,8, A,-;
|
||||
CLK_000_D_0_ = NODE,13, B,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,1, A,-;
|
||||
inst_CLK_OUT_PRE_25 = NODE,14, G,-;
|
||||
inst_CLK_OUT_PRE_D = NODE,2, H,-;
|
||||
IPL_D0_0_ = NODE,14, C,-;
|
||||
IPL_D0_1_ = NODE,14, D,-;
|
||||
IPL_D0_2_ = NODE,10, C,-;
|
||||
CLK_000_D_2_ = NODE,13, E,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,8, F,-;
|
||||
inst_LDS_000_INT = NODE,4, F,-;
|
||||
inst_DS_000_ENABLE = NODE,6, D,-;
|
||||
inst_UDS_000_INT = NODE,10, D,-;
|
||||
SM_AMIGA_6_ = NODE,6, B,-;
|
||||
SM_AMIGA_4_ = NODE,13, G,-;
|
||||
SM_AMIGA_1_ = NODE,12, A,-;
|
||||
SM_AMIGA_0_ = NODE,13, H,-;
|
||||
RST_DLY_0_ = NODE,6, C,-;
|
||||
RST_DLY_1_ = NODE,14, C,-;
|
||||
RST_DLY_2_ = NODE,10, C,-;
|
||||
inst_CLK_030_H = NODE,10, B,-;
|
||||
SM_AMIGA_5_ = NODE,12, A,-;
|
||||
SM_AMIGA_3_ = NODE,13, A,-;
|
||||
SM_AMIGA_2_ = NODE,9, A,-;
|
||||
SM_AMIGA_i_7_ = NODE,8, A,-;
|
||||
CIIN_0 = NODE,14, G,-;
|
||||
RST_DLY_0_ = NODE,13, A,-;
|
||||
RST_DLY_1_ = NODE,6, A,-;
|
||||
RST_DLY_2_ = NODE,2, A,-;
|
||||
inst_CLK_030_H = NODE,6, C,-;
|
||||
SM_AMIGA_5_ = NODE,13, D,-;
|
||||
SM_AMIGA_3_ = NODE,9, A,-;
|
||||
SM_AMIGA_2_ = NODE,5, A,-;
|
||||
SM_AMIGA_i_7_ = NODE,14, B,-;
|
||||
CIIN_0 = NODE,9, E,-;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Signal Name Cross Reference File
|
|||
|
||||
ispLEVER Classic 2.0.00.17.20.15
|
||||
|
||||
Design '68030_tk' created Thu Aug 25 22:27:51 2016
|
||||
Design '68030_tk' created Wed Sep 14 23:54:26 2016
|
||||
|
||||
|
||||
LEGEND: '>' Functional Block Port Separator
|
||||
|
|
|
|||
2615
Logic/BUS68030.bl0
2615
Logic/BUS68030.bl0
File diff suppressed because it is too large
Load Diff
2765
Logic/BUS68030.bl1
2765
Logic/BUS68030.bl1
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,8 @@
|
|||
STYFILENAME: 68030_tk.sty
|
||||
PROJECT: BUS68030
|
||||
WORKING_PATH: "c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic"
|
||||
MODULE: BUS68030
|
||||
VHDL_FILE_LIST: 68030-68000-bus.vhd
|
||||
OUTPUT_FILE_NAME: BUS68030
|
||||
SUFFIX_NAME: edi
|
||||
PART: M4A5-128/64-10VC
|
||||
4698
Logic/BUS68030.edi
4698
Logic/BUS68030.edi
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,6 @@
|
|||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
||||
#-- Written on Thu Aug 25 22:27:39 2016
|
||||
#-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic\BUS68030.prj
|
||||
#-- Written on Wed Sep 14 23:54:13 2016
|
||||
|
||||
|
||||
#device options
|
||||
|
|
|
|||
5206
Logic/BUS68030.srm
5206
Logic/BUS68030.srm
File diff suppressed because it is too large
Load Diff
|
|
@ -6,29 +6,29 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Thu Aug 25 22:27:46 2016
|
||||
#Wed Sep 14 23:54:20 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
@N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N:"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
|
||||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
|
||||
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
|
||||
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
|
||||
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
|
||||
Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 2 of CLK_000_D_3(12 downto 0) -- not in use ...
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
|
||||
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 3 of CLK_000_D_3(12 downto 0) -- not in use ...
|
||||
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -39,24 +39,24 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
|
||||
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
|
||||
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
|
||||
@W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Aug 25 22:27:46 2016
|
||||
# Wed Sep 14 23:54:21 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Aug 25 22:27:48 2016
|
||||
# Wed Sep 14 23:54:22 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -65,7 +65,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
|
|||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
@N:"c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
|
|
@ -80,13 +80,13 @@ original code -> new code
|
|||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 53 uses
|
||||
DFF 54 uses
|
||||
BI_DIR 18 uses
|
||||
BUFTH 4 uses
|
||||
IBUF 38 uses
|
||||
OBUF 15 uses
|
||||
AND2 286 uses
|
||||
INV 258 uses
|
||||
AND2 269 uses
|
||||
INV 239 uses
|
||||
OR2 25 uses
|
||||
XOR2 6 uses
|
||||
|
||||
|
|
@ -98,6 +98,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Aug 25 22:27:48 2016
|
||||
# Wed Sep 14 23:54:22 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -18,9 +18,9 @@
|
|||
<BScanLen>1</BScanLen>
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
|
||||
<FileTime>08/19/16 00:39:40</FileTime>
|
||||
<JedecChecksum>0x4245</JedecChecksum>
|
||||
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk-50Mhz-New.jed</File>
|
||||
<FileTime>08/30/16 22:39:22</FileTime>
|
||||
<JedecChecksum>0xE8C5</JedecChecksum>
|
||||
<Operation>Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -6,29 +6,29 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Thu Aug 25 22:27:46 2016
|
||||
#Wed Sep 14 23:54:20 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
@N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N:"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
|
||||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
|
||||
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
|
||||
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
|
||||
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
|
||||
Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 2 of CLK_000_D_3(12 downto 0) -- not in use ...
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
|
||||
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 3 of CLK_000_D_3(12 downto 0) -- not in use ...
|
||||
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -39,23 +39,23 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
|
||||
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
|
||||
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
|
||||
@W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Aug 25 22:27:46 2016
|
||||
# Wed Sep 14 23:54:21 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Aug 25 22:27:48 2016
|
||||
# Wed Sep 14 23:54:22 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -13,12 +13,13 @@ SF<1kCsOR"b= H:\# bpe_ )B#DN#.HO_#j\$LMbN\#CD\HLP\E8MCkls3HOP"E8R"N=dD"R=E"P8RD"
|
|||
/>S1S<FOksC=Rb"\ :Hp#b )e _NBD#O#H.\_j#b$MLCN#\LDH\8PE\skl_bONHPl3ER8"Nc=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
|
||||
SF<1kCsOR"b= H:\# bpe_ )B#DN#.HO_#j\$LMbN\#CD\HLP\E8N0sHEE3P8N"R=""6R"D=PDE8"DROH=#0""-4RHbD#"0=-/4">S
|
||||
S<k1FsROCb =":#\Hbep B)_D#N#H_O.j$\#MNbL#DC\HPL\Ek8\Mo#HM3C8P"E8R"N=nD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||
/>S1S<FOksC=Rb"\B:ks#C#N\l0\xC8kFOl0CM#H\o0LEk\jnUd j0\oDFHnO\Ujjd-jnUjLj-kP#3ER8"N(=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
|
||||
<F/1kCsO#
|
||||
/>S1S<FOksC=Rb"\B:ks#C#N\l0\xCNolHNN\EsN8IsNCEO\ #ndUjj -0\0oHE\kLDHFoOU\nj-djnjUjjk-L#E3P8N"R=""(R"D=PDE8"DROH=#0""-4RHbD#"0=-/4"><
|
||||
S/k1Fs#OC>S
|
||||
|
||||
<-!-R8vFkRDCs0FFR>--
|
||||
)S<FRF0MI="F3s Anz1Ujjd3ELCNFPHs"ND/
|
||||
>
|
||||
S-<!-FRv8CkDRFsF0-R-><
|
||||
S)0FFR"M=I Fs31AzndUjjC3LEHNPFDsN"
|
||||
/>
|
||||
|
||||
<
|
||||
S!R--vkF8D7CRCMVHHF0HM-R-><
|
||||
S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S>
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version I-2014.03LC
|
||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
||||
#-- Written on Thu Aug 25 22:27:46 2016
|
||||
#-- Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\run_options.txt
|
||||
#-- Written on Wed Sep 14 23:54:20 2016
|
||||
|
||||
|
||||
#project files
|
||||
|
|
@ -52,5 +52,5 @@ set_option -write_apr_constraint 1
|
|||
project -result_file "./BUS68030.edi"
|
||||
|
||||
#set log file
|
||||
set_option log_file "C:/users/matze/documents/github/68030tk/logic/bus68030.srf"
|
||||
set_option log_file "C:/users/matze/amiga/hardwarehacks/68030-tk/github/logic/bus68030.srf"
|
||||
impl -active "logic"
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version I-2014.03LC
|
||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\scratchproject.prs
|
||||
#-- Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\scratchproject.prs
|
||||
|
||||
#project files
|
||||
add_file -vhdl -lib work "C:/users/matze/documents/github/68030tk/logic/68030-68000-bus.vhd"
|
||||
add_file -vhdl -lib work "C:/users/matze/amiga/hardwarehacks/68030-tk/github/logic/68030-68000-bus.vhd"
|
||||
|
||||
|
||||
|
||||
#implementation: "logic"
|
||||
impl -add C:\users\matze\documents\github\68030tk\logic -type fpga
|
||||
impl -add C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic -type fpga
|
||||
|
||||
#device options
|
||||
set_option -technology mach
|
||||
|
|
@ -47,8 +47,8 @@ set_option -auto_infer_blackbox 0
|
|||
set_option -write_apr_constraint 1
|
||||
|
||||
#set result format/file last
|
||||
project -result_file "C:/users/matze/documents/github/68030tk/logic/BUS68030.edi"
|
||||
project -result_file "C:/users/matze/amiga/hardwarehacks/68030-tk/github/logic/BUS68030.edi"
|
||||
|
||||
#set log file
|
||||
set_option log_file "C:/users/matze/documents/github/68030tk/logic/bus68030.srf"
|
||||
set_option log_file "C:/users/matze/amiga/hardwarehacks/68030-tk/github/logic/bus68030.srf"
|
||||
impl -active "logic"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
ABEL5DEV=E:\ispLEVER_Classic2_0\ispcpld\lib5
|
||||
DIOEDA_ABEL5DEV=E:\ispLEVER_Classic2_0\ispcpld\lib5
|
||||
DIOEDA_ActiveHDL=E:\ispLEVER_Classic2_0\active-hdl\BIN
|
||||
DIOEDA_ActiveHDLPath=E:\ispLEVER_Classic2_0\active-hdl\BIN
|
||||
DIOEDA_AppNotes=E:\ispLEVER_Classic2_0\ispcpld\bin
|
||||
DIOEDA_Bin=E:\ispLEVER_Classic2_0\ispcpld\bin
|
||||
DIOEDA_Config=E:\ispLEVER_Classic2_0\ispcpld\config
|
||||
DIOEDA_CONTEXT=ispLEVER CLASSIC
|
||||
DIOEDA_DSPPATH=E:\ispLEVER_Classic2_0\ispLeverDSP
|
||||
DIOEDA_EPICPATH=E:\ispLEVER_Classic2_0\ispfpga\bin\nt
|
||||
DIOEDA_Examples=E:\ispLEVER_Classic2_0\examples
|
||||
DIOEDA_FPGABinPath=E:\ispLEVER_Classic2_0\ispfpga\bin\nt
|
||||
DIOEDA_FPGAPath=E:\ispLEVER_Classic2_0\ispfpga
|
||||
DIOEDA_HDLExplorer=E:\ispLEVER_Classic2_0\hdle\win32
|
||||
DIOEDA_INI=C:\lsc_env
|
||||
DIOEDA_ispVM=E:\ispLEVER_Classic2_0\ispvmsystem
|
||||
DIOEDA_ispVMSystem=E:\ispLEVER_Classic2_0\ispvmsystem
|
||||
DIOEDA_License=E:\ispLEVER_Classic2_0\license
|
||||
DIOEDA_LSEPath=E:\ispLEVER_Classic2_0\lse
|
||||
DIOEDA_MachPath=E:\ispLEVER_Classic2_0\ispcpld\bin
|
||||
DIOEDA_Manuals=E:\ispLEVER_Classic2_0\ispcpld\manuals
|
||||
DIOEDA_ModelSim=E:\ispLEVER_Classic2_0\modelsim\win32loem
|
||||
DIOEDA_ModelsimPath=E:\ispLEVER_Classic2_0\modelsim\win32loem
|
||||
DIOEDA_PDSPath=E:\ispLEVER_Classic2_0\ispcomp
|
||||
DIOEDA_Precision=C:\isptools\precision
|
||||
DIOEDA_PrecisionPath=C:\isptools\precision
|
||||
DIOEDA_ProductName=ispLEVER
|
||||
DIOEDA_ProductPrefix=SYN
|
||||
DIOEDA_ProductTitle=ispLEVER
|
||||
DIOEDA_ProductType=2.0.00.17.20.15_LS_HDL_BASE_PC_N
|
||||
DIOEDA_ProductVersion=2.0.00.17
|
||||
DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 2.0
|
||||
DIOEDA_Root=E:\ispLEVER_Classic2_0\ispcpld
|
||||
DIOEDA_Spectrum=C:\isptools\spectrum
|
||||
DIOEDA_SpectrumPath=C:\isptools\spectrum
|
||||
DIOEDA_Synplify=E:\ispLEVER_Classic2_0\synpbase
|
||||
DIOEDA_SynplifyPath=E:\ispLEVER_Classic2_0\synpbase
|
||||
DIOEDA_Synthesis=E:\ispLEVER_Classic2_0\lse\bin\nt
|
||||
DIOEDA_Tutorial=E:\ispLEVER_Classic2_0\ispcpld\tutorial
|
||||
DIOPRODUCT=ispLEVER
|
||||
PATH=E:\ispLEVER_Classic2_0\ispcpld\bin
|
||||
|
|
@ -1 +1 @@
|
|||
project -load c:/users/matze/documents/github/68030tk/logic/BUS68030.prj
|
||||
project -load c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic/BUS68030.prj
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Aug 25 22:27:48 2016
|
||||
# Wed Sep 14 23:54:22 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
|
|||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
@N:"c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
|
|
@ -17,13 +17,13 @@ original code -> new code
|
|||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 53 uses
|
||||
DFF 54 uses
|
||||
BI_DIR 18 uses
|
||||
BUFTH 4 uses
|
||||
IBUF 38 uses
|
||||
OBUF 15 uses
|
||||
AND2 286 uses
|
||||
INV 258 uses
|
||||
AND2 269 uses
|
||||
INV 239 uses
|
||||
OR2 25 uses
|
||||
XOR2 6 uses
|
||||
|
||||
|
|
@ -35,6 +35,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Aug 25 22:27:48 2016
|
||||
# Wed Sep 14 23:54:22 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
@N|Running in 64-bit mode
|
||||
@N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
|
||||
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
|
||||
@N:"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
|
||||
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
|
||||
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
|
||||
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
|
||||
<job_run_status name="compiler">
|
||||
<report_link name="Detailed report">
|
||||
<data>C:\users\matze\documents\github\68030tk\logic\BUS68030.srr</data>
|
||||
<data>C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\BUS68030.srr</data>
|
||||
<title>Start of Compile</title>
|
||||
</report_link>
|
||||
<job_status>
|
||||
|
|
@ -15,15 +15,15 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<job_info>
|
||||
<info name="Notes">
|
||||
<data>8</data>
|
||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
||||
<report_link name="more"><data>C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>8</data>
|
||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
||||
<report_link name="more"><data>C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Errors">
|
||||
<data>0</data>
|
||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_errors.txt</data></report_link>
|
||||
<report_link name="more"><data>C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synlog\report\BUS68030_compiler_errors.txt</data></report_link>
|
||||
</info>
|
||||
<info name="CPU Time">
|
||||
<data>-</data>
|
||||
|
|
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<data>-</data>
|
||||
</info>
|
||||
<info name="Date &Time">
|
||||
<data type="timestamp">1472156866</data>
|
||||
<data type="timestamp">1473890061</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
@ -1,9 +1,9 @@
|
|||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 2 of CLK_000_D_3(12 downto 0) -- not in use ...
|
||||
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
|
||||
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
|
||||
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 3 of CLK_000_D_3(12 downto 0) -- not in use ...
|
||||
@W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
*******************************************************************************************-->
|
||||
<job_run_status name="Mapper">
|
||||
<report_link name="Detailed report">
|
||||
<data>C:\users\matze\documents\github\68030tk\logic\synlog\BUS68030_fpga_mapper.srr</data>
|
||||
<data>C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synlog\BUS68030_fpga_mapper.srr</data>
|
||||
<title>Synopsys CPLD Technology Mapper</title>
|
||||
</report_link>
|
||||
<job_status>
|
||||
|
|
@ -15,19 +15,19 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
<info name="Notes">
|
||||
<data>2</data>
|
||||
<report_link name="more">
|
||||
<data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_notes.txt</data>
|
||||
<data>C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synlog\report\BUS68030_fpga_mapper_notes.txt</data>
|
||||
</report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>0</data>
|
||||
<report_link name="more">
|
||||
<data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt</data>
|
||||
<data>C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt</data>
|
||||
</report_link>
|
||||
</info>
|
||||
<info name="Errors">
|
||||
<data>0</data>
|
||||
<report_link name="more">
|
||||
<data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_errors.txt</data>
|
||||
<data>C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synlog\report\BUS68030_fpga_mapper_errors.txt</data>
|
||||
</report_link>
|
||||
</info>
|
||||
<info name="CPU Time">
|
||||
|
|
@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
<data>105MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1472156868</data>
|
||||
<data type="timestamp">1473890062</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<html><body><samp><pre>
|
||||
<!@TC:1472156866>
|
||||
<!@TC:1473890060>
|
||||
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
|
||||
#install: E:\ispLEVER_Classic2_0\synpbase
|
||||
#OS: Windows 7 6.2
|
||||
|
|
@ -8,29 +8,29 @@
|
|||
#Implementation: logic
|
||||
|
||||
<a name=compilerReport1>$ Start of Compile</a>
|
||||
#Thu Aug 25 22:27:46 2016
|
||||
#Wed Sep 14 23:54:20 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1472156866> | Running in 64-bit mode
|
||||
@N: : <!@TM:1473890061> | Running in 64-bit mode
|
||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1472156866> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1472156866> | Top entity is set to BUS68030.
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1473890061> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1473890061> | Top entity is set to BUS68030.
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
|
||||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1472156866> | Synthesizing work.bus68030.behavioral
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1472156866> | Using sequential encoding for type sm_e
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1472156866> | Using sequential encoding for type sm_68000
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:128:7:128:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(128)</a><!@TM:1472156866> | Signal clk_out_pre is undriven </font>
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1473890061> | Synthesizing work.bus68030.behavioral
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1473890061> | Using sequential encoding for type sm_e
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1473890061> | Using sequential encoding for type sm_68000
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:128:7:128:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(128)</a><!@TM:1473890061> | Signal clk_out_pre is undriven </font>
|
||||
Post processing for work.bus68030.behavioral
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Pruning register DS_030_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Pruning register nEXP_SPACE_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Pruning register BGACK_030_INT_PRE_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1472156866> | Pruning register CLK_OUT_EXP_INT_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:154:2:154:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(154)</a><!@TM:1472156866> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Pruning bits 12 to 2 of CLK_000_D_3(12 downto 0) -- not in use ... </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Trying to extract state machine for register SM_AMIGA
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1473890061> | Pruning register DS_030_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1473890061> | Pruning register nEXP_SPACE_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1473890061> | Pruning register BGACK_030_INT_PRE_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1473890061> | Pruning register CLK_OUT_EXP_INT_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:154:2:154:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(154)</a><!@TM:1473890061> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1473890061> | Pruning bits 12 to 3 of CLK_000_D_3(12 downto 0) -- not in use ... </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1473890061> | Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -41,24 +41,24 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Trying to extract state machine for register cpu_est
|
||||
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1472156866> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1473890061> | Trying to extract state machine for register cpu_est
|
||||
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1473890061> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Aug 25 22:27:46 2016
|
||||
# Wed Sep 14 23:54:21 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1472156868> | Running in 64-bit mode
|
||||
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
@N: : <!@TM:1473890062> | Running in 64-bit mode
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Aug 25 22:27:48 2016
|
||||
# Wed Sep 14 23:54:22 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -66,8 +66,8 @@ Map & Optimize Report
|
|||
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
|
||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1472156868> | Running in 64-bit mode.
|
||||
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N::@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156868> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1473890062> | Running in 64-bit mode.
|
||||
@N: : <a href="c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N::@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1473890062> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
|
|
@ -82,25 +82,25 @@ original code -> new code
|
|||
<a name=resourceUsage3>Resource Usage Report</a>
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 53 uses
|
||||
DFF 54 uses
|
||||
BI_DIR 18 uses
|
||||
BUFTH 4 uses
|
||||
IBUF 38 uses
|
||||
OBUF 15 uses
|
||||
AND2 286 uses
|
||||
INV 258 uses
|
||||
AND2 269 uses
|
||||
INV 239 uses
|
||||
OR2 25 uses
|
||||
XOR2 6 uses
|
||||
|
||||
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1472156868> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1473890062> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
I-2014.03LC
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Aug 25 22:27:48 2016
|
||||
# Wed Sep 14 23:54:22 2016
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
|
|||
|
|
@ -12,11 +12,11 @@
|
|||
|
||||
<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b>
|
||||
<ul rel="open">
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li>
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
|
||||
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\BUS68030_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li>
|
||||
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
|
||||
<ul rel="open" >
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (22:27 25-Aug)</a>
|
||||
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
|
||||
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\stdout.log" target="srrFrame" title="">Session Log (23:54 14-Sep)</a>
|
||||
<ul ></ul></li> </ul>
|
||||
</li>
|
||||
</ul>
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
<!--
|
||||
Synopsys, Inc.
|
||||
Version I-2014.03LC
|
||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||
Written on Thu Aug 25 22:27:46 2016
|
||||
Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\run_option.xml
|
||||
Written on Wed Sep 14 23:54:20 2016
|
||||
|
||||
|
||||
-->
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
<td>-</td>
|
||||
<td>0m:01s</td>
|
||||
<td>-</td>
|
||||
<td><font size="-1">25.08.2016</font><br/><font size="-2">22:27:46</font></td>
|
||||
<td><font size="-1">14.09.2016</font><br/><font size="-2">23:54:21</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
|
|
@ -49,12 +49,12 @@
|
|||
<td>0m:00s</td>
|
||||
<td>0m:00s</td>
|
||||
<td>105MB</td>
|
||||
<td><font size="-1">25.08.2016</font><br/><font size="-2">22:27:48</font></td>
|
||||
<td><font size="-1">14.09.2016</font><br/><font size="-2">23:54:22</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle">Multi-srs Generator</td>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">25.08.2016</font><br/><font size="-2">22:27:48</font></td> </tbody>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">14.09.2016</font><br/><font size="-2">23:54:22</font></td> </tbody>
|
||||
</table>
|
||||
</td></tr></table></body>
|
||||
</html>
|
||||
|
|
@ -9,8 +9,8 @@
|
|||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1472156857
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1473890048
|
||||
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
0 -1
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@
|
|||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1472156857
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1473890048
|
||||
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
0 -1
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,15 +1,15 @@
|
|||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
|
||||
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
|
||||
@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
|
||||
@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
|
||||
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
|
||||
Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 2 of CLK_000_D_3(12 downto 0) -- not in use ...
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
|
||||
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
|
||||
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 3 of CLK_000_D_3(12 downto 0) -- not in use ...
|
||||
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -20,5 +20,5 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
|
||||
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
|
||||
@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
|
||||
@W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
|
||||
|
|
|
|||
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Reference in New Issue