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Cleaned up and the preempting DSACK is unneccessary?!?

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This commit is contained in:
MHeinrichs 2016-08-25 22:30:49 +02:00
parent 00726c0582
commit cb8dfae058
52 changed files with 17636 additions and 29290 deletions
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73
Logic/68030-68000-bus.vhd
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@ -62,7 +62,7 @@ end BUS68030;
architecture Behavioral of BUS68030 is
-- values are determined empirically
constant DS_SAMPLE : integer := 10; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 25MHZ
constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 25MHZ
--constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 50MHZ
@ -148,7 +148,7 @@ begin
--no ansynchronious reset! the reset is sampled synchroniously
--this mut be because of the e-clock: The E-Clock has to run CONSTANTLY
--or the Amiga will fail to boot from a reset.
--However a compilation with no resets on thEe-Clock and resets on other signals does not work, either!
--However a compilation with no resets on the E-Clock and resets on other signals does not work, either!
pos_clk: process(CLK_OSZI)
begin
if(rising_edge(CLK_OSZI)) then
@ -188,20 +188,6 @@ begin
end case;
end if;
--this is a statemachine to propagate an internal reset to the amiga
--if( (RESET = '0' and RESET_OUT = '1') or RST_DLY_AMIGA /= "11111111") then --reset condition from the tk-board
-- if(RST_DLY_AMIGA = "11111111") then --start of reset
-- RESET_OUT_AMIGA <= '1';
-- RST_DLY_AMIGA <= "00000000";
-- else
-- RST_DLY_AMIGA <= RST_DLY_AMIGA+1;
-- end if;
--else
-- RST_DLY_AMIGA <= "11111111";
-- RESET_OUT_AMIGA <= '0';
--end if;
--the statemachine
if(RST = '0' ) then
VPA_D <= '1';
@ -376,10 +362,10 @@ begin
SM_AMIGA<=DATA_FETCH_P;
end if;
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
if( (CLK_000_D(DS_SAMPLE-2)='0' AND CLK_000_D((DS_SAMPLE-1))='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
(CLK_000_D(DS_SAMPLE-1)='0' AND CLK_000_D((DS_SAMPLE-0))='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
DSACK1_INT <='0';
end if;
--if( (CLK_000_D(DS_SAMPLE-2)='0' AND CLK_000_D((DS_SAMPLE-1))='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
-- (CLK_000_D(DS_SAMPLE-1)='0' AND CLK_000_D((DS_SAMPLE-0))='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
-- DSACK1_INT <='0';
--end if;
if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
SM_AMIGA<=END_CYCLE_N;
DSACK1_INT <='0';
@ -500,19 +486,17 @@ begin
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else
'0' when DS_000_DMA ='0' and AS_000 ='0' else
'1';
A(0) <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else
'0' when A0_DMA ='0' else
'1';
A(0) <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' --tristate on CPU-Cycle
else A0_DMA; --drive on DMA-Cycle
A(1) <= 'Z';
AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else x"00";
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else
"10" when SIZE_DMA ="10" else
"01" when SIZE_DMA ="01" else
"00";
"10" when SIZE_DMA ="10" else
"01" when SIZE_DMA ="01" else
"00";
--rw
RW <= 'Z' when BGACK_030_INT ='1' or RESET_OUT ='0' else
'0' when RW_000_DMA ='0' else
'1';
RW <= 'Z' when BGACK_030_INT ='1' or RESET_OUT ='0' --tristate on CPU cycle
else RW_000_DMA; --drive on DMA-Cycle
BGACK_030 <= BGACK_030_INT;
@ -545,24 +529,23 @@ begin
--as and uds/lds
AS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else
'0' when AS_000_INT ='0' and AS_030 ='0' else
'1';
RW_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else
'0' when RW_000_INT ='0' else
'1';
'0' when AS_000_INT ='0' and AS_030 ='0' else
'1';
RW_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' --tristate on DMA-cycle
else RW_000_INT; -- drive on CPU cycle
UDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else -- output on cpu cycle
--'1' when DS_000_ENABLE ='0' else
'0' when UDS_000_INT ='0' and DS_000_ENABLE ='1' else -- datastrobe not ready jet
'1';
LDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else -- output on cpu cycle
--'1' when DS_000_ENABLE ='0' else
'0' when LDS_000_INT ='0' and DS_000_ENABLE ='1' else -- datastrobe not ready jet
'1';
UDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else --tristate on DMA cycle
--'1' when DS_000_ENABLE ='0' else
UDS_000_INT when DS_000_ENABLE ='1' -- output on cpu cycle
else '1'; -- datastrobe not ready jet
LDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else --tristate on DMA cycle
--'1' when DS_000_ENABLE ='0' else
LDS_000_INT when DS_000_ENABLE ='1' -- output on cpu cycle
else '1'; -- datastrobe not ready jet
--dsack
DSACK1 <= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle
'0' when DSACK1_INT ='0' else
'1';
DSACK1 <= 'Z' when nEXP_SPACE = '0' --tristate on expansionboard cycle
else DSACK1_INT; -- output on amiga cycle
end Behavioral;

3255
Logic/68030_TK.tcl
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File diff suppressed because it is too large Load Diff

2744
Logic/68030_tk.bl2
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File diff suppressed because it is too large Load Diff

662
Logic/68030_tk.bl3
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@ -1,71 +1,63 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 24 22:17:49 2016
#$ DATE Thu Aug 25 22:27:51 2016
#$ MODULE 68030_tk
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 SIZE_0_ \
# AS_000 AHIGH_30_ RW_000 AHIGH_29_ DS_030 AHIGH_28_ UDS_000 AHIGH_27_ LDS_000 AHIGH_26_ \
# nEXP_SPACE AHIGH_25_ BERR AHIGH_24_ BG_030 A_DECODE_22_ BG_000 A_DECODE_21_ BGACK_030 \
# A_DECODE_20_ BGACK_000 A_DECODE_19_ CLK_030 A_DECODE_18_ CLK_000 A_DECODE_17_ \
# CLK_OSZI A_DECODE_16_ CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST \
# RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR A_0_ AMIGA_BUS_ENABLE_LOW IPL_030_1_ \
# AMIGA_BUS_ENABLE_HIGH IPL_030_0_ CIIN IPL_1_ IPL_0_ FC_0_ A_1_
#$ NODES 62 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_3_ cpu_est_0_ cpu_est_1_ \
# cpu_est_2_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 \
# inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \
# CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT \
# inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_8_ CLK_000_D_9_ inst_DTACK_D0 \
# inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 \
# IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ \
# CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_10_ inst_AMIGA_BUS_ENABLE_DMA_HIGH \
# inst_DSACK1_INTreg inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ \
#$ PINS 61 AHIGH_30_ AHIGH_29_ SIZE_1_ AHIGH_28_ AHIGH_27_ AHIGH_31_ AHIGH_26_ \
# AHIGH_25_ A_DECODE_23_ AHIGH_24_ A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ IPL_030_2_ \
# A_DECODE_19_ A_DECODE_18_ IPL_2_ A_DECODE_17_ A_DECODE_16_ FC_1_ AS_030 AS_000 RW_000 \
# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \
# A_0_ CLK_OSZI IPL_030_1_ CLK_DIV_OUT IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE \
# FC_0_ DSACK1 A_1_ DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR \
# AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_
#$ NODES 54 inst_BGACK_030_INTreg un10_ciin_i inst_VMA_INTreg cpu_est_0_ \
# cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW \
# inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA \
# inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D \
# inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 \
# inst_CLK_OUT_PRE_25 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ \
# inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg inst_LDS_000_INT \
# inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ \
# inst_RW_000_INT inst_RW_000_DMA RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_A0_DMA \
# inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ \
# BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg
# inst_CLK_030_H SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg \
# CLK_OUT_INTreg IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg
.model bus68030
.inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \
A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \
A_DECODE_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF \
inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF \
cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF inst_AS_000_INT.BLIF \
inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
inst_BGACK_030_INTreg.BLIF un10_ciin_i.BLIF inst_VMA_INTreg.BLIF \
cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
inst_AS_000_INT.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \
inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF \
SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \
inst_CLK_OUT_PRE_D.BLIF CLK_000_D_8_.BLIF CLK_000_D_9_.BLIF inst_DTACK_D0.BLIF \
inst_RESET_OUT.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF IPL_D0_0_.BLIF \
IPL_D0_1_.BLIF IPL_D0_2_.BLIF CLK_000_D_2_.BLIF CLK_000_D_3_.BLIF \
CLK_000_D_4_.BLIF CLK_000_D_5_.BLIF CLK_000_D_6_.BLIF CLK_000_D_7_.BLIF \
CLK_000_D_10_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF \
inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_0_.BLIF \
SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_CLK_OUT_PRE_50.BLIF \
inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF \
IPL_D0_2_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF \
inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \
inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
RST_DLY_2_.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF \
SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF \
BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF \
IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \
AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \
AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
RST_DLY_2_.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF SM_AMIGA_5_.BLIF \
SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF \
CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF \
IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \
UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \
AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF \
AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF \
A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.C SM_AMIGA_6_.D \
SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C \
SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \
SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \
IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \
IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \
IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_D_4_.D CLK_000_D_4_.C \
CLK_000_D_5_.D CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D \
CLK_000_D_7_.C CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C \
CLK_000_D_10_.D CLK_000_D_10_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \
CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C RST_DLY_1_.C RST_DLY_2_.D \
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_1_.D SM_AMIGA_1_.C \
SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \
IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \
IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \
SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \
SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C \
CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.C \
cpu_est_3_.D cpu_est_3_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.D \
RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \
CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C RST_DLY_0_.D \
RST_DLY_0_.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \
inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \
CYCLE_DMA_0_.D CYCLE_DMA_0_.C inst_AS_000_DMA.D inst_AS_000_DMA.C \
inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D \
inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \
inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \
@ -76,85 +68,18 @@ inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \
inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \
inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_DMA.D inst_RW_000_DMA.C \
inst_RW_000_INT.D inst_RW_000_INT.C inst_BGACK_030_INT_D.D \
inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \
inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D \
inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ \
AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ \
AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE \
AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE \
AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE \
CIIN.OE cpu_est_2_.D.X1 cpu_est_2_.D.X2 RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 \
inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 \
SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2
.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF \
SM_AMIGA_6_.D
11010-0- 1
-1--0111 1
-1-1-111 1
-----01- 0
---01--- 0
--1---0- 0
0-----0- 0
----1-0- 0
---0--0- 0
------10 0
-0------ 0
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \
SM_AMIGA_5_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
1011-- 1
1-1-11 1
10--11 1
---00- 0
--0-0- 0
-1--0- 0
-10--- 0
---0-0 0
0----- 0
--0--0 0
-1---0 0
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF \
SM_AMIGA_5_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D
110-1- 1
1-01-1 1
11-1-1 1
---00- 0
--10-- 0
-0-0-- 0
-01--- 0
----00 0
0----- 0
--1--0 0
-0---0 0
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
BERR.PIN.BLIF SM_AMIGA_2_.D
1010000-101-- 1
1-----10101-- 1
1--------0-11 1
1-------1--11 1
------11---0- 0
-----10----0- 0
----1-0----0- 0
---1--0----0- 0
--0---0----0- 0
-1----0----0- 0
------11----0 0
--------01--- 0
-----10-----0 0
----1-0-----0 0
---1--0-----0 0
--0---0-----0 0
-1----0-----0 0
----------00- 0
---------1-0- 0
--------0--0- 0
----------0-0 0
0------------ 0
---------1--0 0
--------0---0 0
un10_ciin_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \
SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \
AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \
DSACK1.OE RESET.OE CIIN.OE cpu_est_2_.D.X1 cpu_est_2_.D.X2 RST_DLY_1_.D.X1 \
RST_DLY_1_.D.X2 inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 \
SM_AMIGA_3_.D.X2 SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \
SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D
101-1- 1
@ -168,31 +93,19 @@ SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D
0----- 0
--0--0 0
-1---0 0
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_0_.BLIF \
SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D
110-1- 1
1-01-1 1
11-1-1 1
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \
SM_AMIGA_0_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D
1101-- 1
1-0-11 1
11--11 1
---00- 0
--10-- 0
-0-0-- 0
--1-0- 0
-0--0- 0
-01--- 0
----00 0
---0-0 0
0----- 0
--1--0 0
-0---0 0
.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D
-11110 1
10-0-- 1
1---0- 1
1----1 1
0--0-- 0
-10-10 0
-1-010 0
-0-110 0
0---0- 0
0----1 0
.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D
0-01100- 1
@ -274,17 +187,74 @@ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D
1- 1
-0 1
01 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D
100010 1
101-00 1
1011-0 1
--101- 0
.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF \
SM_AMIGA_6_.D
11010-0- 1
-1--0111 1
-1-1-111 1
-----01- 0
---01--- 0
--1---0- 0
0-----0- 0
----1-0- 0
---0--0- 0
------10 0
-0------ 0
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \
SM_AMIGA_5_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
1011-- 1
1-1-11 1
10--11 1
---00- 0
--0-0- 0
--01-- 0
-1---- 0
-1--0- 0
-10--- 0
---0-0 0
0----- 0
-----1 0
--0--0 0
-1---0 0
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF \
SM_AMIGA_5_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D
110-1- 1
1-01-1 1
11-1-1 1
---00- 0
--10-- 0
-0-0-- 0
-01--- 0
----00 0
0----- 0
--1--0 0
-0---0 0
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
BERR.PIN.BLIF SM_AMIGA_2_.D
1000010-101-- 1
1-----10101-- 1
1--------0-11 1
1-------1--11 1
------11---0- 0
-----00----0- 0
----1-0----0- 0
---1--0----0- 0
--1---0----0- 0
-1----0----0- 0
------11----0 0
--------01--- 0
-----00-----0 0
----1-0-----0 0
---1--0-----0 0
--1---0-----0 0
-1----0-----0 0
----------00- 0
---------1-0- 0
--------0--0- 0
----------0-0 0
0------------ 0
---------1--0 0
--------0---0 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D
1010010 1
@ -323,26 +293,28 @@ SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D
110 0
00- 0
0-1 0
.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_000_D_1_.BLIF \
.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_3_.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF cpu_est_1_.D
01010 1
-01-- 1
--10- 1
--1-1 1
1-0-- 0
-1110 0
--00- 0
-00-- 0
--0-1 0
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \
RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_2_.D
11011- 1
1----1 1
0----- 0
----00 0
---0-0 0
--1--0 0
-0---0 0
10010 1
01--- 1
-1-0- 1
-1--1 1
-01-- 0
11-10 0
-0-0- 0
00--- 0
-0--1 0
.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D
111-10 1
0--1-- 1
---10- 1
---1-1 1
1-0-10 0
10--10 0
---00- 0
0--0-- 0
---0-1 0
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \
RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_0_.D
1--111 1
@ -354,24 +326,26 @@ RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_0_.D
--10-- 0
-0-0-- 0
0----- 0
.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D
--1100 1
-10--- 1
0----- 1
100--- 0
1-1-1- 0
1-10-- 0
1-1--1 0
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
1--011 1
1-1--- 1
-0---- 1
-10-0- 0
-101-- 0
01---- 0
-10--0 0
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \
RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_2_.D
11011- 1
1----1 1
0----- 0
----00 0
---0-0 0
--1--0 0
-0---0 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D
100010 1
101-00 1
1011-0 1
--101- 0
--0-0- 0
--01-- 0
-1---- 0
0----- 0
-----1 0
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
LDS_000.PIN.BLIF inst_AS_000_DMA.D
@ -411,49 +385,32 @@ SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D
--1------00--1 0
.names RST.BLIF inst_AS_000_INT.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF BERR.PIN.BLIF inst_AS_000_INT.D
-1---0- 1
-1--0-- 1
-1-1--- 1
--1--0- 1
-1---0- 1
--1-0-- 1
-1--0-- 1
--11--- 1
-1-1--- 1
0------ 1
-----00 1
----0-0 1
---1--0 1
1--011- 0
100---1 0
.names CLK_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_CLK_OUT_PRE_D.BLIF \
CLK_000_D_8_.BLIF CLK_000_D_9_.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
CLK_000_D_10_.BLIF inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF \
inst_DSACK1_INTreg.D
1--0-1-1-1-- 1
1--0-10--1-- 1
-----0-101-- 1
-----00-01-- 1
----11-1-1-- 1
----110--1-- 1
1-10-1-1---- 1
1-10-10----- 1
1--0-1-1---0 1
1--0-10----0 1
--1--0-10--- 1
--1--00-0--- 1
--1-11-1---- 1
--1-110----- 1
---------10- 1
-----0-10--0 1
-----00-0--0 1
----11-1---0 1
----110----0 1
--1-------0- 1
-0---------- 1
----------00 1
-1-101----1- 0
01--01----1- 0
-1---0--1-1- 0
-1----10--1- 0
-10------0-1 0
.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D
----10- 1
---11-- 1
--0-1-- 1
-1---0- 1
-1-1--- 1
-10---- 1
0------ 1
-----00 1
---1--0 1
--0---0 1
1-10-1- 0
10--0-1 0
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \
AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
@ -526,11 +483,11 @@ RW.PIN.BLIF inst_DS_000_ENABLE.D
0-------- 0
.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \
CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
--0--- 1
-1---- 1
----01 1
---0-1 1
0----1 1
--0--- 1
-1---- 1
10111- 0
-01--0 0
.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
@ -565,24 +522,24 @@ inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D
11-0- 0
110-- 0
10--0 0
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF inst_VMA_INTreg.D
--0000-01 1
-1----1-- 1
-1---1--- 1
-11------ 1
-1--1---- 1
0-------- 1
-1-----0- 1
-1--0---- 1
-1-0----- 1
-10------ 1
-1------1 1
1-0110010 0
1-1100010 0
10---1--- 0
101------ 0
10-----1- 0
10--1---- 0
10-----1- 0
10-1----- 0
101------ 0
10------0 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
@ -606,6 +563,24 @@ inst_RW_000_INT.D
1--0001- 0
1-0--01- 0
11---01- 0
.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D
--1100 1
-10--- 1
0----- 1
100--- 0
1-1-1- 0
1-10-- 0
1-1--1 0
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
1--011 1
1-1--- 1
-0---- 1
-10-0- 0
-101-- 0
01---- 0
-10--0 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
0- 1
-1 1
@ -613,6 +588,24 @@ inst_RW_000_INT.D
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
0 1
1 0
.names A_DECODE_23_.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \
inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \
AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \
AHIGH_31_.PIN.BLIF un10_ciin_i
-----------1- 1
----------1-- 1
---------1--- 1
--------1---- 1
-------1----- 1
------1------ 1
-----1------- 1
----1-------- 1
---0--------- 1
--0---------- 1
-0----------- 1
0------------ 1
------------1 1
1111000000000 0
.names IPL_030DFF_2_reg.BLIF IPL_030_2_
1 1
0 0
@ -650,12 +643,12 @@ AS_030.PIN.BLIF FPU_CS
0 0
.names AVEC
1
.names cpu_est_3_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF E
100 1
011 1
0-0 0
-01 0
11- 0
.names cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF E
110 1
001 1
-00 0
1-1 0
01- 0
.names inst_VMA_INTreg.BLIF VMA
1 1
0 0
@ -706,36 +699,12 @@ AHIGH_31_.PIN.BLIF CIIN
.names IPL_030DFF_0_reg.BLIF IPL_030_0_
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
1 1
0 0
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_2_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_3_.C
1 1
0 0
.names CLK_OSZI.BLIF IPL_030DFF_0_reg.C
1 1
0 0
@ -754,49 +723,22 @@ AHIGH_31_.PIN.BLIF CIIN
.names CLK_OSZI.BLIF IPL_D0_2_.C
1 1
0 0
.names CLK_000_D_3_.BLIF CLK_000_D_4_.D
.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_4_.C
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
1 1
0 0
.names CLK_000_D_4_.BLIF CLK_000_D_5_.D
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_5_.C
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
1 1
0 0
.names CLK_000_D_5_.BLIF CLK_000_D_6_.D
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_6_.C
1 1
0 0
.names CLK_000_D_6_.BLIF CLK_000_D_7_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_7_.C
1 1
0 0
.names CLK_000_D_7_.BLIF CLK_000_D_8_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_8_.C
1 1
0 0
.names CLK_000_D_8_.BLIF CLK_000_D_9_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_9_.C
1 1
0 0
.names CLK_000_D_9_.BLIF CLK_000_D_10_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_10_.C
1 1
0 0
.names CLK_OSZI.BLIF CYCLE_DMA_0_.C
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
1 1
0 0
.names CLK_OSZI.BLIF CYCLE_DMA_1_.C
@ -814,6 +756,15 @@ AHIGH_31_.PIN.BLIF CIIN
.names CLK_OSZI.BLIF cpu_est_1_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_2_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_3_.C
1 1
0 0
.names CLK_OSZI.BLIF RST_DLY_0_.C
1 1
0 0
.names CLK_OSZI.BLIF RST_DLY_1_.C
1 1
0 0
@ -832,25 +783,7 @@ AHIGH_31_.PIN.BLIF CIIN
.names CLK_OSZI.BLIF CLK_000_D_1_.C
1 1
0 0
.names CLK_000_D_1_.BLIF CLK_000_D_2_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_2_.C
1 1
0 0
.names CLK_000_D_2_.BLIF CLK_000_D_3_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_3_.C
1 1
0 0
.names CLK_OSZI.BLIF RST_DLY_0_.C
1 1
0 0
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
.names CLK_OSZI.BLIF CYCLE_DMA_0_.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
@ -918,6 +851,12 @@ AHIGH_31_.PIN.BLIF CIIN
.names CLK_OSZI.BLIF inst_RW_000_INT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
1 1
0 0
@ -953,10 +892,10 @@ AHIGH_31_.PIN.BLIF CIIN
.names inst_RW_000_INT.BLIF RW_000
1 1
0 0
.names inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF UDS_000
1- 1
-0 1
01 0
.names inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF UDS_000
0- 1
-1 1
10 0
.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF LDS_000
1- 1
-0 1
@ -1099,25 +1038,10 @@ DS_030.OE
.names inst_RESET_OUT.BLIF RESET.OE
0 1
1 0
.names A_DECODE_23_.BLIF nEXP_SPACE.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \
A_DECODE_20_.BLIF inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \
AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \
AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF CIIN.OE
1-111000000000 1
-1------------ 1
-0----------1- 0
-0---------1-- 0
-0--------1--- 0
-0-------1---- 0
-0------1----- 0
-0-----1------ 0
-0----1------- 0
-0---1-------- 0
-0--0--------- 0
-0-0---------- 0
-00----------- 0
00------------ 0
-0-----------1 0
.names nEXP_SPACE.BLIF un10_ciin_i.BLIF CIIN.OE
1- 1
-0 1
01 0
.names cpu_est_2_.BLIF cpu_est_2_.D.X1
1 1
0 0
@ -1172,13 +1096,13 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2
0-- 0
-0- 0
--0 0
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
BERR.PIN.BLIF SM_AMIGA_3_.D.X2
1-------0110- 1
1-------011-0 1
1010000-10-11 1
1000010-10-11 1
1-----1010-11 1
0------------ 0
--------11--- 0
@ -1187,31 +1111,31 @@ BERR.PIN.BLIF SM_AMIGA_3_.D.X2
--------1--0- 0
--------1---0 0
-1----0-1---- 0
--0---0-1---- 0
--1---0-1---- 0
---1--0-1---- 0
----1-0-1---- 0
-----10-1---- 0
-----00-1---- 0
------111---- 0
--------0--11 0
.names RST.BLIF BERR.PIN.BLIF SM_AMIGA_i_7_.D.X1
11 1
0- 0
-0 0
.names nEXP_SPACE.BLIF RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF \
cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF inst_AS_030_000_SYNC.BLIF \
.names nEXP_SPACE.BLIF RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF inst_AS_030_000_SYNC.BLIF \
inst_VPA_D.BLIF inst_DTACK_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_1_.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \
SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \
SM_AMIGA_i_7_.D.X2
-1--------011------0 1
-1--------01-1-----0 1
-1--------01------10 1
-1--------10---1---0 1
-1--------10--1----0 1
-1--------10----1--0 1
11-----0--10000--000 1
-101000-0-10-----1-0 1
11-----0--1000-0-000 1
-100001-0-10-----1-0 1
-1------1010-----1-0 1
-1--------0100-00001 1
-1--------01000-0001 1
01----------00000001 1
-1-----1----00000001 1
-1--------0-00000001 1
@ -1219,26 +1143,26 @@ SM_AMIGA_i_7_.D.X2
-0------------------ 0
------------1------1 0
-------------1-----1 0
---------------1---1 0
--------------1----1 0
----------------1--1 0
-----------------1-1 0
------------------11 0
----------1---1----1 0
-----------0--1----1 0
----------1----1---1 0
-----------0---1---1 0
----------11-------0 0
----------00-------0 0
----------1-1--000-- 0
----------1--1-000-- 0
----------1---1000-- 0
----------1----0001- 0
----------1-1-0-00-- 0
----------1--10-00-- 0
----------1---0100-- 0
----------1---0-001- 0
1------0--10-------1 0
----------0-00----00 0
--1-----0-1----001-- 0
---0----0-1----001-- 0
----1---0-1----001-- 0
-----1--0-1----001-- 0
------1-0-1----001-- 0
--------111----001-- 0
0---------1----000-0 0
-------1--1----000-0 0
--1-----0-1---0-01-- 0
---1----0-1---0-01-- 0
----1---0-1---0-01-- 0
-----1--0-1---0-01-- 0
------0-0-1---0-01-- 0
--------111---0-01-- 0
0---------1---0-00-0 0
-------1--1---0-00-0 0
.end

2
Logic/68030_tk.crf
View File

@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 2.0.00.17.20.15
// Design '68030_tk' created Wed Aug 24 22:17:49 2016
// Design '68030_tk' created Thu Aug 25 22:27:51 2016
// LEGEND: '>' Functional Block Port Separator

331
Logic/68030_tk.eq3
View File

@ -2,43 +2,41 @@
Copyright(C), 1992-2015, Lattice Semiconductor Corp.
All Rights Reserved.
Design bus68030 created Wed Aug 24 22:17:49 2016
Design bus68030 created Thu Aug 25 22:27:51 2016
P-Terms Fan-in Fan-out Type Name (attributes)
--------- ------ ------- ---- -----------------
1 2 1 Pin SIZE_1_
1 2 1 Pin SIZE_1_.OE
0 0 1 Pin AHIGH_31_
1 3 1 Pin AHIGH_31_.OE
1 2 1 Pin AS_030-
1 3 1 Pin AS_030.OE
1 2 1 Pin SIZE_0_
1 2 1 Pin SIZE_0_.OE
1 2 1 Pin AS_000-
1 2 1 Pin AS_000.OE
0 0 1 Pin AHIGH_30_
1 3 1 Pin AHIGH_30_.OE
0 0 1 Pin AHIGH_29_
1 3 1 Pin AHIGH_29_.OE
1 2 1 Pin DS_030-
1 3 1 Pin DS_030.OE
1 2 1 Pin SIZE_1_
1 2 1 Pin SIZE_1_.OE
0 0 1 Pin AHIGH_28_
1 3 1 Pin AHIGH_28_.OE
1 2 1 Pin UDS_000-
1 2 1 Pin UDS_000.OE
0 0 1 Pin AHIGH_27_
1 3 1 Pin AHIGH_27_.OE
1 2 1 Pin LDS_000-
1 2 1 Pin LDS_000.OE
0 0 1 Pin AHIGH_31_
1 3 1 Pin AHIGH_31_.OE
0 0 1 Pin AHIGH_26_
1 3 1 Pin AHIGH_26_.OE
0 0 1 Pin AHIGH_25_
1 3 1 Pin AHIGH_25_.OE
0 0 1 Pin BERR
1 9 1 Pin BERR.OE
0 0 1 Pin AHIGH_24_
1 3 1 Pin AHIGH_24_.OE
1 2 1 Pin AS_030-
1 3 1 Pin AS_030.OE
1 2 1 Pin AS_000-
1 2 1 Pin AS_000.OE
1 2 1 Pin DS_030-
1 3 1 Pin DS_030.OE
1 2 1 Pin UDS_000-
1 2 1 Pin UDS_000.OE
1 2 1 Pin LDS_000-
1 2 1 Pin LDS_000.OE
0 0 1 Pin BERR
1 9 1 Pin BERR.OE
1 1 1 Pin CLK_DIV_OUT.D
1 1 1 Pin CLK_DIV_OUT.C
1 9 1 Pin FPU_CS-
@ -52,6 +50,8 @@ Design bus68030 created Wed Aug 24 22:17:49 2016
2 3 1 Pin AMIGA_BUS_ENABLE_HIGH
1 13 1 Pin CIIN
1 1 1 Pin CIIN.OE
1 2 1 Pin SIZE_0_
1 2 1 Pin SIZE_0_.OE
10 8 1 Pin IPL_030_2_.D-
1 1 1 Pin IPL_030_2_.C
1 2 1 Pin RW_000.OE
@ -61,16 +61,6 @@ Design bus68030 created Wed Aug 24 22:17:49 2016
1 1 1 Pin BG_000.C
3 6 1 Pin BGACK_030.D
1 1 1 Pin BGACK_030.C
1 1 1 Pin CLK_EXP.D
1 1 1 Pin CLK_EXP.C
1 1 1 Pin DSACK1.OE
5 12 1 Pin DSACK1.D-
1 1 1 Pin DSACK1.C
3 9 1 Pin VMA.T
1 1 1 Pin VMA.C
1 2 1 Pin RW.OE
2 5 1 Pin RW.D-
1 1 1 Pin RW.C
1 3 1 Pin A_0_.OE
3 5 1 Pin A_0_.D
1 1 1 Pin A_0_.C
@ -78,8 +68,17 @@ Design bus68030 created Wed Aug 24 22:17:49 2016
1 1 1 Pin IPL_030_1_.C
10 8 1 Pin IPL_030_0_.D-
1 1 1 Pin IPL_030_0_.C
4 6 1 Node cpu_est_3_.D
1 1 1 Node cpu_est_3_.C
1 1 1 Pin CLK_EXP.D
1 1 1 Pin CLK_EXP.C
1 1 1 Pin DSACK1.OE
2 7 1 Pin DSACK1.D-
1 1 1 Pin DSACK1.C
3 9 1 Pin VMA.T
1 1 1 Pin VMA.C
1 2 1 Pin RW.OE
2 5 1 Pin RW.D-
1 1 1 Pin RW.C
1 13 1 Node un10_ciin_i-
3 3 1 Node cpu_est_0_.D
1 1 1 Node cpu_est_0_.C
4 5 1 Node cpu_est_1_.D
@ -87,6 +86,8 @@ Design bus68030 created Wed Aug 24 22:17:49 2016
1 4 1 NodeX1 cpu_est_2_.D.X1
1 1 1 NodeX2 cpu_est_2_.D.X2
1 1 1 Node cpu_est_2_.C
4 6 1 Node cpu_est_3_.D
1 1 1 Node cpu_est_3_.C
2 7 1 Node inst_AS_000_INT.D-
1 1 1 Node inst_AS_000_INT.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
@ -111,16 +112,6 @@ Design bus68030 created Wed Aug 24 22:17:49 2016
1 1 1 Node SIZE_DMA_1_.C
1 2 1 Node inst_VPA_D.D-
1 1 1 Node inst_VPA_D.C
2 4 1 Node inst_UDS_000_INT.D-
1 1 1 Node inst_UDS_000_INT.C
3 6 1 Node inst_LDS_000_INT.D
1 1 1 Node inst_LDS_000_INT.C
1 1 1 Node inst_CLK_OUT_PRE_D.D
1 1 1 Node inst_CLK_OUT_PRE_D.C
1 1 1 Node CLK_000_D_8_.D
1 1 1 Node CLK_000_D_8_.C
1 1 1 Node CLK_000_D_9_.D
1 1 1 Node CLK_000_D_9_.C
1 2 1 Node inst_DTACK_D0.D-
1 1 1 Node inst_DTACK_D0.C
2 7 1 Node inst_RESET_OUT.D
@ -133,34 +124,28 @@ Design bus68030 created Wed Aug 24 22:17:49 2016
1 1 1 Node inst_CLK_OUT_PRE_50.C
2 2 1 Node inst_CLK_OUT_PRE_25.D
1 1 1 Node inst_CLK_OUT_PRE_25.C
1 1 1 Node inst_CLK_OUT_PRE_D.D
1 1 1 Node inst_CLK_OUT_PRE_D.C
1 2 1 Node IPL_D0_0_.D-
1 1 1 Node IPL_D0_0_.C
1 2 1 Node IPL_D0_1_.D-
1 1 1 Node IPL_D0_1_.C
1 2 1 Node IPL_D0_2_.D-
1 1 1 Node IPL_D0_2_.C
1 1 1 Node CLK_000_D_2_.D
1 1 1 Node CLK_000_D_2_.C
1 1 1 Node CLK_000_D_3_.D
1 1 1 Node CLK_000_D_3_.C
1 1 1 Node CLK_000_D_4_.D
1 1 1 Node CLK_000_D_4_.C
1 1 1 Node CLK_000_D_5_.D
1 1 1 Node CLK_000_D_5_.C
1 1 1 Node CLK_000_D_6_.D
1 1 1 Node CLK_000_D_6_.C
1 1 1 Node CLK_000_D_7_.D
1 1 1 Node CLK_000_D_7_.C
1 1 1 Node CLK_000_D_10_.D
1 1 1 Node CLK_000_D_10_.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
3 6 1 Node inst_LDS_000_INT.D
1 1 1 Node inst_LDS_000_INT.C
3 9 1 Node inst_DS_000_ENABLE.D
1 1 1 Node inst_DS_000_ENABLE.C
2 4 1 Node inst_UDS_000_INT.D-
1 1 1 Node inst_UDS_000_INT.C
3 8 1 Node SM_AMIGA_6_.D
1 1 1 Node SM_AMIGA_6_.C
3 6 1 Node SM_AMIGA_4_.D
1 1 1 Node SM_AMIGA_4_.C
3 6 1 Node SM_AMIGA_1_.D
1 1 1 Node SM_AMIGA_1_.C
3 6 1 Node SM_AMIGA_0_.D
1 1 1 Node SM_AMIGA_0_.C
4 6 1 Node RST_DLY_0_.D
@ -172,8 +157,6 @@ Design bus68030 created Wed Aug 24 22:17:49 2016
1 1 1 Node RST_DLY_2_.C
8 10 1 Node inst_CLK_030_H.D
1 1 1 Node inst_CLK_030_H.C
3 6 1 Node SM_AMIGA_1_.D
1 1 1 Node SM_AMIGA_1_.C
3 6 1 Node SM_AMIGA_5_.D
1 1 1 Node SM_AMIGA_5_.C
4 13 1 NodeX1 SM_AMIGA_3_.D.X1
@ -184,36 +167,16 @@ Design bus68030 created Wed Aug 24 22:17:49 2016
13 20 1 NodeX1 SM_AMIGA_i_7_.D.X1
1 2 1 NodeX2 SM_AMIGA_i_7_.D.X2
1 1 1 Node SM_AMIGA_i_7_.C
2 14 1 Node CIIN_0
1 2 1 Node CIIN_0-
=========
300 P-Term Total: 300
279 P-Term Total: 279
Total Pins: 61
Total Nodes: 52
Total Nodes: 44
Average P-Term/Output: 2
Equations:
SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q);
AHIGH_31_ = (0);
AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q);
!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_30_ = (0);
AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
@ -222,25 +185,21 @@ AHIGH_29_ = (0);
AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q);
AHIGH_28_ = (0);
AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q);
UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_27_ = (0);
AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
AHIGH_31_ = (0);
LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_26_ = (0);
@ -250,14 +209,34 @@ AHIGH_25_ = (0);
AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
BERR = (0);
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
AHIGH_24_ = (0);
AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q);
UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
BERR = (0);
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
CLK_DIV_OUT.C = (CLK_OSZI);
@ -266,8 +245,8 @@ CLK_DIV_OUT.C = (CLK_OSZI);
AVEC = (1);
E = (!cpu_est_3_.Q & cpu_est_1_.Q & cpu_est_2_.Q
# cpu_est_3_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q);
E = (!cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q
# cpu_est_1_.Q & cpu_est_2_.Q & !cpu_est_3_.Q);
RESET = (0);
@ -287,6 +266,10 @@ CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030
CIIN.OE = (CIIN_0);
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q);
!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
# RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
@ -320,33 +303,6 @@ BGACK_030.D = (!RST
BGACK_030.C = (CLK_OSZI);
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
CLK_EXP.C = (CLK_OSZI);
DSACK1.OE = (nEXP_SPACE);
!DSACK1.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
# RST & !CLK_000_D_9_.Q & CLK_000_D_10_.Q & SM_AMIGA_1_.Q
# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN
# !CLK_030 & RST & !CLK_000_D_8_.Q & CLK_000_D_9_.Q & SM_AMIGA_1_.Q
# RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_8_.Q & CLK_000_D_9_.Q & SM_AMIGA_1_.Q);
DSACK1.C = (CLK_OSZI);
VMA.T = (!RST & !VMA.Q
# !VMA.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q
# RST & VMA.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
VMA.C = (CLK_OSZI);
RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
RW.C = (CLK_OSZI);
A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
A_0_.D = (!RST
@ -381,12 +337,31 @@ IPL_030_1_.C = (CLK_OSZI);
IPL_030_0_.C = (CLK_OSZI);
cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q
# cpu_est_3_.Q & CLK_000_D_0_.Q
# cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_2_.Q
# cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
cpu_est_3_.C = (CLK_OSZI);
CLK_EXP.C = (CLK_OSZI);
DSACK1.OE = (nEXP_SPACE);
!DSACK1.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);
DSACK1.C = (CLK_OSZI);
VMA.T = (!RST & !VMA.Q
# !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q
# RST & VMA.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
VMA.C = (CLK_OSZI);
RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
RW.C = (CLK_OSZI);
!un10_ciin_i = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q
# cpu_est_0_.Q & CLK_000_D_0_.Q
@ -397,7 +372,7 @@ cpu_est_0_.C = (CLK_OSZI);
cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q
# cpu_est_1_.Q & !CLK_000_D_1_.Q
# cpu_est_1_.Q & CLK_000_D_0_.Q
# !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
# cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_3_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
cpu_est_1_.C = (CLK_OSZI);
@ -407,6 +382,13 @@ cpu_est_2_.D.X2 = (cpu_est_2_.Q);
cpu_est_2_.C = (CLK_OSZI);
cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q
# cpu_est_3_.Q & !CLK_000_D_1_.Q
# cpu_est_3_.Q & CLK_000_D_0_.Q
# cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
cpu_est_3_.C = (CLK_OSZI);
!inst_AS_000_INT.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q
# RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
@ -486,29 +468,6 @@ SIZE_DMA_1_.C = (CLK_OSZI);
inst_VPA_D.C = (CLK_OSZI);
!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
# RST & SM_AMIGA_6_.Q & !A_0_.PIN);
inst_UDS_000_INT.C = (CLK_OSZI);
inst_LDS_000_INT.D = (!RST
# inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
# SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN);
inst_LDS_000_INT.C = (CLK_OSZI);
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_25.Q);
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
CLK_000_D_8_.D = (CLK_000_D_7_.Q);
CLK_000_D_8_.C = (CLK_OSZI);
CLK_000_D_9_.D = (CLK_000_D_8_.Q);
CLK_000_D_9_.C = (CLK_OSZI);
!inst_DTACK_D0.D = (!DTACK & RST);
inst_DTACK_D0.C = (CLK_OSZI);
@ -535,6 +494,10 @@ inst_CLK_OUT_PRE_25.D = (!inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_25.Q);
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
!IPL_D0_0_.D = (RST & !IPL_0_);
IPL_D0_0_.C = (CLK_OSZI);
@ -547,45 +510,28 @@ IPL_D0_1_.C = (CLK_OSZI);
IPL_D0_2_.C = (CLK_OSZI);
CLK_000_D_2_.D = (CLK_000_D_1_.Q);
CLK_000_D_2_.C = (CLK_OSZI);
CLK_000_D_3_.D = (CLK_000_D_2_.Q);
CLK_000_D_3_.C = (CLK_OSZI);
CLK_000_D_4_.D = (CLK_000_D_3_.Q);
CLK_000_D_4_.C = (CLK_OSZI);
CLK_000_D_5_.D = (CLK_000_D_4_.Q);
CLK_000_D_5_.C = (CLK_OSZI);
CLK_000_D_6_.D = (CLK_000_D_5_.Q);
CLK_000_D_6_.C = (CLK_OSZI);
CLK_000_D_7_.D = (CLK_000_D_6_.Q);
CLK_000_D_7_.C = (CLK_OSZI);
CLK_000_D_10_.D = (CLK_000_D_9_.Q);
CLK_000_D_10_.C = (CLK_OSZI);
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
inst_LDS_000_INT.D = (!RST
# inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
# SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN);
inst_LDS_000_INT.C = (CLK_OSZI);
inst_DS_000_ENABLE.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q
# RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN);
inst_DS_000_ENABLE.C = (CLK_OSZI);
!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
# RST & SM_AMIGA_6_.Q & !A_0_.PIN);
inst_UDS_000_INT.C = (CLK_OSZI);
SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q);
@ -598,6 +544,12 @@ SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q
SM_AMIGA_4_.C = (CLK_OSZI);
SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q
# RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & BERR.PIN
# RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & BERR.PIN);
SM_AMIGA_1_.C = (CLK_OSZI);
SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
# RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q & BERR.PIN);
@ -634,12 +586,6 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst
inst_CLK_030_H.C = (CLK_OSZI);
SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q
# RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & BERR.PIN
# RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & BERR.PIN);
SM_AMIGA_1_.C = (CLK_OSZI);
SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q
# RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q & BERR.PIN
# RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q & BERR.PIN);
@ -649,7 +595,7 @@ SM_AMIGA_5_.C = (CLK_OSZI);
SM_AMIGA_3_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN);
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN);
SM_AMIGA_3_.D.X2 = (RST & SM_AMIGA_3_.Q & BERR.PIN);
@ -658,7 +604,7 @@ SM_AMIGA_3_.C = (CLK_OSZI);
SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q & BERR.PIN
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
SM_AMIGA_2_.C = (CLK_OSZI);
@ -669,19 +615,18 @@ SM_AMIGA_i_7_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q & !BERR.PIN
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# !nEXP_SPACE & RST & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & !CLK_000_D_1_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
# !nEXP_SPACE & RST & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & !CLK_000_D_1_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !BERR.PIN);
SM_AMIGA_i_7_.D.X2 = (RST & BERR.PIN);
SM_AMIGA_i_7_.C = (CLK_OSZI);
CIIN_0 = (nEXP_SPACE
# A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
!CIIN_0 = (!nEXP_SPACE & un10_ciin_i);
Reverse-Polarity Equations:

230
Logic/68030_tk.fti
View File

@ -5,8 +5,8 @@
DATA LOCATION AHIGH_24_:C_8_19 // IO
DATA LOCATION AHIGH_25_:C_12_18 // IO
DATA LOCATION AHIGH_26_:C_5_17 // IO
DATA LOCATION AHIGH_27_:C_9_16 // IO
DATA LOCATION AHIGH_26_:C_4_17 // IO
DATA LOCATION AHIGH_27_:C_5_16 // IO
DATA LOCATION AHIGH_28_:C_0_15 // IO
DATA LOCATION AHIGH_29_:B_8_6 // IO
DATA LOCATION AHIGH_30_:B_0_5 // IO
@ -34,25 +34,16 @@ DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030}
DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000}
DATA LOCATION BG_030:C_*_21 // INP
DATA LOCATION CIIN:E_12_47 // OUT
DATA LOCATION CIIN_0:E_9 // NOD
DATA LOCATION CIIN_0:G_14 // NOD
DATA LOCATION CLK_000:*_*_11 // INP
DATA LOCATION CLK_000_D_0_:E_8 // NOD
DATA LOCATION CLK_000_D_10_:F_6 // NOD
DATA LOCATION CLK_000_D_0_:D_9 // NOD
DATA LOCATION CLK_000_D_1_:H_5 // NOD
DATA LOCATION CLK_000_D_2_:H_6 // NOD
DATA LOCATION CLK_000_D_3_:E_2 // NOD
DATA LOCATION CLK_000_D_4_:D_3 // NOD
DATA LOCATION CLK_000_D_5_:B_14 // NOD
DATA LOCATION CLK_000_D_6_:B_10 // NOD
DATA LOCATION CLK_000_D_7_:E_13 // NOD
DATA LOCATION CLK_000_D_8_:E_6 // NOD
DATA LOCATION CLK_000_D_9_:H_13 // NOD
DATA LOCATION CLK_030:*_*_64 // INP
DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT
DATA LOCATION CLK_EXP:B_1_10 // OUT
DATA LOCATION CLK_OSZI:*_*_61 // Cin
DATA LOCATION CYCLE_DMA_0_:C_14 // NOD
DATA LOCATION CYCLE_DMA_1_:C_10 // NOD
DATA LOCATION CYCLE_DMA_0_:F_1 // NOD
DATA LOCATION CYCLE_DMA_1_:F_0 // NOD
DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1}
DATA LOCATION DS_030:A_0_98 // OUT
DATA LOCATION DTACK:D_*_30 // INP
@ -67,9 +58,9 @@ DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_}
DATA LOCATION IPL_0_:G_*_67 // INP
DATA LOCATION IPL_1_:F_*_56 // INP
DATA LOCATION IPL_2_:G_*_68 // INP
DATA LOCATION IPL_D0_0_:A_13 // NOD
DATA LOCATION IPL_D0_1_:B_3 // NOD
DATA LOCATION IPL_D0_2_:G_7 // NOD
DATA LOCATION IPL_D0_0_:B_14 // NOD
DATA LOCATION IPL_D0_1_:E_9 // NOD
DATA LOCATION IPL_D0_2_:D_10 // NOD
DATA LOCATION LDS_000:D_12_31 // IO
DATA LOCATION RESET:B_2_3 // OUT
DATA LOCATION RN_A_0_:G_8 // NOD {A_0_}
@ -83,49 +74,50 @@ DATA LOCATION RN_RW:G_0 // NOD {RW}
DATA LOCATION RN_RW_000:H_0 // NOD {RW_000}
DATA LOCATION RN_VMA:D_0 // NOD {VMA}
DATA LOCATION RST:*_*_86 // INP
DATA LOCATION RST_DLY_0_:G_10 // NOD
DATA LOCATION RST_DLY_1_:G_3 // NOD
DATA LOCATION RST_DLY_2_:G_14 // NOD
DATA LOCATION RST_DLY_0_:C_6 // NOD
DATA LOCATION RST_DLY_1_:C_14 // NOD
DATA LOCATION RST_DLY_2_:C_10 // NOD
DATA LOCATION RW:G_0_71 // IO {RN_RW}
DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000}
DATA LOCATION SIZE_0_:G_12_70 // IO
DATA LOCATION SIZE_1_:H_12_79 // IO
DATA LOCATION SIZE_DMA_0_:G_2 // NOD
DATA LOCATION SIZE_DMA_1_:G_13 // NOD
DATA LOCATION SM_AMIGA_0_:F_12 // NOD
DATA LOCATION SM_AMIGA_1_:F_8 // NOD
DATA LOCATION SM_AMIGA_2_:F_5 // NOD
DATA LOCATION SM_AMIGA_3_:F_9 // NOD
DATA LOCATION SM_AMIGA_4_:F_2 // NOD
DATA LOCATION SM_AMIGA_5_:F_13 // NOD
DATA LOCATION SM_AMIGA_6_:A_8 // NOD
DATA LOCATION SM_AMIGA_i_7_:F_4 // NOD
DATA LOCATION SM_AMIGA_0_:H_13 // NOD
DATA LOCATION SM_AMIGA_1_:A_1 // NOD
DATA LOCATION SM_AMIGA_2_:A_9 // NOD
DATA LOCATION SM_AMIGA_3_:A_13 // NOD
DATA LOCATION SM_AMIGA_4_:F_4 // NOD
DATA LOCATION SM_AMIGA_5_:A_12 // NOD
DATA LOCATION SM_AMIGA_6_:C_13 // NOD
DATA LOCATION SM_AMIGA_i_7_:A_8 // NOD
DATA LOCATION UDS_000:D_8_32 // IO
DATA LOCATION VMA:D_0_35 // IO {RN_VMA}
DATA LOCATION VPA:*_*_36 // INP
DATA LOCATION cpu_est_0_:D_10 // NOD
DATA LOCATION cpu_est_1_:D_13 // NOD
DATA LOCATION cpu_est_2_:D_6 // NOD
DATA LOCATION cpu_est_3_:D_2 // NOD
DATA LOCATION cpu_est_0_:D_2 // NOD
DATA LOCATION cpu_est_1_:G_5 // NOD
DATA LOCATION cpu_est_2_:G_9 // NOD
DATA LOCATION cpu_est_3_:D_13 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:G_6 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:C_3 // NOD
DATA LOCATION inst_AS_000_DMA:C_2 // NOD
DATA LOCATION inst_AS_000_INT:A_5 // NOD
DATA LOCATION inst_AS_030_000_SYNC:A_12 // NOD
DATA LOCATION inst_AS_030_D0:D_9 // NOD
DATA LOCATION inst_BGACK_030_INT_D:F_0 // NOD
DATA LOCATION inst_CLK_030_H:C_6 // NOD
DATA LOCATION inst_CLK_OUT_PRE_25:A_1 // NOD
DATA LOCATION inst_CLK_OUT_PRE_50:A_2 // NOD
DATA LOCATION inst_CLK_OUT_PRE_D:B_13 // NOD
DATA LOCATION inst_DS_000_DMA:C_13 // NOD
DATA LOCATION inst_DS_000_ENABLE:F_1 // NOD
DATA LOCATION inst_DTACK_D0:C_7 // NOD
DATA LOCATION inst_LDS_000_INT:B_6 // NOD
DATA LOCATION inst_RESET_OUT:G_9 // NOD
DATA LOCATION inst_UDS_000_INT:D_14 // NOD
DATA LOCATION inst_VPA_D:A_9 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:G_10 // NOD
DATA LOCATION inst_AS_000_DMA:B_6 // NOD
DATA LOCATION inst_AS_000_INT:F_5 // NOD
DATA LOCATION inst_AS_030_000_SYNC:C_2 // NOD
DATA LOCATION inst_AS_030_D0:E_8 // NOD
DATA LOCATION inst_BGACK_030_INT_D:E_5 // NOD
DATA LOCATION inst_CLK_030_H:B_10 // NOD
DATA LOCATION inst_CLK_OUT_PRE_25:F_13 // NOD
DATA LOCATION inst_CLK_OUT_PRE_50:F_2 // NOD
DATA LOCATION inst_CLK_OUT_PRE_D:F_9 // NOD
DATA LOCATION inst_DS_000_DMA:B_13 // NOD
DATA LOCATION inst_DS_000_ENABLE:F_8 // NOD
DATA LOCATION inst_DTACK_D0:F_6 // NOD
DATA LOCATION inst_LDS_000_INT:F_12 // NOD
DATA LOCATION inst_RESET_OUT:C_9 // NOD
DATA LOCATION inst_UDS_000_INT:D_6 // NOD
DATA LOCATION inst_VPA_D:A_5 // NOD
DATA LOCATION nEXP_SPACE:*_*_14 // INP
DATA LOCATION un10_ciin_i:E_13 // NOD
DATA IO_DIR AHIGH_24_:BI
DATA IO_DIR AHIGH_25_:BI
DATA IO_DIR AHIGH_26_:BI
@ -188,72 +180,78 @@ DATA IO_DIR VMA:OUT
DATA IO_DIR VPA:IN
DATA IO_DIR nEXP_SPACE:IN
DATA GLB_CLOCK CLK_OSZI
DATA PW_LEVEL SIZE_1_:1
DATA SLEW SIZE_1_:0
DATA PW_LEVEL AHIGH_31_:1
DATA SLEW AHIGH_31_:0
DATA PW_LEVEL A_DECODE_23_:1
DATA SLEW A_DECODE_23_:1
DATA PW_LEVEL IPL_2_:1
DATA SLEW IPL_2_:1
DATA PW_LEVEL FC_1_:1
DATA SLEW FC_1_:1
DATA PW_LEVEL AS_030:1
DATA SLEW AS_030:0
DATA PW_LEVEL SIZE_0_:1
DATA SLEW SIZE_0_:0
DATA PW_LEVEL AS_000:1
DATA SLEW AS_000:0
DATA PW_LEVEL AHIGH_30_:1
DATA SLEW AHIGH_30_:0
DATA PW_LEVEL AHIGH_29_:1
DATA SLEW AHIGH_29_:0
DATA PW_LEVEL DS_030:1
DATA SLEW DS_030:0
DATA PW_LEVEL SIZE_1_:1
DATA SLEW SIZE_1_:0
DATA PW_LEVEL AHIGH_28_:1
DATA SLEW AHIGH_28_:0
DATA PW_LEVEL UDS_000:1
DATA SLEW UDS_000:0
DATA PW_LEVEL AHIGH_27_:1
DATA SLEW AHIGH_27_:0
DATA PW_LEVEL LDS_000:1
DATA SLEW LDS_000:0
DATA PW_LEVEL AHIGH_31_:1
DATA SLEW AHIGH_31_:0
DATA PW_LEVEL AHIGH_26_:1
DATA SLEW AHIGH_26_:0
DATA SLEW nEXP_SPACE:1
DATA PW_LEVEL AHIGH_25_:1
DATA SLEW AHIGH_25_:0
DATA PW_LEVEL BERR:1
DATA SLEW BERR:0
DATA PW_LEVEL A_DECODE_23_:1
DATA SLEW A_DECODE_23_:1
DATA PW_LEVEL AHIGH_24_:1
DATA SLEW AHIGH_24_:0
DATA PW_LEVEL BG_030:1
DATA SLEW BG_030:1
DATA PW_LEVEL A_DECODE_22_:1
DATA SLEW A_DECODE_22_:1
DATA PW_LEVEL A_DECODE_21_:1
DATA SLEW A_DECODE_21_:1
DATA PW_LEVEL A_DECODE_20_:1
DATA SLEW A_DECODE_20_:1
DATA PW_LEVEL BGACK_000:1
DATA SLEW BGACK_000:1
DATA PW_LEVEL A_DECODE_19_:1
DATA SLEW A_DECODE_19_:1
DATA SLEW CLK_030:1
DATA PW_LEVEL A_DECODE_18_:1
DATA SLEW A_DECODE_18_:1
DATA SLEW CLK_000:1
DATA PW_LEVEL IPL_2_:1
DATA SLEW IPL_2_:1
DATA PW_LEVEL A_DECODE_17_:1
DATA SLEW A_DECODE_17_:1
DATA SLEW CLK_OSZI:1
DATA PW_LEVEL A_DECODE_16_:1
DATA SLEW A_DECODE_16_:1
DATA PW_LEVEL FC_1_:1
DATA SLEW FC_1_:1
DATA PW_LEVEL AS_030:1
DATA SLEW AS_030:0
DATA PW_LEVEL AS_000:1
DATA SLEW AS_000:0
DATA PW_LEVEL DS_030:1
DATA SLEW DS_030:0
DATA PW_LEVEL UDS_000:1
DATA SLEW UDS_000:0
DATA PW_LEVEL LDS_000:1
DATA SLEW LDS_000:0
DATA SLEW nEXP_SPACE:1
DATA PW_LEVEL BERR:1
DATA SLEW BERR:0
DATA PW_LEVEL BG_030:1
DATA SLEW BG_030:1
DATA PW_LEVEL BGACK_000:1
DATA SLEW BGACK_000:1
DATA SLEW CLK_030:1
DATA SLEW CLK_000:1
DATA SLEW CLK_OSZI:1
DATA PW_LEVEL CLK_DIV_OUT:1
DATA SLEW CLK_DIV_OUT:0
DATA PW_LEVEL IPL_1_:1
DATA SLEW IPL_1_:1
DATA PW_LEVEL FPU_CS:1
DATA SLEW FPU_CS:0
DATA PW_LEVEL IPL_0_:1
DATA SLEW IPL_0_:1
DATA PW_LEVEL FPU_SENSE:1
DATA SLEW FPU_SENSE:1
DATA PW_LEVEL FC_0_:1
DATA SLEW FC_0_:1
DATA PW_LEVEL A_1_:1
DATA SLEW A_1_:1
DATA PW_LEVEL DTACK:1
DATA SLEW DTACK:1
DATA PW_LEVEL AVEC:1
@ -274,14 +272,8 @@ DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1
DATA SLEW AMIGA_BUS_ENABLE_HIGH:0
DATA PW_LEVEL CIIN:1
DATA SLEW CIIN:0
DATA PW_LEVEL IPL_1_:1
DATA SLEW IPL_1_:1
DATA PW_LEVEL IPL_0_:1
DATA SLEW IPL_0_:1
DATA PW_LEVEL FC_0_:1
DATA SLEW FC_0_:1
DATA PW_LEVEL A_1_:1
DATA SLEW A_1_:1
DATA PW_LEVEL SIZE_0_:1
DATA SLEW SIZE_0_:0
DATA PW_LEVEL IPL_030_2_:1
DATA SLEW IPL_030_2_:0
DATA PW_LEVEL RW_000:1
@ -290,6 +282,12 @@ DATA PW_LEVEL BG_000:1
DATA SLEW BG_000:0
DATA PW_LEVEL BGACK_030:1
DATA SLEW BGACK_030:0
DATA PW_LEVEL A_0_:1
DATA SLEW A_0_:0
DATA PW_LEVEL IPL_030_1_:1
DATA SLEW IPL_030_1_:0
DATA PW_LEVEL IPL_030_0_:1
DATA SLEW IPL_030_0_:0
DATA PW_LEVEL CLK_EXP:1
DATA SLEW CLK_EXP:0
DATA PW_LEVEL DSACK1:1
@ -298,20 +296,16 @@ DATA PW_LEVEL VMA:1
DATA SLEW VMA:0
DATA PW_LEVEL RW:1
DATA SLEW RW:0
DATA PW_LEVEL A_0_:1
DATA SLEW A_0_:0
DATA PW_LEVEL IPL_030_1_:1
DATA SLEW IPL_030_1_:0
DATA PW_LEVEL IPL_030_0_:1
DATA SLEW IPL_030_0_:0
DATA PW_LEVEL cpu_est_3_:1
DATA SLEW cpu_est_3_:1
DATA PW_LEVEL un10_ciin_i:1
DATA SLEW un10_ciin_i:1
DATA PW_LEVEL cpu_est_0_:1
DATA SLEW cpu_est_0_:1
DATA PW_LEVEL cpu_est_1_:1
DATA SLEW cpu_est_1_:1
DATA PW_LEVEL cpu_est_2_:1
DATA SLEW cpu_est_2_:1
DATA PW_LEVEL cpu_est_3_:1
DATA SLEW cpu_est_3_:1
DATA PW_LEVEL inst_AS_000_INT:1
DATA SLEW inst_AS_000_INT:1
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1
@ -336,16 +330,6 @@ DATA PW_LEVEL SIZE_DMA_1_:1
DATA SLEW SIZE_DMA_1_:1
DATA PW_LEVEL inst_VPA_D:1
DATA SLEW inst_VPA_D:1
DATA PW_LEVEL inst_UDS_000_INT:1
DATA SLEW inst_UDS_000_INT:1
DATA PW_LEVEL inst_LDS_000_INT:1
DATA SLEW inst_LDS_000_INT:1
DATA PW_LEVEL inst_CLK_OUT_PRE_D:1
DATA SLEW inst_CLK_OUT_PRE_D:1
DATA PW_LEVEL CLK_000_D_8_:1
DATA SLEW CLK_000_D_8_:1
DATA PW_LEVEL CLK_000_D_9_:1
DATA SLEW CLK_000_D_9_:1
DATA PW_LEVEL inst_DTACK_D0:1
DATA SLEW inst_DTACK_D0:1
DATA PW_LEVEL inst_RESET_OUT:1
@ -358,34 +342,28 @@ DATA PW_LEVEL inst_CLK_OUT_PRE_50:1
DATA SLEW inst_CLK_OUT_PRE_50:1
DATA PW_LEVEL inst_CLK_OUT_PRE_25:1
DATA SLEW inst_CLK_OUT_PRE_25:1
DATA PW_LEVEL inst_CLK_OUT_PRE_D:1
DATA SLEW inst_CLK_OUT_PRE_D:1
DATA PW_LEVEL IPL_D0_0_:1
DATA SLEW IPL_D0_0_:1
DATA PW_LEVEL IPL_D0_1_:1
DATA SLEW IPL_D0_1_:1
DATA PW_LEVEL IPL_D0_2_:1
DATA SLEW IPL_D0_2_:1
DATA PW_LEVEL CLK_000_D_2_:1
DATA SLEW CLK_000_D_2_:1
DATA PW_LEVEL CLK_000_D_3_:1
DATA SLEW CLK_000_D_3_:1
DATA PW_LEVEL CLK_000_D_4_:1
DATA SLEW CLK_000_D_4_:1
DATA PW_LEVEL CLK_000_D_5_:1
DATA SLEW CLK_000_D_5_:1
DATA PW_LEVEL CLK_000_D_6_:1
DATA SLEW CLK_000_D_6_:1
DATA PW_LEVEL CLK_000_D_7_:1
DATA SLEW CLK_000_D_7_:1
DATA PW_LEVEL CLK_000_D_10_:1
DATA SLEW CLK_000_D_10_:1
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
DATA PW_LEVEL inst_LDS_000_INT:1
DATA SLEW inst_LDS_000_INT:1
DATA PW_LEVEL inst_DS_000_ENABLE:1
DATA SLEW inst_DS_000_ENABLE:1
DATA PW_LEVEL inst_UDS_000_INT:1
DATA SLEW inst_UDS_000_INT:1
DATA PW_LEVEL SM_AMIGA_6_:1
DATA SLEW SM_AMIGA_6_:1
DATA PW_LEVEL SM_AMIGA_4_:1
DATA SLEW SM_AMIGA_4_:1
DATA PW_LEVEL SM_AMIGA_1_:1
DATA SLEW SM_AMIGA_1_:1
DATA PW_LEVEL SM_AMIGA_0_:1
DATA SLEW SM_AMIGA_0_:1
DATA PW_LEVEL RST_DLY_0_:1
@ -396,8 +374,6 @@ DATA PW_LEVEL RST_DLY_2_:1
DATA SLEW RST_DLY_2_:1
DATA PW_LEVEL inst_CLK_030_H:1
DATA SLEW inst_CLK_030_H:1
DATA PW_LEVEL SM_AMIGA_1_:1
DATA SLEW SM_AMIGA_1_:1
DATA PW_LEVEL SM_AMIGA_5_:1
DATA SLEW SM_AMIGA_5_:1
DATA PW_LEVEL SM_AMIGA_3_:1
@ -412,10 +388,10 @@ DATA PW_LEVEL RN_IPL_030_2_:1
DATA PW_LEVEL RN_RW_000:1
DATA PW_LEVEL RN_BG_000:1
DATA PW_LEVEL RN_BGACK_030:1
DATA PW_LEVEL RN_DSACK1:1
DATA PW_LEVEL RN_VMA:1
DATA PW_LEVEL RN_RW:1
DATA PW_LEVEL RN_A_0_:1
DATA PW_LEVEL RN_IPL_030_1_:1
DATA PW_LEVEL RN_IPL_030_0_:1
DATA PW_LEVEL RN_DSACK1:1
DATA PW_LEVEL RN_VMA:1
DATA PW_LEVEL RN_RW:1
END

36
Logic/68030_tk.grp
View File

@ -1,22 +1,22 @@
GROUP MACH_SEG_A DS_030 AVEC inst_AS_030_000_SYNC SM_AMIGA_6_ inst_AS_000_INT
inst_CLK_OUT_PRE_25 inst_VPA_D IPL_D0_0_ inst_CLK_OUT_PRE_50
GROUP MACH_SEG_A DS_030 AVEC SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_1_
SM_AMIGA_5_ inst_VPA_D
GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP RESET inst_LDS_000_INT
IPL_D0_1_ CLK_000_D_5_ CLK_000_D_6_ inst_CLK_OUT_PRE_D
RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP RESET inst_DS_000_DMA
inst_CLK_030_H inst_AS_000_DMA IPL_D0_0_
GROUP MACH_SEG_C AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AMIGA_BUS_ENABLE_LOW
inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA CYCLE_DMA_1_ CYCLE_DMA_0_
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_DTACK_D0
inst_AS_030_000_SYNC SM_AMIGA_6_ inst_RESET_OUT RST_DLY_0_ RST_DLY_1_
RST_DLY_2_
GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH
AMIGA_ADDR_ENABLE cpu_est_3_ cpu_est_1_ cpu_est_2_ inst_UDS_000_INT
cpu_est_0_ inst_AS_030_D0 CLK_000_D_4_
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 CLK_000_D_8_
CLK_000_D_0_ CLK_000_D_3_ CLK_000_D_7_
GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ inst_DS_000_ENABLE
SM_AMIGA_4_ SM_AMIGA_0_ SM_AMIGA_1_ SM_AMIGA_5_ inst_BGACK_030_INT_D
CLK_000_D_10_
GROUP MACH_SEG_G A_0_ RN_A_0_ RW RN_RW SIZE_0_ E CLK_DIV_OUT inst_RESET_OUT
SIZE_DMA_0_ SIZE_DMA_1_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
IPL_D0_2_
GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 FPU_CS BGACK_030 RN_BGACK_030
AS_030 SIZE_1_ CLK_000_D_9_ CLK_000_D_2_ CLK_000_D_1_
AMIGA_ADDR_ENABLE cpu_est_3_ inst_UDS_000_INT cpu_est_0_ IPL_D0_2_
CLK_000_D_0_
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 un10_ciin_i inst_AS_030_D0
IPL_D0_1_ inst_BGACK_030_INT_D
GROUP MACH_SEG_F inst_DS_000_ENABLE inst_AS_000_INT CYCLE_DMA_1_ inst_LDS_000_INT
SM_AMIGA_4_ CYCLE_DMA_0_ inst_CLK_OUT_PRE_25 inst_DTACK_D0 inst_CLK_OUT_PRE_50
inst_CLK_OUT_PRE_D
GROUP MACH_SEG_G A_0_ RN_A_0_ RW RN_RW SIZE_0_ E CLK_DIV_OUT SIZE_DMA_0_
SIZE_DMA_1_ cpu_est_1_ cpu_est_2_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH
CIIN_0
GROUP MACH_SEG_H RW_000 RN_RW_000 FPU_CS DSACK1 RN_DSACK1 BGACK_030 RN_BGACK_030
AS_030 SIZE_1_ SM_AMIGA_0_ CLK_000_D_1_

2
Logic/68030_tk.ipr
View File

@ -1 +1 @@
<LATTICE_ENCRYPTED_BLIF>97::254)ch7m\r
<LATTICE_ENCRYPTED_BLIF>26:5144]e @1UtR

1071
Logic/68030_tk.jed
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File diff suppressed because it is too large Load Diff

142
Logic/68030_tk.lco
View File

@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = 68030_tk.tt4;
DATE = 8/24/16;
TIME = 22:17:53;
DATE = 8/25/16;
TIME = 22:27:55;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;
@ -76,41 +76,44 @@ Usercode_Format = Hex;
[LOCATION ASSIGNMENTS]
Layer = OFF;
SIZE_1_ = pin,79,-,H,-;
AHIGH_31_ = pin,4,-,B,-;
A_DECODE_23_ = pin,85,-,H,-;
IPL_2_ = pin,68,-,G,-;
FC_1_ = pin,58,-,F,-;
AS_030 = pin,82,-,H,-;
SIZE_0_ = pin,70,-,G,-;
AS_000 = pin,42,-,E,-;
AHIGH_30_ = pin,5,-,B,-;
AHIGH_29_ = pin,6,-,B,-;
DS_030 = pin,98,-,A,-;
SIZE_1_ = pin,79,-,H,-;
AHIGH_28_ = pin,15,-,C,-;
UDS_000 = pin,32,-,D,-;
AHIGH_27_ = pin,16,-,C,-;
LDS_000 = pin,31,-,D,-;
AHIGH_31_ = pin,4,-,B,-;
AHIGH_26_ = pin,17,-,C,-;
nEXP_SPACE = pin,14,-,-,-;
AHIGH_25_ = pin,18,-,C,-;
BERR = pin,41,-,E,-;
A_DECODE_23_ = pin,85,-,H,-;
AHIGH_24_ = pin,19,-,C,-;
BG_030 = pin,21,-,C,-;
A_DECODE_22_ = pin,84,-,H,-;
A_DECODE_21_ = pin,94,-,A,-;
A_DECODE_20_ = pin,93,-,A,-;
BGACK_000 = pin,28,-,D,-;
A_DECODE_19_ = pin,97,-,A,-;
CLK_030 = pin,64,-,-,-;
A_DECODE_18_ = pin,95,-,A,-;
CLK_000 = pin,11,-,-,-;
IPL_2_ = pin,68,-,G,-;
A_DECODE_17_ = pin,59,-,F,-;
CLK_OSZI = pin,61,-,-,-;
A_DECODE_16_ = pin,96,-,A,-;
FC_1_ = pin,58,-,F,-;
AS_030 = pin,82,-,H,-;
AS_000 = pin,42,-,E,-;
DS_030 = pin,98,-,A,-;
UDS_000 = pin,32,-,D,-;
LDS_000 = pin,31,-,D,-;
nEXP_SPACE = pin,14,-,-,-;
BERR = pin,41,-,E,-;
BG_030 = pin,21,-,C,-;
BGACK_000 = pin,28,-,D,-;
CLK_030 = pin,64,-,-,-;
CLK_000 = pin,11,-,-,-;
CLK_OSZI = pin,61,-,-,-;
CLK_DIV_OUT = pin,65,-,G,-;
IPL_1_ = pin,56,-,F,-;
FPU_CS = pin,78,-,H,-;
IPL_0_ = pin,67,-,G,-;
FPU_SENSE = pin,91,-,A,-;
FC_0_ = pin,57,-,F,-;
A_1_ = pin,60,-,F,-;
DTACK = pin,30,-,D,-;
AVEC = pin,92,-,A,-;
E = pin,66,-,G,-;
@ -122,73 +125,62 @@ AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
CIIN = pin,47,-,E,-;
IPL_1_ = pin,56,-,F,-;
IPL_0_ = pin,67,-,G,-;
FC_0_ = pin,57,-,F,-;
A_1_ = pin,60,-,F,-;
SIZE_0_ = pin,70,-,G,-;
IPL_030_2_ = pin,9,-,B,-;
RW_000 = pin,80,-,H,-;
BG_000 = pin,29,-,D,-;
BGACK_030 = pin,83,-,H,-;
A_0_ = pin,69,-,G,-;
IPL_030_1_ = pin,7,-,B,-;
IPL_030_0_ = pin,8,-,B,-;
CLK_EXP = pin,10,-,B,-;
DSACK1 = pin,81,-,H,-;
VMA = pin,35,-,D,-;
RW = pin,71,-,G,-;
A_0_ = pin,69,-,G,-;
IPL_030_1_ = pin,7,-,B,-;
IPL_030_0_ = pin,8,-,B,-;
cpu_est_3_ = node,-,-,D,2;
cpu_est_0_ = node,-,-,D,10;
cpu_est_1_ = node,-,-,D,13;
cpu_est_2_ = node,-,-,D,6;
inst_AS_000_INT = node,-,-,A,5;
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,C,3;
inst_AS_030_D0 = node,-,-,D,9;
inst_AS_030_000_SYNC = node,-,-,A,12;
inst_BGACK_030_INT_D = node,-,-,F,0;
inst_AS_000_DMA = node,-,-,C,2;
inst_DS_000_DMA = node,-,-,C,13;
CYCLE_DMA_0_ = node,-,-,C,14;
CYCLE_DMA_1_ = node,-,-,C,10;
un10_ciin_i = node,-,-,E,13;
cpu_est_0_ = node,-,-,D,2;
cpu_est_1_ = node,-,-,G,5;
cpu_est_2_ = node,-,-,G,9;
cpu_est_3_ = node,-,-,D,13;
inst_AS_000_INT = node,-,-,F,5;
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,G,10;
inst_AS_030_D0 = node,-,-,E,8;
inst_AS_030_000_SYNC = node,-,-,C,2;
inst_BGACK_030_INT_D = node,-,-,E,5;
inst_AS_000_DMA = node,-,-,B,6;
inst_DS_000_DMA = node,-,-,B,13;
CYCLE_DMA_0_ = node,-,-,F,1;
CYCLE_DMA_1_ = node,-,-,F,0;
SIZE_DMA_0_ = node,-,-,G,2;
SIZE_DMA_1_ = node,-,-,G,13;
inst_VPA_D = node,-,-,A,9;
inst_UDS_000_INT = node,-,-,D,14;
inst_LDS_000_INT = node,-,-,B,6;
inst_CLK_OUT_PRE_D = node,-,-,B,13;
CLK_000_D_8_ = node,-,-,E,6;
CLK_000_D_9_ = node,-,-,H,13;
inst_DTACK_D0 = node,-,-,C,7;
inst_RESET_OUT = node,-,-,G,9;
inst_VPA_D = node,-,-,A,5;
inst_DTACK_D0 = node,-,-,F,6;
inst_RESET_OUT = node,-,-,C,9;
CLK_000_D_1_ = node,-,-,H,5;
CLK_000_D_0_ = node,-,-,E,8;
inst_CLK_OUT_PRE_50 = node,-,-,A,2;
inst_CLK_OUT_PRE_25 = node,-,-,A,1;
IPL_D0_0_ = node,-,-,A,13;
IPL_D0_1_ = node,-,-,B,3;
IPL_D0_2_ = node,-,-,G,7;
CLK_000_D_2_ = node,-,-,H,6;
CLK_000_D_3_ = node,-,-,E,2;
CLK_000_D_4_ = node,-,-,D,3;
CLK_000_D_5_ = node,-,-,B,14;
CLK_000_D_6_ = node,-,-,B,10;
CLK_000_D_7_ = node,-,-,E,13;
CLK_000_D_10_ = node,-,-,F,6;
CLK_000_D_0_ = node,-,-,D,9;
inst_CLK_OUT_PRE_50 = node,-,-,F,2;
inst_CLK_OUT_PRE_25 = node,-,-,F,13;
inst_CLK_OUT_PRE_D = node,-,-,F,9;
IPL_D0_0_ = node,-,-,B,14;
IPL_D0_1_ = node,-,-,E,9;
IPL_D0_2_ = node,-,-,D,10;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,G,6;
inst_DS_000_ENABLE = node,-,-,F,1;
SM_AMIGA_6_ = node,-,-,A,8;
SM_AMIGA_4_ = node,-,-,F,2;
SM_AMIGA_0_ = node,-,-,F,12;
RST_DLY_0_ = node,-,-,G,10;
RST_DLY_1_ = node,-,-,G,3;
RST_DLY_2_ = node,-,-,G,14;
inst_CLK_030_H = node,-,-,C,6;
SM_AMIGA_1_ = node,-,-,F,8;
SM_AMIGA_5_ = node,-,-,F,13;
SM_AMIGA_3_ = node,-,-,F,9;
SM_AMIGA_2_ = node,-,-,F,5;
SM_AMIGA_i_7_ = node,-,-,F,4;
CIIN_0 = node,-,-,E,9;
inst_LDS_000_INT = node,-,-,F,12;
inst_DS_000_ENABLE = node,-,-,F,8;
inst_UDS_000_INT = node,-,-,D,6;
SM_AMIGA_6_ = node,-,-,C,13;
SM_AMIGA_4_ = node,-,-,F,4;
SM_AMIGA_1_ = node,-,-,A,1;
SM_AMIGA_0_ = node,-,-,H,13;
RST_DLY_0_ = node,-,-,C,6;
RST_DLY_1_ = node,-,-,C,14;
RST_DLY_2_ = node,-,-,C,10;
inst_CLK_030_H = node,-,-,B,10;
SM_AMIGA_5_ = node,-,-,A,12;
SM_AMIGA_3_ = node,-,-,A,13;
SM_AMIGA_2_ = node,-,-,A,9;
SM_AMIGA_i_7_ = node,-,-,A,8;
CIIN_0 = node,-,-,G,14;
[GROUP ASSIGNMENTS]
Layer = OFF;

24
Logic/68030_tk.nrp
View File

@ -1,24 +0,0 @@
ispLEVER Classic 2.0.00.17.20.15 SDFGEN
Copyright(C),1992-2015, Lattice Semiconductor Corporation. All Rights Reserved.
Output Files:
Netlist File: 68030_tk.vho
Delay File: 68030_tk.sdf
Parsing E:/ispLEVER_Classic2_0/ispcpld/dat/sdf.mdl
Input file: c:/users/matze/documents/github/68030tk/logic\68030_tk.tte
Reading library information ...
Mapping to combinational gates
Mapping to netlist view.
Note 18862: NODE name cpu_est_2_bus.D.X1 being renamed to GATE_cpu_est_2_bus_D_X1.
Note 18862: NODE name RST_DLY_1_bus.D.X1 being renamed to GATE_RST_DLY_1_bus_D_X1.
Note 18862: NODE name RST_DLY_1_bus.D.X2 being renamed to GATE_RST_DLY_1_bus_D_X2.
Note 18862: NODE name SM_AMIGA_3_bus.D.X1 being renamed to GATE_SM_AMIGA_3_bus_D_X1.
Note 18862: NODE name SM_AMIGA_3_bus.D.X2 being renamed to GATE_SM_AMIGA_3_bus_D_X2.
Note 18862: NODE name SM_AMIGA_i_7_bus.D.X1 being renamed to GATE_SM_AMIGA_i_7_bus_D_X1.
Note 18862: NODE name SM_AMIGA_i_7_bus.D.X2 being renamed to GATE_SM_AMIGA_i_7_bus_D_X2.
Note 18862: NODE name CIIN_0 being renamed to GATE_CIIN_OE.
Utilization Estimate
Combinational Macros: 524
Flip-Flop and Latch Macros: 61
I/O Pads: 61
Elapsed time: 1 seconds

12520
Logic/68030_tk.out
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File diff suppressed because it is too large Load Diff

170
Logic/68030_tk.plc
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@ -8,44 +8,47 @@
; Source file 68030_tk.tt4
; FITTER-generated Placements.
; DEVICE mach447a
; DATE Wed Aug 24 22:17:53 2016
; DATE Thu Aug 25 22:27:55 2016
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287
Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143
Pin 85 A_DECODE_23_
Pin 68 IPL_2_
Pin 58 FC_1_
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125
Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137
Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287
Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149
Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185
Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 163
Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 157
Pin 14 nEXP_SPACE
Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 157
Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143
Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 155
Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167
Pin 41 BERR Comb ; S6=1 S9=1 Pair 197
Pin 85 A_DECODE_23_
Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161
Pin 21 BG_030
Pin 84 A_DECODE_22_
Pin 94 A_DECODE_21_
Pin 93 A_DECODE_20_
Pin 28 BGACK_000
Pin 97 A_DECODE_19_
Pin 64 CLK_030
Pin 95 A_DECODE_18_
Pin 11 CLK_000
Pin 68 IPL_2_
Pin 59 A_DECODE_17_
Pin 61 CLK_OSZI
Pin 96 A_DECODE_16_
Pin 58 FC_1_
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101
Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185
Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
Pin 14 nEXP_SPACE
Pin 41 BERR Comb ; S6=1 S9=1 Pair 197
Pin 21 BG_030
Pin 28 BGACK_000
Pin 64 CLK_030
Pin 11 CLK_000
Pin 61 CLK_OSZI
Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247
Pin 56 IPL_1_
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271
Pin 67 IPL_0_
Pin 91 FPU_SENSE
Pin 57 FC_0_
Pin 60 A_1_
Pin 30 DTACK
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
Pin 66 E Comb ; S6=1 S9=1 Pair 251
@ -57,97 +60,86 @@ Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
Pin 56 IPL_1_
Pin 67 IPL_0_
Pin 57 FC_0_
Pin 60 A_1_
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131
Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133
Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 127
Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 283
Pin 35 VMA Reg ; S6=1 S9=1 Pair 173
Pin 71 RW Reg ; S6=1 S9=1 Pair 245
Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133
Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1
Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1
Node 281 RN_AS_030 Comb ; S6=1 S9=1
Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1
Node 203 RN_AS_000 Comb ; S6=1 S9=1
Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1
Node 137 RN_AHIGH_29_ Comb ; S6=1 S9=1
Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1
Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
Node 163 RN_AHIGH_27_ Comb ; S6=1 S9=1
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
Node 157 RN_AHIGH_26_ Comb ; S6=1 S9=1
Node 157 RN_AHIGH_27_ Comb ; S6=1 S9=1
Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1
Node 155 RN_AHIGH_26_ Comb ; S6=1 S9=1
Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1
Node 197 RN_BERR Comb ; S6=1 S9=1
Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1
Node 281 RN_AS_030 Comb ; S6=1 S9=1
Node 203 RN_AS_000 Comb ; S6=1 S9=1
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
Node 197 RN_BERR Comb ; S6=1 S9=1
Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1
Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1
Node 269 RN_RW_000 Reg ; S6=1 S9=1
Node 175 RN_BG_000 Reg ; S6=1 S9=1
Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
Node 283 RN_DSACK1 Reg ; S6=1 S9=1
Node 173 RN_VMA Reg ; S6=1 S9=1
Node 245 RN_RW Reg ; S6=1 S9=1
Node 257 RN_A_0_ Reg ; S6=1 S9=1
Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1
Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1
Node 176 cpu_est_3_ Reg ; S6=1 S9=1
Node 188 cpu_est_0_ Reg ; S6=1 S9=1
Node 193 cpu_est_1_ Reg ; S6=1 S9=1
Node 182 cpu_est_2_ Reg ; S6=1 S9=1
Node 109 inst_AS_000_INT Reg ; S6=1 S9=1
Node 154 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
Node 187 inst_AS_030_D0 Reg ; S6=1 S9=1
Node 119 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
Node 221 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
Node 152 inst_AS_000_DMA Reg ; S6=1 S9=1
Node 169 inst_DS_000_DMA Reg ; S6=1 S9=1
Node 170 CYCLE_DMA_0_ Reg ; S6=1 S9=1
Node 164 CYCLE_DMA_1_ Reg ; S6=1 S9=1
Node 283 RN_DSACK1 Reg ; S6=1 S9=1
Node 173 RN_VMA Reg ; S6=1 S9=1
Node 245 RN_RW Reg ; S6=1 S9=1
Node 217 un10_ciin_i Comb ; S6=1 S9=1
Node 176 cpu_est_0_ Reg ; S6=1 S9=1
Node 253 cpu_est_1_ Reg ; S6=1 S9=1
Node 259 cpu_est_2_ Reg ; S6=1 S9=1
Node 193 cpu_est_3_ Reg ; S6=1 S9=1
Node 229 inst_AS_000_INT Reg ; S6=1 S9=1
Node 260 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
Node 209 inst_AS_030_D0 Reg ; S6=1 S9=1
Node 152 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
Node 205 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
Node 134 inst_AS_000_DMA Reg ; S6=1 S9=1
Node 145 inst_DS_000_DMA Reg ; S6=1 S9=1
Node 223 CYCLE_DMA_0_ Reg ; S6=1 S9=1
Node 221 CYCLE_DMA_1_ Reg ; S6=1 S9=1
Node 248 SIZE_DMA_0_ Reg ; S6=1 S9=1
Node 265 SIZE_DMA_1_ Reg ; S6=1 S9=1
Node 115 inst_VPA_D Reg ; S6=1 S9=1
Node 194 inst_UDS_000_INT Reg ; S6=1 S9=1
Node 134 inst_LDS_000_INT Reg ; S6=1 S9=1
Node 145 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
Node 206 CLK_000_D_8_ Reg ; S6=1 S9=1
Node 289 CLK_000_D_9_ Reg ; S6=1 S9=1
Node 160 inst_DTACK_D0 Reg ; S6=1 S9=1
Node 259 inst_RESET_OUT Reg ; S6=1 S9=1
Node 109 inst_VPA_D Reg ; S6=1 S9=1
Node 230 inst_DTACK_D0 Reg ; S6=1 S9=1
Node 163 inst_RESET_OUT Reg ; S6=1 S9=1
Node 277 CLK_000_D_1_ Reg ; S6=1 S9=1
Node 209 CLK_000_D_0_ Reg ; S6=1 S9=1
Node 104 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
Node 103 inst_CLK_OUT_PRE_25 Reg ; S6=1 S9=1
Node 121 IPL_D0_0_ Reg ; S6=1 S9=1
Node 130 IPL_D0_1_ Reg ; S6=1 S9=1
Node 256 IPL_D0_2_ Reg ; S6=1 S9=1
Node 278 CLK_000_D_2_ Reg ; S6=1 S9=1
Node 200 CLK_000_D_3_ Reg ; S6=1 S9=1
Node 178 CLK_000_D_4_ Reg ; S6=1 S9=1
Node 146 CLK_000_D_5_ Reg ; S6=1 S9=1
Node 140 CLK_000_D_6_ Reg ; S6=1 S9=1
Node 217 CLK_000_D_7_ Reg ; S6=1 S9=1
Node 230 CLK_000_D_10_ Reg ; S6=1 S9=1
Node 187 CLK_000_D_0_ Reg ; S6=1 S9=1
Node 224 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
Node 241 inst_CLK_OUT_PRE_25 Reg ; S6=1 S9=1
Node 235 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
Node 146 IPL_D0_0_ Reg ; S6=1 S9=1
Node 211 IPL_D0_1_ Reg ; S6=1 S9=1
Node 188 IPL_D0_2_ Reg ; S6=1 S9=1
Node 254 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
Node 223 inst_DS_000_ENABLE Reg ; S6=1 S9=1
Node 113 SM_AMIGA_6_ Reg ; S6=1 S9=1
Node 224 SM_AMIGA_4_ Reg ; S6=1 S9=1
Node 239 SM_AMIGA_0_ Reg ; S6=1 S9=1
Node 260 RST_DLY_0_ Reg ; S6=1 S9=1
Node 250 RST_DLY_1_ Reg ; S6=1 S9=1
Node 266 RST_DLY_2_ Reg ; S6=1 S9=1
Node 158 inst_CLK_030_H Reg ; S6=1 S9=1
Node 233 SM_AMIGA_1_ Reg ; S6=1 S9=1
Node 241 SM_AMIGA_5_ Reg ; S6=1 S9=1
Node 235 SM_AMIGA_3_ Reg ; S6=1 S9=1
Node 229 SM_AMIGA_2_ Reg ; S6=1 S9=1
Node 227 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
Node 211 CIIN_0 Comb ; S6=1 S9=1
Node 239 inst_LDS_000_INT Reg ; S6=1 S9=1
Node 233 inst_DS_000_ENABLE Reg ; S6=1 S9=1
Node 182 inst_UDS_000_INT Reg ; S6=1 S9=1
Node 169 SM_AMIGA_6_ Reg ; S6=1 S9=1
Node 227 SM_AMIGA_4_ Reg ; S6=1 S9=1
Node 103 SM_AMIGA_1_ Reg ; S6=1 S9=1
Node 289 SM_AMIGA_0_ Reg ; S6=1 S9=1
Node 158 RST_DLY_0_ Reg ; S6=1 S9=1
Node 170 RST_DLY_1_ Reg ; S6=1 S9=1
Node 164 RST_DLY_2_ Reg ; S6=1 S9=1
Node 140 inst_CLK_030_H Reg ; S6=1 S9=1
Node 119 SM_AMIGA_5_ Reg ; S6=1 S9=1
Node 121 SM_AMIGA_3_ Reg ; S6=1 S9=1
Node 115 SM_AMIGA_2_ Reg ; S6=1 S9=1
Node 113 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
Node 266 CIIN_0 Comb ; S6=1 S9=1
; Unused Pins & Nodes
; -> None Found.

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Logic/68030_tk.tal
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@ -45,10 +45,11 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. ..
CYCLE_DMA_1_ 1 2 .. .. .. .. 1 1
SIZE_DMA_0_ 1 1 1 1 .. .. 2 2
SIZE_DMA_1_ 1 1 1 1 .. .. 2 2
inst_UDS_000_INT 1 1 1 1 .. .. 2 2
inst_LDS_000_INT 1 1 1 1 .. .. 2 2
inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
inst_UDS_000_INT 1 1 1 1 .. .. 2 2
inst_CLK_030_H 1 2 .. .. .. .. 1 1
CIIN_0 .. .. .. .. 1 2 .. ..
AS_030 .. .. .. .. 1 1 .. ..
AS_000 .. .. .. .. 1 1 .. ..
CIIN .. .. .. .. 1 1 .. ..
@ -58,55 +59,46 @@ inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
RN_RW_000 1 1 0 0 .. .. 1 1
BG_000 1 1 0 0 .. .. 1 1
RN_BG_000 1 1 0 0 .. .. 1 1
DSACK1 1 1 0 0 .. .. 1 1
RN_DSACK1 1 1 0 0 .. .. 1 1
VMA 1 1 0 0 .. .. 1 1
RN_VMA 1 1 0 0 .. .. 1 1
RW 1 1 0 0 .. .. 1 1
RN_RW 1 1 0 0 .. .. 1 1
A_0_ 1 1 0 0 .. .. 1 1
RN_A_0_ 1 1 0 0 .. .. 1 1
IPL_030_1_ 1 1 0 0 .. .. 1 1
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
IPL_030_0_ 1 1 0 0 .. .. 1 1
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
cpu_est_3_ .. .. 1 1 .. .. 1 1
DSACK1 1 1 0 0 .. .. 1 1
RN_DSACK1 1 1 0 0 .. .. 1 1
VMA 1 1 0 0 .. .. 1 1
RN_VMA 1 1 0 0 .. .. 1 1
RW 1 1 0 0 .. .. 1 1
RN_RW 1 1 0 0 .. .. 1 1
un10_ciin_i .. .. .. .. 1 1 .. ..
cpu_est_0_ .. .. .. .. .. .. 1 1
cpu_est_1_ .. .. 1 1 .. .. 1 1
cpu_est_2_ .. .. 1 1 .. .. 1 1
cpu_est_3_ .. .. 1 1 .. .. 1 1
inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. ..
inst_AS_030_000_SYNC 1 1 1 1 .. .. 1 1
inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1
inst_VPA_D 1 1 .. .. .. .. 1 1
inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1
CLK_000_D_8_ .. .. .. .. .. .. 1 1
CLK_000_D_9_ .. .. .. .. .. .. 1 1
inst_DTACK_D0 1 1 .. .. .. .. 1 1
inst_RESET_OUT 1 1 .. .. .. .. .. ..
CLK_000_D_1_ .. .. .. .. .. .. 1 1
CLK_000_D_0_ 1 1 .. .. .. .. 1 1
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
inst_CLK_OUT_PRE_25 .. .. .. .. .. .. 1 1
inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1
IPL_D0_0_ 1 1 .. .. .. .. 1 1
IPL_D0_1_ 1 1 .. .. .. .. 1 1
IPL_D0_2_ 1 1 .. .. .. .. 1 1
CLK_000_D_2_ .. .. .. .. .. .. 1 1
CLK_000_D_3_ .. .. .. .. .. .. 1 1
CLK_000_D_4_ .. .. .. .. .. .. 1 1
CLK_000_D_5_ .. .. .. .. .. .. 1 1
CLK_000_D_6_ .. .. .. .. .. .. 1 1
CLK_000_D_7_ .. .. .. .. .. .. 1 1
CLK_000_D_10_ .. .. .. .. .. .. 1 1
inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. ..
SM_AMIGA_6_ 1 1 .. .. .. .. 1 1
SM_AMIGA_4_ 1 1 .. .. .. .. 1 1
SM_AMIGA_1_ 1 1 .. .. .. .. 1 1
SM_AMIGA_0_ 1 1 .. .. .. .. 1 1
RST_DLY_0_ 1 1 .. .. .. .. 1 1
RST_DLY_1_ 1 1 .. .. .. .. 1 1
RST_DLY_2_ 1 1 .. .. .. .. 1 1
SM_AMIGA_1_ 1 1 .. .. .. .. 1 1
SM_AMIGA_5_ 1 1 .. .. .. .. 1 1
SM_AMIGA_3_ 1 1 .. .. .. .. 1 1
SM_AMIGA_2_ 1 1 .. .. .. .. 1 1
SM_AMIGA_i_7_ 1 1 .. .. .. .. 1 1
CIIN_0 .. .. .. .. 1 1 .. ..
SM_AMIGA_i_7_ 1 1 .. .. .. .. 1 1

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Logic/68030_tk.tt3
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Logic/68030_tk.tt4
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@ -1,285 +1,266 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 24 22:17:49 2016
#$ DATE Thu Aug 25 22:27:51 2016
#$ MODULE BUS68030
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 SIZE_0_ AS_000
AHIGH_30_ AHIGH_29_ DS_030 AHIGH_28_ UDS_000 AHIGH_27_ LDS_000 AHIGH_26_
nEXP_SPACE AHIGH_25_ BERR AHIGH_24_ BG_030 A_DECODE_22_ A_DECODE_21_
A_DECODE_20_ BGACK_000 A_DECODE_19_ CLK_030 A_DECODE_18_ CLK_000 A_DECODE_17_
CLK_OSZI A_DECODE_16_ CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET
#$ PINS 61 AHIGH_30_ AHIGH_29_ SIZE_1_ AHIGH_28_ AHIGH_27_ AHIGH_31_ AHIGH_26_
AHIGH_25_ A_DECODE_23_ AHIGH_24_ A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
A_DECODE_19_ A_DECODE_18_ IPL_2_ A_DECODE_17_ A_DECODE_16_ FC_1_ AS_030 AS_000
DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
CLK_DIV_OUT IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ A_1_ DTACK AVEC E VPA RST RESET
AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH
CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1
VMA RW A_0_ IPL_030_1_ IPL_030_0_
#$ NODES 52 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AS_000_INT
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC
inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_
SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT
inst_CLK_OUT_PRE_D CLK_000_D_8_ CLK_000_D_9_ inst_DTACK_D0 inst_RESET_OUT
CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 IPL_D0_0_
IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_
CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_10_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_
RST_DLY_2_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_
SM_AMIGA_i_7_ CIIN_0
CIIN SIZE_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ IPL_030_0_
CLK_EXP DSACK1 VMA RW
#$ NODES 44 un10_ciin_i cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_
inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_DTACK_D0
inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25
inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_
SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H
SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
.type f
.i 104
.o 178
.i 96
.o 161
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
BGACK_030.Q VMA.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q
inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
BGACK_030.Q un10_ciin_i VMA.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q
cpu_est_3_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q
CLK_000_D_8_.Q CLK_000_D_9_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q
CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q IPL_D0_0_.Q
IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q
CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_10_.Q
inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q inst_DS_000_ENABLE.Q SM_AMIGA_6_.Q
SM_AMIGA_4_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
A_0_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q
SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN
AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
inst_VPA_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q
inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q
IPL_D0_1_.Q IPL_D0_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q
SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q
RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q
SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q
AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN
AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE SIZE_0_
SIZE_0_.OE AS_000% AS_000.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE
DS_030% DS_030.OE AHIGH_28_ AHIGH_28_.OE UDS_000% UDS_000.OE AHIGH_27_
AHIGH_27_.OE LDS_000% LDS_000.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE
BERR BERR.OE AHIGH_24_ AHIGH_24_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS% AVEC E
RESET RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW%
AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C
RW_000.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C
DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% RW.C RW.OE A_0_.D A_0_.C A_0_.OE
IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C cpu_est_3_.D cpu_est_3_.C
.ob AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE SIZE_1_ SIZE_1_.OE AHIGH_28_
AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_31_ AHIGH_31_.OE AHIGH_26_
AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AS_030% AS_030.OE
AS_000% AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR
BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS% AVEC E RESET RESET.OE
AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH
CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C
RW_000.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C A_0_.D A_0_.C A_0_.OE
IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C CLK_EXP.D CLK_EXP.C
DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% RW.C RW.OE un10_ciin_i%
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D.X1
cpu_est_2_.D.X2 cpu_est_2_.C inst_AS_000_INT.D% inst_AS_000_INT.C
inst_AMIGA_BUS_ENABLE_DMA_LOW.D% inst_AMIGA_BUS_ENABLE_DMA_LOW.C
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.end

523
Logic/68030_tk.tte
View File

@ -1,285 +1,266 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Wed Aug 24 22:17:49 2016
#$ DATE Thu Aug 25 22:27:51 2016
#$ MODULE BUS68030
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 SIZE_0_ AS_000
AHIGH_30_ AHIGH_29_ DS_030 AHIGH_28_ UDS_000 AHIGH_27_ LDS_000 AHIGH_26_
nEXP_SPACE AHIGH_25_ BERR AHIGH_24_ BG_030 A_DECODE_22_ A_DECODE_21_
A_DECODE_20_ BGACK_000 A_DECODE_19_ CLK_030 A_DECODE_18_ CLK_000 A_DECODE_17_
CLK_OSZI A_DECODE_16_ CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET
#$ PINS 61 AHIGH_30_ AHIGH_29_ SIZE_1_ AHIGH_28_ AHIGH_27_ AHIGH_31_ AHIGH_26_
AHIGH_25_ A_DECODE_23_ AHIGH_24_ A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
A_DECODE_19_ A_DECODE_18_ IPL_2_ A_DECODE_17_ A_DECODE_16_ FC_1_ AS_030 AS_000
DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
CLK_DIV_OUT IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ A_1_ DTACK AVEC E VPA RST RESET
AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH
CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1
VMA RW A_0_ IPL_030_1_ IPL_030_0_
#$ NODES 52 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AS_000_INT
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC
inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_
SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT
inst_CLK_OUT_PRE_D CLK_000_D_8_ CLK_000_D_9_ inst_DTACK_D0 inst_RESET_OUT
CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 IPL_D0_0_
IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_
CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_10_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_
RST_DLY_2_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_
SM_AMIGA_i_7_ CIIN_0
CIIN SIZE_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ IPL_030_0_
CLK_EXP DSACK1 VMA RW
#$ NODES 44 un10_ciin_i cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_
inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_DTACK_D0
inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25
inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_
SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H
SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
.type f
.i 104
.o 178
.i 96
.o 161
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
BGACK_030.Q VMA.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q
inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
BGACK_030.Q un10_ciin_i VMA.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q
cpu_est_3_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q
CLK_000_D_8_.Q CLK_000_D_9_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q
CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q IPL_D0_0_.Q
IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q
CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_10_.Q
inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q inst_DS_000_ENABLE.Q SM_AMIGA_6_.Q
SM_AMIGA_4_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
A_0_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q
SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN
AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
inst_VPA_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q
inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q
IPL_D0_1_.Q IPL_D0_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q
SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q
RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q
SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q
AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN
AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE SIZE_0_
SIZE_0_.OE AS_000- AS_000.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE
DS_030- DS_030.OE AHIGH_28_ AHIGH_28_.OE UDS_000- UDS_000.OE AHIGH_27_
AHIGH_27_.OE LDS_000- LDS_000.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE
BERR BERR.OE AHIGH_24_ AHIGH_24_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS- AVEC E
RESET RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW-
AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C
RW_000.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C
DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE A_0_.D A_0_.C A_0_.OE
IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C cpu_est_3_.D cpu_est_3_.C
.ob AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE SIZE_1_ SIZE_1_.OE AHIGH_28_
AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_31_ AHIGH_31_.OE AHIGH_26_
AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AS_030- AS_030.OE
AS_000- AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR
BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS- AVEC E RESET RESET.OE
AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH
CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C
RW_000.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C A_0_.D A_0_.C A_0_.OE
IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C CLK_EXP.D CLK_EXP.C
DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE un10_ciin_i-
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D.X1
cpu_est_2_.D.X2 cpu_est_2_.C inst_AS_000_INT.D- inst_AS_000_INT.C
inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C
inst_AS_030_D0.D- inst_AS_030_D0.C inst_AS_030_000_SYNC.D-
inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C
inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C
CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D-
SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C
inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_8_.D CLK_000_D_8_.C
CLK_000_D_9_.D CLK_000_D_9_.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D
inst_RESET_OUT.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C
cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C inst_AS_000_INT.D-
inst_AS_000_INT.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C
inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D-
inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D
inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C
SIZE_DMA_0_.D- SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D-
inst_VPA_D.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C
CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_25.D
inst_CLK_OUT_PRE_25.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C
IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D
CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C
CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C CLK_000_D_10_.D
CLK_000_D_10_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C
SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_0_.D
SM_AMIGA_0_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2
RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.D.X1
SM_AMIGA_3_.D.X2 SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D.X1
SM_AMIGA_i_7_.D.X2 SM_AMIGA_i_7_.C CIIN_0
.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 203
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-------------------------------------------------------------------------------------------------------- 0000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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--1--1---0------0010--1--------------------------------------------------------------0------------------ 0000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D-
IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C
inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
inst_LDS_000_INT.D inst_LDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C
inst_UDS_000_INT.D- inst_UDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D
SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C
RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C
RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_5_.D
SM_AMIGA_5_.C SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 SM_AMIGA_3_.C SM_AMIGA_2_.D
SM_AMIGA_2_.C SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 SM_AMIGA_i_7_.C CIIN_0-
.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 192
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.end

92
Logic/68030_tk.vcl
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 8/24/16;
TIME = 22:17:53;
DATE = 8/25/16;
TIME = 22:27:55;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@ -142,11 +142,11 @@ layer = OFF;
Layer = OFF
AS_000 = OUTPUT,42,4,-;
RW_000 = BIDIR,80,7,-;
AS_030 = OUTPUT,82,7,-;
BERR = OUTPUT,41,4,-;
RW_000 = BIDIR,80,7,-;
A_0_ = BIDIR,69,6,-;
RW = BIDIR,71,6,-;
AS_030 = OUTPUT,82,7,-;
UDS_000 = OUTPUT,32,3,-;
LDS_000 = OUTPUT,31,3,-;
SIZE_1_ = OUTPUT,79,7,-;
@ -162,9 +162,9 @@ AHIGH_31_ = OUTPUT,4,1,-;
IPL_030_2_ = OUTPUT,9,1,-;
IPL_030_0_ = OUTPUT,8,1,-;
IPL_030_1_ = OUTPUT,7,1,-;
DSACK1 = OUTPUT,81,7,-;
BGACK_030 = OUTPUT,83,7,-;
VMA = OUTPUT,35,3,-;
DSACK1 = OUTPUT,81,7,-;
E = OUTPUT,66,6,-;
AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-;
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-;
@ -179,65 +179,57 @@ AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
CLK_EXP = OUTPUT,10,1,-;
RESET = OUTPUT,3,1,-;
RN_BGACK_030 = NODE,-1,7,-;
inst_RESET_OUT = NODE,*,6,-;
CLK_000_D_0_ = NODE,*,4,-;
inst_RESET_OUT = NODE,*,2,-;
CLK_000_D_0_ = NODE,*,3,-;
CLK_000_D_1_ = NODE,*,7,-;
SM_AMIGA_6_ = NODE,*,0,-;
inst_AS_030_D0 = NODE,*,3,-;
inst_AS_030_000_SYNC = NODE,*,0,-;
cpu_est_1_ = NODE,*,3,-;
SM_AMIGA_6_ = NODE,*,2,-;
inst_AS_030_D0 = NODE,*,4,-;
inst_AS_030_000_SYNC = NODE,*,2,-;
cpu_est_3_ = NODE,*,3,-;
inst_CLK_OUT_PRE_D = NODE,*,1,-;
inst_BGACK_030_INT_D = NODE,*,5,-;
cpu_est_2_ = NODE,*,3,-;
SM_AMIGA_i_7_ = NODE,*,5,-;
inst_DS_000_DMA = NODE,*,2,-;
inst_AS_000_DMA = NODE,*,2,-;
cpu_est_1_ = NODE,*,6,-;
cpu_est_0_ = NODE,*,3,-;
cpu_est_2_ = NODE,*,6,-;
SM_AMIGA_i_7_ = NODE,*,0,-;
inst_DS_000_DMA = NODE,*,1,-;
inst_AS_000_DMA = NODE,*,1,-;
CYCLE_DMA_1_ = NODE,*,5,-;
RN_VMA = NODE,-1,3,-;
SM_AMIGA_1_ = NODE,*,5,-;
SM_AMIGA_0_ = NODE,*,5,-;
SM_AMIGA_5_ = NODE,*,0,-;
SM_AMIGA_0_ = NODE,*,7,-;
SM_AMIGA_1_ = NODE,*,0,-;
SM_AMIGA_4_ = NODE,*,5,-;
inst_DS_000_ENABLE = NODE,*,5,-;
inst_LDS_000_INT = NODE,*,1,-;
inst_LDS_000_INT = NODE,*,5,-;
SIZE_DMA_1_ = NODE,*,6,-;
SIZE_DMA_0_ = NODE,*,6,-;
cpu_est_0_ = NODE,*,3,-;
CYCLE_DMA_0_ = NODE,*,5,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,6,-;
inst_CLK_OUT_PRE_25 = NODE,*,0,-;
inst_AS_000_INT = NODE,*,0,-;
CLK_000_D_9_ = NODE,*,7,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,6,-;
inst_AS_000_INT = NODE,*,5,-;
inst_CLK_OUT_PRE_D = NODE,*,5,-;
inst_VPA_D = NODE,*,0,-;
inst_BGACK_030_INT_D = NODE,*,4,-;
RN_IPL_030_0_ = NODE,-1,1,-;
RN_IPL_030_1_ = NODE,-1,1,-;
RN_IPL_030_2_ = NODE,-1,1,-;
inst_CLK_030_H = NODE,*,2,-;
RN_DSACK1 = NODE,-1,7,-;
inst_CLK_030_H = NODE,*,1,-;
RN_RW_000 = NODE,-1,7,-;
SM_AMIGA_2_ = NODE,*,5,-;
SM_AMIGA_3_ = NODE,*,5,-;
RST_DLY_0_ = NODE,*,6,-;
CYCLE_DMA_1_ = NODE,*,2,-;
SM_AMIGA_2_ = NODE,*,0,-;
SM_AMIGA_3_ = NODE,*,0,-;
RST_DLY_0_ = NODE,*,2,-;
RN_A_0_ = NODE,-1,6,-;
SM_AMIGA_5_ = NODE,*,5,-;
SM_AMIGA_4_ = NODE,*,5,-;
CYCLE_DMA_0_ = NODE,*,2,-;
RN_RW = NODE,-1,6,-;
RN_DSACK1 = NODE,-1,7,-;
RN_BG_000 = NODE,-1,3,-;
CIIN_0 = NODE,*,4,-;
RST_DLY_2_ = NODE,*,6,-;
RST_DLY_1_ = NODE,*,6,-;
RST_DLY_2_ = NODE,*,2,-;
RST_DLY_1_ = NODE,*,2,-;
inst_UDS_000_INT = NODE,*,3,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,2,-;
CLK_000_D_10_ = NODE,*,5,-;
CLK_000_D_7_ = NODE,*,4,-;
CLK_000_D_6_ = NODE,*,1,-;
CLK_000_D_5_ = NODE,*,1,-;
CLK_000_D_4_ = NODE,*,3,-;
CLK_000_D_3_ = NODE,*,4,-;
CLK_000_D_2_ = NODE,*,7,-;
IPL_D0_2_ = NODE,*,6,-;
IPL_D0_1_ = NODE,*,1,-;
IPL_D0_0_ = NODE,*,0,-;
inst_CLK_OUT_PRE_50 = NODE,*,0,-;
inst_DTACK_D0 = NODE,*,2,-;
CLK_000_D_8_ = NODE,*,4,-;
inst_CLK_OUT_PRE_25 = NODE,*,5,-;
CIIN_0 = NODE,*,6,-;
IPL_D0_2_ = NODE,*,3,-;
IPL_D0_1_ = NODE,*,4,-;
IPL_D0_0_ = NODE,*,1,-;
inst_CLK_OUT_PRE_50 = NODE,*,5,-;
inst_DTACK_D0 = NODE,*,5,-;
un10_ciin_i = NODE,*,4,-;
CLK_OSZI = INPUT,61,-,-;

142
Logic/68030_tk.vco
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 8/24/16;
TIME = 22:17:53;
DATE = 8/25/16;
TIME = 22:27:55;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@ -141,41 +141,44 @@ layer = OFF;
[LOCATION ASSIGNMENT]
Layer = OFF;
SIZE_1_ = BIDIR,79, H,-;
AHIGH_31_ = BIDIR,4, B,-;
A_DECODE_23_ = INPUT,85, H,-;
IPL_2_ = INPUT,68, G,-;
FC_1_ = INPUT,58, F,-;
AS_030 = BIDIR,82, H,-;
SIZE_0_ = BIDIR,70, G,-;
AS_000 = BIDIR,42, E,-;
AHIGH_30_ = BIDIR,5, B,-;
AHIGH_29_ = BIDIR,6, B,-;
DS_030 = OUTPUT,98, A,-;
SIZE_1_ = BIDIR,79, H,-;
AHIGH_28_ = BIDIR,15, C,-;
UDS_000 = BIDIR,32, D,-;
AHIGH_27_ = BIDIR,16, C,-;
LDS_000 = BIDIR,31, D,-;
AHIGH_31_ = BIDIR,4, B,-;
AHIGH_26_ = BIDIR,17, C,-;
nEXP_SPACE = INPUT,14,-,-;
AHIGH_25_ = BIDIR,18, C,-;
BERR = BIDIR,41, E,-;
A_DECODE_23_ = INPUT,85, H,-;
AHIGH_24_ = BIDIR,19, C,-;
BG_030 = INPUT,21, C,-;
A_DECODE_22_ = INPUT,84, H,-;
A_DECODE_21_ = INPUT,94, A,-;
A_DECODE_20_ = INPUT,93, A,-;
BGACK_000 = INPUT,28, D,-;
A_DECODE_19_ = INPUT,97, A,-;
CLK_030 = INPUT,64,-,-;
A_DECODE_18_ = INPUT,95, A,-;
CLK_000 = INPUT,11,-,-;
IPL_2_ = INPUT,68, G,-;
A_DECODE_17_ = INPUT,59, F,-;
CLK_OSZI = INPUT,61,-,-;
A_DECODE_16_ = INPUT,96, A,-;
FC_1_ = INPUT,58, F,-;
AS_030 = BIDIR,82, H,-;
AS_000 = BIDIR,42, E,-;
DS_030 = OUTPUT,98, A,-;
UDS_000 = BIDIR,32, D,-;
LDS_000 = BIDIR,31, D,-;
nEXP_SPACE = INPUT,14,-,-;
BERR = BIDIR,41, E,-;
BG_030 = INPUT,21, C,-;
BGACK_000 = INPUT,28, D,-;
CLK_030 = INPUT,64,-,-;
CLK_000 = INPUT,11,-,-;
CLK_OSZI = INPUT,61,-,-;
CLK_DIV_OUT = OUTPUT,65, G,-;
IPL_1_ = INPUT,56, F,-;
FPU_CS = OUTPUT,78, H,-;
IPL_0_ = INPUT,67, G,-;
FPU_SENSE = INPUT,91, A,-;
FC_0_ = INPUT,57, F,-;
A_1_ = INPUT,60, F,-;
DTACK = INPUT,30, D,-;
AVEC = OUTPUT,92, A,-;
E = OUTPUT,66, G,-;
@ -187,70 +190,59 @@ AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
CIIN = OUTPUT,47, E,-;
IPL_1_ = INPUT,56, F,-;
IPL_0_ = INPUT,67, G,-;
FC_0_ = INPUT,57, F,-;
A_1_ = INPUT,60, F,-;
SIZE_0_ = BIDIR,70, G,-;
IPL_030_2_ = OUTPUT,9, B,-;
RW_000 = BIDIR,80, H,-;
BG_000 = OUTPUT,29, D,-;
BGACK_030 = OUTPUT,83, H,-;
A_0_ = BIDIR,69, G,-;
IPL_030_1_ = OUTPUT,7, B,-;
IPL_030_0_ = OUTPUT,8, B,-;
CLK_EXP = OUTPUT,10, B,-;
DSACK1 = OUTPUT,81, H,-;
VMA = OUTPUT,35, D,-;
RW = BIDIR,71, G,-;
A_0_ = BIDIR,69, G,-;
IPL_030_1_ = OUTPUT,7, B,-;
IPL_030_0_ = OUTPUT,8, B,-;
cpu_est_3_ = NODE,2, D,-;
cpu_est_0_ = NODE,10, D,-;
cpu_est_1_ = NODE,13, D,-;
cpu_est_2_ = NODE,6, D,-;
inst_AS_000_INT = NODE,5, A,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,3, C,-;
inst_AS_030_D0 = NODE,9, D,-;
inst_AS_030_000_SYNC = NODE,12, A,-;
inst_BGACK_030_INT_D = NODE,0, F,-;
inst_AS_000_DMA = NODE,2, C,-;
inst_DS_000_DMA = NODE,13, C,-;
CYCLE_DMA_0_ = NODE,14, C,-;
CYCLE_DMA_1_ = NODE,10, C,-;
un10_ciin_i = NODE,13, E,-;
cpu_est_0_ = NODE,2, D,-;
cpu_est_1_ = NODE,5, G,-;
cpu_est_2_ = NODE,9, G,-;
cpu_est_3_ = NODE,13, D,-;
inst_AS_000_INT = NODE,5, F,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,10, G,-;
inst_AS_030_D0 = NODE,8, E,-;
inst_AS_030_000_SYNC = NODE,2, C,-;
inst_BGACK_030_INT_D = NODE,5, E,-;
inst_AS_000_DMA = NODE,6, B,-;
inst_DS_000_DMA = NODE,13, B,-;
CYCLE_DMA_0_ = NODE,1, F,-;
CYCLE_DMA_1_ = NODE,0, F,-;
SIZE_DMA_0_ = NODE,2, G,-;
SIZE_DMA_1_ = NODE,13, G,-;
inst_VPA_D = NODE,9, A,-;
inst_UDS_000_INT = NODE,14, D,-;
inst_LDS_000_INT = NODE,6, B,-;
inst_CLK_OUT_PRE_D = NODE,13, B,-;
CLK_000_D_8_ = NODE,6, E,-;
CLK_000_D_9_ = NODE,13, H,-;
inst_DTACK_D0 = NODE,7, C,-;
inst_RESET_OUT = NODE,9, G,-;
inst_VPA_D = NODE,5, A,-;
inst_DTACK_D0 = NODE,6, F,-;
inst_RESET_OUT = NODE,9, C,-;
CLK_000_D_1_ = NODE,5, H,-;
CLK_000_D_0_ = NODE,8, E,-;
inst_CLK_OUT_PRE_50 = NODE,2, A,-;
inst_CLK_OUT_PRE_25 = NODE,1, A,-;
IPL_D0_0_ = NODE,13, A,-;
IPL_D0_1_ = NODE,3, B,-;
IPL_D0_2_ = NODE,7, G,-;
CLK_000_D_2_ = NODE,6, H,-;
CLK_000_D_3_ = NODE,2, E,-;
CLK_000_D_4_ = NODE,3, D,-;
CLK_000_D_5_ = NODE,14, B,-;
CLK_000_D_6_ = NODE,10, B,-;
CLK_000_D_7_ = NODE,13, E,-;
CLK_000_D_10_ = NODE,6, F,-;
CLK_000_D_0_ = NODE,9, D,-;
inst_CLK_OUT_PRE_50 = NODE,2, F,-;
inst_CLK_OUT_PRE_25 = NODE,13, F,-;
inst_CLK_OUT_PRE_D = NODE,9, F,-;
IPL_D0_0_ = NODE,14, B,-;
IPL_D0_1_ = NODE,9, E,-;
IPL_D0_2_ = NODE,10, D,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,6, G,-;
inst_DS_000_ENABLE = NODE,1, F,-;
SM_AMIGA_6_ = NODE,8, A,-;
SM_AMIGA_4_ = NODE,2, F,-;
SM_AMIGA_0_ = NODE,12, F,-;
RST_DLY_0_ = NODE,10, G,-;
RST_DLY_1_ = NODE,3, G,-;
RST_DLY_2_ = NODE,14, G,-;
inst_CLK_030_H = NODE,6, C,-;
SM_AMIGA_1_ = NODE,8, F,-;
SM_AMIGA_5_ = NODE,13, F,-;
SM_AMIGA_3_ = NODE,9, F,-;
SM_AMIGA_2_ = NODE,5, F,-;
SM_AMIGA_i_7_ = NODE,4, F,-;
CIIN_0 = NODE,9, E,-;
inst_LDS_000_INT = NODE,12, F,-;
inst_DS_000_ENABLE = NODE,8, F,-;
inst_UDS_000_INT = NODE,6, D,-;
SM_AMIGA_6_ = NODE,13, C,-;
SM_AMIGA_4_ = NODE,4, F,-;
SM_AMIGA_1_ = NODE,1, A,-;
SM_AMIGA_0_ = NODE,13, H,-;
RST_DLY_0_ = NODE,6, C,-;
RST_DLY_1_ = NODE,14, C,-;
RST_DLY_2_ = NODE,10, C,-;
inst_CLK_030_H = NODE,10, B,-;
SM_AMIGA_5_ = NODE,12, A,-;
SM_AMIGA_3_ = NODE,13, A,-;
SM_AMIGA_2_ = NODE,9, A,-;
SM_AMIGA_i_7_ = NODE,8, A,-;
CIIN_0 = NODE,14, G,-;

3976
Logic/68030_tk.vho
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2
Logic/68030_tk.xrf
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@ -2,7 +2,7 @@ Signal Name Cross Reference File
ispLEVER Classic 2.0.00.17.20.15
Design '68030_tk' created Wed Aug 24 22:17:49 2016
Design '68030_tk' created Thu Aug 25 22:27:51 2016
LEGEND: '>' Functional Block Port Separator

2738
Logic/BUS68030.bl0
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2744
Logic/BUS68030.bl1
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3953
Logic/BUS68030.edi
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2
Logic/BUS68030.prj
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@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Wed Aug 24 22:17:35 2016
#-- Written on Thu Aug 25 22:27:39 2016
#device options

5266
Logic/BUS68030.srm
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17
Logic/BUS68030.srr
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@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Wed Aug 24 22:17:42 2016
#Thu Aug 25 22:27:46 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
@ -27,6 +27,7 @@ Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 2 of CLK_000_D_3(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
@ -42,10 +43,10 @@ State machine has 8 reachable states with original encodings of:
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 24 22:17:43 2016
# Thu Aug 25 22:27:46 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -55,7 +56,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 24 22:17:44 2016
# Thu Aug 25 22:27:48 2016
###########################################################]
Map & Optimize Report
@ -79,13 +80,13 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFF 62 uses
DFF 53 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 38 uses
OBUF 15 uses
AND2 289 uses
INV 262 uses
AND2 286 uses
INV 258 uses
OR2 25 uses
XOR2 6 uses
@ -97,6 +98,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 24 22:17:44 2016
# Thu Aug 25 22:27:48 2016
###########################################################]

BIN
Logic/BUS68030.srs
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971
Logic/bus68030.exf
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9
Logic/bus68030.srf
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@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Wed Aug 24 22:17:42 2016
#Thu Aug 25 22:27:46 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
@ -27,6 +27,7 @@ Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 2 of CLK_000_D_3(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
@ -42,10 +43,10 @@ State machine has 8 reachable states with original encodings of:
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 24 22:17:43 2016
# Thu Aug 25 22:27:46 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -55,6 +56,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 24 22:17:44 2016
# Thu Aug 25 22:27:48 2016
###########################################################]

2
Logic/run_options.txt
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@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version I-2014.03LC
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Wed Aug 24 22:17:42 2016
#-- Written on Thu Aug 25 22:27:46 2016
#project files

2
Logic/synlog/BUS68030_multi_srs_gen.srr
View File

@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 24 22:17:44 2016
# Thu Aug 25 22:27:48 2016
###########################################################]

8
Logic/synlog/bus68030_fpga_mapper.srr
View File

@ -17,13 +17,13 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFF 62 uses
DFF 53 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 38 uses
OBUF 15 uses
AND2 289 uses
INV 262 uses
AND2 286 uses
INV 258 uses
OR2 25 uses
XOR2 6 uses
@ -35,6 +35,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 24 22:17:44 2016
# Thu Aug 25 22:27:48 2016
###########################################################]

4
Logic/synlog/report/BUS68030_compiler_errors.txt
View File

@ -1,3 +1,3 @@
@E: CD415 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":489:6:489:7|Expecting keyword process
@E|Parse errors encountered - exiting
@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":504:12:504:22|No matching overload for "="
@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":549:12:549:26|No matching overload for "="

4
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>7</data>
<data>8</data>
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1472069863</data>
<data type="timestamp">1472156866</data>
</info>
</job_info>
</job_run_status>

1
Logic/synlog/report/BUS68030_compiler_warnings.txt
View File

@ -4,5 +4,6 @@
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 2 of CLK_000_D_3(12 downto 0) -- not in use ...
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused

2
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>105MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1472069864</data>
<data type="timestamp">1472156868</data>
</info>
</job_info>
</job_run_status>

57
Logic/syntmp/BUS68030_srr.htm
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@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1472069862>
<!@TC:1472156866>
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: E:\ispLEVER_Classic2_0\synpbase
#OS: Windows 7 6.2
@ -8,28 +8,29 @@
#Implementation: logic
<a name=compilerReport1>$ Start of Compile</a>
#Wed Aug 24 22:17:42 2016
#Thu Aug 25 22:27:46 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1472069863> | Running in 64-bit mode
@N: : <!@TM:1472156866> | Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1472069863> | Setting time resolution to ns
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1472069863> | Top entity is set to BUS68030.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1472156866> | Setting time resolution to ns
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1472156866> | Top entity is set to BUS68030.
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1472069863> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1472069863> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1472069863> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:128:7:128:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(128)</a><!@TM:1472069863> | Signal clk_out_pre is undriven </font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1472156866> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1472156866> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1472156866> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:128:7:128:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(128)</a><!@TM:1472156866> | Signal clk_out_pre is undriven </font>
Post processing for work.bus68030.behavioral
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069863> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069863> | Pruning register nEXP_SPACE_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069863> | Pruning register BGACK_030_INT_PRE_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1472069863> | Pruning register CLK_OUT_EXP_INT_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:154:2:154:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(154)</a><!@TM:1472069863> | Pruning register CLK_030_D0_2 </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069863> | Trying to extract state machine for register SM_AMIGA
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Pruning register nEXP_SPACE_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Pruning register BGACK_030_INT_PRE_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1472156866> | Pruning register CLK_OUT_EXP_INT_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:154:2:154:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(154)</a><!@TM:1472156866> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Pruning bits 12 to 2 of CLK_000_D_3(12 downto 0) -- not in use ... </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -40,24 +41,24 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069863> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1472069863> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156866> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1472156866> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 24 22:17:43 2016
# Thu Aug 25 22:27:46 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1472069864> | Running in 64-bit mode
@N: : <!@TM:1472156868> | Running in 64-bit mode
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 24 22:17:44 2016
# Thu Aug 25 22:27:48 2016
###########################################################]
Map & Optimize Report
@ -65,8 +66,8 @@ Map & Optimize Report
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1472069864> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N::@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069864> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1472156868> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N::@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472156868> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -81,25 +82,25 @@ original code -> new code
<a name=resourceUsage3>Resource Usage Report</a>
Simple gate primitives:
DFF 62 uses
DFF 53 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 38 uses
OBUF 15 uses
AND2 289 uses
INV 262 uses
AND2 286 uses
INV 258 uses
OR2 25 uses
XOR2 6 uses
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1472069864> | Timing Report not generated for this device, please use place and route tools for timing analysis.
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1472156868> | Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 24 22:17:44 2016
# Thu Aug 25 22:27:48 2016
###########################################################]

2
Logic/syntmp/BUS68030_toc.htm
View File

@ -16,7 +16,7 @@
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
<ul rel="open" >
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (22:17 24-Aug)</a>
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (22:27 25-Aug)</a>
<ul ></ul></li> </ul>
</li>
</ul>

2
Logic/syntmp/run_option.xml
View File

@ -3,7 +3,7 @@
Synopsys, Inc.
Version I-2014.03LC
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Wed Aug 24 22:17:42 2016
Written on Thu Aug 25 22:27:46 2016
-->

8
Logic/syntmp/statusReport.html
View File

@ -33,12 +33,12 @@
<tr>
<td class="optionTitle">Compile Input</td><td>Complete</td>
<td>8</td>
<td>7</td>
<td>8</td>
<td>0</td>
<td>-</td>
<td>0m:01s</td>
<td>-</td>
<td><font size="-1">24.08.2016</font><br/><font size="-2">22:17:43</font></td>
<td><font size="-1">25.08.2016</font><br/><font size="-2">22:27:46</font></td>
</tr>
<tr>
@ -49,12 +49,12 @@
<td>0m:00s</td>
<td>0m:00s</td>
<td>105MB</td>
<td><font size="-1">24.08.2016</font><br/><font size="-2">22:17:44</font></td>
<td><font size="-1">25.08.2016</font><br/><font size="-2">22:27:48</font></td>
</tr>
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">24.08.2016</font><br/><font size="-2">22:17:44</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">25.08.2016</font><br/><font size="-2">22:27:48</font></td> </tbody>
</table>
</td></tr></table></body>
</html>

2
Logic/synwork/BUS68030_comp.fdep
View File

@ -9,7 +9,7 @@
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1472069842
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1472156857
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

2
Logic/synwork/BUS68030_comp.fdeporig
View File

@ -9,7 +9,7 @@
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1472069842
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1472156857
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_comp.srs
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Binary file not shown.

1
Logic/synwork/BUS68030_comp.tlg
View File

@ -8,6 +8,7 @@ Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 2 of CLK_000_D_3(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:

BIN
Logic/synwork/BUS68030_mult.srs
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BIN
Logic/synwork/BUS68030_mult_srs/skeleton.srs
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BIN
Logic/synwork/BUS68030_s.srs
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