Tristating bus drivers

Logic/68030-68000-bus.vhd

@@ -141,7 +141,7 @@ signal	CLK_000_PE: STD_LOGIC 		:= '0';
 signal	CLK_000_NE: STD_LOGIC 		:= '0';
 signal	CLK_000_NE_D0: STD_LOGIC 		:= '0';
 signal	DTACK_D0: STD_LOGIC 		:= '1';
-	
+signal	RESET_DLY:	STD_LOGIC_VECTOR ( 7 downto 0 ) 	:= "00000000";
 
 begin
 
@@ -225,6 +225,18 @@ begin
 	CLK_DIV_OUT	<= CLK_OUT_PRE_D;
 	CLK_EXP		<= CLK_OUT_PRE_D;
 
+	-- i need to delay the board reset by some eclocks, so everything is synced fine afeter a soft reset!
+	reset_delay_machine: process(RST, CLK_OSZI)
+	begin
+		if(RST = '0' ) then
+			RESET_DLY		<= "00000000";	
+		elsif(rising_edge(CLK_OSZI)) then
+			--reset delay: wait 128 E-Clocks!
+			if(CLK_000_NE_D0 = '1' and cpu_est = E1 and RESET = '0') then
+				RESET_DLY <= RESET_DLY +1;
+			end if;
+		end if;
+	end process reset_delay_machine;
 
 	--the state machine
 	state_machine: process(RST, CLK_OSZI)
@@ -260,8 +272,10 @@ begin
 			DS_030_D0		<= '1';
 			CLK_030_H		<= '0';	
 		elsif(rising_edge(CLK_OSZI)) then
-			--reset buffer
+			--reset buffer 
-			RESET <= '1';
+			if(RESET_DLY="01111111")then
+				RESET <= '1';
+			end if;
 
 			--now: 68000 state machine and signals
 			
@@ -479,11 +493,11 @@ begin
 
 
 	-- bus drivers
-	AMIGA_ADDR_ENABLE	<= AMIGA_BUS_ENABLE_INT;
+	AMIGA_ADDR_ENABLE	<= AMIGA_BUS_ENABLE_INT WHEN AS_030='0' ELSE '1';
-	AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' AND AMIGA_BUS_ENABLE_INT ='0' ELSE 
+	AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' AND AMIGA_BUS_ENABLE_INT ='0' AND AS_030='0' ELSE 
-							 '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
+							 '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' AND AS_000_DMA='0' ELSE
 							 '1';
-	AMIGA_BUS_ENABLE_LOW <=  '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE
+	AMIGA_BUS_ENABLE_LOW <=  '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' AND AS_000_DMA='0' ELSE
 							 '1';  
 	
 	

Logic/68030_TK.STY

@@ -1,4 +1,4 @@
 [STRATEGY-LIST]
-Normal=True, 1385910337
+Normal=True, 1412327082
 [synthesis-type]
 tool=Synplify

Logic/68030_TK.syn

@@ -4,8 +4,6 @@ PROJECT 68030_TK
 DESIGN 68030_tk Normal
 DEVKIT M4A5-128/64-10VC
 ENTRY Pure VHDL
-MODULE 2to3divider.vhd
-MODSTYLE clk_div_2by3 Normal
 MODULE 68030-68000-bus.vhd
 MODSTYLE BUS68030 Normal
 SYNTHESIS_TOOL Synplify

Logic/68030_tk.crf

@@ -1,7 +1,7 @@
 // Signal Name Cross Reference File
 // ispLEVER Classic 1.7.00.05.28.13
 
-// Design '68030_tk' created Thu Oct 02 23:55:21 2014
+// Design '68030_tk' created Sun Oct 05 00:12:41 2014
 
 
 // LEGEND:  '>'  Functional Block Port Separator

Logic/BUS68030.prj

@@ -1,6 +1,6 @@
 #-- Lattice Semiconductor Corporation Ltd.
 #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
-#-- Written on Thu Oct 02 23:55:15 2014
+#-- Written on Sun Oct 05 00:12:34 2014
 
 
 #device options

Logic/Programming.xcf

@@ -19,8 +19,8 @@
 				<BScanVal>0</BScanVal>
 			</Bypass>
 			<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
-			<FileTime>09/06/14 22:01:13</FileTime>
+			<FileTime>10/05/14 00:12:48</FileTime>
-			<JedecChecksum>0x1CFA</JedecChecksum>
+			<JedecChecksum>0x0375</JedecChecksum>
 			<Operation>Erase,Program,Verify</Operation>
 			<Option>
 				<SVFVendor>JTAG STANDARD</SVFVendor>

Logic/bus68030.srf

@@ -6,7 +6,7 @@
 #Implementation: logic
 
 $ Start of Compile
-#Thu Oct 02 23:55:15 2014
+#Sun Oct 05 00:12:35 2014
 
 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
 @N|Running in 64-bit mode
@@ -15,8 +15,8 @@ Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentatio
 @N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
 @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
+@W: CD266 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":235:47:235:51|reset is not readable.  This may cause a simulation mismatch.
 VHDL syntax check successful!
-File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
 @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
 @W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized 
 @W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven 
@@ -47,7 +47,7 @@ State machine has 8 reachable states with original encodings of:
    111
 @END
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Oct 02 23:55:15 2014
+# Sun Oct 05 00:12:35 2014
 
 ###########################################################]
 Map & Optimize Report
@@ -71,26 +71,26 @@ original code -> new code
 Resource Usage Report
 
 Simple gate primitives:
-DFFSH           28 uses
+DFFRH           18 uses
-DFFRH           10 uses
 DFF             34 uses
+DFFSH           28 uses
 BI_DIR          13 uses
 IBUF            31 uses
 OBUF            16 uses
 BUFTH           1 use
-AND2            215 uses
+AND2            244 uses
-INV             176 uses
+INV             186 uses
-OR2             23 uses
+OR2             21 uses
-XOR2            1 use
+XOR2            9 uses
 
 
 @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
 G-2012.09LC-SP1 
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Oct 02 23:55:17 2014
+# Sun Oct 05 00:12:36 2014
 
 ###########################################################]

Logic/run_options.txt

@@ -1,7 +1,7 @@
 #--  Synopsys, Inc.
 #--  Version G-2012.09LC-SP1 
 #--  Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
-#--  Written on Thu Oct 02 23:55:15 2014
+#--  Written on Sun Oct 05 00:12:35 2014
 
 
 #project files

Logic/synlog/bus68030_fpga_mapper.srr

@@ -17,26 +17,26 @@ original code -> new code
 Resource Usage Report
 
 Simple gate primitives:
-DFFSH           28 uses
+DFFRH           18 uses
-DFFRH           10 uses
 DFF             34 uses
+DFFSH           28 uses
 BI_DIR          13 uses
 IBUF            31 uses
 OBUF            16 uses
 BUFTH           1 use
-AND2            215 uses
+AND2            244 uses
-INV             176 uses
+INV             186 uses
-OR2             23 uses
+OR2             21 uses
-XOR2            1 use
+XOR2            9 uses
 
 
 @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
 G-2012.09LC-SP1 
 Mapper successful!
 
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Oct 02 23:55:17 2014
+# Sun Oct 05 00:12:36 2014
 
 ###########################################################]

Logic/synlog/report/BUS68030_compiler_errors.txt

@@ -1,3 +1,3 @@
-@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:35:152:35|No identifier "no_reset" in scope
+@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":496:50:496:50|No identifier "as" in scope
 @E|Parse errors encountered - exiting
 

Logic/synlog/report/BUS68030_compiler_runstatus.xml

@@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
   <report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
   </info>
 			<info name="Warnings">
-  <data>14</data>
+  <data>15</data>
   <report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
   </info>
 			<info name="Errors">
@@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
   <data>-</data>
   </info>
 			<info name="Date &amp;Time">
-  <data type="timestamp">1412286915</data>
+  <data type="timestamp">1412460755</data>
   </info>
 			</job_info>
 </job_run_status>

Logic/synlog/report/BUS68030_compiler_warnings.txt

@@ -1,3 +1,4 @@
+@W: CD266 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":235:47:235:51|reset is not readable.  This may cause a simulation mismatch.
 @W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized 
 @W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven 
 @W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:22|Signal clk_out_pre_33_d is undriven 

Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml

@@ -36,10 +36,10 @@ The file contains the job information from mapper to be displayed as part of the
 <data>0h:00m:00s</data>
 </info>
 <info name="Peak Memory">
-<data>95MB</data>
+<data>96MB</data>
 </info>
 <info name="Date &amp; Time">
-<data type="timestamp">1412286917</data>
+<data type="timestamp">1412460756</data>
 </info>
 </job_info>
 </job_run_status>

Logic/syntmp/run_option.xml

@@ -3,7 +3,7 @@
   Synopsys, Inc.
   Version G-2012.09LC-SP1 
   Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
-  Written on Thu Oct 02 23:55:15 2014
+  Written on Sun Oct 05 00:12:35 2014
 
 
 --> 

Logic/synwork/BUS68030_compiler.fdep

@@ -10,7 +10,7 @@
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412286909
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412460751
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)

Logic/synwork/BUS68030_compiler.fdeporig

@@ -10,7 +10,7 @@
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412286909
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412460751
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)