mirror of https://github.com/kr239/68030tk.git
43 lines
1.9 KiB
Plaintext
43 lines
1.9 KiB
Plaintext
Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
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Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
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Product Version I-2014.03LC
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@N: MF248 |Running in 64-bit mode.
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@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030)
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Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
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original code -> new code
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000 -> 00000000
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001 -> 00000011
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010 -> 00000101
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011 -> 00001001
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100 -> 00010001
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101 -> 00100001
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110 -> 01000001
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111 -> 10000001
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@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":190:4:190:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
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@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
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---------------------------------------
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Resource Usage Report
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Simple gate primitives:
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DFF 83 uses
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BI_DIR 11 uses
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IBUF 46 uses
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OBUF 15 uses
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BUFTH 3 uses
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AND2 303 uses
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INV 263 uses
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XOR2 15 uses
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OR2 28 uses
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@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
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I-2014.03LC
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Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Wed May 13 22:59:16 2015
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###########################################################]
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