Merge branch 'master' of github.com:rdolbeau/NuBusFPGA

nubus-to-ztex-gateware/DepVideoEqu.a

@@ -1 +0,0 @@
-NuBusFPGAID EQU $BEEF

nubus-to-ztex-gateware/NuBusFPGAPrimaryInit.a

@@ -1 +0,0 @@
-             DC.B sExec2         ; code revision

nubus-to-ztex-gateware/nubus_to_fpga_export.py

@@ -88,8 +88,10 @@ def get_csr_header_split(regions, constants, csr_base=None, with_access_function
         if not isinstance(region.obj, Memory):
             for csr in region.obj:
                 nr = (csr.size + region.busword - 1)//region.busword
-                r += _get_rw_functions_c(csr.name, origin, nr, region.busword, alignment,
-                    getattr(csr, "read_only", False), with_access_functions)
+                r += _get_rw_functions_c(reg_name=csr.name, reg_base=origin, nwords=nr, busword=region.busword, alignment=alignment,
+                                         read_only=getattr(csr, "read_only", False),
+                                         csr_base=0, with_csr_base_define=False,
+                                         with_access_functions=with_access_functions)
                 origin += alignment//8*nr
                 if hasattr(csr, "fields"):
                     for field in csr.fields.fields:

nubus-to-ztex-gateware/nubus_to_fpga_soc.py

@@ -181,6 +181,7 @@ class NuBusFPGA(SoCCore):
                          sys_clk_freq=sys_clk_freq,
                          clk_freq=sys_clk_freq,
                          csr_paging=0x800, #  default is 0x800
+                         bus_interconnect = "crossbar",
                          **kwargs)
 
         # Quoting the doc:

nubus-to-ztex-gateware/sdram_init.py

@@ -28,7 +28,7 @@ sdram_dfii_pi0_baddress =      sdram_dfii_base + 0x010
 # /!\ keep up to date with csr /!\
 ddrphy_base = 0xf0a00000
 ddrphy_rst                 = ddrphy_base + 0x000
-ddrphy_dly_sel             = ddrphy_base + 0x010
+ddrphy_dly_sel             = ddrphy_base + 0x004
 ddrphy_rdly_dq_rst         = ddrphy_base + 0x014
 ddrphy_rdly_dq_inc         = ddrphy_base + 0x018
 ddrphy_rdly_dq_bitslip_rst = ddrphy_base + 0x01c