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https://github.com/rdolbeau/NuBusFPGA.git
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Merge branch 'master' of github.com:rdolbeau/NuBusFPGA
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@@ -1 +0,0 @@
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NuBusFPGAID EQU $BEEF
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@@ -1 +0,0 @@
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DC.B sExec2 ; code revision
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Submodule nubus-to-ztex-gateware/VintageBusFPGA_Common updated: c7d117677e...342358535e
@@ -88,8 +88,10 @@ def get_csr_header_split(regions, constants, csr_base=None, with_access_function
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if not isinstance(region.obj, Memory):
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if not isinstance(region.obj, Memory):
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for csr in region.obj:
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for csr in region.obj:
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nr = (csr.size + region.busword - 1)//region.busword
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nr = (csr.size + region.busword - 1)//region.busword
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r += _get_rw_functions_c(csr.name, origin, nr, region.busword, alignment,
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r += _get_rw_functions_c(reg_name=csr.name, reg_base=origin, nwords=nr, busword=region.busword, alignment=alignment,
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getattr(csr, "read_only", False), with_access_functions)
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read_only=getattr(csr, "read_only", False),
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csr_base=0, with_csr_base_define=False,
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with_access_functions=with_access_functions)
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origin += alignment//8*nr
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origin += alignment//8*nr
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if hasattr(csr, "fields"):
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if hasattr(csr, "fields"):
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for field in csr.fields.fields:
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for field in csr.fields.fields:
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@@ -181,6 +181,7 @@ class NuBusFPGA(SoCCore):
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sys_clk_freq=sys_clk_freq,
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sys_clk_freq=sys_clk_freq,
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clk_freq=sys_clk_freq,
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clk_freq=sys_clk_freq,
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csr_paging=0x800, # default is 0x800
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csr_paging=0x800, # default is 0x800
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bus_interconnect = "crossbar",
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**kwargs)
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**kwargs)
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# Quoting the doc:
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# Quoting the doc:
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File diff suppressed because one or more lines are too long
@@ -28,7 +28,7 @@ sdram_dfii_pi0_baddress = sdram_dfii_base + 0x010
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# /!\ keep up to date with csr /!\
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# /!\ keep up to date with csr /!\
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ddrphy_base = 0xf0a00000
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ddrphy_base = 0xf0a00000
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ddrphy_rst = ddrphy_base + 0x000
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ddrphy_rst = ddrphy_base + 0x000
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ddrphy_dly_sel = ddrphy_base + 0x010
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ddrphy_dly_sel = ddrphy_base + 0x004
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ddrphy_rdly_dq_rst = ddrphy_base + 0x014
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ddrphy_rdly_dq_rst = ddrphy_base + 0x014
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ddrphy_rdly_dq_inc = ddrphy_base + 0x018
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ddrphy_rdly_dq_inc = ddrphy_base + 0x018
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ddrphy_rdly_dq_bitslip_rst = ddrphy_base + 0x01c
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ddrphy_rdly_dq_bitslip_rst = ddrphy_base + 0x01c
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