try to improve use_sampling by sampling synchronously to nubus_clk everything but the clock
This commit is contained in:
Romain Dolbeau
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c6e33c5caf
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d461da9d8b
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@ -20,12 +20,13 @@ class NuBus(Module):
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#led1 = platform.request("user_led", 1)
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if (usesampling):
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# when using 'sampling', the NuBus signals are sampled at sys_clk frequency instead of synchronously using nubus_clk
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# when using 'sampling', the NuBus clock is sampled at sys_clk frequency instead of used directly
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# the other signals are still sampled synchronously, and the buffer used from sysclk afterwards
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# I'm not completely sure about timings, but in practice it seems to work...
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# The major benefit is that when a read is detected, it is sent to the Wishbone synchronously as the signals are already in sys_clk
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# And when Wishbone answers, we just wait for the next detected NuBus edge to answer
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# It significantly improves read latency
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# Writes don't see the same improvement, are they always are fire-and-forget in a FIFO anyway
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# Writes don't see the same improvement, as they always are fire-and-forget in a FIFO anyway
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nub_clk = ClockSignal(cd_nubus)
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nub_resetn = ~ResetSignal(cd_nubus)
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nub_clk_prev_bits = 4 # how many cycles after posedge do we still dare set some signals (i.e. still before setup time before negedge)
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@ -39,10 +40,16 @@ class NuBus(Module):
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self.sync += [
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nub_clk_prev[i].eq(nub_clk_prev[i-1]) for i in range(1, nub_clk_prev_bits)
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]
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self.sync += [
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nub_clk_negedge.eq(~nub_clk & nub_clk_prev[0]),
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nub_clk_posedge.eq( nub_clk & ~nub_clk_prev[0]),
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nub_clk_insetup.eq( nub_clk & (nub_clk_prev != ((2**nub_clk_prev_bits)-1))), # if one of the previous X cycles is zero, we're early enough to set up signals
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#self.sync += [
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# nub_clk_negedge.eq(~nub_clk & nub_clk_prev[0]),
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# nub_clk_posedge.eq( nub_clk & ~nub_clk_prev[0]),
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# nub_clk_insetup.eq( nub_clk & (nub_clk_prev != ((2**nub_clk_prev_bits)-1))), # if one of the previous X cycles is zero, we're early enough to set up signals
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#]
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# this should use double sampling; however using [1] and [2] break, perhaps the detection is too late?
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self.comb += [
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nub_clk_negedge.eq(~nub_clk_prev[0] & nub_clk_prev[1]),
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nub_clk_posedge.eq( nub_clk_prev[0] & ~nub_clk_prev[1]),
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nub_clk_insetup.eq( nub_clk_prev[0] & (nub_clk_prev[1:nub_clk_prev_bits] != ((2**(nub_clk_prev_bits-1))-1))), # if one of the previous X cycles is zero, we're early enough to set up signals
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]
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# Signals for tri-stated nubus access
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@ -148,66 +155,34 @@ class NuBus(Module):
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write_fifo_din = Record(write_fifo_layout)
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self.comb += write_fifo.din.eq(write_fifo_din.raw_bits())
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if (usesampling):
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# sys_clk sampling of the nubus signals
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self.sync += [
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#If((~nub_clk & nub_clk_prev[0]), # simultaneous with setting negedge
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If(nub_clk_negedge,
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sampled_tm0.eq(~tm0_i_n),
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sampled_tm1.eq(~tm1_i_n),
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sampled_start.eq(~start_i_n),
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sampled_rqst.eq(~rqst_i_n),
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sampled_ack.eq(~ack_i_n),
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sampled_ad.eq(~ad_i_n),
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)
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]
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self.comb += [
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decoded_block.eq(sampled_ad[1] & ~sampled_ad[0] & ~sampled_tm0), # 1x block write or 1x block read
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decoded_sel[3].eq(sampled_tm1 & sampled_ad[1] & sampled_ad[0] & sampled_tm0 # Byte 3
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| sampled_tm1 & sampled_ad[1] & sampled_ad[0] & ~sampled_tm0 # Half 1
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| sampled_tm1 & ~sampled_ad[1] & ~sampled_ad[0] & ~sampled_tm0 # Word
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),
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decoded_sel[2].eq(sampled_tm1 & sampled_ad[1] & ~sampled_ad[0] & sampled_tm0 # Byte 2
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| sampled_tm1 & sampled_ad[1] & sampled_ad[0] & ~sampled_tm0 # Half 1
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| sampled_tm1 & ~sampled_ad[1] & ~sampled_ad[0] & ~sampled_tm0 # Word
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),
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decoded_sel[1].eq(sampled_tm1 & ~sampled_ad[1] & sampled_ad[0] & sampled_tm0 # Byte 1
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| sampled_tm1 & ~sampled_ad[1] & sampled_ad[0] & ~sampled_tm0 # Half 0
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| sampled_tm1 & ~sampled_ad[1] & ~sampled_ad[0] & ~sampled_tm0 # Word
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),
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decoded_sel[0].eq(sampled_tm1 & ~sampled_ad[1] & ~sampled_ad[0] & sampled_tm0 # Byte 0
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| sampled_tm1 & ~sampled_ad[1] & sampled_ad[0] & ~sampled_tm0 # Half 0
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| sampled_tm1 & ~sampled_ad[1] & ~sampled_ad[0] & ~sampled_tm0 # Word
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),
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]
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else:
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# nubus-synchronous sampling (in Verilog for negedge)
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self.specials += Instance("nubus_sampling",
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i_nub_clkn = ClockSignal(cd_nubus),
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i_nub_resetn = ~ResetSignal(cd_nubus),
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i_nub_tm0n = tm0_i_n,
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i_nub_tm1n = tm1_i_n,
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i_nub_startn = start_i_n,
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i_nub_rqstn = rqst_i_n,
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i_nub_ackn = ack_i_n,
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i_nub_adn = ad_i_n,
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o_tm0 = sampled_tm0,
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o_tm1 = sampled_tm1,
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o_start = sampled_start,
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o_rqst = sampled_rqst,
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o_ack = sampled_ack,
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o_ad = sampled_ad,
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o_sel = decoded_sel,
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o_block = decoded_block,
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o_busy = decoded_busy,
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)
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# nubus-synchronous sampling (in Verilog for negedge)
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self.specials += Instance("nubus_sampling",
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i_nub_clkn = ClockSignal(cd_nubus),
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i_nub_resetn = ~ResetSignal(cd_nubus),
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i_nub_tm0n = tm0_i_n,
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i_nub_tm1n = tm1_i_n,
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i_nub_startn = start_i_n,
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i_nub_rqstn = rqst_i_n,
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i_nub_ackn = ack_i_n,
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i_nub_adn = ad_i_n,
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o_tm0 = sampled_tm0,
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o_tm1 = sampled_tm1,
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o_start = sampled_start,
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o_rqst = sampled_rqst,
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o_ack = sampled_ack,
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o_ad = sampled_ad,
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o_sel = decoded_sel,
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o_block = decoded_block,
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o_busy = decoded_busy,
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)
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self.read_ctr = read_ctr = Signal(32)
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self.writ_ctr = writ_ctr = Signal(32)
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if (usesampling):
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# ############# usesampling FSM
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self.submodules.slave_fsm = slave_fsm = FSM(reset_state="Reset")
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slave_fsm.act("Reset",
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NextState("Idle")
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@ -324,7 +299,9 @@ class NuBus(Module):
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ack_o_n.eq(0),
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NextState("Idle"),
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)
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# ############# end of usesampling FSM
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else:
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# ############# non-usesampling FSM
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self.submodules.slave_fsm = slave_fsm = ClockDomainsRenamer(cd_nubus)(FSM(reset_state="Reset"))
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slave_fsm.act("Reset",
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NextState("Idle")
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@ -381,6 +358,7 @@ class NuBus(Module):
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NextState("Idle"),
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)
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)
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# ############# end of non-usesampling FSM
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# connect the write FIFO inputs
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self.comb += [ write_fifo_din.adr.eq(current_adr), # recorded
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@ -800,16 +778,6 @@ class NuBus(Module):
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nf_fpga_to_cpld_signal.eq(~rqst_oe),
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]
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if (usesampling):
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self.sync += [
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If((~nub_clk & nub_clk_prev[0]), # simultaneous with setting negedge
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decoded_busy.eq(~decoded_busy & nub_ackn & ~nub_startn # beginning of transaction
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| decoded_busy & nub_ackn & nub_resetn), # hold during cycle
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)
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]
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if (version == "V1.2"):
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self.nubus_oe = nubus_oe = Signal() # improveme
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self.specials += Instance("nubus_cpldinfpga",
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