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86a6afbd39
...
d9535db3be
@ -1 +1 @@
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|||||||
Subproject commit 0de12910a247bd96f3e90db971de137c6e5ffa43
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Subproject commit bd8d1da000db1c705581670c5307219e46f3f3fc
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@ -1,10 +1,8 @@
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|||||||
(
|
(
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||||||
#source /opt/Xilinx/Vivado/2020.1/settings64.sh
|
source /opt/Xilinx/Vivado/2020.1/settings64.sh
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||||||
#export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2020.1/lib/lnx64.o/SuSE
|
export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2020.1/lib/lnx64.o/SuSE
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||||||
source /opt/Xilinx/Vivado/2023.2/settings64.sh
|
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||||||
export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2023.2/lib/lnx64.o/SuSE
|
|
||||||
|
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||||||
python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi --config-flash # --ethernet # --sdcard # --flash
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python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi --sdcard --config-flash # --ethernet # --flash
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||||||
|
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#python3 nubus_to_fpga_soc.py --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6
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#python3 nubus_to_fpga_soc.py --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6
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||||||
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@ -18,7 +16,6 @@ grep '^\$\$' build_V1_2.log
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|||||||
|
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||||||
|
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||||||
###
|
###
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||||||
# --flash
|
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||||||
# For 16 MiB Flash NOR (W25Q128.V):
|
# For 16 MiB Flash NOR (W25Q128.V):
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||||||
# truncate -s $((16*1024*1024)) vid_decl_rom.bin
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# truncate -s $((16*1024*1024)) vid_decl_rom.bin
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# flashrom -c W25Q128.V -p linux_spi:dev=/dev/spidev0.0,spispeed=2000 -l nubus_prom.layout -i ROM -w vid_decl_rom.bin
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# flashrom -c W25Q128.V -p linux_spi:dev=/dev/spidev0.0,spispeed=2000 -l nubus_prom.layout -i ROM -w vid_decl_rom.bin
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||||||
@ -28,10 +25,3 @@ grep '^\$\$' build_V1_2.log
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|||||||
# 00000000:00007fff ROM
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# 00000000:00007fff ROM
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||||||
# 00008000:00ffffff VDISK
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# 00008000:00ffffff VDISK
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||||||
###
|
###
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||||||
|
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||||||
###
|
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||||||
# --config-flash
|
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||||||
# vid_decl_rom.bin goes directly to sector 40 of the internal flash:
|
|
||||||
###
|
|
||||||
# sudo java -jar FlashSend.jar -n 40 -f rom_V1_2.bin -w
|
|
||||||
###
|
|
||||||
|
168
nubus-to-ztex-gateware/mc68030_fsm.py
Normal file
168
nubus-to-ztex-gateware/mc68030_fsm.py
Normal file
@ -0,0 +1,168 @@
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|||||||
|
from migen import *
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||||||
|
from migen.genlib.fifo import *
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||||||
|
from migen.genlib.cdc import *
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||||||
|
from migen.fhdl.specials import Tristate
|
||||||
|
|
||||||
|
import litex
|
||||||
|
from litex.soc.interconnect import wishbone
|
||||||
|
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||||||
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class MC68030_SYNC_FSM(Module):
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||||||
|
def __init__(self, platform, wb_read, wb_write, cd_m68k="m68k"):
|
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|
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||||||
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# 68030
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||||||
|
A = platform.request("A") # 32 # address, I[O]
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||||||
|
D = platform.request("D") # 32 # data, IO
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||||||
|
RW_n = platform.request("RW_n") # direction of bus transfer with respect to the main processor, I [three-state, high read, write low]
|
||||||
|
DS_n = platform.request("DS_n") # data strobe, I[O]
|
||||||
|
BERR_n = platform.request("BERR_n") # bus error, [I]O
|
||||||
|
HALT_n = platform.request("HALT_n") # Signal indicating that main processor should suspend all bus activity, O
|
||||||
|
SIZ_n = platform.request("SIZ") # 2 # in conjunction with processor’s dynamic bus sizing capabilities to indicate number of bytes remaining to be transferred during current bus cycle, I [three-state]
|
||||||
|
|
||||||
|
FC = platform.request("FC") # 3 # Function code used to identify address space of current bus cycle, I[O]
|
||||||
|
# RESET_n = platform.request("RESET_n") # Bidirectional signal that initiates system reset.
|
||||||
|
# RMC = platform.request("RMC") # identifies current bus cycle as part of indivisible read-modify-write operation, three-state
|
||||||
|
# DSACK_n = platform.request("DSACK_n") # 2 # Data transfer acknowledge, I[O]
|
||||||
|
# CBREQ_n = platform.request("CBREQ_n") # CPU burst reuqest, I ?
|
||||||
|
# CBACK_n = platform.request("CBACK_n") # CPU burst ack, w/ STERM, IO ?
|
||||||
|
#STERM_n = platform.request("STERM_n") # indicates termination of a transfer using the MC68030 synchronous cycle, [I]O
|
||||||
|
# in this version STERM is negated by the driver
|
||||||
|
STERM = platform.request("STERM") # indicates termination of a transfer using the MC68030 synchronous cycle, [I]O
|
||||||
|
|
||||||
|
CPU_AS_n = platform.request("CPU_AS_n") # address strobe, I [three-state]
|
||||||
|
# CIOUT_n = platform.request("CIOUT_n") # cache inhibit out (from cpu), I
|
||||||
|
|
||||||
|
# BR_n = platform.request("BR_n") # bus request, I
|
||||||
|
# CPU_BG_n = platform.request("CPU_BG_n") # processor bus grant, I ?
|
||||||
|
# BGACK_n = platform.request("BGACK_n") # bus grant ack, I
|
||||||
|
|
||||||
|
# IPL = platform.request("IPL") # 3 # Interrupt priority-level lines.
|
||||||
|
## DBEN_n not in PDS slot (buffer enable)
|
||||||
|
## CIIN_n not in PDS slot (cache in inhibit)
|
||||||
|
## OCS_n not in PDS slot (operand cycle start)
|
||||||
|
## ECS_n not in PDS slot (external cycle start) # is on IIfx
|
||||||
|
|
||||||
|
# not 68030
|
||||||
|
# CACHE = platform.request("CACHE")
|
||||||
|
# CLK16M not connected
|
||||||
|
# CPU_CLK = platform.request("CPU_CLK") # handled in CRG
|
||||||
|
# CPU_DISABLE_n = platform.request("CPU_DISABLE_n") # Disables the MC68030 CPU (and MC68882 FPU, if installed) on the main logic board. This signal is used by a PDS card that replaces the main processor.
|
||||||
|
# CPU_TYPE = platform.request("CPU_TYPE") # Defines bus protocol for the PDS; logical one (1) for MC68020 and MC68030, logical zero (0) for MC68040. # not in IIci
|
||||||
|
# FC3 not connected # Additional function code bit, used to indicate that the software is running in 32-bit address mode. (As in the Macintosh LC II, the software always runs in 32-bit mode.) # not in IIci
|
||||||
|
# FPU_SEL_n = platform.request("FPU_SEL_n") # Select signal for an optional MC68881 or MC68882 FPU on the card. # not in IIci
|
||||||
|
# PDS_AS not connected (16 MHz AS)
|
||||||
|
# PDS_DSACK not connected (16 MHz DSACK)
|
||||||
|
# 16MASTER not connected (grounded on board for 32 bits)
|
||||||
|
# SLOT_BG_n = platform.request("SLOT_BG_n") # Bus grant signal to the expansion card. # not in IIci
|
||||||
|
SLOTIRQ_E_n = platform.request("SLOTIRQ_n") # IRQ for (pseudo-)slot E # not in IIci
|
||||||
|
# SLOTIRQ_C_n # not supported on LCIII/LC520 # IRQ for (pseudo-)slot C # not in IIci
|
||||||
|
# SLOTIRQ_D_n # not supported on LCIII/LC520 # IRQ for (pseudo-)slot D # not in IIci
|
||||||
|
# SNDOUT not connected (Apple II-style sound) # not in IIci
|
||||||
|
# # ROMOE_n only in IIci
|
||||||
|
# # BUSLOCK_n only in SE/30, IIsi (nubus bus lock)
|
||||||
|
# # NUBUS_n only in SE/30, IIsi (signal nubus access)
|
||||||
|
# # BCLK only in SE/30, IIsi (VIA clock)
|
||||||
|
# # PFW only in SE/30, IIsi (power failure)
|
||||||
|
|
||||||
|
#card_select = Signal()
|
||||||
|
# we don't have 24-bits mode, FC3 is assumed to be 1
|
||||||
|
#self.comb += card_select.eq(A[31] & (~FC[0] | ~FC[1] | ~FC[2])) # high-order address bit set & not in CPU space
|
||||||
|
|
||||||
|
|
||||||
|
A_i = Signal(32)
|
||||||
|
#A_o = Signal(32)
|
||||||
|
#A_oe = Signal(reset = 0)
|
||||||
|
#self.specials += Tristate(A, A_o, A_oe, A_i)
|
||||||
|
A_latch = Signal(32)
|
||||||
|
self.comb += [ A_I.eq(A) ]
|
||||||
|
|
||||||
|
D_i = Signal(32)
|
||||||
|
D_o = Signal(32)
|
||||||
|
D_oe = Signal(reset = 0)
|
||||||
|
self.specials += Tristate(D, D_o, D_oe, D_i)
|
||||||
|
D_latch = Signal(32)
|
||||||
|
|
||||||
|
#DSACK_i_n = Signal(2)
|
||||||
|
#DSACK_o_n = Signal(2)
|
||||||
|
#DSACK_oe = Signal(reset = 0)
|
||||||
|
#self.specials += Tristate(DSACK_n, DSACK_o_n, DSACK_oe, DSACK_i_n)
|
||||||
|
|
||||||
|
SIZ_i_n = Signal(2)
|
||||||
|
#SIZ_o_n = Signal(2)
|
||||||
|
#SIZ_oe = Signal(reset = 0)
|
||||||
|
#self.specials += Tristate(SIZ_n, SIZ_o_n, SIZ_oe, SIZ_i_n)
|
||||||
|
self.comb += [ SIZ_i_n.eq(SIZ_n) ]
|
||||||
|
|
||||||
|
AS_i_n = Signal()
|
||||||
|
#AS_o_n = Signal()
|
||||||
|
#AS_oe = Signal(reset = 0)
|
||||||
|
#self.specials += Tristate(CPU_AS_n, AS_o_n, AS_oe, AS_i_n)
|
||||||
|
self.comb += [ AS_i_n.eq(AS_n) ]
|
||||||
|
|
||||||
|
DS_i_n = Signal()
|
||||||
|
#DS_o_n = Signal()
|
||||||
|
#DS_oe = Signal(reset = 0)
|
||||||
|
#self.specials += Tristate(DS_n, DS_o_n, DS_oe, DS_i_n)
|
||||||
|
self.comb += [ DS_i_n.eq(DS_n) ]
|
||||||
|
|
||||||
|
my_space = Signal()
|
||||||
|
self.comb += [ my_space.eq((A_i[24:31] == 0xf9) & (~FC[0] | ~FC[1] | ~FC[2])) ] # checkme
|
||||||
|
|
||||||
|
self.submodules.slave_fsm = slave_fsm = ClockDomainsRenamer(cd_m68k)(FSM(reset_state="Reset"))
|
||||||
|
slave_fsm.act("Reset",
|
||||||
|
NextState("Idle")
|
||||||
|
)
|
||||||
|
slave_fsm.act("Idle",
|
||||||
|
If((my_space & ~AS_i_n & RW_n), # Read
|
||||||
|
wb_read.cyc.eq(1),
|
||||||
|
wb_read.stb.eq(1),
|
||||||
|
wb_read.we.eq(0),
|
||||||
|
wb_read.sel.eq(0xf), # always read 32-bits for cache
|
||||||
|
wb_read.adr.eq(A_i[2:32]),
|
||||||
|
NextValue(A_latch, A_i[2:32]),
|
||||||
|
STERM.eq(0), # insert delay
|
||||||
|
NextState("Read"),
|
||||||
|
).Elif((my_space & ~AS_i_n & ~RW_n), # Write, data not ready just yet
|
||||||
|
NextValue(A_latch, A_i[2:32]),
|
||||||
|
STERM.eq(0), # insert delay
|
||||||
|
NextState("Write"),
|
||||||
|
)
|
||||||
|
)
|
||||||
|
slave_fsm.act("Read",
|
||||||
|
wb_read.cyc.eq(1),
|
||||||
|
wb_read.stb.eq(1),
|
||||||
|
wb_read.we.eq(0),
|
||||||
|
wb_read.sel.eq(0xf),
|
||||||
|
wb_read.adr.eq(A_latch[2:32]),
|
||||||
|
STERM.eq(0), # insert delay
|
||||||
|
If(wb_read.ack,
|
||||||
|
NextValue(D_latch, wb_read.dat_r),
|
||||||
|
D_oe.eq(1),
|
||||||
|
D_o.eq(wb_read.dat_r),
|
||||||
|
STERM.eq(1), # ACK 32-bits for 1 cycle
|
||||||
|
NextState("FinishRead"),
|
||||||
|
)
|
||||||
|
)
|
||||||
|
slave_fsm.act("FinishRead",
|
||||||
|
D_oe.eq(1), # keep data one more cycle
|
||||||
|
D_o.eq(D_latch),
|
||||||
|
STERM.eq(1), # ACK finished after 1 cycle
|
||||||
|
NextState("Idle"),
|
||||||
|
)
|
||||||
|
slave_fsm.act("Write",
|
||||||
|
wb_write.cyc.eq(1),
|
||||||
|
wb_write.stb.eq(1),
|
||||||
|
wb_write.we.eq(1),
|
||||||
|
# assumes SIZ & A_i[0:2] are both 0 (longword, aligned), checkme
|
||||||
|
wb_write.sel.eq(0xF),
|
||||||
|
wb_write.adr.eq(A_latch[2:32]),
|
||||||
|
wb_write.dat_w.eq(D_i), # data available this cycle (and later)
|
||||||
|
STERM.eq(0), # wait
|
||||||
|
If(wb_write.ack,
|
||||||
|
STERM.eq(1),
|
||||||
|
NextState("FinishWrite"),
|
||||||
|
)
|
||||||
|
)
|
||||||
|
slave_fsm.act("FinishWrite", # unnecessary ?
|
||||||
|
STERM.eq(0), # finish ACK after one cycle
|
||||||
|
NextState("Idle"),
|
||||||
|
)
|
@ -17,10 +17,50 @@ from litex.build.generic_platform import *
|
|||||||
from litex.build.xilinx import XilinxPlatform
|
from litex.build.xilinx import XilinxPlatform
|
||||||
from litex.build.openocd import OpenOCD
|
from litex.build.openocd import OpenOCD
|
||||||
|
|
||||||
from VintageBusFPGA_Common.ztex_21x_common import ZTexPlatform
|
|
||||||
|
|
||||||
# IOs ----------------------------------------------------------------------------------------------
|
# IOs ----------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
# FPGA daughterboard I/O
|
||||||
|
|
||||||
|
_io = [
|
||||||
|
## 48 MHz clock reference
|
||||||
|
("clk48", 0, Pins("P15"), IOStandard("LVCMOS33")),
|
||||||
|
## embedded 256 MiB DDR3 DRAM
|
||||||
|
("ddram", 0,
|
||||||
|
Subsignal("a", Pins("C5 B6 C7 D5 A3 E7 A4 C6", "A6 D8 B2 A5 B3 B7"),
|
||||||
|
IOStandard("SSTL135")),
|
||||||
|
Subsignal("ba", Pins("E5 A1 E6"), IOStandard("SSTL135")),
|
||||||
|
Subsignal("ras_n", Pins("E3"), IOStandard("SSTL135")),
|
||||||
|
Subsignal("cas_n", Pins("D3"), IOStandard("SSTL135")),
|
||||||
|
Subsignal("we_n", Pins("D4"), IOStandard("SSTL135")),
|
||||||
|
# Subsignal("cs_n", Pins(""), IOStandard("SSTL135")),
|
||||||
|
Subsignal("dm", Pins("G1 G6"), IOStandard("SSTL135")),
|
||||||
|
Subsignal("dq", Pins(
|
||||||
|
"H1 F1 E2 E1 F4 C1 F3 D2",
|
||||||
|
"G4 H5 G3 H6 J2 J3 K1 K2"),
|
||||||
|
IOStandard("SSTL135"),
|
||||||
|
Misc("IN_TERM=UNTUNED_SPLIT_40")),
|
||||||
|
Subsignal("dqs_p", Pins("H2 J4"),
|
||||||
|
IOStandard("DIFF_SSTL135"),
|
||||||
|
Misc("IN_TERM=UNTUNED_SPLIT_40")),
|
||||||
|
Subsignal("dqs_n", Pins("G2 H4"),
|
||||||
|
IOStandard("DIFF_SSTL135"),
|
||||||
|
Misc("IN_TERM=UNTUNED_SPLIT_40")),
|
||||||
|
Subsignal("clk_p", Pins("C4"), IOStandard("DIFF_SSTL135")),
|
||||||
|
Subsignal("clk_n", Pins("B4"), IOStandard("DIFF_SSTL135")),
|
||||||
|
Subsignal("cke", Pins("B1"), IOStandard("SSTL135")),
|
||||||
|
Subsignal("odt", Pins("F5"), IOStandard("SSTL135")),
|
||||||
|
Subsignal("reset_n", Pins("J5"), IOStandard("SSTL135")),
|
||||||
|
Misc("SLEW=FAST"),
|
||||||
|
),
|
||||||
|
("config_spiflash", 0,
|
||||||
|
Subsignal("cs_n", Pins("L13")),
|
||||||
|
# Subsignal("clk", Pins("E9")), # 'E9' isn't a user pin, access clock via STARTUPE2 primitive, disabling the pads should do it in LiteSPIClkGen ?
|
||||||
|
Subsignal("mosi", Pins("K17")),
|
||||||
|
Subsignal("miso", Pins("K18")),
|
||||||
|
IOStandard("LVCMOS33"),
|
||||||
|
),
|
||||||
|
]
|
||||||
|
|
||||||
# NuBusFPGA I/O
|
# NuBusFPGA I/O
|
||||||
|
|
||||||
# I/O
|
# I/O
|
||||||
@ -208,23 +248,31 @@ def rmii_eth_extpmod_io(extpmod):
|
|||||||
Subsignal("crs_dv", Pins(f"{extpmod}:6")),
|
Subsignal("crs_dv", Pins(f"{extpmod}:6")),
|
||||||
Subsignal("tx_en", Pins(f"{extpmod}:2")),
|
Subsignal("tx_en", Pins(f"{extpmod}:2")),
|
||||||
Subsignal("tx_data", Pins(f"{extpmod}:0 {extpmod}:1")),
|
Subsignal("tx_data", Pins(f"{extpmod}:0 {extpmod}:1")),
|
||||||
#Subsignal("mdc", Pins(f"{extpmod}:4")),
|
Subsignal("mdc", Pins(f"{extpmod}:4")),
|
||||||
#Subsignal("mdio", Pins(f"{extpmod}:7")),
|
Subsignal("mdio", Pins(f"{extpmod}:7")),
|
||||||
Subsignal("rx_er", Pins(f"{extpmod}:9")),
|
Subsignal("rx_er", Pins(f"{extpmod}:9")),
|
||||||
Subsignal("int_n", Pins(f"{extpmod}:5")),
|
Subsignal("int_n", Pins(f"{extpmod}:5")),
|
||||||
IOStandard("LVCMOS33"),
|
IOStandard("LVCMOS33"),
|
||||||
),
|
),
|
||||||
("sep_mdc", 0, Pins(f"{extpmod}:4"), IOStandard("LVCMOS33")),
|
|
||||||
("sep_mdio", 0, Pins(f"{extpmod}:7"), IOStandard("LVCMOS33")),
|
|
||||||
]
|
]
|
||||||
_rmii_eth_extpmod_io_v1_2 = rmii_eth_extpmod_io("P1")
|
_rmii_eth_extpmod_io_v1_2 = rmii_eth_extpmod_io("P1")
|
||||||
|
|
||||||
# Platform -----------------------------------------------------------------------------------------
|
# Platform -----------------------------------------------------------------------------------------
|
||||||
|
|
||||||
class Platform(ZTexPlatform):
|
class Platform(XilinxPlatform):
|
||||||
|
default_clk_name = "clk48"
|
||||||
|
default_clk_period = 1e9/48e6
|
||||||
|
|
||||||
def __init__(self, variant="ztex2.13a", version="V1.0"):
|
def __init__(self, variant="ztex2.13a", version="V1.0"):
|
||||||
|
device = {
|
||||||
|
"ztex2.12a": "xc7a15tcsg324-1", #untested, too small?
|
||||||
|
"ztex2.12b": "xc7a35tcsg324-1", #untested
|
||||||
|
"ztex2.13a": "xc7a35tcsg324-1",
|
||||||
|
"ztex2.13b": "xc7a50tcsg324-1", #untested
|
||||||
|
"ztex2.13b2": "xc7a50tcsg324-1", #untested
|
||||||
|
"ztex2.13c": "xc7a75tcsg324-2", #untested
|
||||||
|
"ztex2.13d": "xc7a100tcsg324-2" #untested
|
||||||
|
}[variant]
|
||||||
nubus_io = {
|
nubus_io = {
|
||||||
"V1.0" : _nubus_io_v1_0,
|
"V1.0" : _nubus_io_v1_0,
|
||||||
"V1.2" : _nubus_io_v1_2,
|
"V1.2" : _nubus_io_v1_2,
|
||||||
@ -237,9 +285,31 @@ class Platform(ZTexPlatform):
|
|||||||
"V1.0" : connectors_v1_0,
|
"V1.0" : connectors_v1_0,
|
||||||
"V1.2" : connectors_v1_2,
|
"V1.2" : connectors_v1_2,
|
||||||
}[version]
|
}[version]
|
||||||
|
self.speedgrade = -1
|
||||||
|
if (device[-1] == '2'):
|
||||||
|
self.speedgrade = -2
|
||||||
|
|
||||||
ZTexPlatform.__init__(self, variant=variant, version=version, connectors=connectors)
|
XilinxPlatform.__init__(self, device, _io, connectors, toolchain="vivado")
|
||||||
|
|
||||||
self.add_extension(nubus_io)
|
self.add_extension(nubus_io)
|
||||||
#print(nubus_nubus)
|
print(nubus_nubus)
|
||||||
self.add_extension(nubus_nubus)
|
self.add_extension(nubus_nubus)
|
||||||
|
|
||||||
|
self.toolchain.bitstream_commands = \
|
||||||
|
["set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]",
|
||||||
|
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]",
|
||||||
|
"set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]",
|
||||||
|
"set_property BITSTREAM.GENERAL.COMPRESS true [current_design]",
|
||||||
|
"set_property BITSTREAM.GENERAL.CRC DISABLE [current_design]",
|
||||||
|
"set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]",
|
||||||
|
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
|
||||||
|
"set_property CFGBVS VCCO [current_design]"
|
||||||
|
# , "set_property STEPS.SYNTH_DESIGN.ARGS.DIRECTIVE AreaOptimized_high [get_runs synth_1]"
|
||||||
|
]
|
||||||
|
|
||||||
|
def create_programmer(self):
|
||||||
|
bscan_spi = "bscan_spi_xc7a35t.bit"
|
||||||
|
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi) #FIXME
|
||||||
|
|
||||||
|
def do_finalize(self, fragment):
|
||||||
|
XilinxPlatform.do_finalize(self, fragment)
|
||||||
|
#self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
|
||||||
|
Loading…
Reference in New Issue
Block a user