SE-VGA/old/vgaout.sv

69 lines
1.7 KiB
Systemverilog
Raw Normal View History

2021-04-07 04:15:48 +00:00
/******************************************************************************
* SE-VGA
* VGA video output
* techav
* 2021-04-06
******************************************************************************
* Fetches video data from VRAM and shifts out
*****************************************************************************/
2021-04-18 17:07:42 +00:00
`include "vgashiftout.sv"
2021-04-07 04:15:48 +00:00
module vgaout (
input wire pixClock,
input wire nReset,
input logic [9:0] hCount,
input logic [9:0] vCount,
input wire hSEActive,
input wire vSEActive,
2021-04-12 04:46:29 +00:00
input logic [7:0] vramData,
output logic [14:0] vramAddr,
2021-04-07 04:15:48 +00:00
output wire nvramOE,
output wire vidOut
);
2021-04-18 19:31:05 +00:00
wire vidMuxOut; // pixel data shift out
2021-04-07 04:15:48 +00:00
wire vidActive; // combined active video signal
2021-04-13 03:07:18 +00:00
wire nVidLoad; // Load VRAM data into shifter
2021-04-18 17:07:42 +00:00
vgaShiftOut vOut(
2021-04-13 03:07:18 +00:00
.nReset(nReset),
.clk(pixClock),
.nLoad(nVidLoad),
2021-04-13 03:07:18 +00:00
.parIn(vramData),
.out(vidMuxOut)
);
2021-04-07 04:15:48 +00:00
always_comb begin
if(hCount[2:0] == 0) nVidLoad <= 0;
else nVidLoad <= 1;
2021-04-18 18:19:16 +00:00
2021-04-07 04:15:48 +00:00
// combined video active signal
if(hSEActive == 1'b1 && vSEActive == 1'b1) begin
vidActive <= 1'b1;
end else begin
vidActive <= 1'b0;
end
// video data output
if(vidActive == 1'b1) begin
vidOut <= ~vidMuxOut;
2021-04-07 04:15:48 +00:00
end else begin
vidOut <= 1'b0;
end
// vram read signal
2021-04-18 18:19:16 +00:00
if(vidActive == 1'b1 && hCount[2:0] == 0) begin
2021-04-07 04:15:48 +00:00
nvramOE <= 1'b0;
end else begin
nvramOE <= 1'b1;
end
// vram address signals
// these will be mux'd with cpu addresses externally
2021-04-12 04:46:29 +00:00
vramAddr[14:6] <= vCount[8:0];
2021-04-07 04:15:48 +00:00
vramAddr[5:0] <= hCount[8:3];
end
endmodule