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Refactor Video Out Sequence

This commit is contained in:
techav 2021-04-18 13:19:16 -05:00
parent 995be6b5dc
commit 14e5c8eb39
4 changed files with 109 additions and 68 deletions
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4
cpusnoop.sv
View File

@ -118,7 +118,7 @@ module cpusnoop (
S2 : begin
// wait for sequence
if(pendWriteHi == 1 && pendWriteLo == 1) begin
if(seq < 5) begin
if(seq < 6) begin
// we have enough time to write both before the next VRAM read
cycleState <= S3;
end else begin
@ -126,7 +126,7 @@ module cpusnoop (
cycleState <= S2;
end
end else if(pendWriteHi == 1 || pendWriteLo == 1) begin
if(seq < 6) begin
if(seq < 7) begin
// we have enough time for the pending write
if(pendWriteLo == 0) begin
// move on to write high byte

32
sevga.vwf
View File

@ -1961,8 +1961,8 @@ TRANSITION_LIST("vramData[7]")
LEVEL 0 FOR 80.0;
LEVEL Z FOR 240.0;
LEVEL 0 FOR 80.0;
LEVEL Z FOR 280.0;
LEVEL 0 FOR 640.0;
LEVEL Z FOR 500.0;
LEVEL 0 FOR 420.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 320.0;
LEVEL 1 FOR 320.0;
@ -2024,8 +2024,8 @@ TRANSITION_LIST("vramData[6]")
LEVEL 1 FOR 80.0;
LEVEL Z FOR 240.0;
LEVEL 0 FOR 80.0;
LEVEL Z FOR 280.0;
LEVEL 0 FOR 960.0;
LEVEL Z FOR 500.0;
LEVEL 0 FOR 740.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 320.0;
LEVEL 1 FOR 320.0;
@ -2087,8 +2087,8 @@ TRANSITION_LIST("vramData[5]")
LEVEL 0 FOR 80.0;
LEVEL Z FOR 240.0;
LEVEL 1 FOR 80.0;
LEVEL Z FOR 280.0;
LEVEL 0 FOR 320.0;
LEVEL Z FOR 500.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 640.0;
LEVEL 1 FOR 1600.0;
@ -2152,8 +2152,8 @@ TRANSITION_LIST("vramData[4]")
LEVEL 1 FOR 80.0;
LEVEL Z FOR 240.0;
LEVEL 1 FOR 80.0;
LEVEL Z FOR 280.0;
LEVEL 1 FOR 320.0;
LEVEL Z FOR 500.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 1600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 320.0;
@ -2214,8 +2214,8 @@ TRANSITION_LIST("vramData[3]")
LEVEL 0 FOR 80.0;
LEVEL Z FOR 240.0;
LEVEL 1 FOR 80.0;
LEVEL Z FOR 280.0;
LEVEL 0 FOR 640.0;
LEVEL Z FOR 500.0;
LEVEL 0 FOR 420.0;
LEVEL 1 FOR 640.0;
LEVEL 0 FOR 640.0;
LEVEL 1 FOR 320.0;
@ -2280,8 +2280,8 @@ TRANSITION_LIST("vramData[2]")
LEVEL 1 FOR 80.0;
LEVEL Z FOR 240.0;
LEVEL 1 FOR 80.0;
LEVEL Z FOR 280.0;
LEVEL 1 FOR 960.0;
LEVEL Z FOR 500.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 960.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 640.0;
@ -2345,8 +2345,8 @@ TRANSITION_LIST("vramData[1]")
LEVEL 0 FOR 80.0;
LEVEL Z FOR 240.0;
LEVEL 0 FOR 80.0;
LEVEL Z FOR 280.0;
LEVEL 1 FOR 640.0;
LEVEL Z FOR 500.0;
LEVEL 1 FOR 420.0;
LEVEL 0 FOR 320.0;
LEVEL 1 FOR 640.0;
LEVEL 0 FOR 640.0;
@ -2412,8 +2412,8 @@ TRANSITION_LIST("vramData[0]")
LEVEL 1 FOR 80.0;
LEVEL Z FOR 240.0;
LEVEL 0 FOR 80.0;
LEVEL Z FOR 280.0;
LEVEL 0 FOR 640.0;
LEVEL Z FOR 500.0;
LEVEL 0 FOR 420.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 320.0;
LEVEL 1 FOR 320.0;

28
vgaout.sv
View File

@ -26,27 +26,33 @@ module vgaout (
wire vidMuxOut;
wire vidActive; // combined active video signal
//wire vgaShiftEn; // Enable pixel shift out
wire vgaShiftL1; // Load VRAM data into register
wire vgaShiftL2; // Load VRAM data into shifter
vgaShiftOut vOut(
.nReset(nReset),
.clk(pixClock),
.vidActive(vidActive),
.seq(hCount[2:0]),
.shiftEn(vidActive),
.nLoad1(vgaShiftL1),
.nLoad2(vgaShiftL2),
.parIn(vramData),
.out(vidMuxOut)
);
always_comb begin
// load VRAM data into register
if(hCount[2:0] == 0) vgaShiftL1 <= !pixClock;
else vgaShiftL1 <= 1;
// load VRAM data into shifter
if(hCount[2:0] == 0) vgaShiftL2 <= !pixClock;
else if(hCount[2:0] == 1) vgaShiftL2 <= pixClock;
else vgaShiftL2 <= 1;
// combined video active signal
if(hSEActive == 1'b1 && vSEActive == 1'b1) begin
vidActive <= 1'b1;
/*end else if(hCount == 799 && vCount == 524) begin
// this is the exception to ensure the first byte of video is loaded
// just before the new frame starts
vidActive <= 1'b1;
end else if(vSEActive == 1'b1 && hCount == 10'd799) begin
// this is the exception to ensure the first byte of video is loaded
// just before a new line starts
vidActive <= 1'b1;*/
end else begin
vidActive <= 1'b0;
end
@ -59,7 +65,7 @@ always_comb begin
end
// vram read signal
if(vidActive == 1'b1 && hCount[2:0] == 3'h7) begin
if(vidActive == 1'b1 && hCount[2:0] == 0) begin
nvramOE <= 1'b0;
end else begin
nvramOE <= 1'b1;

113
vgashiftout.sv
View File

@ -13,57 +13,92 @@
module vgaShiftOut (
input wire nReset,
input wire clk,
input wire vidActive,
input logic [2:0] seq,
input wire shiftEn,
input wire nLoad1,
input wire nLoad2,
input logic [7:0] parIn,
output wire out
);
/* Shift register functioning similar to a 74597, with 8-bit input latch
* and 8-bit PISO shift register output stage.
* In sequence 7 new data is loaded from VRAM into the input stage, and in
* sequence 0 the input stage is copied to the output stage to be shifted.
*/
reg [7:0] inReg;
reg [7:0] outReg;
// to meet VRAM timing requirements, data from VRAM has to be clocked into
// our input register on the rising edge of the pixel clock
always @(posedge clk or negedge nReset) begin
if(nReset == 0) begin
inReg <= 0;
end else begin
if(seq == 7) begin
inReg <= parIn;
if(!nReset) inReg <= 0;
else if(!nLoad1) inReg <= parIn;
end
always @(negedge clk or negedge nReset) begin
if(!nReset) outReg <= 0;
else begin
if(!nLoad2) outReg <= inReg;
else if(shiftEn) begin
outReg[7] <= outReg[6];
outReg[6] <= outReg[5];
outReg[5] <= outReg[4];
outReg[4] <= outReg[3];
outReg[3] <= outReg[2];
outReg[2] <= outReg[1];
outReg[1] <= outReg[0];
outReg[0] <= 0;
end
end
end
// pixels are shifted out on the falling edge of the pixel clock
always @(negedge clk or negedge nReset) begin
if(nReset == 1'b0) begin
//inReg <= 0;
outReg <= 0;
end else begin
if(vidActive == 1'b1) begin
if(seq == 0) begin
outReg <= inReg;
end else begin
outReg[7] <= outReg[6];
outReg[6] <= outReg[5];
outReg[5] <= outReg[4];
outReg[4] <= outReg[3];
outReg[3] <= outReg[2];
outReg[2] <= outReg[1];
outReg[1] <= outReg[0];
outReg[0] <= 1'b0;
end
/*if(seq == 7) begin
inReg <= parIn;
end*/
end
end
end
assign out = outReg[7];
endmodule
// module vgaShiftOut (
// input wire nReset,
// input wire clk,
// input wire vidActive,
// input logic [2:0] seq,
// input logic [7:0] parIn,
// output wire out
// );
// /* Shift register functioning similar to a 74597, with 8-bit input latch
// * and 8-bit PISO shift register output stage.
// * In sequence 0 new data is loaded from VRAM into the input stage, and in
// * sequence 1 the input stage is copied to the output stage to be shifted.
// */
// reg [7:0] inReg;
// reg [7:0] outReg;
// // to meet VRAM timing requirements, data from VRAM has to be clocked into
// // our input register on the rising edge of the pixel clock
// always @(posedge clk or negedge nReset) begin
// if(nReset == 0) begin
// inReg <= 0;
// end else begin
// if(seq == 0) begin
// inReg <= parIn;
// end
// end
// end
// // pixels are shifted out on the falling edge of the pixel clock
// always @(negedge clk or negedge nReset) begin
// if(nReset == 1'b0) begin
// //inReg <= 0;
// outReg <= 0;
// end else begin
// if(vidActive == 1'b1) begin
// if(seq == 0) begin
// outReg <= inReg;
// end else begin
// outReg[7] <= outReg[6];
// outReg[6] <= outReg[5];
// outReg[5] <= outReg[4];
// outReg[4] <= outReg[3];
// outReg[3] <= outReg[2];
// outReg[2] <= outReg[1];
// outReg[1] <= outReg[0];
// outReg[0] <= 1'b0;
// end
// end
// end
// end
// assign out = outReg[7];
// endmodule
`endif