CPU Cycle Improvements 2
This commit is contained in:
techav
parent
3b00823d6c
commit
c4bc1c4be5
175
cpusnoop.sv
175
cpusnoop.sv
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@ -36,12 +36,12 @@ module cpusnoop (
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// define state machine states
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parameter
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S0 = 3'h0,
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S1 = 3'h1,
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S2 = 3'h2,
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S3 = 3'h3,
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S4 = 3'h4,
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S5 = 3'h5;
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S0 = 0,
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//S1 = 3'h1,
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S2 = 2,
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S3 = 3,
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S4 = 4,
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S5 = 5;
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// when cpu addresses the framebuffer, set our enable signal
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/* framebuffer starts $5900 below the top of RAM
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@ -89,28 +89,11 @@ module cpusnoop (
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case (cycleState)
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S0 : begin
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// idle state, wait for valid address and ncpuAS asserted
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if(ncpuAS == 0 && cpuBufSel == 1 && cpuRnW == 0) begin
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cycleState <= S1;
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end else begin
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cycleState <= S0;
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end
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end
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S1 : begin
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// wait for either ncpuUDS or ncpuLDS to assert
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// if ncpuAS negates first, then abort back to S0
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if(ncpuAS == 1) begin
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// cpu aborted cycle
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cycleState <= S0;
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end else if(ncpuUDS == 0 || ncpuLDS == 0) begin
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if (ncpuUDS == 0) begin
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pendWriteHi <= 1;
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dataCacheHi <= cpuData[15:8];
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end
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if (ncpuLDS == 0) begin
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pendWriteLo <= 1;
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dataCacheLo <= cpuData[7:0];
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end
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if(ncpuAS == 0 && cpuBufSel == 1 && cpuRnW == 0 && (ncpuLDS == 0 || ncpuUDS == 0)) begin
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pendWriteHi <= !ncpuUDS;
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pendWriteLo <= !ncpuLDS;
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dataCacheHi <= cpuData[15:8];
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dataCacheLo <= cpuData[7:0];
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// Valid CPU-VRAM cycle, so subtract constant $1380 from the
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// cpu address and store the result in addrCache register.
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// Constant $1380 corresponds to $2700 shifted right by 1.
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@ -126,27 +109,39 @@ module cpusnoop (
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// offset: 0000 0000 0010 0111 0000 0000 = $002700
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// shifted offset: 0000 0000 0001 0011 1000 0000 = $001380
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addrCache <= cpuAddr[13:0] - 14'h1380;
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cycleState <= S2;
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end else begin
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cycleState <= S1;
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cycleState <= S0;
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end
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end
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S2 : begin
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// wait for sequence
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if(pendWriteHi == 1 && pendWriteLo == 1 && seq < 5) begin
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// we have enough time to write both before the next VRAM read
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cycleState <= S3;
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end else if(seq < 6) begin
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// we have enough time to write the one pending before next VRAM read
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if(pendWriteLo == 0) begin
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cycleState <= S4;
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end else begin
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if(pendWriteHi == 1 && pendWriteLo == 1) begin
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if(seq < 5) begin
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// we have enough time to write both before the next VRAM read
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cycleState <= S3;
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end else begin
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// we don't have enough time to write both. hold for now
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cycleState <= S2;
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end
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end else if(pendWriteHi == 1 || pendWriteLo == 1) begin
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if(seq < 6) begin
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// we have enough time for the pending write
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if(pendWriteLo == 0) begin
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// move on to write high byte
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cycleState <= S4;
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end else begin
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// move on to write low byte
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cycleState <= S3;
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end
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end else begin
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// not enough time for a write cycle. hold for now
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cycleState <= S2;
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end
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end else begin
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// no time for a write sequence, wait
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cycleState <= S2;
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// we shouldn't be here. Somehow we have slipped through without setting flags.
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cycleState <= S0;
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end
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end
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S3 : begin
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@ -165,7 +160,6 @@ module cpusnoop (
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end
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S5 : begin
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// wait for CPU to negate both ncpuUDS and ncpuLDS
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//if(ncpuUDS == 1 && ncpuLDS == 1) begin
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if(cpuCycleEnded == 1) begin
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cycleState <= S0;
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end else begin
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@ -183,9 +177,9 @@ module cpusnoop (
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always_comb begin
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vramAddr[14:1] <= addrCache[13:0];
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if(cycleState == S4) begin
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vramAddr[0] <= 1;
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end else begin
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vramAddr[0] <= 0;
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end else begin
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vramAddr[0] <= 1;
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end
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if(cycleState == S3 || cycleState == S4) begin
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@ -203,99 +197,4 @@ module cpusnoop (
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end
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end
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/*
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// when cpu addresses the framebuffer, save the address
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always @(negedge ncpuAS or negedge nReset) begin
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if(nReset == 1'b0) begin
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addrCache <= 0;
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end else begin
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// here we match our ramSize jumpers and constants to confirm
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// the CPU is accessing the primary frame buffer
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//if(cpuBufSel == 1'b1) begin
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if(ramSize == cpuAddr[20:18] && cpuAddr[22:21] == 2'b00 && cpuAddr[17:14] == 4'b1111) begin
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// We have a match, so subtract constant $1380 from the
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// cpu address and store the result in addrCache register.
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// Constant $1380 corresponds to $2700 shifted right by 1.
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// Once the selection bits above are masked out, we're left
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// with buffer addresses starting with $2700
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// e.g. with 4MB of RAM, fram buffer starts at $3FA700
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// buffer address: 0011 1111 1010 0111 0000 0000 = $3FA700
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// vram addr mask: 0000 0000 0011 1111 1111 1111 - $003FFF
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// vram address: 0000 0000 0010 0111 0000 0000 = $002700
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// Since CPU is 16-bit and does not provide A0, our cpuAddr
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// signals are shifted right by one, so we need to do the same
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// to our offset before subtracting it from cpuAddr
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// offset: 0000 0000 0010 0111 0000 0000 = $002700
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// shifted offset: 0000 0000 0001 0011 1000 0000 = $001380
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addrCache <= cpuAddr[13:0] - 14'h1380;
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end
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end
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end
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// when cpu addresses the framebuffer, save high byte
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always @(negedge ncpuUDS or negedge nReset) begin
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if(nReset == 1'b0) begin
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dataCacheHi <= 8'h0;
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end else begin
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if(cpuBufSel == 1'b1 && cpuRnW == 1'b0) begin
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dataCacheHi <= cpuData[15:8];
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end
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end
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end
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// when cpu addresses the framebuffer, save low byte
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always @(negedge ncpuLDS or negedge nReset) begin
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if(nReset == 1'b0) begin
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dataCacheLo <= 8'h0;
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end else begin
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if(cpuBufSel == 1'b1 && cpuRnW == 1'b0) begin
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dataCacheLo <= cpuData[7:0];
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end
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end
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end
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// set pending flags for cpu accesses & clear when that cycle comes back around
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/*always @(negedge pixClock or negedge nReset) begin
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if(nReset == 1'b0) begin
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pendWriteLo <= 1'b0;
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pendWriteHi <= 1'b0;
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end else begin
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if(cpuBufSel == 1'b1 && cpuRnW == 1'b0) begin
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if(ncpuUDS == 1'b0) begin
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pendWriteHi <= 1'b1;
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end
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if(ncpuLDS == 1'b0) begin
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pendWriteLo <= 1'b1;
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end
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end else begin
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if(seq == 1 || seq == 3 || seq == 5) begin
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pendWriteLo <= 1'b0;
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end
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if(seq == 2 || seq == 4 || seq == 6) begin
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pendWriteHi <= 1'b0;
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end
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end
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end
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end*/
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/*
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always_comb begin
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vramAddr[14:1] <= addrCache[13:0];
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if(pendWriteLo == 1'b1 && (seq == 1 || seq == 3 || seq == 5)) begin
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vramAddr[0] <= 1'b0;
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nvramWE <= 1'b0;
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vramDataOut <= dataCacheLo;
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end else if(pendWriteHi == 1'b1 && (seq == 2 || seq == 4 || seq == 6)) begin
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vramAddr[0] <= 1'b1;
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nvramWE <= 1'b0;
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vramDataOut <= dataCacheHi;
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end else begin
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vramAddr[0] <= 1'b0;
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nvramWE <= 1'b1;
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vramDataOut <= 8'h0;
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end
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end
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*/
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endmodule
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@ -1,157 +0,0 @@
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/******************************************************************************
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* SE-VGA
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* Primitives
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* techav
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* 2021-04-06
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******************************************************************************
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* Basic modules to be used elsewhere
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*****************************************************************************/
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`ifndef PRIMS
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`define PRIMS
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/*
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// basic d-flipflop
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module myDff (
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input wire nReset,
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input wire clk,
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input wire d,
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output reg q
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);
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always @(posedge clk or negedge nReset) begin
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if(nReset == 1'b0) begin
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q <= 1'b0;
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end else begin
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q <= d;
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end
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end
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endmodule
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*/
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/*
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// basic 8-bit mux
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module mux8 (
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input logic [7:0] inA,
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input logic [7:0] inB,
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input wire select,
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output logic [7:0] out
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);
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always_comb begin
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if(select == 1'b0) begin
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out <= inA;
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end else begin
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out <= inB;
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end
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end
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endmodule
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*/
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/*
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// basic 8-to-1 mux
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module mux8x1 (
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input logic[7:0] in,
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input logic[2:0] select,
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output wire out
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);
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assign out = in[select];
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endmodule
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*/
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/*
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// basic 8-to-1 mux with transparent output latch
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module mux8x1latch (
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input logic[7:0] in,
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input logic[2:0] select,
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input wire clock,
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input wire nReset,
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output reg out
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);
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wire muxOut;
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mux8x1 mux (in,select,muxOut);
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// transparent latch -- when clock is low, output will
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// follow the output of the mux. When clock is high,
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// output will hold its last value.
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always @(clock or nReset or muxOut or out) begin
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if(nReset == 1'b0) begin
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out = 1'b0;
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end else if(clock == 1'b0) begin
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out = muxOut;
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end else begin
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out = out;
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end
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end
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endmodule
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*/
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/*
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// basic 8-bit PISO shift register
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module piso8 (
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input wire nReset,
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input wire clk,
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input wire load,
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input logic [7:0] parIn,
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output wire out
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);
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logic [7:0] muxIns;
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logic [7:0] muxOuts;
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mux8 loader(muxIns[7:0],parIn[7:0],load,muxOuts[7:0]);
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myDff u0(nReset,clk,muxOuts[0],muxIns[1]);
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myDff u1(nReset,clk,muxOuts[1],muxIns[2]);
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myDff u2(nReset,clk,muxOuts[2],muxIns[3]);
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myDff u3(nReset,clk,muxOuts[3],muxIns[4]);
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myDff u4(nReset,clk,muxOuts[4],muxIns[5]);
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myDff u5(nReset,clk,muxOuts[5],muxIns[6]);
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myDff u6(nReset,clk,muxOuts[6],muxIns[7]);
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myDff u7(nReset,clk,muxOuts[7],muxIns[0]);
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assign out = muxIns[0];
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endmodule
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*/
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module vidShiftOut (
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input wire nReset,
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input wire clk,
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input wire vidActive,
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input logic [2:0] seq,
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input logic [7:0] parIn,
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output wire out
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);
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/* Shift register functioning similar to a 74597, with 8-bit input latch
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* and 8-bit PISO shift register output stage.
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* In sequence 7 new data is loaded from VRAM into the input stage, and in
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* sequence 0 the input stage is copied to the output stage to be shifted.
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*/
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reg [7:0] inReg;
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reg [7:0] outReg;
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always @(negedge clk or negedge nReset) begin
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if(nReset == 1'b0) begin
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inReg <= 0;
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outReg <= 0;
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end else begin
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if(vidActive == 1'b1) begin
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if(seq == 0) begin
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outReg <= inReg;
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end else begin
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outReg[7] <= outReg[6];
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outReg[6] <= outReg[5];
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outReg[5] <= outReg[4];
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outReg[4] <= outReg[3];
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outReg[3] <= outReg[2];
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outReg[2] <= outReg[1];
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outReg[1] <= outReg[0];
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outReg[0] <= 1'b0;
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end
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if(seq == 7) begin
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inReg <= parIn;
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end
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end
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end
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end
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assign out = outReg[7];
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endmodule
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`endif
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@ -70,7 +70,7 @@ vgaout vidvram(
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.vidOut(vidOut)
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);
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// link module that handles cpu writes
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// link module that snoops cpu writes
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cpusnoop cpusnp(
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.nReset(nReset),
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.pixClock(pixClk),
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@ -92,8 +92,10 @@ always_comb begin
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// vramAddr muxing
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if(nvramWEpre == 1'b0) begin
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vramAddr <= cpuVramAddr;
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end else begin
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end else if(nvramOE == 0) begin
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vramAddr <= vidVramAddr;
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end else begin
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vramAddr <= 0;
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end
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end
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413
sevga.vwf
413
sevga.vwf
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@ -1961,7 +1961,55 @@ TRANSITION_LIST("vramData[7]")
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 240.0;
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 32000.0;
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LEVEL Z FOR 280.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 2880.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 960.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 960.0;
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LEVEL 1 FOR 1920.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 960.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 1280.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 960.0;
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LEVEL 0 FOR 1920.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 1280.0;
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LEVEL 1 FOR 1280.0;
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LEVEL 0 FOR 960.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 40.0;
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}
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}
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@ -1976,7 +2024,55 @@ TRANSITION_LIST("vramData[6]")
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LEVEL 1 FOR 80.0;
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LEVEL Z FOR 240.0;
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 32000.0;
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LEVEL Z FOR 280.0;
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LEVEL 0 FOR 960.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 960.0;
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LEVEL 0 FOR 1600.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 960.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 1280.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 1280.0;
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LEVEL 1 FOR 1280.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 1280.0;
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LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 1280.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 1600.0;
|
||||
LEVEL 1 FOR 40.0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1986,12 +2082,62 @@ TRANSITION_LIST("vramData[5]")
|
|||
{
|
||||
REPEAT = 1;
|
||||
LEVEL Z FOR 280.0;
|
||||
LEVEL 1 FOR 80.0;
|
||||
LEVEL 0 FOR 80.0;
|
||||
LEVEL Z FOR 240.0;
|
||||
LEVEL 0 FOR 80.0;
|
||||
LEVEL Z FOR 240.0;
|
||||
LEVEL 1 FOR 80.0;
|
||||
LEVEL Z FOR 32000.0;
|
||||
LEVEL Z FOR 280.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 1600.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 1280.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 1600.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 1600.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 1600.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 1280.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 1280.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 40.0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2006,7 +2152,54 @@ TRANSITION_LIST("vramData[4]")
|
|||
LEVEL 1 FOR 80.0;
|
||||
LEVEL Z FOR 240.0;
|
||||
LEVEL 1 FOR 80.0;
|
||||
LEVEL Z FOR 32000.0;
|
||||
LEVEL Z FOR 280.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 1600.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 1920.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 1600.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 2560.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 1600.0;
|
||||
LEVEL 1 FOR 40.0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2016,12 +2209,63 @@ TRANSITION_LIST("vramData[3]")
|
|||
{
|
||||
REPEAT = 1;
|
||||
LEVEL Z FOR 280.0;
|
||||
LEVEL 1 FOR 80.0;
|
||||
LEVEL 0 FOR 80.0;
|
||||
LEVEL Z FOR 240.0;
|
||||
LEVEL 0 FOR 80.0;
|
||||
LEVEL Z FOR 240.0;
|
||||
LEVEL 1 FOR 80.0;
|
||||
LEVEL Z FOR 32000.0;
|
||||
LEVEL Z FOR 280.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 2560.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 1600.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 40.0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2036,7 +2280,57 @@ TRANSITION_LIST("vramData[2]")
|
|||
LEVEL 1 FOR 80.0;
|
||||
LEVEL Z FOR 240.0;
|
||||
LEVEL 1 FOR 80.0;
|
||||
LEVEL Z FOR 32000.0;
|
||||
LEVEL Z FOR 280.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 1920.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 1600.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 1600.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 40.0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2051,7 +2345,59 @@ TRANSITION_LIST("vramData[1]")
|
|||
LEVEL 0 FOR 80.0;
|
||||
LEVEL Z FOR 240.0;
|
||||
LEVEL 0 FOR 80.0;
|
||||
LEVEL Z FOR 32000.0;
|
||||
LEVEL Z FOR 280.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 2240.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 1920.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 1280.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 40.0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2061,12 +2407,57 @@ TRANSITION_LIST("vramData[0]")
|
|||
{
|
||||
REPEAT = 1;
|
||||
LEVEL Z FOR 280.0;
|
||||
LEVEL 0 FOR 80.0;
|
||||
LEVEL 1 FOR 80.0;
|
||||
LEVEL Z FOR 240.0;
|
||||
LEVEL 1 FOR 80.0;
|
||||
LEVEL Z FOR 240.0;
|
||||
LEVEL 0 FOR 80.0;
|
||||
LEVEL Z FOR 32000.0;
|
||||
LEVEL Z FOR 280.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 960.0;
|
||||
LEVEL 0 FOR 1920.0;
|
||||
LEVEL 1 FOR 2240.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 960.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 320.0;
|
||||
LEVEL 1 FOR 640.0;
|
||||
LEVEL 0 FOR 1920.0;
|
||||
LEVEL 1 FOR 1920.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 640.0;
|
||||
LEVEL 1 FOR 1280.0;
|
||||
LEVEL 0 FOR 2240.0;
|
||||
LEVEL 1 FOR 320.0;
|
||||
LEVEL 0 FOR 360.0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
45
vgaout.sv
45
vgaout.sv
|
|
@ -7,7 +7,7 @@
|
|||
* Fetches video data from VRAM and shifts out
|
||||
*****************************************************************************/
|
||||
|
||||
`include "primitives/primitives.sv"
|
||||
`include "vgashiftout.sv"
|
||||
|
||||
module vgaout (
|
||||
input wire pixClock,
|
||||
|
|
@ -26,7 +26,7 @@ module vgaout (
|
|||
wire vidMuxOut;
|
||||
wire vidActive; // combined active video signal
|
||||
|
||||
vidShiftOut vOut(
|
||||
vgaShiftOut vOut(
|
||||
.nReset(nReset),
|
||||
.clk(pixClock),
|
||||
.vidActive(vidActive),
|
||||
|
|
@ -35,47 +35,6 @@ vidShiftOut vOut(
|
|||
.out(vidMuxOut)
|
||||
);
|
||||
|
||||
/*module vidShiftOut (
|
||||
input wire nReset,
|
||||
input wire clk,
|
||||
input logic [2:0] seq,
|
||||
input logic [7:0] parIn,
|
||||
output wire out,
|
||||
);*/
|
||||
|
||||
/*
|
||||
wire vidMuxClk; // latch mux output just before updating rVid
|
||||
|
||||
// select bits 0..7 from the vram data in rVid, and latch if
|
||||
// vidMuxClk goes high
|
||||
mux8x1latch vidOutMux(rVid,hCount[2:0],vidMuxClk,nReset,vidMuxOut);
|
||||
|
||||
// vidMuxClk should be low during sequence 0..6, and high for 7
|
||||
// this may lead to a race condition trying to change the mux
|
||||
// before the output is latched. The alternative is to latch on
|
||||
// the rising edge of pixClock during sequence 7, but then we may
|
||||
// have a race condition with the data coming in from VRAM.
|
||||
// What we really need is a half clock delay :-/
|
||||
always_comb begin
|
||||
if(hCount[2:0] == 3'd7) begin
|
||||
vidMuxClk <= 1'b1;
|
||||
end else begin
|
||||
vidMuxClk <= 1'b0;
|
||||
end
|
||||
end
|
||||
*/
|
||||
|
||||
// latch incoming vram data on rising clock and sequence 7
|
||||
/*always @(posedge pixClock or negedge nReset) begin
|
||||
if(nReset == 1'b0) begin
|
||||
rVid <= 8'h0;
|
||||
end else begin
|
||||
if(hCount[2:0] == 3'h7) begin
|
||||
rVid <= vramData;
|
||||
end
|
||||
end
|
||||
end*/
|
||||
|
||||
always_comb begin
|
||||
// combined video active signal
|
||||
if(hSEActive == 1'b1 && vSEActive == 1'b1) begin
|
||||
|
|
|
|||
|
|
@ -0,0 +1,69 @@
|
|||
/******************************************************************************
|
||||
* SE-VGA
|
||||
* VGA Shift Out
|
||||
* techav
|
||||
* 2021-04-06
|
||||
******************************************************************************
|
||||
* 2-stage shift register for storing & shifting out pixel data
|
||||
*****************************************************************************/
|
||||
|
||||
`ifndef VGASHIFTOUT
|
||||
`define VGASHIFTOUT
|
||||
|
||||
module vgaShiftOut (
|
||||
input wire nReset,
|
||||
input wire clk,
|
||||
input wire vidActive,
|
||||
input logic [2:0] seq,
|
||||
input logic [7:0] parIn,
|
||||
output wire out
|
||||
);
|
||||
/* Shift register functioning similar to a 74597, with 8-bit input latch
|
||||
* and 8-bit PISO shift register output stage.
|
||||
* In sequence 7 new data is loaded from VRAM into the input stage, and in
|
||||
* sequence 0 the input stage is copied to the output stage to be shifted.
|
||||
*/
|
||||
reg [7:0] inReg;
|
||||
reg [7:0] outReg;
|
||||
|
||||
// to meet VRAM timing requirements, data from VRAM has to be clocked into
|
||||
// our input register on the rising edge of the pixel clock
|
||||
always @(posedge clk or negedge nReset) begin
|
||||
if(nReset == 0) begin
|
||||
inReg <= 0;
|
||||
end else begin
|
||||
if(seq == 7) begin
|
||||
inReg <= parIn;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// pixels are shifted out on the falling edge of the pixel clock
|
||||
always @(negedge clk or negedge nReset) begin
|
||||
if(nReset == 1'b0) begin
|
||||
//inReg <= 0;
|
||||
outReg <= 0;
|
||||
end else begin
|
||||
if(vidActive == 1'b1) begin
|
||||
if(seq == 0) begin
|
||||
outReg <= inReg;
|
||||
end else begin
|
||||
outReg[7] <= outReg[6];
|
||||
outReg[6] <= outReg[5];
|
||||
outReg[5] <= outReg[4];
|
||||
outReg[4] <= outReg[3];
|
||||
outReg[3] <= outReg[2];
|
||||
outReg[2] <= outReg[1];
|
||||
outReg[1] <= outReg[0];
|
||||
outReg[0] <= 1'b0;
|
||||
end
|
||||
/*if(seq == 7) begin
|
||||
inReg <= parIn;
|
||||
end*/
|
||||
end
|
||||
end
|
||||
end
|
||||
assign out = outReg[7];
|
||||
endmodule
|
||||
|
||||
`endif
|
||||
Loading…
Reference in New Issue