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Merge pull request #1 from techav-homebrew/XGA 

Xga
This commit is contained in:
techav 2021-10-22 22:24:59 -05:00 committed by GitHub
parent 89ce4cbc1d a9b119fb6d
commit 42f59513e1
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GPG Key ID: 4AEE18F83AFDEB23
24 changed files with 92702 additions and 56448 deletions
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M02*

1478
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File diff suppressed because it is too large Load Diff

8
Gerbers/solderpaste_bottom.gbr
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@ -8,6 +8,14 @@ G75*
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M02*

905
Gerbers/solderpaste_top.gbr
View File

@ -10,110 +10,815 @@ G75*
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X436400Y334000D03*
X431400Y334000D03*
X426400Y334000D03*
X421400Y334000D03*
X416400Y334000D03*
X411400Y334000D03*
X406400Y334000D03*
X401400Y334000D03*
X396400Y334000D03*
X391400Y334000D03*
X386400Y334000D03*
X381400Y334000D03*
X376400Y334000D03*
X371400Y334000D03*
X366400Y334000D03*
X361400Y334000D03*
X356400Y334000D03*
X351400Y334000D03*
X346400Y334000D03*
G36*
X436898Y602930D02*
X434423Y600455D01*
X423818Y611060D01*
X426293Y613535D01*
X436898Y602930D01*
G37*
G36*
X433362Y599394D02*
X430887Y596919D01*
X420282Y607524D01*
X422757Y609999D01*
X433362Y599394D01*
G37*
G36*
X429827Y595859D02*
X427352Y593384D01*
X416747Y603989D01*
X419222Y606464D01*
X429827Y595859D01*
G37*
G36*
X426291Y592323D02*
X423816Y589848D01*
X413211Y600453D01*
X415686Y602928D01*
X426291Y592323D01*
G37*
G36*
X422756Y588788D02*
X420281Y586313D01*
X409676Y596918D01*
X412151Y599393D01*
X422756Y588788D01*
G37*
G36*
X419220Y585252D02*
X416745Y582777D01*
X406140Y593382D01*
X408615Y595857D01*
X419220Y585252D01*
G37*
G36*
X415685Y581717D02*
X413210Y579242D01*
X402605Y589847D01*
X405080Y592322D01*
X415685Y581717D01*
G37*
G36*
X412149Y578181D02*
X409674Y575706D01*
X399069Y586311D01*
X401544Y588786D01*
X412149Y578181D01*
G37*
G36*
X408614Y574646D02*
X406139Y572171D01*
X395534Y582776D01*
X398009Y585251D01*
X408614Y574646D01*
G37*
G36*
X405078Y571110D02*
X402603Y568635D01*
X391998Y579240D01*
X394473Y581715D01*
X405078Y571110D01*
G37*
G36*
X401543Y567575D02*
X399068Y565100D01*
X388463Y575705D01*
X390938Y578180D01*
X401543Y567575D01*
G37*
G36*
X398007Y564039D02*
X395532Y561564D01*
X384927Y572169D01*
X387402Y574644D01*
X398007Y564039D01*
G37*
G36*
X394471Y560504D02*
X391996Y558029D01*
X381391Y568634D01*
X383866Y571109D01*
X394471Y560504D01*
G37*
G36*
X390936Y556968D02*
X388461Y554493D01*
X377856Y565098D01*
X380331Y567573D01*
X390936Y556968D01*
G37*
G36*
X387400Y553432D02*
X384925Y550957D01*
X374320Y561562D01*
X376795Y564037D01*
X387400Y553432D01*
G37*
G36*
X383865Y549897D02*
X381390Y547422D01*
X370785Y558027D01*
X373260Y560502D01*
X383865Y549897D01*
G37*
G36*
X380329Y546361D02*
X377854Y543886D01*
X367249Y554491D01*
X369724Y556966D01*
X380329Y546361D01*
G37*
G36*
X376794Y542826D02*
X374319Y540351D01*
X363714Y550956D01*
X366189Y553431D01*
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X360178Y547420D01*
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G37*
G36*
X369723Y535755D02*
X367248Y533280D01*
X356643Y543885D01*
X359118Y546360D01*
X369723Y535755D01*
G37*
G36*
X366187Y532219D02*
X363712Y529744D01*
X353107Y540349D01*
X355582Y542824D01*
X366187Y532219D01*
G37*
G36*
X362652Y528684D02*
X360177Y526209D01*
X349572Y536814D01*
X352047Y539289D01*
X362652Y528684D01*
G37*
G36*
X359116Y525148D02*
X356641Y522673D01*
X346036Y533278D01*
X348511Y535753D01*
X359116Y525148D01*
G37*
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X353106Y519138D01*
X342501Y529743D01*
X344976Y532218D01*
X355581Y521613D01*
G37*
G36*
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X349570Y515602D01*
X338965Y526207D01*
X341440Y528682D01*
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X736600Y538640D03*
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X264000Y502920D03*
D12*
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X327660Y518000D03*
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X566420Y498000D03*
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X160020Y523400D03*
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X160020Y594200D03*
D14*
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X710550Y443000D03*
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X694050Y573000D03*
X688550Y573000D03*
X797350Y573000D03*
X791850Y573000D03*
X786350Y573000D03*
X780850Y573000D03*
X775350Y573000D03*
X769850Y573000D03*
X764350Y573000D03*
X764350Y443000D03*
X769850Y443000D03*
X775350Y443000D03*
X780850Y443000D03*
X786350Y443000D03*
X791850Y443000D03*
X797350Y443000D03*
X802850Y443000D03*
X808350Y443000D03*
X813850Y443000D03*
X819350Y443000D03*
X824850Y443000D03*
X830350Y443000D03*
X835850Y443000D03*
X835850Y573000D03*
X830350Y573000D03*
X824850Y573000D03*
X819350Y573000D03*
X813850Y573000D03*
X808350Y573000D03*
X802850Y573000D03*
D15*
X244500Y457200D03*
X263500Y457200D03*
X244500Y431800D03*
X263500Y431800D03*
X244500Y406400D03*
X263500Y406400D03*
D16*
X127000Y574700D03*
X127000Y593700D03*
X101600Y574700D03*
X101600Y593700D03*
D17*
X234950Y528066D03*
X234950Y589534D03*
X247650Y528066D03*
X260350Y528066D03*
X247650Y589534D03*
X260350Y589534D03*
X273050Y528066D03*
X273050Y589534D03*
D18*
X198120Y607060D03*
X198120Y510540D03*
M02*

30
README.md
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@ -1,24 +1,28 @@
# SE-VGA
Simple CPLD project to mirror the Mac SE video over VGA. No scaling is performed -- the Mac 512x342 video is displayed letterboxed (black borders) in a 640x480 frame. Plugs into SE PDS slot and snoops writes to the frame buffer memory locations. Writes are cached and copied to VRAM.
Simple CPLD project to mirror the Mac SE video over VGA. The image is pixel-doubled to 1024x684 and displayed letterboxed (black borders) in a 1024x768 video frame. Device snoops writes to the frame buffer memory locations and caches the data to its own VRAM for display. Plugs into the PDS slot in a Mac SE, or plugs in place of the CPU on Mac SE, Plus, or 512k models (128k Mac could be made to work with some adjustment to the CPLD configuration, but is not a configuration supported by the memory selection jumpers).
Circuit uses a single AFT1508AS-100AU CPLD, a pair of 256kbit (32kx8) 15ns SRAM, and a 25.175MHz can oscillator, along with some passives.
Circuit uses a single AFT1508AS-7AX100 CPLD, a pair of 256kbit (32kx8) 15ns or faster SRAM, a 13MHz crystal with 5x clock multiplier for 65MHz pixel clock, along with some passives.
## Bill of Materials
| Qty | Manufacturer | Part No. | Name | Description |
|:---:|:----------------|:-------------------|:-------------------|:----------------------------------------------|
| 2 | Renesas | 71256SA12TPG | VRAM-ALT, VRAM-MAIN| 32kx8 15ns SRAM |
| 1 | Microchip | ATF1508AS-7AX100 | LOGIC | ATF1508AS or EPM7128 CPLD |
| 1 | CTS | MXO45HS-3C-25M1750 | CLK | 25.175MHz oscillator |
| 2 | ISSI | IS61C256AL-12TLI | VRAM-ALT, VRAM-MAIN| 32kx8 12ns SRAM, TSOP-28 |
| 1 | Microchip | ATF1508AS-7AX100 | LOGIC | ATF1508AS or EPM7128 CPLD, TQFP-100 |
| 1 | Renesas / IDT | 511MLF | CLK | Programmable Clock Multiplier, SO-8 |
| 1 | ECS | ECS-130-20-46X | XTAL | 13MHz Crystal, HC-46X or HC-49UP |
| 1 | TE Connectivity | 650473-5 | PDS | DIN 41612 Right-angle 3x32 pin male connector |
| 5 | | | C1, C2, C3, C4, C5 | 0.1uF Decoupling Capacitor |
| 5 | | | C1, C2, C3, C4, C5 | 0.1uF Decoupling Capacitor, 0805 |
| 2 | | | C6, C7 | 10uF Electrolytic Capacitor |
| 2 | | | R7, R8, R9 | 4k7 pullup resistor (value not critical) |
| 3 | | | R1, R2, R3 | 470 ohm resistor |
| 3 | | | R4, R5, R6 | 75 ohm resistor |
| 2 | | | C8, C9 | 20pF Capacitor, 0805 |
| 2 | | | R3, R4, R5 | 10k pullup resistor, 0805 or axial |
| 3 | | | R2 | 460 ohm resistor, 0805 or axial |
| 3 | | | R1 | 75 ohm resistor, 0805 or axial |
| 1 | | | PGM | 2x5 pin header for CPLD JTAG programming |
| 1 | | | VGA | 6x1 pin header for VGA adapter |
| 1 | | | VGA | 2x5 pin header for VGA adapter |
| 1 | | | RAMSIZE | 3x2 jumper |
| 1 | | | BRD | 64-pin DIP header, male |
| 1 | | | CPU | 64-pin DIP socket, female |
## Frame Buffer Addressing
@ -124,11 +128,11 @@ Logic uses nearly all available resources in the CPLD (104 of 128 macrocells).
|TMS|Input|PIN_15
## Known Issues
First run schematic and gerbers used three pairs of resistor dividers for R, G, B output channels. A better approach would be to use a single divider and tie all three output channels together. Also 470 ohm is a bit too high, so the image is quite dark.
~~First run schematic and gerbers used three pairs of resistor dividers for R, G, B output channels. A better approach would be to use a single divider and tie all three output channels together. Also 470 ohm is a bit too high, so the image is quite dark.~~ Removed extraneous resistor dividers. Changed 470ohm resistor to 460.
The resistor footprints are too small for 1/4W parts. Might work with 1/8W parts.
~~The resistor footprints are too small for 1/4W parts. Might work with 1/8W parts.~~ Added footprints for 0805 resistors.
Timing for the SE window is a bit off. It appears to be starting the window a couple pixels early on the left, and it might be cutting off the last pixel or two on the right.
## Wish List
I would like to bump up the pixel clock to 65MHz and run the output video at 1024x768@60. This would allow the SE frame to be pixel doubled to 1024x684, which would only leave black bars on the top and bottom, instead of on all four sides. This could also be a useful starting point for a future project to output video for an early iPad display for units missing a CRT.
~~I would like to bump up the pixel clock to 65MHz and run the output video at 1024x768@60. This would allow the SE frame to be pixel doubled to 1024x684, which would only leave black bars on the top and bottom, instead of on all four sides. This could also be a useful starting point for a future project to output video for an early iPad display for units missing a CRT. ~~

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/******************************************************************************
* SE-VGA
* Top-level module
* techav
* 2021-10-16
******************************************************************************
* Trying again again again
*****************************************************************************/
module sevga (
input wire nReset, // System reset signal
input wire pixClk, // 65MHz pixel clock
output reg nhSync, // HSync signal
output reg nvSync, // VSync signal
output reg vidOut, // 1-bit Monochrome video signal
output logic [14:0] vramAddr, // VRAM Address bus
inout logic [7:0] vramData, // VRAM Data bus
output reg nvramOE, // VRAM Read strobe
output reg nvramWE, // VRAM Write strobe
output reg nvramCE0, // VRAM Main chip select signal
output reg nvramCE1, // VRAM Alt chip select signal
input wire [23:1] cpuAddr, // CPU Address bus
input wire [15:0] cpuData, // CPU Data bus
input wire ncpuAS, // CPU Address Strobe signal
input wire ncpuUDS, // CPU Upper Data Strobe signal
input wire ncpuLDS, // CPU Lower Data Strobe signal
input wire cpuRnW, // CPU Read/Write select signal
input logic [2:0] ramSize // Select installed RAM size
);
/******************************************************************************
* Initial Video Signal Timing
* The following functions establish the basic XGA signal timing and
* assert the horizontal and vertical sync signals as appropriate.
* These functions are the minimum required for a signal presence detect test.
*****************************************************************************/
// Primary sync counters
logic [10:0] hCount; // 0..1343
logic [9:0] vCount; // 0..805
always @(negedge pixClk) begin
if(hCount < 1343) hCount <= hCount + 11'h1;
else begin
hCount <= 0;
if(vCount <= 805) vCount <= vCount + 10'h1;
else vCount <= 0;
end
end
// Horizontal sync
always @(negedge pixClk) begin
if(hCount == 0) nhSync <= 1;
else if(hCount == 1052) nhSync <= 0;
else if(hCount == 1186) nhSync <= 1;
end
// Vertical sync
always @(negedge pixClk) begin
if(vCount == 0) nvSync <= 1;
else if(vCount == 729) nvSync <= 0;
else if(vCount == 734) nvSync <= 0;
end
/******************************************************************************
* Useful signals
* Here we break out a few useful signals, derived from the timing above, that
* will help us elsewhere.
*****************************************************************************/
// Horizontal active
reg hActive;
always @(negedge pixClk) begin
if(hCount == 0) hActive <= 1;
else if(hCount == 1023) hActive <= 0;
else if(hCount == 1343) hActive <= 1;
end
// Vertical active
reg vActive;
always @(negedge pixClk) begin
if(vCount == 0) vActive <= 1;
else if(vCount == 683) vActive <= 0;
else if(vCount == 805) vActive <= 1;
end
// Horizontal fetch active
// asserted just before active video to enable video data pre-fetch
reg fhActive;
always @(negedge pixClk) begin
if(hCount == 0) fhActive <= 1;
else if(hCount == 1022) fhActive <= 0;
else if(hCount == 1342) fhActive <= 1;
end
// Vertical fetch active
//
reg fvActive;
always @(negedge pixClk) begin
if(vCount == 0) fvActive <= 1;
else if(vCount == 684) fvActive <= 0;
if(vCount == 805) fvActive <= 1;
end
// combined active signals
wire vidActive = hActive & vActive;
wire fetchActive = fhActive & fvActive;
/******************************************************************************
* VRAM State Machine
* Coordinates VRAM load/store actions
*****************************************************************************/
// rising edge signals: nvramWE, nvramOE, nvramCE[1:0]
// falling edge signals: vramAddr, vramData
// VRAM read signal
//always @(posedge pixClk) begin nvramOE <= ~(hCount == 7); end
// VRAM write signal
always @(posedge pixClk) begin
if(hCount[3:1] == 0) nvramWE <= 1;
else if(hCount[3:1] == 1) nvramWE <= 0;
else if(hCount[3:1] == 6) nvramWE <= 1;
end
// VRAM data/address busses
always @(negedge pixClk) begin
if(hCount[0] && !hCount[1]) begin
case(hCount[3:2])
3: begin
// start read cycle
vramData <= 8'hZ;
vramAddr[14:6] <= vCount[9:1];
vramAddr[5:0] <= hCount[9:4];
end
default: begin
// write slots
vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
if(!ncpuUDSr && !cpuLDSsrv) begin
vramAddr[0] <= 0;
vramData <= cpuData[15:8];
end else if(!ncpuLDSr && !cpuLDSsrv) begin
vramAddr[0] <= 1;
vramData <= cpuData[7:0];
end
end
endcase
end
end
// VRAM chip enable signals
reg cpuUDSsrv, cpuLDSsrv;
always @(posedge pixClk) begin
if(hCount[3:1] == 7 && fetchActive) begin
nvramCE0 <= vidBufSel;
nvramCE1 <= ~vidBufSel;
nvramOE <= 0;
end else if(!hCount[0] && hCount[1]) begin
// write cycle
if(!ncpuUDSr && !cpuUDSsrv) begin
nvramCE0 <= ~cpuAddr[15];
nvramCE1 <= cpuAddr[15];
cpuUDSsrv <= 1;
end else if(!ncpuLDSr && !cpuLDSsrv) begin
nvramCE0 <= ~cpuAddr[15];
nvramCE1 <= cpuAddr[15];
cpuLDSsrv <= 1;
end else begin
nvramCE0 <= 1;
nvramCE1 <= 1;
end
nvramOE <= 1;
end else begin
nvramCE0 <= 1;
nvramCE1 <= 1;
nvramOE <= 1;
end
// reset the upper/lower serve signals when cycle ended by CPU
if(ncpuLDS) cpuLDSsrv <= 0;
if(ncpuUDS) cpuUDSsrv <= 0;
end
// Video data shift register & output
reg [7:0] vidShiftr;
always @(negedge pixClk) begin
if(hCount[3:0] == 4'hF) vidShiftr <= ~vramData;
else if(hCount[0]) begin
vidShiftr[7:1] <= vidShiftr[6:0];
vidShiftr[0] <= 0;
end
end
always_comb begin
if(vidActive) vidOut = vidShiftr[7];
else vidOut <= 0;
end
/******************************************************************************
* CPU Bus Snooping
* Watches the CPU bus and aligns its operations with the pixel clock
*****************************************************************************/
reg ncpuUDSr, ncpuLDSr;
always @(negedge pixClk) begin
// this condition evaluates true when cpu is writing to video buffer
if(!ncpuAS && !cpuRnW
&& !cpuAddr[23] && !cpuAddr[22]
&& !(cpuAddr[21] ^ ramSize[2])
&& !(cpuAddr[20] ^ ramSize[1])
&& !(cpuAddr[19] ^ ramSize[0])
&& cpuAddr[18] && cpuAddr[17]
&& cpuAddr[16]
&& ((cpuAddr[14:1] >= 14'h1380)
&& (cpuAddr[14:1] < 14'h3E40)))
begin
if(!ncpuUDS) ncpuUDSr <= 0;
else ncpuUDSr <= 1;
if(!ncpuLDS) ncpuLDSr <= 0;
else ncpuLDSr <= 1;
end else begin
ncpuUDSr <= 1;
ncpuLDSr <= 1;
end
end
// hold low for now
reg vidBufSel = 0;
endmodule

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/******************************************************************************
* SE-VGA
* Top-level module
* techav
* 2021-10-12
******************************************************************************
* This is ... mostly working. It has some write glitches and a vertical line
* five pixels from the left side of the screen.
*****************************************************************************/
module sevga (
input wire nReset, // System reset signal
input wire pixClk, // 65MHz pixel clock
output wire nhSync, // HSync signal
output wire nvSync, // VSync signal
output wire vidOut, // 1-bit Monochrome video signal
output logic [14:0] vramAddr, // VRAM Address bus
inout logic [7:0] vramData, // VRAM Data bus
output wire nvramOE, // VRAM Read strobe
output wire nvramWE, // VRAM Write strobe
output wire nvramCE0, // VRAM Main chip select signal
output wire nvramCE1, // VRAM Alt chip select signal
input logic [23:1] cpuAddr, // CPU Address bus
input logic [15:0] cpuData, // CPU Data bus
input wire ncpuAS, // CPU Address Strobe signal
input wire ncpuUDS, // CPU Upper Data Strobe signal
input wire ncpuLDS, // CPU Lower Data Strobe signal
input wire cpuRnW, // CPU Read/Write select signal
input logic [2:0] ramSize // Select installed RAM size
);
/******************************************************************************
* Initial Video Signal Timing
* The following four functions establish the basic XGA signal timing and
* assert the horizontal and vertical sync signals as appropriate.
* These functions are the minimum required for a signal presence detect test.
*****************************************************************************/
logic [10:0] hCount; // 0..1343
logic [9:0] vCount; // 0..805
wire nhSyncInner;
// Primary video sync counters -- Now more synchronous!
always @(negedge pixClk) begin
if(hCount < 11'd1343) hCount <= hCount + 11'd1;
else begin
hCount <= 11'd0;
if(vCount < 10'd805) vCount <= vCount + 10'd1;
else vCount <= 10'd0;
end
end
// horizontal and vertical sync signals
always_comb begin
//if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
if(hCount >= 11'd1052 && hCount < 11'd1187) nhSyncInner <= 0;
else nhSyncInner <= 1;
nhSync <= nhSyncInner;
if(vCount >= 10'd729 && vCount < 10'd735) nvSync <= 0;
else nvSync <= 1;
end
/******************************************************************************
* Useful signals
* Here we break out a few useful signals, derived from the timing above, that
* will help us elsewhere.
*****************************************************************************/
wire hActive, vActive; // active video signals. vidout black when negated
wire vidActive; // active when both hActive and vActive asserted
wire hLoad; // load pixel data from vram when asserted
assign vidActive = hActive & vActive;
always_comb begin
if(hCount >= 3 && hCount < 1027) hActive <= 1;
else hActive <= 0;
if(vCount >= 0 && vCount < 684) vActive <= 1;
else vActive <= 0;
if(hCount >= 0 && hCount < 1024 && vActive) hLoad <= 1;
else hLoad <= 0;
end
/******************************************************************************
* Primary State Machine
* This is the primary state machine which runs the entire system, handling
* VRAM reads, VRAM writes, VIA writes, and idle states
*****************************************************************************/
// used to align primary state machine with horizontal counter
wire [3:0] vSeq = hCount[3:0];
// define state machine states (Gray code)
parameter
S0 = 4'b0000, // VRAM Read 0
S1 = 4'b0001, // VRAM Read 1
S2 = 4'b0011, // Idle
S3 = 4'b0010, // VRAM Write Upper 0
S4 = 4'b0110, // VRAM Write Upper 1
S5 = 4'b0111, // VRAM Write Lower 0
S6 = 4'b0101, // VRAM Write Lower 1
S7 = 4'b0100, // VIA Write
S8 = 4'b1100, // VSync (to be added later)
S9 = 4'b1101, // undefined
S10 = 4'b1111, // undefined
S11 = 4'b1110, // undefined
S12 = 4'b1010, // undefined
S13 = 4'b1011, // undefined
S14 = 4'b1001, // undefined
S15 = 4'b1000; // undefined
logic [3:0] pState;
// And here is the much simplified primary state machine
always @(negedge pixClk or negedge nReset) begin
if(!nReset) pState <= S2; // resync on reset by jumping to idle state
else begin
case(pState)
S0: pState <= S1; // first VRAM read state, always move to S1
S3: pState <= S4; // first UDS write state, always move to S4
S5: pState <= S6; // first LDS write state, always move to S6
/*S7: begin
pState <= S2;
end*/
S2: begin
// here is where everything actually happens.
if(vSeq == 4'hF) pState <= S0; // time for a read state
else if(cpuUWriteReq && !cpuUWriteSrv && vSeq < 4'hD) pState <= S3;
else if(cpuLWriteReq && !cpuLWriteSrv && vSeq < 4'hD) pState <= S5;
else if(cpuVIAReq && !cpuVIASrv && vSeq < 4'hE) pState <= S7;
else pState <= S2;
end
default: pState <= S2; // everyone ends up at S2 (idle)
endcase
end
end
// primary VRAM signal combination, based on the primary state machine
always_comb begin
// VRAM Read Strobe
if((pState == S0 || pState == S1) && hLoad) nvramOE <= 0;
else nvramOE <= 1;
// VRAM Write Strobe
if(pState == S3 || pState == S5) nvramWE <= 0;
else nvramWE <= 1;
// VRAM Chip Enable Signals
case(pState)
S0, S1: begin
if(hLoad) begin
nvramCE0 <= ~vidBufSel;
nvramCE1 <= vidBufSel;
end else begin
nvramCE0 <= 1;
nvramCE1 <= 1;
end
end
S3, S4, S5, S6: begin
nvramCE0 <= ~cpuBufSel;
nvramCE1 <= cpuBufSel;
end
default: begin
nvramCE0 <= 1;
nvramCE1 <= 1;
end
endcase
// VRAM Address Bus
case(pState)
S0, S1: begin
// address bus for read cycles
if(hLoad) begin
vramAddr[14:6] <= vCount[9:1];
vramAddr[5:0] <= hCount[9:4];
end else begin
vramAddr <= 0;
end
end
S3, S4: begin
// address bus for upper write cycles
vramAddr[14:1] <= cpuAddrShift;
vramAddr[0] <= 0;
end
S5, S6: begin
// address bus for lower write cycles
vramAddr[14:1] <= cpuAddrShift;
vramAddr[0] <= 1;
end
default: begin
// address bus for idle cycles
vramAddr <= 0;
end
endcase
// VRAM Data bus
case(pState)
S3, S4 : vramData <= cpuData[15:8];
S5, S6 : vramData <= cpuData[7:0];
default: vramData <= 8'hZ;
endcase
end
/******************************************************************************
* Video Output Sequencing
* Here is the primary video output shift register sequencing.
* With these functions in place, it should be possible to strap the VRAM data
* signals and see the strapped pattern output on screen.
*****************************************************************************/
logic [8:0] vidData; // the video data we are displaying
// output shift register
always @(posedge pixClk) begin
if(pState == S1 && hLoad) begin
// store VRAM data in shift register
vidData[7:0] <= vramData;
end else if(!hCount[0] && vidActive) begin
// shift out video data
vidData[8:1] <= vidData[7:0];
vidData[0] <= 1;
end
end
// final video output
always_comb begin
if(vidActive) vidOut <= ~vidData[8];
else vidOut <= 0;
end
/******************************************************************************
* CPU Bus Snooping
* Watch the CPU bus for writes to the video buffer regions of memory and write
* that data to VRAM. VRAM write cycles can occur during vidSeq 1 through 7.
* High-order bytes are passed to VRAM on tick states and low-order bytes are
* passed to VRAM on tock states. After the VRAM writes are complete, state
* machine waits for the CPU cycle to end before returning to idle.
*****************************************************************************/
/* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
* $8000 below the main frame buffer
* ramSize is used to mask the CPU Address bits [21:19] to select the amount
* of memory installed in the computer. Not all possible ramSize selections
* are valid memory sizes when using 30-pin SIMMs in the Mac SE.
* They may be possible using PDS RAM expansion cards.
* ramSize mainBuffer altBuffer ramTop+1 ramSize Valid? Installed SIMMs
* $7 $3fa700 $3f2700 $400000 4.0MB Y [ 1MB 1MB ][ 1MB 1MB ]
* $6 $37a700 $372700 $380000 3.5MB N
* $5 $2fa700 $2f2700 $300000 3.0MB N
* $4 $27a700 $272700 $280000 2.5MB Y [ 1MB 1MB ][256kB 256kB]
* $3 $1fa700 $1f2700 $200000 2.0MB Y [ 1MB 1MB ][ --- --- ]
* $2 $17a700 $172700 $180000 1.5MB N
* $1 $0fa700 $0f2700 $100000 1.0MB Y [256kB 256kB][256kB 256kB]
* $0 $07a700 $072700 $080000 0.5MB Y [256kB 256kB][ --- --- ]
*/
// keep track of pending CPU write requests and whether they have been serviced
wire cpuUWriteReq, cpuLWriteReq, cpuVIAReq;
reg cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
wire cpuBufSel;
wire cpuBufAddr;
reg vidBufSel;
wire [13:0] cpuAddrShift = cpuAddr[14:1] - 14'h1380;
wire cpuBufRange;
// these are some helpful signals that shortcut the CPU buffer & VIA addresses
always_comb begin
/*if(cpuAddr[14:1] >= 14'h1380
&& cpuAddr[14:1] < 14'h3E40) cpuBufRange <= 1;
else cpuBufRange <= 0;*/
cpuBufRange <= (cpuAddr[14:1] >= 14'h1380) & (cpuAddr[14:1] < 14'h3E40);
if(!ncpuAS && !cpuRnW
&& !cpuAddr[23] && !cpuAddr[22] // first two bits always 0
&& !(cpuAddr[21] ^ ramSize[2]) // compare with RAM Size bits
&& !(cpuAddr[20] ^ ramSize[1])
&& !(cpuAddr[19] ^ ramSize[0])
&& cpuAddr[18] && cpuAddr[17] // next three bits always 1
&& cpuAddr[16] // skip 15, it selects buffers
&& cpuBufRange // only select buffer addresses
) begin
cpuBufAddr <= 1;
end else begin
cpuBufAddr <= 0;
end
cpuBufSel <= ~cpuAddr[15]; // address bit 15 selects buffer
if(cpuBufAddr && !ncpuUDS) cpuUWriteReq <= 1;
else cpuUWriteReq <= 0;
if(cpuBufAddr && !ncpuLDS) cpuLWriteReq <= 1;
else cpuLWriteReq <= 0;
// VIA is in address block $E8,0000 - $EF,FFFF
// VIA register select pins (RS[3:0]) are wired to cpuAddr[12:9]
// VIA Output Register A is selected when RS[3:0]==$F
/*if(!ncpuAS && !cpuRnW && !ncpuUDS
&& cpuAddr[23] && cpuAddr[22] // VIA Address Select
&& cpuAddr[21] && !cpuAddr[20]
&& cpuAddr[19]
&& cpuAddr[12] && cpuAddr[11] // VIA ORA
&& cpuAddr[10] && cpuAddr[9]
) cpuVIAReq <= 1;
else cpuVIAReq <= 0;*/
// Mac ROM addresses Data Register A as vBase+vBufA:
// $EF,E1FE + (512*15) = $EF,FFFE
// shift right by one because no A0 and we get $77,FFFF
// This bit is giving me hell, so let's expand it
if(ncpuAS==0 && cpuRnW==0 && ncpuUDS==0
&& cpuAddr == 22'h77FFFF) cpuVIAReq <= 1;
else cpuVIAReq <= 0;
end
// if there's an active CPU request and we've reached the state for servicing
// that CPU request, then set a flag to mark that we have serviced it
always @(posedge pixClk or posedge ncpuAS) begin
if(ncpuAS) begin
cpuUWriteSrv <= 0;
cpuLWriteSrv <= 0;
cpuVIASrv <= 0;
end else begin
if(ncpuAS) begin
cpuUWriteSrv <= 0;
cpuLWriteSrv <= 0;
cpuVIASrv <= 0;
end else begin
if(cpuUWriteReq && pState == S3) cpuUWriteSrv <= 1;
if(cpuLWriteReq && pState == S5) cpuLWriteSrv <= 1;
if(cpuVIAReq && pState == S7) cpuVIASrv <= 1;
end
end
end
// store the video buffer selection bit
always @(posedge pixClk or negedge nReset) begin
if(!nReset) vidBufSel <= 0;
// fine. no video buffer select. we use Main only.
//else if(pState == S7) vidBufSel <= ~cpuData[14];
end
endmodule