Warp-LC/fpga/ipcore_dir/CLK.veo

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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____66.667______0.000______50.0______300.590____267.927
//
//----------------------------------------------------------------------------
// "Input Clock   Freq (MHz)    Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________33.3333___________0.00833333333333

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

  CLK instance_name
   (// Clock in ports
    .CLKIN(CLKIN),      // IN
    .CLKFB_IN(CLKFB_IN),     // IN
    // Clock out ports
    .FSBCLK(FSBCLK),     // OUT
    .CLKFB_OUT(CLKFB_OUT));   // OUT
// INST_TAG_END ------ End INSTANTIATION Template ---------