mirror of
https://github.com/garrettsworkshop/Warp-LC.git
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464 lines
18 KiB
HTML
464 lines
18 KiB
HTML
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='4'><B>WarpLC Project Status (10/29/2021 - 10:03:11)</B></TD></TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
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<TD>WarpLC.xise</TD>
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<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
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<TD> No Errors </TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
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<TD>WarpLC</TD>
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<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
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<TD>Placed and Routed</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
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<TD>xc6slx9-2ftg256</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
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<TD>
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No Errors</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
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<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/*.xmsgs?&DataKey=Warning'>527 Warnings (2 new)</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
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<TD>Balanced</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
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<TD>
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<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes'>All Signals Completely Routed</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
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<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
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<TD>
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<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
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<TD>
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<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_envsettings.html'>
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System Settings</A>
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</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
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<TD>0 <A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
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</TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
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<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
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<TD ALIGN=RIGHT>56</TD>
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<TD ALIGN=RIGHT>11,440</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
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<TD ALIGN=RIGHT>56</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
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<TD ALIGN=RIGHT>59</TD>
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<TD ALIGN=RIGHT>5,720</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
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<TD ALIGN=RIGHT>56</TD>
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<TD ALIGN=RIGHT>5,720</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
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<TD ALIGN=RIGHT>24</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
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<TD ALIGN=RIGHT>29</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
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<TD ALIGN=RIGHT>3</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD ALIGN=RIGHT>1,440</TD>
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<TD ALIGN=RIGHT>0%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD>
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<TD ALIGN=RIGHT>3</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
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<TD ALIGN=RIGHT>2</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
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<TD ALIGN=RIGHT>25</TD>
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<TD ALIGN=RIGHT>1,430</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
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<TD ALIGN=RIGHT>56</TD>
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<TD ALIGN=RIGHT>2,860</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
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<TD ALIGN=RIGHT>76</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
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<TD ALIGN=RIGHT>22</TD>
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<TD ALIGN=RIGHT>76</TD>
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<TD ALIGN=RIGHT>28%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
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<TD ALIGN=RIGHT>17</TD>
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<TD ALIGN=RIGHT>76</TD>
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<TD ALIGN=RIGHT>22%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
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<TD ALIGN=RIGHT>37</TD>
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<TD ALIGN=RIGHT>76</TD>
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<TD ALIGN=RIGHT>48%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
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<TD ALIGN=RIGHT>4</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
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<TD ALIGN=RIGHT>16</TD>
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<TD ALIGN=RIGHT>11,440</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
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<TD ALIGN=RIGHT>49</TD>
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<TD ALIGN=RIGHT>186</TD>
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<TD ALIGN=RIGHT>26%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Flip Flops</TD>
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<TD ALIGN=RIGHT>5</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Latches</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD ALIGN=RIGHT>32</TD>
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<TD ALIGN=RIGHT>0%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD ALIGN=RIGHT>64</TD>
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<TD ALIGN=RIGHT>0%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD ALIGN=RIGHT>32</TD>
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<TD ALIGN=RIGHT>3%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2s</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2_2CLKs</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD ALIGN=RIGHT>32</TD>
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<TD ALIGN=RIGHT>3%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2FBs</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2FB_2CLKs</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
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<TD ALIGN=RIGHT>3</TD>
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<TD ALIGN=RIGHT>16</TD>
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<TD ALIGN=RIGHT>18%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD>
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<TD ALIGN=RIGHT>3</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD ALIGN=RIGHT>4</TD>
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<TD ALIGN=RIGHT>0%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD ALIGN=RIGHT>200</TD>
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<TD ALIGN=RIGHT>1%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ILOGIC2s</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ISERDES2s</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD> </TD>
|
||
|
|
<TD> </TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>200</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
|
||
|
|
<TD ALIGN=RIGHT>5</TD>
|
||
|
|
<TD ALIGN=RIGHT>200</TD>
|
||
|
|
<TD ALIGN=RIGHT>2%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as OLOGIC2s</TD>
|
||
|
|
<TD ALIGN=RIGHT>5</TD>
|
||
|
|
<TD> </TD>
|
||
|
|
<TD> </TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as OSERDES2s</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD> </TD>
|
||
|
|
<TD> </TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>4</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>128</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>8</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>4</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>16</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>1</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>2</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>2</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
|
||
|
|
<TD ALIGN=RIGHT>1</TD>
|
||
|
|
<TD ALIGN=RIGHT>2</TD>
|
||
|
|
<TD ALIGN=RIGHT>50%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>1</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>1</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
|
||
|
|
<TD ALIGN=RIGHT>0</TD>
|
||
|
|
<TD ALIGN=RIGHT>1</TD>
|
||
|
|
<TD ALIGN=RIGHT>0%</TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
|
||
|
|
<TD ALIGN=RIGHT>2.16</TD>
|
||
|
|
<TD> </TD>
|
||
|
|
<TD> </TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TR>
|
||
|
|
</TABLE>
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
|
||
|
|
<TR ALIGN=LEFT>
|
||
|
|
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
|
||
|
|
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
|
||
|
|
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
|
||
|
|
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=LEFT>
|
||
|
|
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
|
||
|
|
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes'>All Signals Completely Routed</A></TD>
|
||
|
|
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
|
||
|
|
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
|
||
|
|
</TR>
|
||
|
|
<TR ALIGN=LEFT>
|
||
|
|
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
|
||
|
|
<TD>
|
||
|
|
<A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
|
||
|
|
<TD BGCOLOR='#FFFF99'><B> </B></TD>
|
||
|
|
<TD COLSPAN='2'> </TD>
|
||
|
|
</TABLE>
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||
|
|
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||
|
|
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:02:50 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>272 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
|
||
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:02:55 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>254 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:03:01 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (1 new)</A></TD></TR>
|
||
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:03:06 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||
|
|
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Oct 29 10:03:09 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||
|
|
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||
|
|
</TABLE>
|
||
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||
|
|
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||
|
|
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||
|
|
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri Oct 29 08:28:45 2021</TD></TR>
|
||
|
|
</TABLE>
|
||
|
|
|
||
|
|
|
||
|
|
<br><center><b>Date Generated:</b> 10/29/2021 - 10:03:11</center>
|
||
|
|
</BODY></HTML>
|