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Warp-LC
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Zane Kaminski 2023-05-03 23:32:00 -04:00
parent ea671fe500
commit 45ff80f44a
33 changed files with 50165 additions and 21336 deletions
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<html>
<head>
<title>Garrett's Workshop - Warp-LC Timing</title>
<style type="text/css">
ul {
margin-top: 0;
}
h3 {
margin-bottom: 0;
}
h2, h4 {
margin-bottom: 3px;
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margin-top:6px;
}
p {
margin-top:0;
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<script src="https://cdnjs.cloudflare.com/ajax/libs/wavedrom/2.6.8/wavedrom.min.js" type="text/javascript"></script>
</head>
<body onload="WaveDrom.ProcessAll()">
<h1>Garrett's Workshop Warp-LC 33 MHz 68030 Accelerator Documentation</h1>
<h3 id="t0">1. Three consecutive reads - row activate, row hit, row miss, next hit</h3>
<script type="WaveDrom">{signal: [
{name: 'RS', wave: '22222222222222222222222', data:['X',0,1,2,3,4,5,6,7,0,1,4,5,6,7,0,1,2,3,4,5,6,7,0]},
{name: 'FCLK', wave: 'p......................'},
{name: 'MCLK', wave: '10101010101010101010101', phase: 0.15, period:1.0},
{name: 'A', wave: 'x2......x2....x2......x', phase: 0.15, period:1.0},
{name: '/AS', wave: '.x0....x1x0..x1x0....x1', phase: 0.15, period:1.0},
{name: 'RCLK', wave: '0101010101010101010101010101010101010101010101', phase:0, period:0.5},
{name: 'RCMD', wave: '22222222222222222222222', phase:0, data:[
'NOP','NOP','NOP','ACT','RD','RD','NOP','NOP','NOP','NOP','RD','RD','NOP','NOP','NOP','NOP','PC','ACT','RD','RD','NOP','NOP','NOP','NOP']},
{name: 'RCKE', wave: '1....0101..0101....0101', phase:0},
{name: 'RD', wave: 'z..........x.2.x.2.z...x.2.x.2.z.......x.2.x.2', phase:0, period:0.5},
{name: '/RDOE', wave: '1....0..1..0..1..0....1', phase:0},
{name: 'MCLK', wave: '10101010101010101010101', phase: 0.15, period:1.0},
{name: 'STERM', wave: '1.........x0..x1......x0..x1..........x0..x1..', phase:0, period:0.5},
]}</script><br/><p>
<h3 id="t0">1. Three consecutive reads - non-prefeteched read, two next hits, next hit after idle, row hit</h3>
<script type="WaveDrom">{signal: [
{name: 'RS', wave: '22222222222222222222222222222222222', data:[7,0,1,2,3,4,5,6,7,0]},
{name: 'FCLK', wave: 'p..................................'},
{name: 'MCLK', wave: '10101010101010101010101010101010101', phase: 0.15, period:1.0},
{name: 'A', wave: '2...x2..x2..x2x2..x2....x2..x2x2..x', phase: 0.15, period:1.0},
{name: '/AS', wave: '0..x1x0x1x0x1..x0x1x0..x1x0x1..x0x1', phase: 0.15, period:1.0},
{name: 'RCLK', wave: '0101010101010101010101010101010101010101010101010101010101010101010101', phase:0, period:0.5},
{name: 'RCMD', wave: '22222222222222222222222222222222222', phase:0, data:[
'RD','NOP','NOP','NOP','RD','NOP','NOP','NOP','RD','NOP','NOP','NOP','RD','NOP','RD','NOP','NOP','NOP','RD','NOP','RD','NOP']},
{name: 'RCKE', wave: '101......01..0101', phase:0},
{name: 'RD', wave: 'z..........x.2.z...x.2.z...x.2.x.2.z...x.2.x.2.', phase:0, period:0.5},
{name: '/RDOE', wave: '0...1x0.1', phase:0},
{name: 'MCLK', wave: '101010101', phase: 0.15, period:1.0},
{name: 'STERM', wave: '1.x0..x1..x0..x1..', phase:0, period:0.5},
]}</script><br/><p>
<h3 id="t0">2. Three consecutive writes - row activate, row hit, row miss</h3>
<script type="WaveDrom">{signal: [
{name: 'RS', wave: '222222222222222222', data:['X',0,1,4,5,6,7,0,1,4,5,6,7,0,1,4,5,6,7,0]},
{name: 'FCLK', wave: 'p.................'},
{name: 'MCLK', wave: '101010101010101010', phase: 0.15, period:1.0},
{name: 'A', wave: 'x2....x2..x2....x2', phase: 0.15, period:1.0},
{name: '/AS', wave: '.x0..x1x0x1x0..x1.', phase: 0.15, period:1.0},
{name: 'RCLK', wave: '010101010101010101010101010101010101', phase:0, period:0.5},
{name: 'RCMD', wave: '222222222222222222', phase:0, data:[
'NOP','NOP','NOP','ACT','WR','NOP','NOP','NOP','NOP','WR','NOP','NOP','PC','ACT','WR','NOP','NOP','NOP']},
{name: 'RCKE', wave: '1.................', phase:0},
{name: 'RD', wave: 'z.....x.2.xz..x.2.xz......x.2.xz....', phase:0, period:0.5},
{name: '/RDOE', wave: '1..0.1.0.1...0.1..', phase:0},
{name: 'MCLK', wave: '101010101010101010', phase: 0.15, period:1.0},
{name: 'STERM', wave: '1..0.1.0.1...0.1..', phase:0},
]}</script><br/><p>
<h3 id="t0">3. MC68030 read row hit, then MC68030 changes its mind -- read, row activate, row hit, row miss</h3>
<script type="WaveDrom">{signal: [
{name: 'RS', wave: '22222222222222222222222222222', data:['X',0,1,0,1,2,3,4,5,6,7,0,1,0,1,4,5,6,7,0,1,0,1,2,3,4,5,6,7,0]},
{name: 'FCLK', wave: 'p............................'},
{name: 'MCLK', wave: '10101010101010101010101010101', phase: 0.15, period:1.0},
{name: 'A', wave: 'x2x2......x2x2....x2x2......x', phase: 0.15, period:1.0},
{name: '/AS', wave: '1..x0....x1..x0..x1..x0....x1', phase: 0.15, period:1.0},
{name: 'RCLK', wave: '0101010101010101010101010101010101010101010101010101010101', phase:0, period:0.5},
{name: 'RCMD', wave: '22222222222222222222222222222', phase:0, data:[
'NOP','NOP','RD','NOP','NOP','ACT','RD','NOP','NOP','NOP','NOP','NOP','RD','NOP','RD','NOP','NOP','NOP','NOP','NOP','RD','NOP','PC','ACT','RD','NOP','NOP','NOP','NOP']},
{name: 'RCKE', wave: '1......01......01........01..', phase:0},
{name: 'RD', wave: 'z......x.z.....x.2.z.......x.z.x.2.z..z....x.z.....x.2.z..', phase:0, period:0.5},
{name: '/RDOE', wave: '1....0.....1...0...1...0.....', phase:0},
{name: 'MCLK', wave: '10101010101010101010101010101', phase: 0.15, period:1.0},
{name: 'STERM', wave: '1......0.1.....0.1.......0.1.', phase:0},
]}</script><br/><p>
<h3 id="t0">4. MC68030 read row hit, then MC68030 changes its mind -- write, row miss</h3>
<script type="WaveDrom">{signal: [
{name: 'RS', wave: '222222222', data:['X',0,1,0,1,2,3,4,5]},
{name: 'FCLK', wave: 'p........'},
{name: 'MCLK', wave: '101010101', phase: 0.15, period:1.0},
{name: 'A', wave: 'x2x2....x', phase: 0.15, period:1.0},
{name: '/AS', wave: '1..x0..x1', phase: 0.15, period:1.0},
{name: 'RCLK', wave: '010101010101010101', phase:0, period:0.5},
{name: 'RCMD', wave: '222222222', phase:0, data:[
'NOP','NOP','RD','NOP','PC','ACT','WR','NOP','NOP','NOP','NOP','NOP','RD','NOP','RD','NOP','NOP','NOP','NOP','NOP','RD','NOP','PC','ACT','RD','NOP','NOP','NOP','NOP']},
{name: 'RCKE', wave: '1........', phase:0},
{name: 'RD', wave: 'z......x.zx.2.x.z.', phase:0, period:0.5},
{name: '/RDOE', wave: '1....0.1.', phase:0},
{name: 'MCLK', wave: '101010101', phase: 0.15, period:1.0},
{name: 'STERM', wave: '1....0.1.', phase:0},
]}</script><br/><p>
<h3 id="t0">5. MC68030 idle afte read</h3>
<script type="WaveDrom">{signal: [
{name: 'RS', wave: '22222222222', data:[5,6,7,0,1,0,1,0,1,0,1]},
{name: 'FCLK', wave: 'p..........'},
{name: 'MCLK', wave: '10101010101', phase: 0.15, period:1.0},
{name: 'A', wave: '2..........', phase: 0.15, period:1.0},
{name: '/AS', wave: '0x1........', phase: 0.15, period:1.0},
{name: 'RCLK', wave: '0101010101010101010101', phase:0, period:0.5},
{name: 'RCMD', wave: '22222222222', phase:0, data:[
'NOP','NOP','NOP','NOP','RD','NOP','RD','NOP','RD','NOP','RD','NOP','NOP','NOP','RD','NOP','RD','NOP','NOP','NOP','NOP','NOP','RD','NOP','PC','ACT','RD','NOP','NOP','NOP','NOP']},
{name: 'RCKE', wave: '1..........', phase:0},
{name: 'RD', wave: '2.....xz...x.z.x.z.x.z', phase:0, period:0.5},
{name: '/RDOE', wave: '0..1........', phase:0},
]}</script><br/><p>
<h3 id="t0">6. MC68030 idle afte write</h3>
<script type="WaveDrom">{signal: [
{name: 'RS', wave: '22222222222', data:[5,6,7,0,1,0,1,0,1,0,1]},
{name: 'FCLK', wave: 'p..........'},
{name: 'MCLK', wave: '10101010101', phase: 0.15, period:1.0},
{name: 'A', wave: '2..........', phase: 0.15, period:1.0},
{name: '/AS', wave: '0x1........', phase: 0.15, period:1.0},
{name: 'RCLK', wave: '0101010101010101010101', phase:0, period:0.5},
{name: 'RCMD', wave: '22222222222', phase:0, data:[
'WR','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','PC','ACT','NOP','NOP','NOP','NOP','NOP']},
{name: 'RCKE', wave: '1..........', phase:0},
{name: 'RD', wave: '2.xz..................', phase:0, period:0.5},
{name: '/RDOE', wave: '01.........', phase:0},
]}</script><br/><p>
</body>
</html>

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<html>
<head>
<title>Garrett's Workshop - Warp-LC Timing</title>
<style type="text/css">
ul {
margin-top: 0;
}
h3 {
margin-bottom: 0;
}
h2, h4 {
margin-bottom: 3px;
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h3 + h4 {
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}
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<script src="https://cdnjs.cloudflare.com/ajax/libs/wavedrom/2.6.8/skins/default.js" type="text/javascript"></script>
<script src="https://cdnjs.cloudflare.com/ajax/libs/wavedrom/2.6.8/wavedrom.min.js" type="text/javascript"></script>
</head>
<body onload="WaveDrom.ProcessAll()">
<h1>Garrett's Workshop Warp-LC 50 MHz 68030 Accelerator Documentation</h1>
<h3 id="t0">RAM single read - cache miss, wrong row open</h3>
<script type="WaveDrom">{signal: [
{name: '100 MHz CLK', wave: 'p.....................', phase: 0.00, period: 1.0},
{name: 'CPUCLK', wave: '0101010101010101010101', phase: 0.00, period: 1.0},
["'030 bus inputs",
{name: 'R/W', wave: 'xxxxxxxxxx1...................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, FC, /RMC', wave: 'xxxxxxxxxx2...................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxxx2...................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x..0................x..1............', phase: 0.00, period: 0.5},
{name: '/ASr', wave: '1..0....1..', phase: 0.00, period: 2.0},
{name: '/CBREQ', wave: '1...........................................', phase: 0.00, period: 0.5}],
{name: '/STERM', wave: '1...........0.1.......', phase: 0.00, period: 1.0},
["L2$ ctrl.",
{name: 'L2RDCLK', wave: '0.....1.........0.....', phase: 0.00, period: 1.0},
{name: 'L2WRCLK', wave: '0.............10......', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '22.2.2.2.2.2.2.2.2.2.2', phase: 0.00, period: 1.0, data:[
'idle', 'idle', 'idle', 'idle', 'read0', 'read1', 'read2', 'read3', 'read4', 'idle', 'idle', 'idle']},
{name: 'RAMCMD', wave: '2222222222222222222222', phase: 0.00, period: 1.0, data:[
'NOP','NOP',
'NOP','NOP',
'NOP','NOP',
'NOP','PC',
'NOP','ACT',
'NOP','RD',
'NOP','NOP',
'NOP','NOP',
'NOP','PC',
'NOP','NOP',
'NOP','NOP']},
{name: 'RAMCKE', wave: '1...........01........', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '01010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: '/FDOE', wave: '1......01.............', phase: 0.00, period: 1.0},
{name: '/BDOE', wave: '1.......0......1......', phase: 0.00, period: 1.0},
{name: 'BDDIR', wave: '1......0........1.....', phase: 0.00, period: 1.0}],
{name: 'BD', wave: 'zzzzzzzzzzzzzzxxxxzzzzzzzx2..xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzxxxxxxxxxxx2.xxzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
]}</script><br/><p>
</p>
<h3 id="t0">RAM single read - cache hit, wrong row open</h3>
<script type="WaveDrom">{signal: [
{name: '100 MHz CLK', wave: 'p.................', phase: 0.00, period: 1.0},
{name: 'CPUCLK', wave: '010101010101010101', phase: 0.00, period: 1.0},
["'030 bus inputs",
{name: 'R/W', wave: 'xxxxxxxxxx1...........xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, FC, /RMC', wave: 'xxxxxxxxxx2...........xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxxx2...........xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x..0........x..1............', phase: 0.00, period: 0.5},
{name: '/ASr', wave: '1..0..1..', phase: 0.00, period: 2.0},
{name: '/CBREQ', wave: '1...................................', phase: 0.00, period: 0.5}],
{name: '/STERM', wave: '1.......0.1.......', phase: 0.00, period: 1.0},
["L2$ ctrl.",
{name: 'L2RDCLK', wave: '0.....1.....0.....', phase: 0.00, period: 1.0},
{name: 'L2WRCLK', wave: '0.................', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '22.2.2.2.2.2.2.2.2', phase: 0.00, period: 1.0, data:[
'idle', 'idle', 'idle', 'idle', 'read0', 'read1', 'read2', 'read3', 'read4', 'idle', 'idle', 'idle']},
{name: 'RAMCMD', wave: '222222222222222222', phase: 0.00, period: 1.0, data:[
'NOP','NOP',
'NOP','NOP',
'NOP','NOP',
'NOP','PC',
'NOP','ACT',
'NOP','NOP',
'NOP','NOP',
'NOP','NOP',
'NOP','NOP']},
{name: 'RAMCKE', wave: '1.................', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: '/FDOE', wave: '1......0...1......', phase: 0.00, period: 1.0},
{name: '/BDOE', wave: '1.......0..1......', phase: 0.00, period: 1.0},
{name: 'BDDIR', wave: '1......0....1.....', phase: 0.00, period: 1.0}],
{name: 'BD', wave: 'zzzzzzzzzzzzzzxxx2....xxzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzxxx2..xxzzzzzzzzzzzz', phase: 0.00, period: 0.5},
]}</script><br/><p>
</p>
</body>
</html>

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<html>
<head>
<title>Garrett's Workshop - Mac IIci RAM card timing</title>
<style type="text/css">
ul {
margin-top: 0;
}
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margin-bottom: 0;
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<body onload="WaveDrom.ProcessAll()">
<h1>Garrett's Workshop IIci RAM card timing Documentation</h1>
<h3 id="t0">RAM single read - cache miss, bank precharged or wrong row open</h3>
<script type="WaveDrom">{signal: [
{name: '100 MHz CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CPUCLK', wave: 'n' +'n' +'n' +'n' +'n' +'n' +'n', phase: 0.00, period: 4.0}],
["'030 bus inputs",
{name: 'FC', wave: 'xxxxxxxx2...........................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, R/W', wave: 'xxxxxxxx2...........................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...................x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.................................................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'CACHE', wave: 'x...' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxxx1........................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'....' +'0...' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.............x0......x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'....' +'.10.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'....' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle', 'idle', 'ready', 'read0', 'read1', 'idle', 'idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'PC', 'NOP','ACT','NOP',
'RD', 'NOP','NOP','NOP',
'NOP','PC', 'NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'....' +'.0..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '01010101010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzzzzzzzzzzxx2.....xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzzzzzzzzzxxxxx2..xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'....' +'.0..' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'....' +'0...' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM single read - cache miss, row hit</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'FC', wave: 'xxxxxxxxx2..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, R/W, /RMC', wave: 'xxxxxxxxx2..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...........x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.........................................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxx1.................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'0...' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.....x0......x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'.10.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle', 'idle', 'read0', 'read1', 'idle', 'idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'RD', 'NOP','NOP','NOP',
'NOP','PC', 'NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'.0..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzzxx2.....xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzxxxxx2..xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'.0..' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'0...' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM single read - cache hit</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'FC', wave: 'xxxxxxxxx2..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, R/W, /RMC', wave: 'xxxxxxxxx2..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...........x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.........................................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxx1.................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'0...' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.....x0......x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle', 'idle', 'L2read0', 'L2read1', 'idle', 'idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'.0..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzxx2.....xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzxxxx2...xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'.0..' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'0...' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM burst read - cache miss, bank precharged or wrong row open</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'FC', wave: 'xxxxxxxxx2..................................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, R/W, /RMC', wave: 'xxxxxxxxx2..................................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..................................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...........................................x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.......x...0...................................x...1.....................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxx1.................................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'....' +'0...' +'....' +'....' +'....' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.............x0..............................x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'....' +'.10.' +'.10.' +'.10.' +'.10.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'....' +'1.0.' +'1.0.' +'1.0.' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle','idle','ready','burst0','burst1','burst2','burst3','burst4','idle','idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'PC', 'NOP','ACT','NOP',
'RD', 'RD', 'NOP','NOP',
'NOP','RD', 'NOP','NOP',
'NOP','RD', 'NOP','NOP',
'NOP','PC', 'NOP','NOP',
'NOP','ACT','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'....' +'.0..' +'10..' +'10..' +'10..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '01010101010101010101010101010101010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzzzzzzzzzzxx2.....xx2.....xx2.....xx2.....xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzzzzzzzzzzxxxx2...xxxx2...xxxx2...xxxx2..xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'....' +'.0..' +'....' +'....' +'....' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'....' +'0...' +'....' +'....' +'....' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM burst read - cache miss, row hit</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'FC', wave: 'xxxxxxxxx2..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, R/W, /RMC', wave: 'xxxxxxxxx2..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...................................x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.......x...0...........................x...1.....................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxx1.........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'0...' +'....' +'....' +'....' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.....x0..............................x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'.10.' +'.10.' +'.10.' +'.10.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'1.0.' +'1.0.' +'1.0.' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle','idle','burst0','burst1','burst2','burst3','burst4','idle','idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'RD', 'RD', 'NOP','NOP',
'NOP','RD', 'NOP','NOP',
'NOP','RD', 'NOP','NOP',
'NOP','PC', 'NOP','NOP',
'NOP','ACT','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'.0..' +'10..' +'10..' +'10..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '010101010101010101010101010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzzxx2.....xx2.....xx2.....xx2.....xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzzxxxx2...xxxx2...xxxx2...xxxx2..xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'.0..' +'....' +'....' +'....' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'0...' +'....' +'....' +'....' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM burst read - cache hit</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'FC', wave: 'xxxxxxxxx2..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, R/W, /RMC', wave: 'xxxxxxxxx2..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...................................x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.......x...0...........................x...1.....................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxx1.........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'0...' +'....' +'....' +'....' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.....x0..............................x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'....' +'.10.' +'.10.' +'.10.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'1.0.' +'1.0.' +'1.0.' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle','idle','L2burst0','L2burst1','L2burst2','L2burst3','L2burst4','idle','idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'PC', 'NOP','ACT','NOP',
'RD', 'RD', 'NOP','NOP',
'NOP','RD', 'NOP','NOP',
'NOP','PC', 'NOP','NOP',
'NOP','ACT','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'.0..' +'10..' +'10..' +'10..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '010101010101010101010101010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzzxx2.....xx2.....xx2.....xx2.....xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzzxxxx2...xxxx2...xxxx2...xxxx2..xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'.0..' +'....' +'....' +'....' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'0...' +'....' +'....' +'....' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM write - row miss</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3,0]},
{name: 'CCLK', wave: '0.1.0.1.0.1.0.1.0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'FC', wave: 'xxxxxxxxx2..........xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, R/W, /RMC', wave: 'xxxxxxxxx2..........xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..........xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.................................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'0...' +'1...' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxx' +'xx0.....' +'....xxxx' +'xxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxx' +'xxx0....' +'x1......' +'..........', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'.10.' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'1.0.' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle','idle','ready','write','idle','idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'ACT','NOP','NOP','NOP',
'WR', 'NOP','PC', 'NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '0101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzxxxxxx2.xzx2..xzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzxxxx2...xzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'0.1.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
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<html>
<head>
<title>Garrett's Workshop - Warp-LC Timing</title>
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</head>
<body onload="WaveDrom.ProcessAll()">
<h1>Garrett's Workshop Warp-LC 33 MHz 68030 Accelerator Documentation</h1>
<h3 id="t0">RAM single read - cache miss, bank precharged or wrong row open</h3>
<script type="WaveDrom">{signal: [
{name: '133 MHz CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CPUCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'R/W', wave: 'xxxxxxxxx1..........................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, FC, /RMC', wave: 'xxxxxxxxx2..........................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..........................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...................x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.................................................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxxx1........................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'....' +'0...' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.............x0......x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'....' +'.10.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'....' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle', 'idle', 'read0', 'read1', 'read2', 'idle', 'idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'PC', 'NOP','ACT','NOP',
'RD', 'NOP','NOP','NOP',
'NOP','PC', 'NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'....' +'.0..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '01010101010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzzzzzzzzzzxx2.....xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzzzzzzzzzxxxxx2..xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'....' +'.0..' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'....' +'0...' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM single read - cache miss, row hit</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'R/W', wave: 'xxxxxxxxx1..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, FC, /RMC', wave: 'xxxxxxxxx2..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...........x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.........................................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxx1.................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'0...' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.....x0......x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'.10.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle', 'idle', 'read1', 'read2', 'idle', 'idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'RD', 'NOP','NOP','NOP',
'NOP','PC', 'NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'.0..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzzxx2.....xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzxxxxx2..xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'.0..' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'0...' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM single read - cache hit</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'R/W', wave: 'xxxxxxxxx1..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, FC, /RMC', wave: 'xxxxxxxxx2..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...........x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.........................................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxx1.................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'0...' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.....x0......x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle', 'idle', 'L2read1', 'L2read2', 'idle', 'idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'.0..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzxx2.....xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzxxxx2...xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'.0..' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'0...' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM burst read - cache miss, bank precharged or wrong row open</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'R/W', wave: 'xxxxxxxxx1..................................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, FC, /RMC', wave: 'xxxxxxxxx2..................................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..................................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...........................................x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.......x...0...................................x...1.....................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxx1.................................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'....' +'0...' +'....' +'....' +'....' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.............x0..............................x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'....' +'.10.' +'.10.' +'.10.' +'.10.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'....' +'1.0.' +'1.0.' +'1.0.' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle','idle','burst0','burst1','burst2','burst3','burst4','burst5','idle','idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'PC', 'NOP','ACT','NOP',
'RD', 'RD', 'NOP','NOP',
'NOP','RD', 'NOP','NOP',
'NOP','RD', 'NOP','NOP',
'NOP','PC', 'NOP','NOP',
'NOP','ACT','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'....' +'.0..' +'10..' +'10..' +'10..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '01010101010101010101010101010101010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzzzzzzzzzzxx2.....xx2.....xx2.....xx2.....xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzzzzzzzzzzxxxx2...xxxx2...xxxx2...xxxx2..xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'....' +'.0..' +'....' +'....' +'....' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'....' +'0...' +'....' +'....' +'....' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM burst read - cache miss, row hit</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'R/W', wave: 'xxxxxxxxx1..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, FC, /RMC', wave: 'xxxxxxxxx2..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...................................x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.......x...0...........................x...1.....................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxx1.........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'0...' +'....' +'....' +'....' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.....x0..............................x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'.10.' +'.10.' +'.10.' +'.10.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'1.0.' +'1.0.' +'1.0.' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle','idle','burst1','burst2','burst3','burst4','burst5','idle','idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'RD', 'RD', 'NOP','NOP',
'NOP','RD', 'NOP','NOP',
'NOP','RD', 'NOP','NOP',
'NOP','PC', 'NOP','NOP',
'NOP','ACT','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'.0..' +'10..' +'10..' +'10..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '010101010101010101010101010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzzxx2.....xx2.....xx2.....xx2.....xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzzxxxx2...xxxx2...xxxx2...xxxx2..xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'.0..' +'....' +'....' +'....' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'0...' +'....' +'....' +'....' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM burst read - cache hit</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3, 0]},
{name: 'CCLK', wave: '0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0.1.' +'0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'R/W', wave: 'xxxxxxxxx1..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, FC, /RMC', wave: 'xxxxxxxxx2..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...................................x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.......x...0...........................x...1.....................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'....' +'....' +'....' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxxxx1.........................................xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'0...' +'....' +'....' +'....' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxxxx1.....x0..............................x1................', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'....' +'.10.' +'.10.' +'.10.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'1.0.' +'1.0.' +'1.0.' +'1.0.' +'....' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle','idle','L2burst1','L2burst2','L2burst3','L2burst4','L2burst5','idle','idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','NOP','NOP',
'PC', 'NOP','ACT','NOP',
'RD', 'RD', 'NOP','NOP',
'NOP','RD', 'NOP','NOP',
'NOP','PC', 'NOP','NOP',
'NOP','ACT','NOP','NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'.0..' +'10..' +'10..' +'10..' +'1...' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '010101010101010101010101010101010101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzzzzzzzzxx2.....xx2.....xx2.....xx2.....xzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzzzzzzzzxxxx2...xxxx2...xxxx2...xxxx2..xzzzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'.0..' +'....' +'....' +'....' +'.1..' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'0...' +'....' +'....' +'....' +'..1.' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
<h3 id="t0">RAM write</h3>
<script type="WaveDrom">{signal: [
{name: 'CLK', wave: 'p...' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
["'030 clock/state",
{name: 'CS', wave: '2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3,0]},
{name: 'CCLK', wave: '0.1.0.1.0.1.0.1.0', phase: 0.00, period: 1.0}],
["'030 bus inputs",
{name: 'FC', wave: 'xxxxxxxxx2..........xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'A, R/W, /RMC', wave: 'xxxxxxxxx2..........xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: 'CIOUT', wave: 'xxxxxxxxx2..........xxxxxxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/AS', wave: '1.......x...0...x...1.............', phase: 0.00, period: 0.5},
{name: '/CBREQ', wave: '1.................................', phase: 0.00, period: 0.5}],
["Cycle term. ctrl.",
{name: 'ASTERMEN', wave: '1...' +'....' +'0...' +'1...' +'.', phase: 0.00, period: 1.0},
{name: '/ASTERM', wave: 'xxxxxxxx' +'xx0.....' +'....xxxx' +'xxxxxxxxxx', phase: 0.00, period: 0.5},
{name: '/SSTERM', wave: '1...' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: '/STERM', wave: 'xxxxxxxx' +'xxx0....' +'x1......' +'..........', phase: 0.00, period: 0.5}],
["L2$ ctrl.",
{name: 'L2CLK', wave: '0...' +'..10' +'....' +'.10.' +'.', phase: 0.00, period: 1.0},
{name: 'L2WR', wave: '0...' +'....' +'....' +'1.0.' +'.', phase: 0.00, period: 1.0}],
["SDRAM ctrl.",
{name: 'RS', wave: '2...' +'2...' +'2...' +'2...' +'2', phase: 0.00, period: 1.0, data:[
'idle','idle','write0','write-idle','idle','idle']},
{name: 'RAMCMD', wave: '2222' +'2222' +'2222' +'2222' +'2', phase: 0.00, period: 1.0, data:[
'NOP','NOP','NOP','NOP',
'NOP','NOP','PC', 'NOP',
'ACT','NOP','NOP','NOP',
'WR', 'NOP','PC', 'NOP',
'NOP','NOP','NOP','NOP',
'NOP']},
{name: 'RAMCKE', wave: '1...' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'RAMCLK', wave: '0101010101010101010101010101010101', phase: 0.00, period: 0.5}],
["Data bus",
{name: 'BD', wave: 'zzzzzzzzzzzzxxxxxx2.xzx2..xzzzzzzz', phase: 0.00, period: 0.5},
{name: 'D', wave: 'zzzzzzzzzzzzxxxx2...xzzzzzzzzzzzzz', phase: 0.00, period: 0.5},
{name: '/DOE', wave: '1...' +'....' +'0.1.' +'....' +'.', phase: 0.00, period: 1.0},
{name: 'DDIR', wave: '1...' +'....' +'....' +'....' +'.', phase: 0.00, period: 1.0}],
]}</script><br/><p>
</p>
</body>
</html>

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1 3700 6300
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Wire Wire Line
2400 4500 2400 4400
$Comp
L power:+3V3 #PWR0127
U 1 1 632761AA
P 2400 2200
F 0 "#PWR0127" H 2400 2050 50 0001 C CNN
F 1 "+3V3" H 2400 2350 50 0000 C CNN
F 2 "" H 2400 2200 50 0001 C CNN
F 3 "" H 2400 2200 50 0001 C CNN
1 2400 2200
1 0 0 -1
$EndComp
Wire Wire Line
2400 2200 2400 2300
Wire Wire Line
3400 3700 3600 3700
Entry Wire Line
3600 3700 3700 3800
Wire Wire Line
3400 3600 3600 3600
Entry Wire Line
3600 3600 3700 3700
Wire Wire Line
3400 3500 3600 3500
Entry Wire Line
3600 3500 3700 3600
Wire Wire Line
3400 3400 3600 3400
Entry Wire Line
3600 3400 3700 3500
Wire Wire Line
3400 3300 3600 3300
Entry Wire Line
3600 3300 3700 3400
Wire Wire Line
3400 3200 3600 3200
Entry Wire Line
3600 3200 3700 3300
Wire Wire Line
3400 3100 3600 3100
Entry Wire Line
3600 3100 3700 3200
Wire Wire Line
3400 3000 3600 3000
Entry Wire Line
3600 3000 3700 3100
Wire Wire Line
3400 2900 3600 2900
Entry Wire Line
3600 2900 3700 3000
Wire Wire Line
3400 2800 3600 2800
Entry Wire Line
3600 2800 3700 2900
Wire Wire Line
3400 2700 3600 2700
Entry Wire Line
3600 2700 3700 2800
Wire Wire Line
3400 2600 3600 2600
Entry Wire Line
3600 2600 3700 2700
Wire Wire Line
3400 2500 3600 2500
Entry Wire Line
3600 2500 3700 2600
Wire Wire Line
3400 2400 3600 2400
Entry Wire Line
3600 2400 3700 2500
Wire Wire Line
3400 2300 3600 2300
Entry Wire Line
3600 2300 3700 2400
Wire Wire Line
3400 2200 3600 2200
Entry Wire Line
3600 2200 3700 2300
Wire Wire Line
3400 3900 3600 3900
Entry Wire Line
3600 3900 3700 4000
Wire Wire Line
3400 3800 3600 3800
Entry Wire Line
3600 3800 3700 3900
Wire Wire Line
2400 3900 2200 3900
Entry Wire Line
2200 3900 2100 4000
Wire Wire Line
2400 3800 2200 3800
Entry Wire Line
2200 3800 2100 3900
Wire Wire Line
2400 3700 2200 3700
Entry Wire Line
2200 3700 2100 3800
Wire Wire Line
2400 3600 2200 3600
Entry Wire Line
2200 3600 2100 3700
Wire Wire Line
2400 3500 2200 3500
Entry Wire Line
2200 3500 2100 3600
Wire Wire Line
2400 3400 2200 3400
Entry Wire Line
2200 3400 2100 3500
Wire Wire Line
2400 3300 2200 3300
Entry Wire Line
2200 3300 2100 3400
Wire Wire Line
2400 3200 2200 3200
Entry Wire Line
2200 3200 2100 3300
Wire Wire Line
2400 3100 2200 3100
Entry Wire Line
2200 3100 2100 3200
Wire Wire Line
2400 3000 2200 3000
Entry Wire Line
2200 3000 2100 3100
Wire Wire Line
2400 2900 2200 2900
Entry Wire Line
2200 2900 2100 3000
Wire Wire Line
2400 2800 2200 2800
Entry Wire Line
2200 2800 2100 2900
Wire Wire Line
2400 2700 2200 2700
Entry Wire Line
2200 2700 2100 2800
Wire Wire Line
2400 2600 2200 2600
Entry Wire Line
2200 2600 2100 2700
Wire Wire Line
2400 2500 2200 2500
Entry Wire Line
2200 2500 2100 2600
Wire Bus Line
3700 3900 3700 4000
Wire Bus Line
2100 3900 2100 4000
Wire Bus Line
3700 2300 3750 2300
Wire Bus Line
2100 2600 2050 2600
Wire Bus Line
2100 3900 2050 3900
Text HLabel 4250 2600 0 50 Input ~ 0
RA[12..0]
Text HLabel 3750 2300 2 50 BiDi ~ 0
D[31..0]
Text HLabel 5950 2300 2 50 BiDi ~ 0
D[31..0]
Wire Bus Line
4300 3900 4250 3900
Wire Bus Line
4300 2600 4250 2600
Connection ~ 4600 2200
Wire Bus Line
5900 2300 5950 2300
Wire Bus Line
5900 3900 5900 4000
Wire Bus Line
4300 4000 4300 3900
Entry Wire Line
4400 2500 4300 2600
Wire Wire Line
4600 2500 4400 2500
Entry Wire Line
4400 2600 4300 2700
Wire Wire Line
4600 2600 4400 2600
Entry Wire Line
4400 2700 4300 2800
Wire Wire Line
4600 2700 4400 2700
Entry Wire Line
4400 2800 4300 2900
Wire Wire Line
4600 2800 4400 2800
Entry Wire Line
4400 2900 4300 3000
Wire Wire Line
4600 2900 4400 2900
Entry Wire Line
4400 3000 4300 3100
Wire Wire Line
4600 3000 4400 3000
Entry Wire Line
4400 3100 4300 3200
Wire Wire Line
4600 3100 4400 3100
Entry Wire Line
4400 3200 4300 3300
Wire Wire Line
4600 3200 4400 3200
Entry Wire Line
4400 3300 4300 3400
Wire Wire Line
4600 3300 4400 3300
Entry Wire Line
4400 3400 4300 3500
Wire Wire Line
4600 3400 4400 3400
Entry Wire Line
4400 3500 4300 3600
Wire Wire Line
4600 3500 4400 3500
Entry Wire Line
4400 3600 4300 3700
Wire Wire Line
4600 3600 4400 3600
Entry Wire Line
4400 3700 4300 3800
Wire Wire Line
4600 3700 4400 3700
Entry Wire Line
4400 3800 4300 3900
Wire Wire Line
4600 3800 4400 3800
Entry Wire Line
4400 3900 4300 4000
Wire Wire Line
4600 3900 4400 3900
Entry Wire Line
5800 3800 5900 3900
Wire Wire Line
5600 3800 5800 3800
Entry Wire Line
5800 3900 5900 4000
Wire Wire Line
5600 3900 5800 3900
Entry Wire Line
5800 3000 5900 3100
Wire Wire Line
5600 3000 5800 3000
Entry Wire Line
5800 3100 5900 3200
Wire Wire Line
5600 3100 5800 3100
Entry Wire Line
5800 3200 5900 3300
Wire Wire Line
5600 3200 5800 3200
Entry Wire Line
5800 3300 5900 3400
Wire Wire Line
5600 3300 5800 3300
Entry Wire Line
5800 3400 5900 3500
Wire Wire Line
5600 3400 5800 3400
Entry Wire Line
5800 3500 5900 3600
Wire Wire Line
5600 3500 5800 3500
Entry Wire Line
5800 3600 5900 3700
Wire Wire Line
5600 3600 5800 3600
Entry Wire Line
5800 3700 5900 3800
Wire Wire Line
5600 3700 5800 3700
Entry Wire Line
5800 2200 5900 2300
Wire Wire Line
5600 2200 5800 2200
Entry Wire Line
5800 2300 5900 2400
Wire Wire Line
5600 2300 5800 2300
Entry Wire Line
5800 2400 5900 2500
Wire Wire Line
5600 2400 5800 2400
Entry Wire Line
5800 2500 5900 2600
Wire Wire Line
5600 2500 5800 2500
Entry Wire Line
5800 2600 5900 2700
Wire Wire Line
5600 2600 5800 2600
Entry Wire Line
5800 2700 5900 2800
Wire Wire Line
5600 2700 5800 2700
Entry Wire Line
5800 2800 5900 2900
Wire Wire Line
5600 2800 5800 2800
Entry Wire Line
5800 2900 5900 3000
Wire Wire Line
5600 2900 5800 2900
Wire Wire Line
4600 2200 4600 2300
$Comp
L power:+3V3 #PWR0128
U 1 1 63276882
P 4600 2200
F 0 "#PWR0128" H 4600 2050 50 0001 C CNN
F 1 "+3V3" H 4600 2350 50 0000 C CNN
F 2 "" H 4600 2200 50 0001 C CNN
F 3 "" H 4600 2200 50 0001 C CNN
1 4600 2200
1 0 0 -1
$EndComp
Connection ~ 4600 4500
Wire Wire Line
4600 4500 4600 4400
$Comp
L power:GND #PWR0129
U 1 1 63274829
P 4600 4500
F 0 "#PWR0129" H 4600 4250 50 0001 C CNN
F 1 "GND" H 4600 4350 50 0000 C CNN
F 2 "" H 4600 4500 50 0001 C CNN
F 3 "" H 4600 4500 50 0001 C CNN
1 4600 4500
1 0 0 -1
$EndComp
Text HLabel 4600 4200 0 50 Input ~ 0
CLK23
Text HLabel 4600 4100 0 50 Input ~ 0
CKE
Text HLabel 5600 4500 2 50 Input ~ 0
~RAS~
Text HLabel 5600 4400 2 50 Input ~ 0
~CAS~
Text HLabel 5600 4300 2 50 Input ~ 0
~WE~
Text HLabel 5600 4200 2 50 Input ~ 0
~CS~
Text Label 5600 3700 0 50 ~ 0
D31
Text Label 5600 3600 0 50 ~ 0
D30
Text Label 5600 3500 0 50 ~ 0
D29
Text Label 5600 3400 0 50 ~ 0
D28
Text Label 5600 3300 0 50 ~ 0
D27
Text Label 5600 3200 0 50 ~ 0
D26
Text Label 5600 3100 0 50 ~ 0
D25
Text Label 5600 3000 0 50 ~ 0
D24
Text Label 5600 2900 0 50 ~ 0
D23
Text Label 5600 2800 0 50 ~ 0
D22
Text Label 5600 2700 0 50 ~ 0
D21
Text Label 5600 2600 0 50 ~ 0
D20
Text Label 5600 2500 0 50 ~ 0
D19
Text Label 5600 2400 0 50 ~ 0
D18
Text Label 5600 2300 0 50 ~ 0
D17
Text Label 5600 2200 0 50 ~ 0
D16
Text Label 5600 3900 0 50 ~ 0
DQM3
Text Label 5600 3800 0 50 ~ 0
DQM2
Text Label 4600 3900 2 50 ~ 0
BA1
Text Label 4600 3800 2 50 ~ 0
BA0
Text Label 4600 3700 2 50 ~ 0
RA12
Text Label 4600 3600 2 50 ~ 0
RA11
Text Label 4600 3500 2 50 ~ 0
RA10
Text Label 4600 3400 2 50 ~ 0
RA9
Text Label 4600 3300 2 50 ~ 0
RA8
Text Label 4600 3200 2 50 ~ 0
RA7
Text Label 4600 3100 2 50 ~ 0
RA6
Text Label 4600 3000 2 50 ~ 0
RA5
Text Label 4600 2800 2 50 ~ 0
RA3
Text Label 4600 2900 2 50 ~ 0
RA4
Text Label 4600 2700 2 50 ~ 0
RA2
Text Label 4600 2600 2 50 ~ 0
RA1
Text Label 4600 2500 2 50 ~ 0
RA0
Text HLabel 2050 2600 0 50 Input ~ 0
RA[12..0]
Text HLabel 2050 3900 0 50 Input ~ 0
BA[1..0]
Text HLabel 4250 3900 0 50 Input ~ 0
BA[1..0]
Wire Bus Line
3700 4000 3750 4000
Wire Bus Line
5900 4000 5950 4000
Text HLabel 3750 4000 2 50 Input ~ 0
DQM[3..0]
Text HLabel 5950 4000 2 50 Input ~ 0
DQM[3..0]
$Comp
L GW_RAM:SDRAM-16Mx16-TSOP2-54 U5
U 1 1 6327223F
P 5100 3200
F 0 "U5" H 5100 4350 50 0000 C CNN
F 1 "W9825G6KH-6" V 5100 3200 50 0000 C CNN
F 2 "stdpads:Winbond_TSOPII-54" H 5100 1550 50 0001 C CIN
F 3 "" H 5100 2950 50 0001 C CNN
1 5100 3200
1 0 0 -1
$EndComp
Wire Bus Line
3700 2300 3700 3800
Wire Bus Line
2100 2600 2100 3800
Wire Bus Line
4300 2600 4300 3800
Wire Bus Line
5900 2300 5900 3800
$EndSCHEMATC

BIN
SE-030-backups/SE-030-2022-02-02_021941.zip
View File

Binary file not shown.

BIN
SE-030-backups/SE-030-2022-02-02_152026.zip
View File

Binary file not shown.

BIN
SE-030-backups/SE-030-2022-02-02_153807.zip
View File

Binary file not shown.

29452
SE-030.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

75
SE-030.kicad_prl
View File

@ -1,75 +0,0 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
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"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
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],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "SE-030.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

2634
SE-030.kicad_pro
View File

File diff suppressed because it is too large Load Diff

1618
SE-030.kicad_sch Normal file
View File

File diff suppressed because it is too large Load Diff

269
SE-030.pro
View File

@ -1,269 +0,0 @@
update=Friday, October 22, 2021 at 05:54:57 AM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=SE-030.net
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.15
MinViaDiameter=0.5
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.15
TrackWidth2=0.2
TrackWidth3=0.25
TrackWidth4=0.3
TrackWidth5=0.35
TrackWidth6=0.4
TrackWidth7=0.45
TrackWidth8=0.5
TrackWidth9=0.55
TrackWidth10=0.6
TrackWidth11=0.8
TrackWidth12=1
TrackWidth13=1.27
TrackWidth14=1.524
ViaDiameter1=0.5
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
ViaDiameter4=1
ViaDrill4=0.5
ViaDiameter5=1.524
ViaDrill5=0.762
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.1524
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.07619999999999999
SolderMaskMinWidth=0.09999999999999999
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=1
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.15
TrackWidth=0.15
ViaDiameter=0.5
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

529
SE-030.sch
View File

@ -1,529 +0,0 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr USLetter 11000 8500
encoding utf-8
Sheet 1 7
Title "RAM2E II"
Date "2020-07-25"
Rev "1.0"
Comp "Garrett's Workshop"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Mechanical:MountingHole_Pad H5
U 1 1 5ED15A93
P 1950 7250
F 0 "H5" H 2050 7301 50 0000 L CNN
F 1 " " H 2050 7210 50 0000 L CNN
F 2 "stdpads:PasteHole_1.1mm_PTH" H 1950 7250 50 0001 C CNN
F 3 "~" H 1950 7250 50 0001 C CNN
1 1950 7250
1 0 0 -1
$EndComp
$Comp
L Mechanical:Fiducial FID1
U 1 1 5CC47A28
P 750 7550
F 0 "FID1" H 850 7596 50 0000 L CNN
F 1 "Fiducial" H 850 7505 50 0000 L CNN
F 2 "stdpads:Fiducial" H 750 7550 50 0001 C CNN
F 3 "~" H 750 7550 50 0001 C CNN
1 750 7550
1 0 0 -1
$EndComp
$Comp
L Mechanical:Fiducial FID3
U 1 1 5CC4921D
P 1250 7550
F 0 "FID3" H 1350 7596 50 0000 L CNN
F 1 "Fiducial" H 1350 7505 50 0000 L CNN
F 2 "stdpads:Fiducial" H 1250 7550 50 0001 C CNN
F 3 "~" H 1250 7550 50 0001 C CNN
1 1250 7550
1 0 0 -1
$EndComp
$Comp
L Mechanical:Fiducial FID2
U 1 1 5CC4DBD8
P 750 7750
F 0 "FID2" H 850 7796 50 0000 L CNN
F 1 "Fiducial" H 850 7705 50 0000 L CNN
F 2 "stdpads:Fiducial" H 750 7750 50 0001 C CNN
F 3 "~" H 750 7750 50 0001 C CNN
1 750 7750
1 0 0 -1
$EndComp
$Comp
L Mechanical:Fiducial FID4
U 1 1 5CC4DBDF
P 1250 7750
F 0 "FID4" H 1350 7796 50 0000 L CNN
F 1 "Fiducial" H 1350 7705 50 0000 L CNN
F 2 "stdpads:Fiducial" H 1250 7750 50 0001 C CNN
F 3 "~" H 1250 7750 50 0001 C CNN
1 1250 7750
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H1
U 1 1 5CC53461
P 750 7250
F 0 "H1" H 850 7301 50 0000 L CNN
F 1 " " H 850 7210 50 0000 L CNN
F 2 "stdpads:PasteHole_1.1mm_PTH" H 750 7250 50 0001 C CNN
F 3 "~" H 750 7250 50 0001 C CNN
1 750 7250
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H2
U 1 1 5CC795A2
P 1050 7250
F 0 "H2" H 1150 7301 50 0000 L CNN
F 1 " " H 1150 7210 50 0000 L CNN
F 2 "stdpads:PasteHole_1.1mm_PTH" H 1050 7250 50 0001 C CNN
F 3 "~" H 1050 7250 50 0001 C CNN
1 1050 7250
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H3
U 1 1 5CC7E0B9
P 1350 7250
F 0 "H3" H 1450 7301 50 0000 L CNN
F 1 " " H 1450 7210 50 0000 L CNN
F 2 "stdpads:PasteHole_1.1mm_PTH" H 1350 7250 50 0001 C CNN
F 3 "~" H 1350 7250 50 0001 C CNN
1 1350 7250
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H4
U 1 1 5CC7E0C0
P 1650 7250
F 0 "H4" H 1750 7301 50 0000 L CNN
F 1 " " H 1750 7210 50 0000 L CNN
F 2 "stdpads:PasteHole_1.1mm_PTH" H 1650 7250 50 0001 C CNN
F 3 "~" H 1650 7250 50 0001 C CNN
1 1650 7250
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0101
U 1 1 5CC8BAFD
P 1650 7350
F 0 "#PWR0101" H 1650 7100 50 0001 C CNN
F 1 "GND" H 1655 7177 50 0000 C CNN
F 2 "" H 1650 7350 50 0001 C CNN
F 3 "" H 1650 7350 50 0001 C CNN
1 1650 7350
1 0 0 -1
$EndComp
Wire Wire Line
1050 7350 750 7350
Connection ~ 1050 7350
Connection ~ 1350 7350
Wire Wire Line
1350 7350 1050 7350
Wire Wire Line
1950 7350 1650 7350
Wire Wire Line
1650 7350 1350 7350
Connection ~ 1650 7350
Wire Bus Line
1100 700 1300 700
Wire Bus Line
1100 800 1300 800
Wire Wire Line
1100 900 1300 900
Wire Bus Line
1100 1600 1300 1600
Wire Wire Line
1100 1000 1300 1000
Wire Wire Line
1100 5000 1300 5000
Wire Wire Line
1300 2100 1100 2100
Wire Wire Line
1300 2200 1100 2200
Wire Wire Line
1300 2500 1100 2500
Wire Wire Line
1300 2600 1100 2600
$Sheet
S 550 600 550 5700
U 5F6DA71D
F0 "PDS" 50
F1 "PDS.sch" 50
F2 "A[31..0]" I R 1100 800 50
F3 "~AS~" I R 1100 2100 50
F4 "R~W~" I R 1100 900 50
F5 "~RESET~" B R 1100 3400 50
F6 "~BERR~" O R 1100 5900 50
F7 "C16M" O R 1100 5000 50
F8 "~DS~" I R 1100 2200 50
F9 "~DSACK~0" B R 1100 2600 50
F10 "~DSACK~1" O R 1100 2500 50
F11 "SIZ[1..0]" I R 1100 1600 50
F12 "~HALT~" O R 1100 5800 50
F13 "FC[2..0]" I R 1100 700 50
F14 "~RMC~" I R 1100 1000 50
F15 "D[31..0]" B R 1100 3100 50
F16 "~IPL~[2..0]" O R 1100 6200 50
$EndSheet
Wire Bus Line
1100 3100 1300 3100
Wire Wire Line
1200 3400 1300 3400
Connection ~ 1200 3400
Wire Wire Line
1100 3400 1200 3400
Wire Bus Line
4150 3100 4150 3500
Wire Bus Line
2500 700 4000 700
Wire Wire Line
4300 1800 3900 1800
Wire Bus Line
4150 3500 4300 3500
Wire Wire Line
2500 900 4200 900
Wire Bus Line
4000 700 4000 1200
Wire Bus Line
4000 1200 3900 1200
Connection ~ 4000 700
Wire Bus Line
4000 700 4300 700
Wire Bus Line
3900 1300 4100 1300
Wire Bus Line
4100 1300 4100 800
Connection ~ 4100 800
Wire Bus Line
4100 800 4300 800
Wire Wire Line
4200 900 4200 1400
Wire Wire Line
4200 1400 3900 1400
Connection ~ 4200 900
Wire Wire Line
4200 900 4300 900
Wire Bus Line
2500 800 4100 800
$Sheet
S 5650 600 550 5700
U 5F72F108
F0 "MC68k" 50
F1 "MC68k.sch" 50
F2 "~AS~" O L 5650 2100 50
F3 "~RESET~" B L 5650 6100 50
F4 "~BERR~" I L 5650 5900 50
F5 "~CBREQ~" O L 5650 2300 50
F6 "D[31..0]" B L 5650 3100 50
F7 "~CIOUT~" O L 5650 1700 50
F8 "R~W~" O L 5650 900 50
F9 "~RMC~" O L 5650 1000 50
F10 "A[31..0]" O L 5650 800 50
F11 "FC[2..0]" O L 5650 700 50
F12 "SIZ[1..0]" O L 5650 1600 50
F13 "~DSACK~1" B L 5650 2500 50
F14 "~DSACK~0" B L 5650 2600 50
F15 "~IPL~[2..0]" I L 5650 6200 50
F16 "~DS~" O L 5650 2200 50
F17 "CPUCLK" I L 5650 5000 50
F18 "~CIIN~" I L 5650 5700 50
F19 "~STERM~" I L 5650 5500 50
F20 "~HALT~" I L 5650 5800 50
F21 "~CBACK~" I L 5650 5600 50
F22 "~ECS~" O L 5650 2000 50
F23 "FPUCLK" I L 5650 5200 50
F24 "FPU~CS~" I L 5650 5300 50
$EndSheet
Connection ~ 4150 3100
Wire Bus Line
4150 3100 4300 3100
Wire Bus Line
4300 1600 3900 1600
Wire Wire Line
4300 1700 3900 1700
Wire Wire Line
1200 6100 5650 6100
Wire Bus Line
1100 6200 5650 6200
Wire Wire Line
3900 2900 4300 2900
Wire Wire Line
3900 3000 4300 3000
Wire Wire Line
3900 2100 4300 2100
Wire Wire Line
3900 2000 4300 2000
Wire Wire Line
3900 2300 4300 2300
Wire Wire Line
3900 2200 4300 2200
Wire Wire Line
3900 2600 4300 2600
Wire Wire Line
3900 2700 4300 2700
Wire Wire Line
3900 2500 4300 2500
Wire Bus Line
3900 3100 4150 3100
Wire Wire Line
3900 5000 5650 5000
Wire Wire Line
3900 5200 5650 5200
Wire Wire Line
3900 5300 5650 5300
Wire Wire Line
3900 5600 5650 5600
Wire Wire Line
3900 5500 5650 5500
Wire Wire Line
3900 5700 5650 5700
Wire Wire Line
3900 5900 5650 5900
Wire Wire Line
3900 5800 5650 5800
Wire Wire Line
2600 5000 2500 5000
Wire Wire Line
2600 3400 2500 3400
Wire Wire Line
2600 3300 2500 3300
Wire Wire Line
2600 5900 2500 5900
Wire Wire Line
2600 5800 2500 5800
Wire Bus Line
2500 1300 2600 1300
Wire Bus Line
2600 1600 2500 1600
Wire Wire Line
2600 1800 2500 1800
Wire Wire Line
2600 1900 2500 1900
Wire Wire Line
2600 2100 2500 2100
Wire Wire Line
2600 2200 2500 2200
Wire Wire Line
2600 2500 2500 2500
Wire Wire Line
2600 2600 2500 2600
Wire Wire Line
2600 2900 2500 2900
Wire Wire Line
2600 3000 2500 3000
Wire Bus Line
2500 3100 2600 3100
Wire Bus Line
5550 3100 5650 3100
Wire Wire Line
5650 2600 5550 2600
Wire Wire Line
5650 2500 5550 2500
Wire Wire Line
5650 2300 5550 2300
Wire Wire Line
5650 2200 5550 2200
Wire Wire Line
5650 2100 5550 2100
Wire Wire Line
5650 2000 5550 2000
Wire Wire Line
5650 1700 5550 1700
Wire Bus Line
5550 1600 5650 1600
Wire Wire Line
5650 1000 5550 1000
Wire Wire Line
5650 900 5550 900
Wire Bus Line
5550 800 5650 800
Wire Bus Line
5550 700 5650 700
$Sheet
S 4300 3400 1250 1500
U 63261D60
F0 "RAM" 50
F1 "RAM.sch" 50
F2 "~RAS~" I L 4300 3800 50
F3 "~CAS~" I L 4300 3900 50
F4 "~CS~" I L 4300 3700 50
F5 "~WE~" I L 4300 4000 50
F6 "CKE" I L 4300 4100 50
F7 "CLK01" I L 4300 4700 50
F8 "RA[12..0]" I L 4300 4400 50
F9 "D[31..0]" B L 4300 3500 50
F10 "CLK23" I L 4300 4800 50
F11 "BA[1..0]" I L 4300 4300 50
F12 "DQM[3..0]" I L 4300 4500 50
$EndSheet
Wire Wire Line
3900 4800 4300 4800
Wire Wire Line
3900 4700 4300 4700
Wire Bus Line
4300 4500 3900 4500
Wire Bus Line
4300 4400 3900 4400
Wire Bus Line
4300 4300 3900 4300
Wire Wire Line
3900 4100 4300 4100
Wire Wire Line
3900 4000 4300 4000
Wire Wire Line
3900 3900 4300 3900
Wire Wire Line
3900 3800 4300 3800
Wire Wire Line
3900 3700 4300 3700
Wire Wire Line
1100 5900 1300 5900
Wire Wire Line
1300 5800 1100 5800
Wire Wire Line
1200 3400 1200 6100
$Sheet
S 1300 600 1200 5400
U 60941922
F0 "PDSBuf" 50
F1 "PDSBuf.sch" 50
F2 "A~OE~" I R 2500 1800 50
F3 "ADoutLE" I R 2500 1900 50
F4 "IOB_R~W~" O L 1300 900 50
F5 "IOB_SIZ[1..0]" O L 1300 1600 50
F6 "IOB_FC[2..0]" O L 1300 700 50
F7 "IOB_C16M" I L 1300 5000 50
F8 "IOB_~RESET~" B L 1300 3400 50
F9 "IOB_~HALT~" I L 1300 5800 50
F10 "IOB_~DSACK~1" I L 1300 2500 50
F11 "IOB_~DSACK~0" I L 1300 2600 50
F12 "IOB_~AS~" O L 1300 2100 50
F13 "D~OE~" I R 2500 2900 50
F14 "IOB_D[31..0]" B L 1300 3100 50
F15 "DDIR" I R 2500 3000 50
F16 "IOB_~DS~" O L 1300 2200 50
F17 "IOC_SIZ[1..0]" I R 2500 1600 50
F18 "IOC_~AS~" I R 2500 2100 50
F19 "IOC_~DS~" I R 2500 2200 50
F20 "FSB_R~W~" I R 2500 900 50
F21 "IOC_D[31..0]" B R 2500 3100 50
F22 "IOB_A[31..0]" O L 1300 800 50
F23 "IOC_C16M" O R 2500 5000 50
F24 "FSB_~RESET~" O R 2500 3400 50
F25 "IOC_~HALT~" O R 2500 5800 50
F26 "IOC_~DSACK~1" O R 2500 2500 50
F27 "IOC_~DSACK~0" O R 2500 2600 50
F28 "IOB_~RMC~" I L 1300 1000 50
F29 "IOC_~BERR~" O R 2500 5900 50
F30 "FSB_A[31..4]" I R 2500 800 50
F31 "IOC_A[3..0]" I R 2500 1300 50
F32 "FSB_FC[2..0]" I R 2500 700 50
F33 "IOB_~BERR~" I L 1300 5900 50
F34 "RESET~OE~" I R 2500 3300 50
$EndSheet
$Sheet
S 2600 1100 1300 4900
U 5F723173
F0 "Control" 50
F1 "Control.sch" 50
F2 "IOB_A~OE~" I L 2600 1800 50
F3 "IOC_~AS~" O L 2600 2100 50
F4 "IOC_~DS~" O L 2600 2200 50
F5 "FSB_R~W~" B R 3900 1400 50
F6 "IOB_D[31..0]" B L 2600 3100 50
F7 "FSB_A[31..0]" B R 3900 1300 50
F8 "IOB_C16M" I L 2600 5000 50
F9 "IOB_~HALT~" I L 2600 5800 50
F10 "IOB_~DSACK~1" I L 2600 2500 50
F11 "IOB_~DSACK~0" I L 2600 2600 50
F12 "FSB_~RMC~" B R 3900 1500 50
F13 "IOB_~BERR~" I L 2600 5900 50
F14 "IOB_A[3..0]" O L 2600 1300 50
F15 "FSB_FC[2..0]" B R 3900 1200 50
F16 "RESET~OE~" O L 2600 3300 50
F17 "IOB_ADoutLE" I L 2600 1900 50
F18 "IOB_DDIR" I L 2600 3000 50
F19 "IOB_D~OE~" I L 2600 2900 50
F20 "~RESET~" I L 2600 3400 50
F21 "IOB_SIZ[1..0]" O L 2600 1600 50
F22 "FSB_D[31..0]" B R 3900 3100 50
F23 "FSB_~DS~" I R 3900 2200 50
F24 "FSB_~AS~" I R 3900 2100 50
F25 "FSB_~CIOUT~" I R 3900 1700 50
F26 "FSB_SIZ[1..0]" I R 3900 1600 50
F27 "FSB_~CBREQ~" I R 3900 2300 50
F28 "CPU_~DSACK~1" O R 3900 2500 50
F29 "CPU_~DSACK~0" O R 3900 2600 50
F30 "FSB_~ECS~" I R 3900 2000 50
F31 "DSACK~OE~" O R 3900 2700 50
F32 "CPU_D~OE~" O R 3900 2900 50
F33 "CPU_DDIR" O R 3900 3000 50
F34 "CPU_A~OE~" O R 3900 1800 50
F35 "CPUCLK" O R 3900 5000 50
F36 "FPUCLK" O R 3900 5200 50
F37 "FPU~CS~" O R 3900 5300 50
F38 "CPU_~STERM~" O R 3900 5500 50
F39 "CPU_~CBACK~" O R 3900 5600 50
F40 "CPU_~CIIN~" O R 3900 5700 50
F41 "CPU_~HALT~" O R 3900 5800 50
F42 "CPU_~BERR~" O R 3900 5900 50
F43 "RAM_~CS~" O R 3900 3700 50
F44 "RAM_~RAS~" O R 3900 3800 50
F45 "RAM_~CAS~" O R 3900 3900 50
F46 "RAM_~WE~" O R 3900 4000 50
F47 "RAM_CKE" O R 3900 4100 50
F48 "RAM_BA[1..0]" O R 3900 4300 50
F49 "RAM_RA[12..0]" O R 3900 4400 50
F50 "RAM_DQM[3..0]" O R 3900 4500 50
F51 "RAM_CLK01" O R 3900 4700 50
F52 "RAM_CLK23" O R 3900 4800 50
$EndSheet
$Sheet
S 4300 600 1250 2600
U 629B918A
F0 "CPUBuf" 50
F1 "CPUBuf.sch" 50
F2 "D~OE~" I L 4300 2900 50
F3 "DDIR" I L 4300 3000 50
F4 "CPU_D[31..0]" B R 5550 3100 50
F5 "A~OE~" I L 4300 1800 50
F6 "CPU_~CBREQ~" I R 5550 2300 50
F7 "CPU_~DS~" I R 5550 2200 50
F8 "CPU_~AS~" I R 5550 2100 50
F9 "CPU_~CIOUT~" I R 5550 1700 50
F10 "CPU_R~W~" I R 5550 900 50
F11 "CPU_~RMC~" I R 5550 1000 50
F12 "FSB_~DS~" O L 4300 2200 50
F13 "FSB_~AS~" O L 4300 2100 50
F14 "FSB_R~W~" T L 4300 900 50
F15 "FSB_~RMC~" T L 4300 1500 50
F16 "FSB_~CIOUT~" O L 4300 1700 50
F17 "FSB_A[31..0]" T L 4300 800 50
F18 "CPU_A[31..0]" I R 5550 800 50
F19 "FSB_FC[2..0]" T L 4300 700 50
F20 "FSB_SIZ[1..0]" O L 4300 1600 50
F21 "FSB_~CBREQ~" O L 4300 2300 50
F22 "FSB_D[31..0]" B L 4300 3100 50
F23 "CPU_FC[2..0]" I R 5550 700 50
F24 "CPU_SIZ[1..0]" I R 5550 1600 50
F25 "DSACK~OE~" I L 4300 2700 50
F26 "CPU_~DSACK~1" T R 5550 2500 50
F27 "CPU_~DSACK~0" T R 5550 2600 50
F28 "FSB_~DSACK~1" I L 4300 2500 50
F29 "FSB_~DSACK~0" I L 4300 2600 50
F30 "CPU_~ECS~" I R 5550 2000 50
F31 "FSB_~ECS~" O L 4300 2000 50
$EndSheet
Wire Wire Line
3900 1500 4300 1500
$EndSCHEMATC

51
VDAC.kicad_sch Normal file
View File

@ -0,0 +1,51 @@
(kicad_sch (version 20230121) (generator eeschema)
(uuid 64c4bf04-4028-4228-977f-f8b89c9897a9)
(paper "A4")
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(hierarchical_label "Bi[5..0]" (shape input) (at 142.2401 99.1875 180) (fields_autoplaced)
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(hierarchical_label "Ri[5..0]" (shape input) (at 142.2401 94.1075 180) (fields_autoplaced)
(effects (font (size 1.27 1.27)) (justify right))
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39
VidControl.kicad_sch Normal file
View File

@ -0,0 +1,39 @@
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(uuid 79236db8-66fd-4de5-857b-cf2ce3e5dc9b)
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(hierarchical_label "VCLK" (shape input) (at 76.2 106.68 180) (fields_autoplaced)
(effects (font (size 1.27 1.27)) (justify right))
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19
sym-lib-table
View File

@ -1,11 +1,12 @@
(sym_lib_table
(lib (name GW_PLD)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_PLD.lib)(options "")(descr ""))
(lib (name GW_Logic)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Logic.lib)(options "")(descr ""))
(lib (name GW_Power)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Power.lib)(options "")(descr ""))
(lib (name GW_RFModule)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_RFModule.lib)(options "")(descr ""))
(lib (name GW_MCU)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_MCU.lib)(options "")(descr ""))
(lib (name GW_Connector)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Connector.lib)(options "")(descr ""))
(lib (name GW_Digital)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Digital.lib)(options "")(descr ""))
(lib (name GW_RAM)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_RAM.lib)(options "")(descr ""))
(lib (name GW_CPU)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_CPU.lib)(options "")(descr ""))
(version 7)
(lib (name "GW_PLD")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_PLD.kicad_sym")(options "")(descr ""))
(lib (name "GW_Logic")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
(lib (name "GW_Power")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Power.kicad_sym")(options "")(descr ""))
(lib (name "GW_RFModule")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_RFModule.kicad_sym")(options "")(descr ""))
(lib (name "GW_MCU")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_MCU.kicad_sym")(options "")(descr ""))
(lib (name "GW_Connector")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Connector.kicad_sym")(options "")(descr ""))
(lib (name "GW_Digital")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Digital.kicad_sym")(options "")(descr ""))
(lib (name "GW_RAM")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_RAM.kicad_sym")(options "")(descr ""))
(lib (name "GW_CPU")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_CPU.kicad_sym")(options "")(descr ""))
)