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Better CPLD stuff
2022-03-29 08:23:54 +00:00
<html><body>
<pre>
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
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Design Name: WarpSE Date: 3-27-2023, 9:56AM
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Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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119/144 ( 83%) 380 /720 ( 53%) 214/432 ( 50%) 94 /144 ( 65%) 71 /81 ( 88%)
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** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 22/54 24/90 11/11*
FB2 5/18 3/54 5/90 8/10
idk
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FB3 9/18 34/54 82/90 10/10*
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FB4 18/18* 25/54 39/90 10/10*
FB5 17/18 30/54 60/90 8/10
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FB6 18/18* 34/54 63/90 10/10*
FB7 18/18* 31/54 34/90 8/10
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FB8 16/18 35/54 73/90 6/10
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----- ----- ----- -----
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119/144 214/432 380/720 71/81
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* - Resource is exhausted
** Global Control Resources **
idk
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Signal 'C16M' mapped onto global clock net GCK1.
Signal 'C8M' mapped onto global clock net GCK2.
Signal 'FCLK' mapped onto global clock net GCK3.
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Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Redo CNT timers
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Input : 32 32 | I/O : 65 73
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Output : 35 35 | GCK/IO : 3 3
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Bidirectional : 1 1 | GTS/IO : 3 4
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GCK : 3 3 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Redo CNT timers
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Total 71 71
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** Power Data **
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There are 119 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'WarpSE.ise'.
idk
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INFO:Cpld - Inferring BUFG constraint for signal 'C16M' based upon the LOC
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constraint 'P22'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
idk
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INFO:Cpld - Inferring BUFG constraint for signal 'C8M' based upon the LOC
constraint 'P23'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
idk
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INFO:Cpld - Inferring BUFG constraint for signal 'FCLK' based upon the LOC
constraint 'P27'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
idk
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WARNING:Cpld:1007 - Removing unused input(s) 'SW<1>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'SW<2>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
idk
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WARNING:Cpld:1007 - Removing unused input(s) 'SW<3>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
Redo CNT timers
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WARNING:Cpld:1007 - Removing unused input(s) 'nBG_IOB'. The input(s) are unused
after optimization. Please verify functionality via simulation.
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************************* Summary of Mapped Logic ************************
idk
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** 36 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
idk
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nDTACK_FSB 9 26 FB3_9 28 I/O O STD FAST RESET
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nROMWE 1 2 FB3_17 34 I/O O STD FAST
idk
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nAoutOE 2 4 FB4_2 87 I/O O STD FAST SET
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nDoutOE 1 2 FB4_5 89 I/O O STD FAST
Redo CNT timers
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nDinOE 3 6 FB4_6 90 I/O O STD FAST
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nRES 1 1 FB4_8 91 I/O I/O STD FAST
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nVPA_FSB 1 2 FB4_11 93 I/O O STD FAST
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nROMCS 2 5 FB5_2 35 I/O O STD FAST
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nCAS 1 1 FB5_5 36 I/O O STD FAST RESET
nOE 1 2 FB5_6 37 I/O O STD FAST
RA<4> 2 3 FB5_9 40 I/O O STD FAST
RA<3> 2 3 FB5_11 41 I/O O STD FAST
RA<5> 2 3 FB5_12 42 I/O O STD FAST
RA<2> 2 3 FB5_14 43 I/O O STD FAST
RA<6> 2 3 FB5_15 46 I/O O STD FAST
nVMA_IOB 3 10 FB6_2 74 I/O O STD FAST RESET
nLDS_IOB 4 6 FB6_9 79 I/O O STD FAST RESET
nUDS_IOB 4 6 FB6_11 80 I/O O STD FAST RESET
nAS_IOB 3 4 FB6_12 81 I/O O STD FAST RESET
nADoutLE1 2 3 FB6_14 82 I/O O STD FAST SET
nADoutLE0 1 2 FB6_15 85 I/O O STD FAST
nDinLE 1 2 FB6_17 86 I/O O STD FAST RESET
RA<1> 2 3 FB7_2 50 I/O O STD FAST
RA<7> 2 3 FB7_5 52 I/O O STD FAST
RA<0> 2 3 FB7_6 53 I/O O STD FAST
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RA<8> 5 6 FB7_8 54 I/O O STD FAST
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RA<10> 1 1 FB7_9 55 I/O O STD FAST
RA<9> 2 3 FB7_11 56 I/O O STD FAST
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C25MEN 0 0 FB7_12 58 I/O O STD FAST
C20MEN 0 0 FB7_14 59 I/O O STD FAST
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RA<11> 1 1 FB8_2 63 I/O O STD FAST
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nRAS 2 6 FB8_5 64 I/O O STD FAST
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nRAMLWE 1 4 FB8_6 65 I/O O STD FAST
nRAMUWE 1 4 FB8_8 66 I/O O STD FAST
nBERR_FSB 4 8 FB8_12 70 I/O O STD FAST RESET
nBR_IOB 2 4 FB8_15 72 I/O O STD FAST RESET
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** 83 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
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ram/RegUrgSync 1 1 FB1_1 STD RESET
ram/RefUrg 1 2 FB1_2 STD RESET
ram/RefReqSync 1 1 FB1_3 STD RESET
idk
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iobs/IOACTr 1 1 FB1_4 STD RESET
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iobm/Er2 1 1 FB1_5 STD RESET
iobm/Er 1 1 FB1_6 STD RESET
iobm/DTACKrr 1 1 FB1_7 STD RESET
iobm/DTACKrf 1 1 FB1_8 STD RESET
iobm/BERRrr 1 1 FB1_9 STD RESET
iobm/BERRrf 1 1 FB1_10 STD RESET
fsb/ASrf 1 1 FB1_11 STD RESET
cnt/nIPL2r 1 1 FB1_12 STD RESET
cnt/Er<0> 1 1 FB1_13 STD RESET
idk
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iobs/IOU1 2 2 FB1_14 STD RESET
iobs/IOL1 2 2 FB1_15 STD RESET
iobm/IOS_FSM_FFd1 2 3 FB1_16 STD RESET
ALE0M 2 4 FB1_17 STD RESET
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IOU0 3 5 FB1_18 STD RESET
iobm/VPArr 1 1 FB2_14 STD RESET
iobm/VPArf 1 1 FB2_15 STD RESET
iobm/RESrr 1 1 FB2_16 STD RESET
iobm/RESrf 1 1 FB2_17 STD RESET
iobm/IOREQr 1 1 FB2_18 STD RESET
idk
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IORW0 17 20 FB3_1 STD RESET
fsb/VPA 16 26 FB3_6 STD RESET
iobs/IORW1 16 19 FB3_11 STD RESET
fsb/Ready1r 6 17 FB3_13 STD RESET
cs/nOverlay 3 8 FB3_14 STD RESET
IOREQ 13 19 FB3_16 STD RESET
iobs/Clear1 1 3 FB3_18 STD RESET
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cnt/LTimer<0> 1 3 FB4_1 STD RESET
cnt/INITS_FSM_FFd1 1 7 FB4_3 STD RESET
cnt/Er<1> 1 1 FB4_4 STD RESET
cnt/TimerTC 2 6 FB4_7 STD RESET
cnt/Timer<0> 2 4 FB4_9 STD RESET
cnt/LTimer<3> 2 6 FB4_10 STD RESET
cnt/LTimer<2> 2 5 FB4_12 STD RESET
cnt/LTimer<1> 2 4 FB4_13 STD RESET
cnt/INITS_FSM_FFd2 2 6 FB4_14 STD RESET
RefReq 2 5 FB4_15 STD RESET
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Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
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cnt/Timer<1> 4 5 FB4_16 STD RESET
cnt/Timer<2> 5 6 FB4_17 STD RESET
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RefUrg 5 7 FB4_18 STD RESET
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ram/RAMEN 9 12 FB5_3 STD RESET
ram/RAMReady 9 12 FB5_4 STD RESET
ram/RS_FSM_FFd2 7 11 FB5_7 STD RESET
fsb/Ready0r 2 7 FB5_8 STD RESET
ram/RefDone 2 4 FB5_10 STD RESET
ram/BACTr 1 2 FB5_13 STD RESET
ram/RefRAS 1 2 FB5_16 STD RESET
ram/RefReq 1 2 FB5_17 STD RESET
ram/RASEL 14 12 FB5_18 STD RESET
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iobm/ETACK 1 6 FB6_1 STD RESET
idk
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iobm/IOS_FSM_FFd3 3 6 FB6_3 STD RESET
iobm/ES<3> 3 6 FB6_4 STD RESET
iobm/ES<1> 3 4 FB6_5 STD RESET
iobm/ES<0> 3 7 FB6_6 STD RESET
iobm/DoutOE 3 6 FB6_7 STD RESET
iobm/ES<4> 4 7 FB6_8 STD RESET
iobm/IOS_FSM_FFd2 5 11 FB6_10 STD RESET
iobm/ES<2> 5 7 FB6_13 STD RESET
IOACT 6 12 FB6_16 STD RESET
IOBERR 9 13 FB6_18 STD RESET
cnt/LTimerTC 2 16 FB7_1 STD RESET
cnt/LTimer<9> 2 12 FB7_3 STD RESET
cnt/LTimer<8> 2 11 FB7_4 STD RESET
cnt/LTimer<7> 2 10 FB7_7 STD RESET
cnt/LTimer<6> 2 9 FB7_10 STD RESET
cnt/LTimer<5> 2 8 FB7_13 STD RESET
cnt/LTimer<4> 2 7 FB7_15 STD RESET
cnt/LTimer<12> 2 15 FB7_16 STD RESET
cnt/LTimer<11> 2 14 FB7_17 STD RESET
cnt/LTimer<10> 2 13 FB7_18 STD RESET
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iobs/Load1 14 18 FB8_3 STD RESET
iobs/IOReady 4 8 FB8_4 STD RESET
iobs/PS_FSM_FFd2 12 19 FB8_7 STD RESET
ram/RS_FSM_FFd3 7 10 FB8_9 STD RESET
IOL0 3 5 FB8_10 STD RESET
ram/RS_FSM_FFd1 3 9 FB8_11 STD RESET
iobs/PS_FSM_FFd1 2 3 FB8_13 STD RESET
idk
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Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
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ALE0S 1 2 FB8_14 STD RESET
nRESout 1 2 FB8_16 STD RESET
iobs/Once 15 18 FB8_17 STD RESET
idk
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Redo CNT timers
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** 35 Inputs **
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Signal Loc Pin Pin Pin
Name No. Type Use
A_FSB<13> FB1_2 11 I/O I
A_FSB<14> FB1_3 12 I/O I
A_FSB<15> FB1_5 13 I/O I
A_FSB<16> FB1_6 14 I/O I
A_FSB<17> FB1_8 15 I/O I
A_FSB<18> FB1_9 16 I/O I
A_FSB<19> FB1_11 17 I/O I
A_FSB<20> FB1_12 18 I/O I
A_FSB<21> FB1_14 19 I/O I
A_FSB<22> FB1_15 20 I/O I
idk
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C16M FB1_17 22 GCK/I/O GCK
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A_FSB<5> FB2_6 2 GTS/I/O I
A_FSB<6> FB2_8 3 GTS/I/O I
A_FSB<7> FB2_9 4 GTS/I/O I
A_FSB<8> FB2_11 6 I/O I
A_FSB<9> FB2_12 7 I/O I
A_FSB<10> FB2_14 8 I/O I
A_FSB<11> FB2_15 9 I/O I
A_FSB<12> FB2_17 10 I/O I
idk
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C8M FB3_2 23 GCK/I/O GCK/I
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A_FSB<23> FB3_5 24 I/O I
idk
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E FB3_6 25 I/O I
FCLK FB3_8 27 GCK/I/O GCK
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nWE_FSB FB3_11 29 I/O I
nLDS_FSB FB3_12 30 I/O I
nAS_FSB FB3_14 32 I/O I
nUDS_FSB FB3_15 33 I/O I
nIPL2 FB4_9 92 I/O I
A_FSB<1> FB4_12 94 I/O I
A_FSB<2> FB4_14 95 I/O I
A_FSB<3> FB4_15 96 I/O I
A_FSB<4> FB4_17 97 I/O I
nBERR_IOB FB6_5 76 I/O I
nVPA_IOB FB6_6 77 I/O I
nDTACK_IOB FB6_8 78 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
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Number of function block inputs used/remaining: 22/32
Number of signals used by logic mapping into function block: 22
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
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ram/RegUrgSync 1 0 0 4 FB1_1 (b) (b)
ram/RefUrg 1 0 0 4 FB1_2 11 I/O I
ram/RefReqSync 1 0 0 4 FB1_3 12 I/O I
idk
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iobs/IOACTr 1 0 0 4 FB1_4 (b) (b)
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iobm/Er2 1 0 0 4 FB1_5 13 I/O I
iobm/Er 1 0 0 4 FB1_6 14 I/O I
iobm/DTACKrr 1 0 0 4 FB1_7 (b) (b)
iobm/DTACKrf 1 0 0 4 FB1_8 15 I/O I
iobm/BERRrr 1 0 0 4 FB1_9 16 I/O I
iobm/BERRrf 1 0 0 4 FB1_10 (b) (b)
fsb/ASrf 1 0 0 4 FB1_11 17 I/O I
cnt/nIPL2r 1 0 0 4 FB1_12 18 I/O I
cnt/Er<0> 1 0 0 4 FB1_13 (b) (b)
idk
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iobs/IOU1 2 0 0 3 FB1_14 19 I/O I
iobs/IOL1 2 0 0 3 FB1_15 20 I/O I
iobm/IOS_FSM_FFd1 2 0 0 3 FB1_16 (b) (b)
ALE0M 2 0 0 3 FB1_17 22 GCK/I/O GCK
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IOU0 3 0 0 2 FB1_18 (b) (b)
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Signals Used by Logic in Function Block
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1: E 9: iobm/IOS_FSM_FFd3 16: nBERR_IOB
2: IOACT 10: iobs/IOU1 17: nDTACK_IOB
3: RefReq 11: iobs/Load1 18: nIPL2
4: RefUrg 12: iobs/PS_FSM_FFd1 19: nLDS_FSB
5: iobm/Er 13: iobs/PS_FSM_FFd2 20: nUDS_FSB
6: iobm/IOREQr 14: nADoutLE1 21: ram/RefDone
7: iobm/IOS_FSM_FFd1 15: nAS_FSB 22: ram/RegUrgSync
8: iobm/IOS_FSM_FFd2
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Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
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ram/RegUrgSync ...X.................................... 1
ram/RefUrg ....................XX.................. 2
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ram/RefReqSync ..X..................................... 1
iobs/IOACTr .X...................................... 1
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iobm/Er2 ....X................................... 1
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iobm/Er X....................................... 1
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iobm/DTACKrr ................X....................... 1
iobm/DTACKrf ................X....................... 1
iobm/BERRrr ...............X........................ 1
iobm/BERRrf ...............X........................ 1
fsb/ASrf ..............X......................... 1
cnt/nIPL2r .................X...................... 1
idk
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cnt/Er<0> X....................................... 1
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iobs/IOU1 ..........X........X.................... 2
iobs/IOL1 ..........X.......X..................... 2
iobm/IOS_FSM_FFd1 ......XXX............................... 3
ALE0M .....XXXX............................... 4
IOU0 .........X.XXX.....X.................... 5
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0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
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Number of function block inputs used/remaining: 3/51
Number of signals used by logic mapping into function block: 3
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Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 99 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 1 GTS/I/O
(unused) 0 0 0 5 FB2_6 2 GTS/I/O I
Redo CNT timers
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(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 3 GTS/I/O I
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(unused) 0 0 0 5 FB2_9 4 GTS/I/O I
(unused) 0 0 0 5 FB2_10 (b)
(unused) 0 0 0 5 FB2_11 6 I/O I
(unused) 0 0 0 5 FB2_12 7 I/O I
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(unused) 0 0 0 5 FB2_13 (b)
iobm/VPArr 1 0 0 4 FB2_14 8 I/O I
iobm/VPArf 1 0 0 4 FB2_15 9 I/O I
iobm/RESrr 1 0 0 4 FB2_16 (b) (b)
iobm/RESrf 1 0 0 4 FB2_17 10 I/O I
iobm/IOREQr 1 0 0 4 FB2_18 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
Put back all chip selects.
2023-03-27 14:17:22 +00:00
1: IOREQ 2: nRES.PIN 3: nVPA_IOB
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Put back all chip selects.
2023-03-27 14:17:22 +00:00
iobm/VPArr ..X..................................... 1
iobm/VPArf ..X..................................... 1
Redo CNT timers
2023-03-25 07:49:44 +00:00
iobm/RESrr .X...................................... 1
iobm/RESrf .X...................................... 1
idk
2023-03-26 08:33:59 +00:00
iobm/IOREQr X....................................... 1
Better CPLD stuff
2022-03-29 08:23:54 +00:00
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
idk
2023-03-26 08:33:59 +00:00
Number of function block inputs used/remaining: 34/20
Number of signals used by logic mapping into function block: 34
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
idk
2023-03-26 08:33:59 +00:00
IORW0 17 12<- 0 0 FB3_1 (b) (b)
Redo CNT timers
2023-03-25 07:49:44 +00:00
(unused) 0 0 /\5 0 FB3_2 23 GCK/I/O GCK/I
(unused) 0 0 /\3 2 FB3_3 (b) (b)
idk
2023-03-26 08:33:59 +00:00
(unused) 0 0 \/1 4 FB3_4 (b) (b)
Redo CNT timers
2023-03-25 07:49:44 +00:00
(unused) 0 0 \/5 0 FB3_5 24 I/O I
idk
2023-03-26 08:33:59 +00:00
fsb/VPA 16 11<- 0 0 FB3_6 25 I/O I
(unused) 0 0 /\5 0 FB3_7 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
(unused) 0 0 \/5 0 FB3_8 27 GCK/I/O GCK
idk
2023-03-26 08:33:59 +00:00
nDTACK_FSB 9 5<- \/1 0 FB3_9 28 I/O O
(unused) 0 0 \/5 0 FB3_10 (b) (b)
iobs/IORW1 16 11<- 0 0 FB3_11 29 I/O I
(unused) 0 0 /\5 0 FB3_12 30 I/O I
fsb/Ready1r 6 1<- 0 0 FB3_13 (b) (b)
cs/nOverlay 3 0 /\1 1 FB3_14 32 I/O I
(unused) 0 0 \/5 0 FB3_15 33 I/O I
IOREQ 13 8<- 0 0 FB3_16 (b) (b)
nROMWE 1 0 /\3 1 FB3_17 34 I/O O
iobs/Clear1 1 0 \/4 0 FB3_18 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
idk
2023-03-26 08:33:59 +00:00
1: A_FSB<10> 13: A_FSB<22> 24: iobs/IOACTr
2: A_FSB<11> 14: A_FSB<23> 25: iobs/IORW1
3: A_FSB<12> 15: A_FSB<8> 26: iobs/IOReady
4: A_FSB<13> 16: A_FSB<9> 27: iobs/Once
5: A_FSB<14> 17: IORW0 28: iobs/PS_FSM_FFd1
6: A_FSB<15> 18: nRES.PIN 29: iobs/PS_FSM_FFd2
7: A_FSB<16> 19: cs/nOverlay 30: nADoutLE1
8: A_FSB<17> 20: fsb/ASrf 31: nAS_FSB
9: A_FSB<18> 21: fsb/Ready0r 32: nDTACK_FSB
10: A_FSB<19> 22: fsb/Ready1r 33: nWE_FSB
11: A_FSB<20> 23: fsb/VPA 34: ram/RAMReady
12: A_FSB<21>
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
idk
2023-03-26 08:33:59 +00:00
IORW0 ...XX.XXXXXXXX..X.XX....X.XXXXX.X....... 20
fsb/VPA XXXXXXXXXXXXXXXX..XXXXX..X...XX.XX...... 26
nDTACK_FSB XXXXXXXXXXXXXXXX..XXXX...X...XXXXX...... 26
iobs/IORW1 ...XX.XXXXXXXX....XX....X.XXXXX.X....... 19
fsb/Ready1r ...XX.XXXXXXXX....XX.X...X...XX.X....... 17
cs/nOverlay ..........XXXX...XXX..........X......... 8
IOREQ ...XX.XXXXXXXX....XX...X..XXXXX.X....... 19
nROMWE ..............................X.X....... 2
iobs/Clear1 ...........................XXX.......... 3
Better CPLD stuff
2022-03-29 08:23:54 +00:00
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Put back all chip selects.
2023-03-27 14:17:22 +00:00
Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Put back all chip selects.
2023-03-27 14:17:22 +00:00
cnt/LTimer<0> 1 0 0 4 FB4_1 (b) (b)
idk
2023-03-26 08:33:59 +00:00
nAoutOE 2 0 0 3 FB4_2 87 I/O O
Put back all chip selects.
2023-03-27 14:17:22 +00:00
cnt/INITS_FSM_FFd1 1 0 0 4 FB4_3 (b) (b)
cnt/Er<1> 1 0 0 4 FB4_4 (b) (b)
idk
2023-03-22 01:11:58 +00:00
nDoutOE 1 0 0 4 FB4_5 89 I/O O
Redo CNT timers
2023-03-25 07:49:44 +00:00
nDinOE 3 0 0 2 FB4_6 90 I/O O
Put back all chip selects.
2023-03-27 14:17:22 +00:00
cnt/TimerTC 2 0 0 3 FB4_7 (b) (b)
idk
2023-03-22 01:11:58 +00:00
nRES 1 0 0 4 FB4_8 91 I/O I/O
Put back all chip selects.
2023-03-27 14:17:22 +00:00
cnt/Timer<0> 2 0 0 3 FB4_9 92 I/O I
cnt/LTimer<3> 2 0 0 3 FB4_10 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
nVPA_FSB 1 0 0 4 FB4_11 93 I/O O
Put back all chip selects.
2023-03-27 14:17:22 +00:00
cnt/LTimer<2> 2 0 0 3 FB4_12 94 I/O I
cnt/LTimer<1> 2 0 0 3 FB4_13 (b) (b)
cnt/INITS_FSM_FFd2 2 0 0 3 FB4_14 95 I/O I
idk
2023-03-26 08:33:59 +00:00
RefReq 2 0 0 3 FB4_15 96 I/O I
Put back all chip selects.
2023-03-27 14:17:22 +00:00
cnt/Timer<1> 4 0 0 1 FB4_16 (b) (b)
cnt/Timer<2> 5 0 0 0 FB4_17 97 I/O I
idk
2023-03-26 08:33:59 +00:00
RefUrg 5 0 0 0 FB4_18 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
Put back all chip selects.
2023-03-27 14:17:22 +00:00
1: A_FSB<20> 10: cnt/LTimer<0> 18: cnt/nIPL2r
2: A_FSB<21> 11: cnt/LTimer<1> 19: fsb/VPA
3: A_FSB<22> 12: cnt/LTimer<2> 20: iobm/DoutOE
4: A_FSB<23> 13: cnt/LTimerTC 21: nAS_FSB
5: RefUrg 14: cnt/Timer<0> 22: nAoutOE
6: cnt/Er<0> 15: cnt/Timer<1> 23: nBR_IOB
7: cnt/Er<1> 16: cnt/Timer<2> 24: nRESout
8: cnt/INITS_FSM_FFd1 17: cnt/TimerTC 25: nWE_FSB
9: cnt/INITS_FSM_FFd2
idk
2023-03-22 01:11:58 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Put back all chip selects.
2023-03-27 14:17:22 +00:00
cnt/LTimer<0> .....XX.........X....................... 3
nAoutOE .......XX............XX................. 4
cnt/INITS_FSM_FFd1 .....XXXX...X...XX...................... 7
idk
2023-03-26 08:33:59 +00:00
cnt/Er<1> .....X.................................. 1
Put back all chip selects.
2023-03-27 14:17:22 +00:00
nDoutOE ...................X.X.................. 2
nDinOE XXXX................X...X............... 6
cnt/TimerTC ....XXX......XXX........................ 6
nRES .......................X................ 1
cnt/Timer<0> .....XX......X..X....................... 4
cnt/LTimer<3> .....XX..XXX....X....................... 6
nVPA_FSB ..................X.X................... 2
cnt/LTimer<2> .....XX..XX.....X....................... 5
cnt/LTimer<1> .....XX..X......X....................... 4
cnt/INITS_FSM_FFd2 .....XXXX...X...X....................... 6
RefReq ....XXX.......XX........................ 5
cnt/Timer<1> .....XX......XX.X....................... 5
cnt/Timer<2> .....XX......XXXX....................... 6
RefUrg ....XXX......XXXX....................... 7
idk
2023-03-22 01:11:58 +00:00
0----+----1----+----2----+----3----+----4
0 0 0 0
Better CPLD stuff
2022-03-29 08:23:54 +00:00
*********************************** FB5 ***********************************
Put back all chip selects.
2023-03-27 14:17:22 +00:00
Number of function block inputs used/remaining: 30/24
Number of signals used by logic mapping into function block: 30
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Put back all chip selects.
2023-03-27 14:17:22 +00:00
(unused) 0 0 /\5 0 FB5_1 (b) (b)
nROMCS 2 0 \/3 0 FB5_2 35 I/O O
ram/RAMEN 9 4<- 0 0 FB5_3 (b) (b)
ram/RAMReady 9 5<- /\1 0 FB5_4 (b) (b)
nCAS 1 1<- /\5 0 FB5_5 36 I/O O
nOE 1 0 /\1 3 FB5_6 37 I/O O
ram/RS_FSM_FFd2 7 2<- 0 0 FB5_7 (b) (b)
fsb/Ready0r 2 0 /\2 1 FB5_8 39 I/O (b)
RA<4> 2 0 0 3 FB5_9 40 I/O O
ram/RefDone 2 0 0 3 FB5_10 (b) (b)
idk
2023-03-26 08:33:59 +00:00
RA<3> 2 0 0 3 FB5_11 41 I/O O
RA<5> 2 0 0 3 FB5_12 42 I/O O
Put back all chip selects.
2023-03-27 14:17:22 +00:00
ram/BACTr 1 0 0 4 FB5_13 (b) (b)
RA<2> 2 0 0 3 FB5_14 43 I/O O
RA<6> 2 0 0 3 FB5_15 46 I/O O
ram/RefRAS 1 0 0 4 FB5_16 (b) (b)
ram/RefReq 1 0 \/4 0 FB5_17 49 I/O (b)
ram/RASEL 14 9<- 0 0 FB5_18 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
Put back all chip selects.
2023-03-27 14:17:22 +00:00
1: A_FSB<12> 11: A_FSB<4> 21: ram/RAMEN
2: A_FSB<13> 12: A_FSB<5> 22: ram/RAMReady
3: A_FSB<14> 13: A_FSB<6> 23: ram/RASEL
4: A_FSB<15> 14: A_FSB<7> 24: ram/RS_FSM_FFd1
5: A_FSB<16> 15: cs/nOverlay 25: ram/RS_FSM_FFd2
6: A_FSB<20> 16: fsb/ASrf 26: ram/RS_FSM_FFd3
7: A_FSB<21> 17: fsb/Ready0r 27: ram/RefDone
8: A_FSB<22> 18: nAS_FSB 28: ram/RefReq
9: A_FSB<23> 19: nWE_FSB 29: ram/RefReqSync
10: A_FSB<3> 20: ram/BACTr 30: ram/RefUrg
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Put back all chip selects.
2023-03-27 14:17:22 +00:00
nROMCS .....XXXX.....X......................... 5
ram/RAMEN .......XX.....XX.X.XX..XXX.X.X.......... 12
ram/RAMReady .......XX.....XX.X.XX..XXX.X.X.......... 12
nCAS ......................X................. 1
nOE .................XX..................... 2
ram/RS_FSM_FFd2 .......XX.....XX.X.X...XXX.X.X.......... 11
fsb/Ready0r .......XX.....XXXX...X.................. 7
RA<4> ..X........X..........X................. 3
ram/RefDone .......................XX.X.X........... 4
RA<3> .X........X...........X................. 3
RA<5> ...X........X.........X................. 3
ram/BACTr ...............X.X...................... 2
RA<2> X........X............X................. 3
RA<6> ....X........X........X................. 3
ram/RefRAS .......................XX............... 2
ram/RefReq ..........................X.X........... 2
ram/RASEL .......XX.....XX.X.XX..XXX.X.X.......... 12
Better CPLD stuff
2022-03-29 08:23:54 +00:00
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
idk
2023-03-26 08:33:59 +00:00
Number of function block inputs used/remaining: 34/20
Number of signals used by logic mapping into function block: 34
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
idk
2023-03-22 01:11:58 +00:00
iobm/ETACK 1 0 0 4 FB6_1 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
nVMA_IOB 3 0 0 2 FB6_2 74 I/O O
idk
2023-03-26 08:33:59 +00:00
iobm/IOS_FSM_FFd3 3 0 0 2 FB6_3 (b) (b)
iobm/ES<3> 3 0 0 2 FB6_4 (b) (b)
iobm/ES<1> 3 0 0 2 FB6_5 76 I/O I
iobm/ES<0> 3 0 0 2 FB6_6 77 I/O I
iobm/DoutOE 3 0 0 2 FB6_7 (b) (b)
iobm/ES<4> 4 0 0 1 FB6_8 78 I/O I
Better CPLD stuff
2022-03-29 08:23:54 +00:00
nLDS_IOB 4 0 0 1 FB6_9 79 I/O O
idk
2023-03-26 08:33:59 +00:00
iobm/IOS_FSM_FFd2 5 0 0 0 FB6_10 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
nUDS_IOB 4 0 0 1 FB6_11 80 I/O O
nAS_IOB 3 0 0 2 FB6_12 81 I/O O
idk
2023-03-26 08:33:59 +00:00
iobm/ES<2> 5 0 0 0 FB6_13 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
nADoutLE1 2 0 0 3 FB6_14 82 I/O O
idk
2023-03-26 08:33:59 +00:00
nADoutLE0 1 0 \/1 3 FB6_15 85 I/O O
IOACT 6 1<- 0 0 FB6_16 (b) (b)
nDinLE 1 0 \/4 0 FB6_17 86 I/O O
IOBERR 9 4<- 0 0 FB6_18 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
idk
2023-03-26 08:33:59 +00:00
1: ALE0M 13: iobm/ES<0> 24: iobm/IOS_FSM_FFd3
2: ALE0S 14: iobm/ES<1> 25: iobm/RESrf
3: C8M 15: iobm/ES<2> 26: iobm/RESrr
4: IOACT 16: iobm/ES<3> 27: iobm/VPArf
5: IOBERR 17: iobm/ES<4> 28: iobm/VPArr
6: IOL0 18: iobm/ETACK 29: iobs/Clear1
7: IORW0 19: iobm/Er 30: iobs/Load1
8: IOU0 20: iobm/Er2 31: nADoutLE1
9: iobm/BERRrf 21: iobm/IOREQr 32: nAoutOE
10: iobm/BERRrr 22: iobm/IOS_FSM_FFd1 33: nBERR_IOB
11: iobm/DTACKrf 23: iobm/IOS_FSM_FFd2 34: nVMA_IOB
12: iobm/DTACKrr
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
idk
2023-03-26 08:33:59 +00:00
iobm/ETACK ............XXXXX................X...... 6
nVMA_IOB ...X........XXXXX.........XX...X.X...... 10
iobm/IOS_FSM_FFd3 ..X.................XXXX.......X........ 6
iobm/ES<3> ............XXXX..XX.................... 6
iobm/ES<1> ............XX....XX.................... 4
iobm/ES<0> ............XXXXX.XX.................... 7
iobm/DoutOE ......X.............XXXX.......X........ 6
iobm/ES<4> ............XXXXX.XX.................... 7
nLDS_IOB .....XX..............XXX.......X........ 6
iobm/IOS_FSM_FFd2 ..X.....XXXX.....X...XXXXX.............. 11
nUDS_IOB ......XX.............XXX.......X........ 6
nAS_IOB .....................XXX.......X........ 4
iobm/ES<2> ............XXXXX.XX.................... 7
nADoutLE1 ............................XXX......... 3
nADoutLE0 XX...................................... 2
IOACT ..X.....XXXX.....X..XXXXXX.............. 12
nDinLE .....................XX................. 2
IOBERR ..X.X...XXXX.....X...XXXXX......X....... 13
Better CPLD stuff
2022-03-29 08:23:54 +00:00
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
idk
2023-03-26 08:33:59 +00:00
Number of function block inputs used/remaining: 31/23
Number of signals used by logic mapping into function block: 31
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
idk
2023-03-26 08:33:59 +00:00
cnt/LTimerTC 2 0 0 3 FB7_1 (b) (b)
idk
2023-03-22 01:11:58 +00:00
RA<1> 2 0 0 3 FB7_2 50 I/O O
idk
2023-03-26 08:33:59 +00:00
cnt/LTimer<9> 2 0 0 3 FB7_3 (b) (b)
cnt/LTimer<8> 2 0 0 3 FB7_4 (b) (b)
idk
2023-03-22 01:11:58 +00:00
RA<7> 2 0 0 3 FB7_5 52 I/O O
Better CPLD stuff
2022-03-29 08:23:54 +00:00
RA<0> 2 0 0 3 FB7_6 53 I/O O
idk
2023-03-26 08:33:59 +00:00
cnt/LTimer<7> 2 0 0 3 FB7_7 (b) (b)
RA<8> 5 0 0 0 FB7_8 54 I/O O
RA<10> 1 0 0 4 FB7_9 55 I/O O
cnt/LTimer<6> 2 0 0 3 FB7_10 (b) (b)
idk
2023-03-22 01:11:58 +00:00
RA<9> 2 0 0 3 FB7_11 56 I/O O
C25MEN 0 0 0 5 FB7_12 58 I/O O
idk
2023-03-26 08:33:59 +00:00
cnt/LTimer<5> 2 0 0 3 FB7_13 (b) (b)
idk
2023-03-22 01:11:58 +00:00
C20MEN 0 0 0 5 FB7_14 59 I/O O
idk
2023-03-26 08:33:59 +00:00
cnt/LTimer<4> 2 0 0 3 FB7_15 60 I/O (b)
cnt/LTimer<12> 2 0 0 3 FB7_16 (b) (b)
cnt/LTimer<11> 2 0 0 3 FB7_17 61 I/O (b)
cnt/LTimer<10> 2 0 0 3 FB7_18 (b) (b)
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signals Used by Logic in Function Block
idk
2023-03-26 08:33:59 +00:00
1: A_FSB<10> 12: A_FSB<8> 22: cnt/LTimer<3>
2: A_FSB<11> 13: A_FSB<9> 23: cnt/LTimer<4>
3: A_FSB<17> 14: cnt/Er<0> 24: cnt/LTimer<5>
4: A_FSB<18> 15: cnt/Er<1> 25: cnt/LTimer<6>
5: A_FSB<19> 16: cnt/LTimer<0> 26: cnt/LTimer<7>
6: A_FSB<1> 17: cnt/LTimer<10> 27: cnt/LTimer<8>
7: A_FSB<20> 18: cnt/LTimer<11> 28: cnt/LTimer<9>
8: A_FSB<21> 19: cnt/LTimer<12> 29: cnt/TimerTC
9: A_FSB<22> 20: cnt/LTimer<1> 30: cs/nOverlay
10: A_FSB<23> 21: cnt/LTimer<2> 31: ram/RASEL
11: A_FSB<2>
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
idk
2023-03-26 08:33:59 +00:00
cnt/LTimerTC .............XXXXXXXXXXXXXXXX........... 16
RA<1> .X........X...................X......... 3
cnt/LTimer<9> .............XXX...XXXXXXXX.X........... 12
cnt/LTimer<8> .............XXX...XXXXXXX..X........... 11
RA<7> ..X........X..................X......... 3
RA<0> X....X........................X......... 3
cnt/LTimer<7> .............XXX...XXXXXX...X........... 10
RA<8> ...X....XX..X................XX......... 6
Better CPLD stuff
2022-03-29 08:23:54 +00:00
RA<10> .......X................................ 1
idk
2023-03-26 08:33:59 +00:00
cnt/LTimer<6> .............XXX...XXXXX....X........... 9
RA<9> ....X.X.......................X......... 3
idk
2023-03-22 01:11:58 +00:00
C25MEN ........................................ 0
idk
2023-03-26 08:33:59 +00:00
cnt/LTimer<5> .............XXX...XXXX.....X........... 8
idk
2023-03-22 01:11:58 +00:00
C20MEN ........................................ 0
idk
2023-03-26 08:33:59 +00:00
cnt/LTimer<4> .............XXX...XXX......X........... 7
cnt/LTimer<12> .............XXXXX.XXXXXXXXXX........... 15
cnt/LTimer<11> .............XXXX..XXXXXXXXXX........... 14
cnt/LTimer<10> .............XXX...XXXXXXXXXX........... 13
Better CPLD stuff
2022-03-29 08:23:54 +00:00
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
idk
2023-03-26 08:33:59 +00:00
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
Put back all chip selects.
2023-03-27 14:17:22 +00:00
(unused) 0 0 \/1 4 FB8_1 (b) (b)
RA<11> 1 1<- \/5 0 FB8_2 63 I/O O
iobs/Load1 14 9<- 0 0 FB8_3 (b) (b)
iobs/IOReady 4 3<- /\4 0 FB8_4 (b) (b)
nRAS 2 0 /\3 0 FB8_5 64 I/O O
nRAMLWE 1 0 \/4 0 FB8_6 65 I/O O
iobs/PS_FSM_FFd2 12 7<- 0 0 FB8_7 (b) (b)
nRAMUWE 1 0 /\3 1 FB8_8 66 I/O O
ram/RS_FSM_FFd3 7 2<- 0 0 FB8_9 67 I/O (b)
IOL0 3 0 /\2 0 FB8_10 (b) (b)
ram/RS_FSM_FFd1 3 0 0 2 FB8_11 68 I/O (b)
nBERR_FSB 4 0 0 1 FB8_12 70 I/O O
iobs/PS_FSM_FFd1 2 0 0 3 FB8_13 (b) (b)
ALE0S 1 0 0 4 FB8_14 71 I/O (b)
nBR_IOB 2 0 \/1 2 FB8_15 72 I/O O
nRESout 1 1<- \/5 0 FB8_16 (b) (b)
iobs/Once 15 10<- 0 0 FB8_17 73 I/O (b)
(unused) 0 0 /\5 0 FB8_18 (b) (b)
Better CPLD stuff
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Signals Used by Logic in Function Block
Put back all chip selects.
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1: A_FSB<13> 13: cnt/INITS_FSM_FFd2 25: nBERR_FSB
2: A_FSB<14> 14: cnt/nIPL2r 26: nBR_IOB
3: A_FSB<16> 15: cs/nOverlay 27: nLDS_FSB
4: A_FSB<17> 16: fsb/ASrf 28: nUDS_FSB
5: A_FSB<18> 17: iobs/IOACTr 29: nWE_FSB
6: A_FSB<19> 18: iobs/IOL1 30: ram/RAMEN
7: A_FSB<20> 19: iobs/IOReady 31: ram/RS_FSM_FFd1
8: A_FSB<21> 20: iobs/Once 32: ram/RS_FSM_FFd2
9: A_FSB<22> 21: iobs/PS_FSM_FFd1 33: ram/RS_FSM_FFd3
10: A_FSB<23> 22: iobs/PS_FSM_FFd2 34: ram/RefRAS
11: IOBERR 23: nADoutLE1 35: ram/RefUrg
12: cnt/INITS_FSM_FFd1 24: nAS_FSB
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Put back all chip selects.
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RA<11> .....X.................................. 1
iobs/Load1 XXXXXXXXXX....XX...XXXXX....X........... 18
iobs/IOReady ..........X....XX.XX.XXX................ 8
nRAS ........XX....X........X.....X...X...... 6
nRAMLWE .......................X..X.XX.......... 4
iobs/PS_FSM_FFd2 XXXXXXXXXX....XXX..XXXXX....X........... 19
nRAMUWE .......................X...XXX.......... 4
ram/RS_FSM_FFd3 ........XX....XX.......X.....XXXX.X..... 10
IOL0 .................X..XXX...X............. 5
ram/RS_FSM_FFd1 ........XX....XX.......X.....XXXX....... 9
nBERR_FSB ..........X....XX..X.XXXX............... 8
iobs/PS_FSM_FFd1 ................X...XX.................. 3
ALE0S ....................XX.................. 2
nBR_IOB ...........XXX...........X.............. 4
nRESout ...........XX........................... 2
iobs/Once XXXXXXXXXX....XX...XXXXX....X........... 18
Better CPLD stuff
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0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
idk
2023-03-26 08:33:59 +00:00
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,C16M,'0','0');
ALE0M_D <= ((iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2 AND
NOT iobm/IOREQr));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_ALE0S: FDCPE port map (ALE0S,ALE0S_D,FCLK,'0','0');
ALE0S_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
C20MEN <= '1';
Better CPLD stuff
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idk
2023-03-26 08:33:59 +00:00
C25MEN <= '1';
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Redo CNT timers
2023-03-25 07:49:44 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,C16M,'0','0');
IOACT_D <= ((C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/RESrf AND iobm/RESrr)
OR (iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2 AND
NOT iobm/IOREQr)
OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/ETACK)
OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/DTACKrf AND iobm/DTACKrr)
OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/BERRrf AND iobm/BERRrr));
FTCPE_IOBERR: FTCPE port map (IOBERR,IOBERR_T,C16M,'0','0');
IOBERR_T <= ((C8M AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/RESrf AND
iobm/RESrr)
OR (C8M AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/DTACKrf AND
iobm/DTACKrr)
OR (C8M AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/BERRrf AND
iobm/BERRrr)
OR (C8M AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/RESrf AND
iobm/RESrr)
OR (iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
NOT iobm/IOS_FSM_FFd2 AND IOBERR)
OR (C8M AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/ETACK)
OR (C8M AND NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND NOT IOBERR AND iobm/ETACK)
OR (C8M AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/DTACKrf AND
iobm/DTACKrr)
OR (C8M AND nBERR_IOB AND iobm/IOS_FSM_FFd3 AND
iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2 AND IOBERR AND iobm/BERRrf AND
iobm/BERRrr));
FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,FCLK,'0','0',IOL0_CE);
IOL0_D <= ((NOT nLDS_FSB AND nADoutLE1)
OR (iobs/IOL1 AND NOT nADoutLE1));
IOL0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,FCLK,'0','0');
IOREQ_D <= ((A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd1)
OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd1)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd1)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd1)
OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr)
OR (NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd1)
OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd1 AND
fsb/ASrf));
FDCPE_IORW0: FDCPE port map (IORW0,IORW0_D,FCLK,'0','0');
IORW0_D <= ((EXP11_.EXP)
OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND NOT nWE_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND NOT nWE_FSB AND
NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND NOT nWE_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
nADoutLE1)
OR (NOT iobs/IORW1 AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND
NOT nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND NOT IORW0 AND
nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Once AND NOT nWE_FSB AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Once AND NOT nWE_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf AND nADoutLE1)
OR (NOT IORW0 AND iobs/PS_FSM_FFd2)
OR (NOT IORW0 AND iobs/PS_FSM_FFd1)
OR (iobs/Once AND NOT IORW0 AND nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT IORW0 AND nADoutLE1)
OR (NOT IORW0 AND nAS_FSB AND NOT fsb/ASrf AND nADoutLE1));
Redo CNT timers
2023-03-25 07:49:44 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,FCLK,'0','0',IOU0_CE);
IOU0_D <= ((NOT nUDS_FSB AND nADoutLE1)
OR (iobs/IOU1 AND NOT nADoutLE1));
IOU0_CE <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1);
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(0) <= ((A_FSB(10) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(1)));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(1) <= ((A_FSB(11) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(2)));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(2) <= ((A_FSB(12) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(3)));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(3) <= ((A_FSB(13) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(4)));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(4) <= ((A_FSB(14) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(5)));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(5) <= ((A_FSB(15) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(6)));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Put back all chip selects.
2023-03-27 14:17:22 +00:00
RA(6) <= ((A_FSB(16) AND NOT ram/RASEL)
OR (ram/RASEL AND A_FSB(7)));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(7) <= ((A_FSB(8) AND ram/RASEL)
OR (A_FSB(17) AND NOT ram/RASEL));
idk
2023-03-22 01:11:58 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(8) <= ((A_FSB(23) AND A_FSB(18))
OR (A_FSB(22) AND A_FSB(18))
OR (A_FSB(18) AND NOT cs/nOverlay)
OR (A_FSB(18) AND NOT ram/RASEL)
OR (A_FSB(9) AND NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
ram/RASEL));
idk
2023-03-22 01:11:58 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(9) <= ((A_FSB(20) AND ram/RASEL)
OR (A_FSB(19) AND NOT ram/RASEL));
idk
2023-03-22 01:11:58 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(10) <= A_FSB(21);
idk
2023-03-22 01:11:58 +00:00
idk
2023-03-26 08:33:59 +00:00
RA(11) <= A_FSB(19);
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_RefReq: FDCPE port map (RefReq,RefReq_D,FCLK,'0','0',RefReq_CE);
RefReq_D <= (NOT RefUrg AND NOT cnt/Timer(1) AND NOT cnt/Timer(2));
RefReq_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_RefUrg: FTCPE port map (RefUrg,RefUrg_T,FCLK,'0','0',RefUrg_CE);
RefUrg_T <= ((RefUrg AND cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1))
OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
NOT cnt/TimerTC)
OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
cnt/Er(0))
OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2) AND
NOT cnt/Er(1)));
RefUrg_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_cnt/Er0: FDCPE port map (cnt/Er(0),E,FCLK,'0','0');
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_cnt/Er1: FDCPE port map (cnt/Er(1),cnt/Er(0),FCLK,'0','0');
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_cnt/INITS_FSM_FFd1: FTCPE port map (cnt/INITS_FSM_FFd1,cnt/INITS_FSM_FFd1_T,FCLK,'0','0');
cnt/INITS_FSM_FFd1_T <= (cnt/TimerTC AND cnt/LTimerTC AND NOT cnt/INITS_FSM_FFd1 AND
cnt/INITS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/nIPL2r AND cnt/Er(1));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_cnt/INITS_FSM_FFd2: FTCPE port map (cnt/INITS_FSM_FFd2,cnt/INITS_FSM_FFd2_T,FCLK,'0','0');
cnt/INITS_FSM_FFd2_T <= ((cnt/TimerTC AND cnt/LTimerTC AND cnt/INITS_FSM_FFd1 AND
cnt/INITS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1))
OR (cnt/TimerTC AND cnt/LTimerTC AND NOT cnt/INITS_FSM_FFd1 AND
NOT cnt/INITS_FSM_FFd2 AND NOT cnt/Er(0) AND cnt/Er(1)));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_cnt/LTimer0: FTCPE port map (cnt/LTimer(0),'1',FCLK,'0','0',cnt/LTimer_CE(0));
cnt/LTimer_CE(0) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_cnt/LTimer1: FTCPE port map (cnt/LTimer(1),cnt/LTimer(0),FCLK,'0','0',cnt/LTimer_CE(1));
cnt/LTimer_CE(1) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0',cnt/LTimer_CE(2));
cnt/LTimer_T(2) <= (cnt/LTimer(0) AND cnt/LTimer(1));
cnt/LTimer_CE(2) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_cnt/LTimer3: FTCPE port map (cnt/LTimer(3),cnt/LTimer_T(3),FCLK,'0','0',cnt/LTimer_CE(3));
cnt/LTimer_T(3) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2));
cnt/LTimer_CE(3) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_cnt/LTimer4: FTCPE port map (cnt/LTimer(4),cnt/LTimer_T(4),FCLK,'0','0',cnt/LTimer_CE(4));
cnt/LTimer_T(4) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3));
cnt/LTimer_CE(4) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_cnt/LTimer5: FTCPE port map (cnt/LTimer(5),cnt/LTimer_T(5),FCLK,'0','0',cnt/LTimer_CE(5));
cnt/LTimer_T(5) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4));
cnt/LTimer_CE(5) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_cnt/LTimer6: FTCPE port map (cnt/LTimer(6),cnt/LTimer_T(6),FCLK,'0','0',cnt/LTimer_CE(6));
cnt/LTimer_T(6) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5));
cnt/LTimer_CE(6) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_cnt/LTimer7: FTCPE port map (cnt/LTimer(7),cnt/LTimer_T(7),FCLK,'0','0',cnt/LTimer_CE(7));
cnt/LTimer_T(7) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6));
cnt/LTimer_CE(7) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer8: FTCPE port map (cnt/LTimer(8),cnt/LTimer_T(8),FCLK,'0','0',cnt/LTimer_CE(8));
cnt/LTimer_T(8) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7));
cnt/LTimer_CE(8) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer9: FTCPE port map (cnt/LTimer(9),cnt/LTimer_T(9),FCLK,'0','0',cnt/LTimer_CE(9));
cnt/LTimer_T(9) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7) AND cnt/LTimer(8));
cnt/LTimer_CE(9) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer10: FTCPE port map (cnt/LTimer(10),cnt/LTimer_T(10),FCLK,'0','0',cnt/LTimer_CE(10));
cnt/LTimer_T(10) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
cnt/LTimer_CE(10) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer11: FTCPE port map (cnt/LTimer(11),cnt/LTimer_T(11),FCLK,'0','0',cnt/LTimer_CE(11));
cnt/LTimer_T(11) <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND
cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
cnt/LTimer_CE(11) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/LTimer12: FTCPE port map (cnt/LTimer(12),cnt/LTimer_T(12),FCLK,'0','0',cnt/LTimer_CE(12));
cnt/LTimer_T(12) <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(11) AND
cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND
cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND
cnt/LTimer(9));
cnt/LTimer_CE(12) <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/LTimerTC: FDCPE port map (cnt/LTimerTC,cnt/LTimerTC_D,FCLK,'0','0',cnt/LTimerTC_CE);
cnt/LTimerTC_D <= (NOT cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(11) AND
cnt/LTimer(1) AND cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND
cnt/LTimer(5) AND cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND
cnt/LTimer(9) AND cnt/LTimer(12));
cnt/LTimerTC_CE <= (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1));
FTCPE_cnt/Timer0: FTCPE port map (cnt/Timer(0),cnt/Timer_T(0),FCLK,'0','0',cnt/Timer_CE(0));
cnt/Timer_T(0) <= (NOT cnt/Timer(0) AND cnt/TimerTC AND NOT cnt/Er(0) AND
cnt/Er(1));
cnt/Timer_CE(0) <= (NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/Timer1: FDCPE port map (cnt/Timer(1),cnt/Timer_D(1),FCLK,'0','0',cnt/Timer_CE(1));
Put back all chip selects.
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cnt/Timer_D(1) <= ((cnt/Timer(0) AND cnt/Timer(1))
OR (NOT cnt/Timer(0) AND NOT cnt/Timer(1))
OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
idk
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cnt/Timer_CE(1) <= (NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/Timer2: FDCPE port map (cnt/Timer(2),cnt/Timer_D(2),FCLK,'0','0',cnt/Timer_CE(2));
Put back all chip selects.
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cnt/Timer_D(2) <= ((NOT cnt/Timer(0) AND NOT cnt/Timer(2))
idk
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OR (NOT cnt/Timer(1) AND NOT cnt/Timer(2))
Put back all chip selects.
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OR (cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2))
idk
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OR (cnt/TimerTC AND NOT cnt/Er(0) AND cnt/Er(1)));
cnt/Timer_CE(2) <= (NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/TimerTC: FDCPE port map (cnt/TimerTC,cnt/TimerTC_D,FCLK,'0','0',cnt/TimerTC_CE);
cnt/TimerTC_D <= (RefUrg AND cnt/Timer(0) AND NOT cnt/Timer(1) AND
NOT cnt/Timer(2));
cnt/TimerTC_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
FDCPE_cnt/nIPL2r: FDCPE port map (cnt/nIPL2r,nIPL2,FCLK,'0','0');
FTCPE_cs/nOverlay: FTCPE port map (cs/nOverlay,cs/nOverlay_T,FCLK,NOT nRES.PIN,'0');
cs/nOverlay_T <= ((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay AND NOT nAS_FSB)
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
NOT cs/nOverlay AND fsb/ASrf));
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT FCLK,'0','0');
FDCPE_fsb/Ready0r: FDCPE port map (fsb/Ready0r,fsb/Ready0r_D,FCLK,'0','0');
fsb/Ready0r_D <= ((nAS_FSB AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
NOT fsb/Ready0r AND NOT ram/RAMReady));
FDCPE_fsb/Ready1r: FDCPE port map (fsb/Ready1r,fsb/Ready1r_D,FCLK,'0','0');
fsb/Ready1r_D <= ((A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
NOT fsb/Ready1r AND NOT nWE_FSB AND NOT iobs/IOReady AND NOT nADoutLE1)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady)
OR (A_FSB(22) AND A_FSB(21) AND NOT fsb/Ready1r AND
NOT iobs/IOReady)
OR (A_FSB(22) AND A_FSB(20) AND NOT fsb/Ready1r AND
NOT iobs/IOReady)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
NOT fsb/Ready1r AND NOT nWE_FSB AND NOT iobs/IOReady AND NOT nADoutLE1));
FDCPE_fsb/VPA: FDCPE port map (fsb/VPA,fsb/VPA_D,FCLK,'0','0');
fsb/VPA_D <= ((EXP12_.EXP)
OR (A_FSB(22) AND A_FSB(20) AND NOT fsb/Ready1r AND fsb/VPA AND
NOT iobs/IOReady AND fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
NOT fsb/Ready0r AND fsb/VPA AND NOT nAS_FSB AND NOT ram/RAMReady)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
NOT fsb/Ready0r AND fsb/VPA AND fsb/ASrf AND NOT ram/RAMReady)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
NOT fsb/Ready1r AND fsb/VPA AND NOT nWE_FSB AND NOT iobs/IOReady AND NOT nAS_FSB AND
NOT nADoutLE1)
OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
NOT fsb/Ready1r AND fsb/VPA AND NOT nWE_FSB AND NOT iobs/IOReady AND NOT nAS_FSB AND
NOT nADoutLE1)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
NOT fsb/Ready1r AND fsb/VPA AND NOT nWE_FSB AND NOT iobs/IOReady AND fsb/ASrf AND
NOT nADoutLE1)
OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
NOT fsb/Ready1r AND fsb/VPA AND NOT nWE_FSB AND NOT iobs/IOReady AND fsb/ASrf AND
NOT nADoutLE1)
OR (A_FSB(9) AND A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND A_FSB(23) AND
A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
A_FSB(17) AND A_FSB(16) AND fsb/Ready1r AND NOT nAS_FSB)
OR (A_FSB(9) AND A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND A_FSB(23) AND
A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
A_FSB(17) AND A_FSB(16) AND iobs/IOReady AND NOT nAS_FSB)
OR (A_FSB(9) AND A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND A_FSB(23) AND
A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
A_FSB(17) AND A_FSB(16) AND iobs/IOReady AND fsb/ASrf)
OR (A_FSB(23) AND NOT fsb/Ready1r AND fsb/VPA AND
NOT iobs/IOReady AND NOT nAS_FSB)
OR (A_FSB(23) AND NOT fsb/Ready1r AND fsb/VPA AND
NOT iobs/IOReady AND fsb/ASrf)
OR (A_FSB(22) AND A_FSB(21) AND NOT fsb/Ready1r AND fsb/VPA AND
NOT iobs/IOReady AND NOT nAS_FSB)
OR (A_FSB(22) AND A_FSB(21) AND NOT fsb/Ready1r AND fsb/VPA AND
NOT iobs/IOReady AND fsb/ASrf)
OR (A_FSB(22) AND A_FSB(20) AND NOT fsb/Ready1r AND fsb/VPA AND
NOT iobs/IOReady AND NOT nAS_FSB));
FDCPE_iobm/BERRrf: FDCPE port map (iobm/BERRrf,NOT nBERR_IOB,NOT C16M,'0','0');
FDCPE_iobm/BERRrr: FDCPE port map (iobm/BERRrr,NOT nBERR_IOB,C16M,'0','0');
FDCPE_iobm/DTACKrf: FDCPE port map (iobm/DTACKrf,NOT nDTACK_IOB,NOT C16M,'0','0');
FDCPE_iobm/DTACKrr: FDCPE port map (iobm/DTACKrr,NOT nDTACK_IOB,C16M,'0','0');
FDCPE_iobm/DoutOE: FDCPE port map (iobm/DoutOE,iobm/DoutOE_D,C16M,'0','0');
iobm/DoutOE_D <= ((NOT IORW0 AND iobm/IOS_FSM_FFd3)
OR (NOT IORW0 AND iobm/IOS_FSM_FFd2)
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
NOT iobm/IOS_FSM_FFd2 AND NOT iobm/IOREQr AND NOT nAoutOE));
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),C16M,'0','0');
iobm/ES_T(0) <= ((iobm/ES(0) AND NOT iobm/Er AND iobm/Er2)
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4) AND iobm/Er)
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4) AND NOT iobm/Er2));
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),C16M,'0','0');
iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
OR (NOT iobm/Er AND iobm/Er2));
FDCPE_iobm/ES2: FDCPE port map (iobm/ES(2),iobm/ES_D(2),C16M,'0','0');
iobm/ES_D(2) <= ((NOT iobm/ES(0) AND NOT iobm/ES(2))
OR (NOT iobm/ES(1) AND NOT iobm/ES(2))
OR (NOT iobm/Er AND iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2))
OR (NOT iobm/ES(2) AND NOT iobm/ES(3) AND iobm/ES(4)));
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),C16M,'0','0');
iobm/ES_T(3) <= ((iobm/ES(3) AND NOT iobm/Er AND iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND iobm/Er)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND NOT iobm/Er2));
FTCPE_iobm/ES4: FTCPE port map (iobm/ES(4),iobm/ES_T(4),C16M,'0','0');
iobm/ES_T(4) <= ((iobm/ES(4) AND NOT iobm/Er AND iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
iobm/ES(3) AND iobm/Er)
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
iobm/ES(3) AND NOT iobm/Er2)
OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND iobm/ES(4)));
FDCPE_iobm/ETACK: FDCPE port map (iobm/ETACK,iobm/ETACK_D,C16M,'0','0');
iobm/ETACK_D <= (NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND iobm/ES(4));
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E,NOT C8M,'0','0');
FDCPE_iobm/Er2: FDCPE port map (iobm/Er2,iobm/Er,C16M,'0','0');
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,NOT C16M,'0','0');
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd1_D,C16M,'0','0');
iobm/IOS_FSM_FFd1_D <= ((iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1)
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2));
FTCPE_iobm/IOS_FSM_FFd2: FTCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_T,C16M,'0','0');
iobm/IOS_FSM_FFd2_T <= ((iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
NOT iobm/IOS_FSM_FFd2)
OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/IOS_FSM_FFd2 AND iobm/ETACK)
OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/IOS_FSM_FFd2 AND iobm/DTACKrf AND iobm/DTACKrr)
OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/IOS_FSM_FFd2 AND iobm/BERRrf AND iobm/BERRrr)
OR (C8M AND iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd1 AND
iobm/IOS_FSM_FFd2 AND iobm/RESrf AND iobm/RESrr));
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,'0','0');
iobm/IOS_FSM_FFd3_D <= ((iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2)
OR (iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd1 AND
NOT iobm/IOS_FSM_FFd2)
OR (NOT C8M AND NOT iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2 AND
iobm/IOREQr AND NOT nAoutOE));
FDCPE_iobm/RESrf: FDCPE port map (iobm/RESrf,NOT nRES.PIN,NOT C16M,'0','0');
FDCPE_iobm/RESrr: FDCPE port map (iobm/RESrr,NOT nRES.PIN,C16M,'0','0');
FDCPE_iobm/VPArf: FDCPE port map (iobm/VPArf,NOT nVPA_IOB,NOT C16M,'0','0');
FDCPE_iobm/VPArr: FDCPE port map (iobm/VPArr,NOT nVPA_IOB,C16M,'0','0');
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,FCLK,'0','0');
iobs/Clear1_D <= (iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1);
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,FCLK,'0','0');
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,FCLK,'0','0',iobs/Load1);
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,FCLK,'0','0');
iobs/IORW1_T <= ((iobs/Once)
OR (NOT nADoutLE1)
OR (nDTACK_FSB_OBUF.EXP)
OR (nAS_FSB AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(19))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND nWE_FSB)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(20))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(18))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(17))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(16))
OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20))
OR (nWE_FSB AND iobs/IORW1)
OR (NOT nWE_FSB AND NOT iobs/IORW1)
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
FTCPE_iobs/IOReady: FTCPE port map (iobs/IOReady,iobs/IOReady_T,FCLK,'0','0');
Put back all chip selects.
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iobs/IOReady_T <= ((iobs/Once AND iobs/IOReady AND NOT iobs/PS_FSM_FFd2 AND
idk
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NOT iobs/IOACTr AND IOBERR AND nADoutLE1)
OR (iobs/Once AND NOT iobs/IOReady AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND NOT IOBERR AND nADoutLE1)
OR (iobs/Once AND NOT iobs/IOReady AND NOT iobs/PS_FSM_FFd2 AND
Put back all chip selects.
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NOT iobs/IOACTr AND NOT IOBERR AND fsb/ASrf AND nADoutLE1)
OR (iobs/IOReady AND nAS_FSB AND NOT fsb/ASrf));
idk
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FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,FCLK,'0','0',iobs/Load1);
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,FCLK,'0','0');
iobs/Load1_D <= ((iobs/Once)
OR (NOT nADoutLE1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(21))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(19))
Put back all chip selects.
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(17))
idk
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OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(16))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND nWE_FSB)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(20))
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT A_FSB(18))
OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20))
OR (NOT A_FSB(14) AND NOT A_FSB(13) AND NOT A_FSB(23) AND NOT A_FSB(22))
OR (nAS_FSB AND NOT fsb/ASrf)
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/nOverlay));
FTCPE_iobs/Once: FTCPE port map (iobs/Once,iobs/Once_T,FCLK,'0','0');
iobs/Once_T <= ((A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(14) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
NOT iobs/Once AND cs/nOverlay AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
OR (A_FSB(14) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
NOT iobs/Once AND cs/nOverlay AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
OR (A_FSB(13) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
NOT iobs/Once AND cs/nOverlay AND NOT nWE_FSB AND NOT nAS_FSB AND nADoutLE1)
OR (A_FSB(13) AND NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND
A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND
NOT iobs/Once AND cs/nOverlay AND NOT nWE_FSB AND fsb/ASrf AND nADoutLE1)
OR (iobs/Once AND nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
FDCPE_iobs/PS_FSM_FFd1: FDCPE port map (iobs/PS_FSM_FFd1,iobs/PS_FSM_FFd1_D,FCLK,'0','0');
iobs/PS_FSM_FFd1_D <= ((iobs/PS_FSM_FFd2)
OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr));
FTCPE_iobs/PS_FSM_FFd2: FTCPE port map (iobs/PS_FSM_FFd2,iobs/PS_FSM_FFd2_T,FCLK,'0','0');
iobs/PS_FSM_FFd2_T <= ((A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (A_FSB(22) AND A_FSB(20) AND NOT iobs/Once AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
Put back all chip selects.
2023-03-27 14:17:22 +00:00
NOT nWE_FSB AND NOT nAS_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND NOT iobs/Once AND cs/nOverlay AND
idk
2023-03-26 08:33:59 +00:00
NOT nWE_FSB AND NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (iobs/PS_FSM_FFd1 AND iobs/IOACTr)
OR (NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1 AND NOT nADoutLE1)
OR (A_FSB(23) AND NOT iobs/Once AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1)
OR (A_FSB(23) AND NOT iobs/Once AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/PS_FSM_FFd1 AND fsb/ASrf)
OR (A_FSB(22) AND A_FSB(21) AND NOT iobs/Once AND NOT nAS_FSB AND
NOT iobs/PS_FSM_FFd2 AND NOT iobs/PS_FSM_FFd1));
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,FCLK,'0','0');
nADoutLE1_D <= ((iobs/Load1)
OR (NOT iobs/Clear1 AND NOT nADoutLE1));
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT C16M,'0','0');
nAS_IOB <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd2)
OR (iobm/IOS_FSM_FFd1 AND NOT iobm/IOS_FSM_FFd2));
nAS_IOB <= nAS_IOB_I when nAS_IOB_OE = '1' else 'Z';
nAS_IOB_OE <= NOT nAoutOE;
FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,FCLK,'0','0');
nAoutOE_D <= ((NOT nBR_IOB AND cnt/INITS_FSM_FFd1 AND
cnt/INITS_FSM_FFd2)
OR (cnt/INITS_FSM_FFd1 AND NOT cnt/INITS_FSM_FFd2 AND
NOT nAoutOE));
FTCPE_nBERR_FSB: FTCPE port map (nBERR_FSB,nBERR_FSB_T,FCLK,'0','0');
Put back all chip selects.
2023-03-27 14:17:22 +00:00
nBERR_FSB_T <= ((nAS_FSB AND NOT nBERR_FSB AND NOT fsb/ASrf)
idk
2023-03-26 08:33:59 +00:00
OR (iobs/Once AND NOT nBERR_FSB AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/IOACTr AND NOT IOBERR AND nADoutLE1)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (iobs/Once AND NOT nAS_FSB AND nBERR_FSB AND
idk
2023-03-26 08:33:59 +00:00
NOT iobs/PS_FSM_FFd2 AND NOT iobs/IOACTr AND IOBERR AND nADoutLE1)
OR (iobs/Once AND nBERR_FSB AND NOT iobs/PS_FSM_FFd2 AND
NOT iobs/IOACTr AND IOBERR AND fsb/ASrf AND nADoutLE1));
FTCPE_nBR_IOB: FTCPE port map (nBR_IOB,nBR_IOB_T,FCLK,'0','0');
Put back all chip selects.
2023-03-27 14:17:22 +00:00
nBR_IOB_T <= ((nBR_IOB AND NOT cnt/INITS_FSM_FFd1 AND
NOT cnt/INITS_FSM_FFd2)
OR (NOT nBR_IOB AND NOT cnt/INITS_FSM_FFd1 AND
cnt/INITS_FSM_FFd2 AND NOT cnt/nIPL2r));
idk
2023-03-26 08:33:59 +00:00
FDCPE_nCAS: FDCPE port map (nCAS,NOT ram/RASEL,NOT FCLK,'0','0');
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0','0');
nDTACK_FSB_D <= ((nAS_FSB AND NOT fsb/ASrf)
OR (A_FSB(23) AND NOT fsb/Ready1r AND NOT iobs/IOReady AND
Redo CNT timers
2023-03-25 07:49:44 +00:00
nDTACK_FSB)
idk
2023-03-26 08:33:59 +00:00
OR (A_FSB(22) AND A_FSB(20) AND NOT fsb/Ready1r AND
NOT iobs/IOReady AND nDTACK_FSB)
OR (A_FSB(9) AND A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND A_FSB(23) AND
A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
A_FSB(17) AND A_FSB(16) AND fsb/Ready1r)
OR (A_FSB(9) AND A_FSB(8) AND A_FSB(15) AND A_FSB(14) AND
A_FSB(13) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND A_FSB(23) AND
A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
A_FSB(17) AND A_FSB(16) AND iobs/IOReady)
OR (A_FSB(22) AND A_FSB(21) AND NOT fsb/Ready1r AND
NOT iobs/IOReady AND nDTACK_FSB)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
NOT fsb/Ready0r AND nDTACK_FSB AND NOT ram/RAMReady)
OR (A_FSB(14) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
NOT fsb/Ready1r AND NOT nWE_FSB AND NOT iobs/IOReady AND nDTACK_FSB AND NOT nADoutLE1)
OR (A_FSB(13) AND A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND
A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND cs/nOverlay AND
NOT fsb/Ready1r AND NOT nWE_FSB AND NOT iobs/IOReady AND nDTACK_FSB AND NOT nADoutLE1));
idk
2023-03-22 01:11:58 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT C16M,'0','0');
nDinLE_D <= (iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2);
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Put back all chip selects.
2023-03-27 14:17:22 +00:00
nDinOE <= NOT (((A_FSB(23) AND nWE_FSB AND NOT nAS_FSB)
idk
2023-03-26 08:33:59 +00:00
OR (A_FSB(22) AND A_FSB(21) AND nWE_FSB AND NOT nAS_FSB)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (A_FSB(22) AND A_FSB(20) AND nWE_FSB AND NOT nAS_FSB)));
idk
2023-03-22 01:11:58 +00:00
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
nDoutOE <= NOT ((iobm/DoutOE AND NOT nAoutOE));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT C16M,'0','0');
nLDS_IOB <= ((IOL0 AND NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2)
OR (IOL0 AND iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2)
OR (IORW0 AND IOL0 AND iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd1));
nLDS_IOB <= nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z';
nLDS_IOB_OE <= NOT nAoutOE;
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
nOE <= NOT ((nWE_FSB AND NOT nAS_FSB));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
nRAMLWE <= NOT ((NOT nLDS_FSB AND NOT nWE_FSB AND NOT nAS_FSB AND ram/RAMEN));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND NOT nAS_FSB AND ram/RAMEN));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Put back all chip selects.
2023-03-27 14:17:22 +00:00
nRAS <= NOT (((ram/RefRAS)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
ram/RAMEN)));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
nRES_I <= '0';
nRES <= nRES_I when nRES_OE = '1' else 'Z';
nRES_OE <= NOT nRESout;
idk
2023-03-22 01:11:58 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_nRESout: FDCPE port map (nRESout,nRESout_D,FCLK,'0','0');
nRESout_D <= (cnt/INITS_FSM_FFd1 AND NOT cnt/INITS_FSM_FFd2);
idk
2023-03-22 01:11:58 +00:00
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Put back all chip selects.
2023-03-27 14:17:22 +00:00
nROMCS <= NOT (((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20))
OR (NOT A_FSB(23) AND NOT A_FSB(21) AND NOT A_FSB(20) AND NOT cs/nOverlay)));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
nROMWE <= NOT ((NOT nWE_FSB AND NOT nAS_FSB));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT C16M,'0','0');
nUDS_IOB <= ((IOU0 AND NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd2)
OR (IOU0 AND iobm/IOS_FSM_FFd1 AND iobm/IOS_FSM_FFd2)
OR (IORW0 AND IOU0 AND iobm/IOS_FSM_FFd3 AND
NOT iobm/IOS_FSM_FFd1));
nUDS_IOB <= nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z';
nUDS_IOB_OE <= NOT nAoutOE;
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,C16M,'0','0');
nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4))
OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND
NOT iobm/ES(3) AND NOT iobm/ES(4) AND IOACT AND iobm/VPArf AND iobm/VPArr));
nVMA_IOB <= nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z';
nVMA_IOB_OE <= NOT nAoutOE;
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
nVPA_FSB <= NOT ((fsb/VPA AND NOT nAS_FSB));
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_ram/BACTr: FDCPE port map (ram/BACTr,ram/BACTr_D,FCLK,'0','0');
ram/BACTr_D <= (nAS_FSB AND NOT fsb/ASrf);
FDCPE_ram/RAMEN: FDCPE port map (ram/RAMEN,ram/RAMEN_D,FCLK,'0','0');
Put back all chip selects.
2023-03-27 14:17:22 +00:00
ram/RAMEN_D <= ((ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND ram/RAMEN)
OR (NOT ram/RS_FSM_FFd1 AND ram/RS_FSM_FFd3 AND ram/RAMEN)
OR (nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
idk
2023-03-26 08:33:59 +00:00
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (NOT ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND ram/RAMEN)
idk
2023-03-26 08:33:59 +00:00
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RefUrg AND ram/RAMEN AND
idk
2023-03-22 01:11:58 +00:00
ram/BACTr)
idk
2023-03-26 08:33:59 +00:00
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RefUrg AND ram/RAMEN AND
NOT ram/RefReq)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd1 AND ram/RAMEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
NOT ram/RS_FSM_FFd1 AND ram/RAMEN AND fsb/ASrf));
FDCPE_ram/RAMReady: FDCPE port map (ram/RAMReady,ram/RAMReady_D,FCLK,'0','0');
Put back all chip selects.
2023-03-27 14:17:22 +00:00
ram/RAMReady_D <= ((A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
idk
2023-03-26 08:33:59 +00:00
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND ram/BACTr)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
idk
2023-03-26 08:33:59 +00:00
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT ram/RefReq)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (A_FSB(22) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
idk
2023-03-26 08:33:59 +00:00
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND ram/BACTr)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (A_FSB(22) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT ram/RefReq)
OR (NOT cs/nOverlay AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
idk
2023-03-26 08:33:59 +00:00
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND ram/BACTr)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND NOT ram/RefUrg)
OR (NOT cs/nOverlay AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
idk
2023-03-26 08:33:59 +00:00
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT ram/RefReq)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
idk
2023-03-26 08:33:59 +00:00
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
Put back all chip selects.
2023-03-27 14:17:22 +00:00
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND
idk
2023-03-26 08:33:59 +00:00
NOT ram/RAMEN));
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,FCLK,'0','0');
ram/RASEL_D <= ((A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RefUrg AND NOT ram/RefReq)
OR (A_FSB(22) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RefUrg AND NOT ram/RefReq)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RefUrg AND NOT fsb/ASrf)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND NOT ram/RAMEN)
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND NOT ram/RAMEN AND fsb/ASrf)
OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RefUrg AND ram/BACTr)
OR (A_FSB(22) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RefUrg AND ram/BACTr)
OR (NOT cs/nOverlay AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RefUrg AND ram/BACTr)
OR (NOT cs/nOverlay AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RefUrg AND NOT ram/RefReq)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
OR (NOT nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3)
OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3 AND NOT ram/RefUrg)
OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3 AND fsb/ASrf));
FTCPE_ram/RS_FSM_FFd1: FTCPE port map (ram/RS_FSM_FFd1,ram/RS_FSM_FFd1_T,FCLK,'0','0');
ram/RS_FSM_FFd1_T <= ((ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd3)
idk
2023-03-26 08:33:59 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
Put back all chip selects.
2023-03-27 14:17:22 +00:00
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND ram/RAMEN)
idk
2023-03-26 08:33:59 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
Put back all chip selects.
2023-03-27 14:17:22 +00:00
NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND ram/RAMEN AND
fsb/ASrf));
idk
2023-03-26 08:33:59 +00:00
Put back all chip selects.
2023-03-27 14:17:22 +00:00
FTCPE_ram/RS_FSM_FFd2: FTCPE port map (ram/RS_FSM_FFd2,ram/RS_FSM_FFd2_T,FCLK,'0','0');
ram/RS_FSM_FFd2_T <= ((ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd3)
OR (nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RefUrg AND NOT fsb/ASrf)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND
ram/BACTr)
OR (NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND
NOT ram/RefReq)
OR (nAS_FSB AND NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND
NOT ram/RefUrg AND NOT fsb/ASrf)
idk
2023-03-26 08:33:59 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND NOT nAS_FSB AND
Put back all chip selects.
2023-03-27 14:17:22 +00:00
NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3)
idk
2023-03-26 08:33:59 +00:00
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND cs/nOverlay AND
Put back all chip selects.
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NOT ram/RS_FSM_FFd1 AND NOT ram/RS_FSM_FFd3 AND fsb/ASrf));
FTCPE_ram/RS_FSM_FFd3: FTCPE port map (ram/RS_FSM_FFd3,ram/RS_FSM_FFd3_T,FCLK,'0','0');
ram/RS_FSM_FFd3_T <= ((nAS_FSB AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT fsb/ASrf)
OR (NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3 AND NOT ram/RefUrg AND NOT ram/RAMEN)
OR (A_FSB(23) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
OR (A_FSB(22) AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
idk
2023-03-26 08:33:59 +00:00
NOT ram/RS_FSM_FFd3)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (NOT cs/nOverlay AND NOT ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
NOT ram/RS_FSM_FFd3)
OR (NOT nAS_FSB AND ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND ram/RefUrg)
OR (ram/RS_FSM_FFd2 AND ram/RS_FSM_FFd1 AND
ram/RS_FSM_FFd3 AND ram/RefUrg AND fsb/ASrf));
idk
2023-03-22 01:11:58 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_ram/RefDone: FDCPE port map (ram/RefDone,ram/RefDone_D,FCLK,'0','0');
ram/RefDone_D <= ((ram/RefDone AND ram/RefReqSync)
Put back all chip selects.
2023-03-27 14:17:22 +00:00
OR (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1 AND
ram/RefReqSync));
FDCPE_ram/RefRAS: FDCPE port map (ram/RefRAS,ram/RefRAS_D,FCLK,'0','0');
ram/RefRAS_D <= (ram/RS_FSM_FFd2 AND NOT ram/RS_FSM_FFd1);
Better CPLD stuff
2022-03-29 08:23:54 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_ram/RefReq: FDCPE port map (ram/RefReq,ram/RefReq_D,FCLK,'0','0');
ram/RefReq_D <= (NOT ram/RefDone AND ram/RefReqSync);
idk
2023-03-22 01:11:58 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_ram/RefReqSync: FDCPE port map (ram/RefReqSync,RefReq,FCLK,'0','0');
idk
2023-03-22 01:11:58 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_ram/RefUrg: FDCPE port map (ram/RefUrg,ram/RefUrg_D,FCLK,'0','0');
ram/RefUrg_D <= (NOT ram/RefDone AND ram/RegUrgSync);
idk
2023-03-22 01:11:58 +00:00
idk
2023-03-26 08:33:59 +00:00
FDCPE_ram/RegUrgSync: FDCPE port map (ram/RegUrgSync,RefUrg,FCLK,'0','0');
idk
2023-03-22 01:11:58 +00:00
Better CPLD stuff
2022-03-29 08:23:54 +00:00
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC95144XL-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 51 VCC
2 A_FSB<5> 52 RA<7>
3 A_FSB<6> 53 RA<0>
4 A_FSB<7> 54 RA<8>
5 VCC 55 RA<10>
6 A_FSB<8> 56 RA<9>
7 A_FSB<9> 57 VCC
idk
2023-03-22 01:11:58 +00:00
8 A_FSB<10> 58 C25MEN
9 A_FSB<11> 59 C20MEN
10 A_FSB<12> 60 KPR
11 A_FSB<13> 61 KPR
Better CPLD stuff
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12 A_FSB<14> 62 GND
13 A_FSB<15> 63 RA<11>
14 A_FSB<16> 64 nRAS
15 A_FSB<17> 65 nRAMLWE
16 A_FSB<18> 66 nRAMUWE
17 A_FSB<19> 67 KPR
18 A_FSB<20> 68 KPR
19 A_FSB<21> 69 GND
20 A_FSB<22> 70 nBERR_FSB
21 GND 71 KPR
idk
2023-03-22 01:11:58 +00:00
22 C16M 72 nBR_IOB
Redo CNT timers
2023-03-25 07:49:44 +00:00
23 C8M 73 KPR
Better CPLD stuff
2022-03-29 08:23:54 +00:00
24 A_FSB<23> 74 nVMA_IOB
idk
2023-03-22 01:11:58 +00:00
25 E 75 GND
Better CPLD stuff
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26 VCC 76 nBERR_IOB
idk
2023-03-22 01:11:58 +00:00
27 FCLK 77 nVPA_IOB
Better CPLD stuff
2022-03-29 08:23:54 +00:00
28 nDTACK_FSB 78 nDTACK_IOB
29 nWE_FSB 79 nLDS_IOB
30 nLDS_FSB 80 nUDS_IOB
31 GND 81 nAS_IOB
32 nAS_FSB 82 nADoutLE1
33 nUDS_FSB 83 TDO
34 nROMWE 84 GND
35 nROMCS 85 nADoutLE0
36 nCAS 86 nDinLE
37 nOE 87 nAoutOE
38 VCC 88 VCC
39 KPR 89 nDoutOE
40 RA<4> 90 nDinOE
41 RA<3> 91 nRES
42 RA<5> 92 nIPL2
43 RA<2> 93 nVPA_FSB
44 GND 94 A_FSB<1>
45 TDI 95 A_FSB<2>
46 RA<6> 96 A_FSB<3>
47 TMS 97 A_FSB<4>
48 TCK 98 VCC
49 KPR 99 KPR
50 RA<1> 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
idk
2023-03-26 08:33:59 +00:00
Pterm Limit : 25
Better CPLD stuff
2022-03-29 08:23:54 +00:00
</pre>
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