2023-03-20 05:13:11 +00:00
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Release 14.7 - xst P.20131013 (nt64)
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2021-10-29 10:04:59 +00:00
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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2023-03-20 05:13:11 +00:00
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.09 secs
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2021-10-29 10:04:59 +00:00
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--> Parameter xsthdpdir set to xst
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2023-03-20 05:13:11 +00:00
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.09 secs
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2021-10-29 10:04:59 +00:00
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2022-03-29 08:23:54 +00:00
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--> Reading design: WarpSE.prj
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2021-10-29 10:04:59 +00:00
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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2022-03-29 08:23:54 +00:00
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Input File Name : "WarpSE.prj"
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2021-10-29 10:04:59 +00:00
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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2022-03-29 08:23:54 +00:00
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Output File Name : "WarpSE"
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2021-10-29 10:04:59 +00:00
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Output Format : NGC
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Target Device : XC9500XL CPLDs
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---- Source Options
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2022-03-29 08:23:54 +00:00
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Top Module Name : WarpSE
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2021-10-29 10:04:59 +00:00
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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Mux Extraction : Yes
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 2
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Keep Hierarchy : No
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2021-10-29 10:04:59 +00:00
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Verilog 2001 : YES
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---- Other Options
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../RAM.v" in library work
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2023-03-20 05:13:11 +00:00
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ERROR:HDLCompilers:28 - "../RAM.v" line 38 'BACTr' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 96 'RefFromRS0Next' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 100 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 101 'RefFromRS0Pre' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 107 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 113 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 118 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 124 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 132 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 139 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 146 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 153 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 160 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 167 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 176 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 184 'RAMDIS1' has not been declared
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ERROR:HDLCompilers:28 - "../RAM.v" line 190 'RAMDIS1' has not been declared
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2022-09-04 01:32:05 +00:00
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Compiling verilog file "../IOBS.v" in library work
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2023-03-20 05:13:11 +00:00
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Module <RAM> compiled
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2021-10-29 10:04:59 +00:00
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Compiling verilog file "../IOBM.v" in library work
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Module <IOBS> compiled
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Compiling verilog file "../FSB.v" in library work
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Module <IOBM> compiled
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2023-03-20 05:13:11 +00:00
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ERROR:HDLCompilers:28 - "../FSB.v" line 71 'BERR' has not been declared
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2021-10-29 10:04:59 +00:00
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Compiling verilog file "../CS.v" in library work
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Module <FSB> compiled
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Compiling verilog file "../CNT.v" in library work
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Module <CS> compiled
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2022-09-04 01:32:05 +00:00
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Compiling verilog file "../WarpSE.v" in library work
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2023-03-20 05:13:11 +00:00
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Module <CNT> compiled
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2022-03-29 08:23:54 +00:00
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Module <WarpSE> compiled
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2022-09-04 01:32:05 +00:00
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Analysis of file <"WarpSE.prj"> failed.
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2021-10-29 10:04:59 +00:00
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-->
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2023-03-20 05:13:11 +00:00
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Total memory usage is 232068 kilobytes
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2021-10-29 10:04:59 +00:00
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2023-03-20 05:13:11 +00:00
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Number of errors : 18 ( 0 filtered)
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2022-09-04 01:32:05 +00:00
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Number of warnings : 0 ( 0 filtered)
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2021-10-29 10:04:59 +00:00
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Number of infos : 0 ( 0 filtered)
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