Warp-SE/cpld/WarpSE.v

157 lines
3.4 KiB
Coq
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module WarpSE(
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input [23:1] A_FSB,
input nAS_FSB,
input nLDS_FSB,
input nUDS_FSB,
input nWE_FSB,
output nDTACK_FSB,
output nVPA_FSB,
output nBERR_FSB,
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input FCLK,
input C16M,
input C8M,
input E,
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input nDTACK_IOB,
input nVPA_IOB,
output nVMA_IOB,
output nAS_IOB,
output nUDS_IOB,
output nLDS_IOB,
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output nBR_IOB,
input nBG_IOB,
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input nBERR_IOB,
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inout nRES,
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input nIPL2,
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output nROMCS,
output nRAMLWE,
output nRAMUWE,
output nROMWE,
output nRAS,
output nCAS,
output [11:0] RA,
output nOE,
output nADoutLE0,
output nADoutLE1,
output nAoutOE,
output nDoutOE,
output nDinOE,
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output nDinLE,
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input [3:1] SW,
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input C20MEN,
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output C25MEN);
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/* FSB clock oscillator enable */
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assign C25MEN = 1;
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/* Reset input and open-drain output */
wire nRESin = nRES;
wire nRESout;
assign nRES = !nRESout ? 1'b0 : 1'bZ;
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/* AS cycle detection */
wire BACT;
/* Refresh request/ack signals */
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wire RefReq, RefUrg;
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/* FSB chip select signals */
wire IOCS, IOPWCS, IACS;
wire ROMCS, ROMCS4X;
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wire RAMCS, RAMCS0X, SndRAMCSWR;
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CS cs(
/* MC68HC000 interface */
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A_FSB[23:08], FCLK, nRESin, nWE_FSB,
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/* AS cycle detection */
BACT,
/* Device select outputs */
IOCS, IOPWCS, IACS,
ROMCS, ROMCS4X,
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RAMCS, RAMCS0X, SndRAMCSWR);
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wire RAMReady;
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RAM ram(
/* MC68HC000 interface */
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FCLK, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
/* AS cycle detection */
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BACT,
/* Select and ready signals */
RAMCS, ROMCS, RAMReady,
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/* Refresh Counter Interface */
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RefReq, RefUrg,
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/* DRAM and NOR flash interface */
RA[11:0], nRAS, nCAS,
nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
wire IONPReady, IOPWReady;
wire IORDREQ, IOWRREQ;
wire IOL0, IOU0;
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wire ALE0S, ALE0M, ALE1;
assign nADoutLE0 = ~(ALE0S || ALE0M);
assign nADoutLE1 = ~ALE1;
wire IOACT, IODONE, IOBERR;
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IOBS iobs(
/* MC68HC000 interface */
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FCLK, nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
/* AS cycle detection */
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BACT,
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/* Select signals */
IOCS, IOPWCS, ROMCS,
/* FSB cycle termination outputs */
IONPReady, IOPWReady, nBERR_FSB,
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/* Read data OE control */
nDinOE,
/* IOB Master Controller Interface */
IORDREQ, IOWRREQ,
IOACT, IODONE, IOBERR,
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/* FIFO primary level control */
ALE0S, IOL0, IOU0,
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/* FIFO secondary level control */
ALE1);
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wire AoutOE;
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assign nAoutOE = !AoutOE;
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wire nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout;
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assign nAS_IOB = AoutOE ? nAS_IOBout : 1'bZ;
assign nLDS_IOB = AoutOE ? nLDS_IOBout : 1'bZ;
assign nUDS_IOB = AoutOE ? nUDS_IOBout : 1'bZ;
assign nVMA_IOB = AoutOE ? nVMA_IOBout : 1'bZ;
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IOBM iobm(
/* PDS interface */
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C16M, C8M, E,
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nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
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nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
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/* PDS address and data latch control */
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AoutOE, nDoutOE, ALE0M, nDinLE,
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/* IO bus slave port interface */
IORDREQ, IOWRREQ, IOL0, IOU0,
IOACT, IODONE, IOBERR);
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wire QoSReady;
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CNT cnt(
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/* FSB clock and E clock inputs */
FCLK, E,
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/* Refresh request */
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RefReq, RefUrg,
/* Reset, button */
nRESout, nIPL2,
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/* Mac PDS bus master control outputs */
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AoutOE, nBR_IOB,
/* Sound QoS */
BACT, SndRAMCSWR, QoSReady);
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FSB fsb(
/* MC68HC000 interface */
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FCLK, nAS_FSB, nDTACK_FSB, nVPA_FSB,
/* FSB cycle detection */
BACT,
/* Ready inputs */
ROMCS4X,
RAMCS0X, RAMReady,
IOPWCS, IOPWReady, IONPReady,
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/* Interrupt acknowledge select */
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IACS,
/* Sound QoS */
QoSReady);
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endmodule