Improved a lot of stuff
This commit is contained in:
Zane Kaminski
parent
f68adf22ea
commit
fb6b6debcc
146
cpld/CNT.v
146
cpld/CNT.v
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@ -1,107 +1,121 @@
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module CNT(
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/* C16M clock */
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input C16M,
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/* C8M clock input */
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input C8M,
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/* FSB clock and bus active signal */
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input FCLK, input BACT,
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input FCLK, input LBACT,
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/* Refresh request */
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output reg RefReq, output RefUrgent,
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/* BERR and QoS speed limit output */
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output reg BERRTimeout, output reg QoSGate,
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/* BERR output */
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output reg BERRTimeout,
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/* Reset, switch, button */
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input [3:1] SW, input nRESin, output reg nRESout, input nIPL2,
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/* Mac PDS bus master control outputs */
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output reg AoutOE, output nAoutOE, output nBR_IOB,
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/* Configuration outputs */
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output reg nBR_IOB, output reg FastROMEN, output reg C20MEN, output reg C25MEN);
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output reg WarpEnable, output reg FastROMEN, output C20MEN, output C25MEN);
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/* Timer counts from 0 to 11100000 (224) -- 225 states == 14.36 uS */
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reg [7:0] Timer = 0;
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wire TimerTC = Timer[7:5]==3'b111;
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always @(posedge C16M) Timer <= TimerTC ? 0 : Timer+1;
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/* Timer counts from 0 to 1100000 (96) -- 97 states == 12.382 us */
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reg [6:0] Timer = 0;
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wire TimerTC = Timer[6:5]==2'b11;
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always @(posedge C8M) Timer <= TimerTC ? 0 : Timer+1;
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/* Refresh timer outputs
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* ___ ______________________________________
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* RefReq |___________| |__________
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* ___ ^ Timer==0 ^ Timer==17 _____________^ Timer==0
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* RefUrg |____________________________________| |__________
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* ^ Timer==0 ^ Timer==128 ^ Timer==0
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/* Refresh timer sequence
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* | Timer | RefReq | RefUrgent |
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* |----------------------------|
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* | 0 | 0 | 0 |
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* | 1 | 0 | 0 |
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* | 2 | 0 | 0 |
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* | 3 | 0 | 0 |
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* | 4 | 0 | 0 |
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* | 5 | 0 | 0 |
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* | 6 | 0 | 0 |
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* | 7 | 0 | 0 |
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* | 8 | 0 | 0 |
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* | 9 | 1 | 0 |
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* | 10 | 1 | 0 |
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* | 11 | 1 | 0 |
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* | ... | 1 | 0 |
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* | 62 | 1 | 0 |
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* | 63 | 1 | 0 |
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* | 64 | 1 | 1 |
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* | 65 | 1 | 1 |
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* | 66 | 1 | 1 |
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* | ... | 1 | 1 |
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* | 93 | 1 | 1 |
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* | 94 | 1 | 1 |
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* | 95 | 1 | 1 |
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* | 96 | 1 | 1 |
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* back to timer==0
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*/
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assign RefUrgent = Timer[7];
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always @(posedge C16M) begin
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if (Timer[4]) RefREQ <= 1;
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assign RefUrgent = Timer[6];
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always @(posedge C8M) begin
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if (Timer[3]) RefREQ <= 1;
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else if (TimerTC) RefREQ <= 0;
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end
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/* NBACT - "Narrow BACT" in FCLK clock domain */
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reg [1:0] BACTCnt = 0;
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reg NBACT;
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always @(posedge FCLK) begin
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if (!BACT) begin
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BACTCnt <= 0;
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NBACT <= 0;
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end else begin
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BACTCnt <= BACTCnt+1;
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if (BACTCnt==2'b11 && BACT) NBACT <= 1;
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end
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end
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/* LBACTr - LBACT synchronized to C16M clock domain */
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reg LBACTr;
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always @(posedge C8M) LBACTr <= LBACT;
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/* NBACTr - NBACT synchronized to C16M clock domain */
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reg NBACTr;
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always @(posedge C16M) NBACTr <= NBACT;
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/* BERR generation in C16M clock domain */
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/* BERR generation in C8M clock domain */
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reg BERRArm = 0;
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reg BERRTimeout = 0;
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always @(posedge C16M) begin
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if (NBACTr && TimerTC) begin
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always @(posedge C8M) begin
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if (LBACTr && TimerTC) begin
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BERRArm <= 1;
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if (BERRArm) BERRTimeout <= 1;
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end else if (!NBACTr) begin
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end else if (!LBACTr) begin
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BERRArm <= 0;
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BERRTimeout <= 0;
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end
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end
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/* Sound QoS counter */
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reg [13:0] SC; // Sound counter
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always @(posedge C16M) begin
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if (TimerTC) SC <= SC+1; // SC increment
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end
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/* IPL2 registration */
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reg nIPL2r, nRESr;
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always @(negedge C16M) begin
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nIPL2r <= nIPL2;
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nRESr <= nRES;
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/* Long timer counts from 0 to 16384 -- 16385 states == 202.888 ms */
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reg [14:0] LTimer; // Long timer
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wire LTimerTC <= LTimer[14];
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always @(posedge C8M) begin
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if (LTimerTC) LTimer <= 0;
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else LTimer <= LTimer+1;
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end
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/* Startup sequence control */
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reg [1:0] PORS = 0;
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always @(posedge C16M) begin
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reg Disable = 0;
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reg BR_IOB = 0; assign nBR_IOB <= !BR_IOB;
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assign nAoutOE <= !AoutOE;
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always @(posedge C8M) begin
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case (PORS)
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0: begin
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nRESout <= !nRESr;
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if (nRESr) PORS <= 1;
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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Disable <= 0;
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if (LTimerTC) PORS <= 1;
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end 1: begin
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nRESout <= 0;
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if (TimerTC && SC[13:0]==14'h3FFF && nIPL2r) PORS <= 2;
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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Disable <= Disable | !nIPL2; // No need to synchronize /IPL2
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if (!IPL2r && LTimerTC) begin
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BR_IOB <= !Disable;
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PORS <= 2;
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end
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end 2: begin
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nRESout <= 0;
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if (TimerTC && SC[13:0]==14'h3FFF) PORS <= 3;
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AoutOE <= 0; // Tristate PDS address and control
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nRESout <= 0; // Hold reset low
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if (LTimerTC) PORS <= 3;
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end 3: begin
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nRESout <= 1;
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AoutOE <= BR_IOB;
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// Wait until LTimerTC to release reset
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if (LTimerTC) nRESout <= 1;
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else nRESout = 0;
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PORS <= 3;
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end
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endcase
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end
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/* Accelerator enable/disable control */
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always @(posedge CLK) begin
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if (PORS==0) begin
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if (nRESr) nBR_IOB <= nIPL2r;
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else nBR_IOB <= 1;
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end
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end
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// Enable both oscillators... only mount one
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assign C20MEN = 1;
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assign C25MEN = 1;
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// Enable fast ROM
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assign FastROMEN = 1;
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endmodule
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17
cpld/FSB.v
17
cpld/FSB.v
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@ -2,7 +2,7 @@ module FSB(
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/* MC68HC000 interface */
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input FCLK, input nAS, output reg nDTACK, output nVPA, output nBERR,
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/* AS cycle detection */
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output BACT,
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output BACT, output LBACT,
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/* Ready inputs */
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input Ready0, input Ready1, input Ready2,
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/* BERR inputs */
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@ -13,7 +13,20 @@ module FSB(
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/* AS cycle detection */
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reg ASrf = 0;
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always @(negedge FCLK) begin ASrf <= ~nAS; end
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assign BACT = ~nAS || ASrf;
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assign BACT = ~nAS || ASrf; // BACT - bus active
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/* LBACT - "Long BACT" */
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reg [1:0] BACTCnt = 0;
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reg LBACT;
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always @(posedge FCLK) begin
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if (!BACT) begin
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BACTCnt <= 0;
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LBACT <= 0;
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end else begin
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BACTCnt <= BACTCnt+1;
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if (BACTCnt==2'b11 && BACT) LBACT <= 1;
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end
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end
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/* Ready generation and bypass */
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reg Ready0r, Ready1r, Ready2r;
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@ -4,7 +4,7 @@ module IOBM(
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output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA,
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input nASin, input nBG, input nDTACK, input nVPA, input nBERR, input nRES,
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/* PDS address and data latch control */
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output nAoutOE, output reg nDoutOE, output reg ALE0, output reg nDinLE,
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input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
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/* IO bus slave port interface */
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output reg IOACT, output reg IOBERR,
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input IOREQ, input IOLDS, input IOUDS, input IOWE);
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@ -107,11 +107,11 @@ module IOBM(
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end
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/* PDS address and data latch control */
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assign nAoutOE = !BG;
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always @(negedge C16M) begin nDinLE <= IOS==4 || IOS==5; end
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reg DoutOE = 0; assign nDoutOE <= !(AoutOE && DoutOE);
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always @(posedge C16M) begin
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nDoutOE <= ~(IOWE && (IOS==1 || IOS==2 || IOS==3 ||
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IOS==4 || IOS==5 || IOS==6));
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DoutOE <= IOWE && (IOS==1 || IOS==2 || IOS==3 ||
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IOS==4 || IOS==5 || IOS==6);
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end
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/* AS, DS control */
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@ -47,6 +47,7 @@ module WarpSE(
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/* AS cycle detection */
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wire BACT;
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wire LBACT;
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/* Refresh request/ack signals */
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wire RefReq, RefUrgent;
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@ -112,31 +113,34 @@ module WarpSE(
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nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
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nAS_IOB, nBG_IOB, nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
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/* PDS address and data latch control */
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nAoutOE, nDoutOE, ALE0M, nDinLE,
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AoutOE, nDoutOE, ALE0M, nDinLE,
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/* IO bus slave port interface */
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IOACT, IOBERR,
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IOREQ, IOL0, IOU0, IORW0);
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wire BERRTimeout, QoSReady;
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wire BERRTimeout;
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wire AoutOE;
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CNT cnt(
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/* C16M clock */
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C16M,
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/* FSB clock and bus active signal */
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FCLK, BACT,
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/* C8M clock */
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C8M,
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/* FSB bus active signals */
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BACT, LBACT,
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/* Refresh request */
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RefReq, RefUrgent,
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/* BERR and QoS speed limit output */
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BERRTimeout, QoSReady,
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BERRTimeout,
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/* Reset, switch, button */
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SW[3:1], nRESin, nRESout, nIPL2,
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/* Mac PDS bus master control outputs */
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nAoutOE, AoutOE, nBR_IOB,
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/* Configuration outputs */
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nBR_IOB, FastROMEN, C20MEN, C25MEN);
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FastROMEN, C20MEN, C25MEN);
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FSB fsb(
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/* MC68HC000 interface */
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CLK_FSB, nAS_FSB, nDTACK_FSB, nVPA_FSB, nBERR_FSB,
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/* AS cycle detection */
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BACT,
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BACT, LBACT,
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/* Ready and IA inputs */
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Ready_RAM, Ready_IOBS, (!SndRAMCSWR || QoSReady),
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/* BERR inputs */
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