2021-10-29 10:04:59 +00:00
|
|
|
Release 14.7 - xst P.20131013 (nt)
|
|
|
|
|
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
|
|
|
|
--> Parameter TMPDIR set to xst/projnav.tmp
|
|
|
|
|
|
|
|
|
|
|
2022-03-28 03:45:53 +00:00
|
|
|
Total REAL time to Xst completion: 1.00 secs
|
2022-09-04 01:32:05 +00:00
|
|
|
Total CPU time to Xst completion: 0.97 secs
|
2021-10-29 10:04:59 +00:00
|
|
|
|
|
|
|
|
--> Parameter xsthdpdir set to xst
|
|
|
|
|
|
|
|
|
|
|
2022-03-28 03:45:53 +00:00
|
|
|
Total REAL time to Xst completion: 1.00 secs
|
2022-09-04 01:32:05 +00:00
|
|
|
Total CPU time to Xst completion: 0.98 secs
|
2021-10-29 10:04:59 +00:00
|
|
|
|
2022-03-29 08:23:54 +00:00
|
|
|
--> Reading design: WarpSE.prj
|
2021-10-29 10:04:59 +00:00
|
|
|
|
|
|
|
|
TABLE OF CONTENTS
|
|
|
|
|
1) Synthesis Options Summary
|
|
|
|
|
2) HDL Compilation
|
|
|
|
|
3) Design Hierarchy Analysis
|
|
|
|
|
4) HDL Analysis
|
|
|
|
|
5) HDL Synthesis
|
|
|
|
|
5.1) HDL Synthesis Report
|
|
|
|
|
6) Advanced HDL Synthesis
|
|
|
|
|
6.1) Advanced HDL Synthesis Report
|
|
|
|
|
7) Low Level Synthesis
|
|
|
|
|
8) Partition Report
|
|
|
|
|
9) Final Report
|
|
|
|
|
|
|
|
|
|
=========================================================================
|
|
|
|
|
* Synthesis Options Summary *
|
|
|
|
|
=========================================================================
|
|
|
|
|
---- Source Parameters
|
2022-03-29 08:23:54 +00:00
|
|
|
Input File Name : "WarpSE.prj"
|
2021-10-29 10:04:59 +00:00
|
|
|
Input Format : mixed
|
|
|
|
|
Ignore Synthesis Constraint File : NO
|
|
|
|
|
|
|
|
|
|
---- Target Parameters
|
2022-03-29 08:23:54 +00:00
|
|
|
Output File Name : "WarpSE"
|
2021-10-29 10:04:59 +00:00
|
|
|
Output Format : NGC
|
|
|
|
|
Target Device : XC9500XL CPLDs
|
|
|
|
|
|
|
|
|
|
---- Source Options
|
2022-03-29 08:23:54 +00:00
|
|
|
Top Module Name : WarpSE
|
2021-10-29 10:04:59 +00:00
|
|
|
Automatic FSM Extraction : YES
|
|
|
|
|
FSM Encoding Algorithm : Auto
|
|
|
|
|
Safe Implementation : No
|
|
|
|
|
Mux Extraction : Yes
|
|
|
|
|
Resource Sharing : YES
|
|
|
|
|
|
|
|
|
|
---- Target Options
|
|
|
|
|
Add IO Buffers : YES
|
|
|
|
|
MACRO Preserve : YES
|
|
|
|
|
XOR Preserve : YES
|
|
|
|
|
Equivalent register Removal : YES
|
|
|
|
|
|
|
|
|
|
---- General Options
|
|
|
|
|
Optimization Goal : Speed
|
2022-03-29 08:23:54 +00:00
|
|
|
Optimization Effort : 2
|
|
|
|
|
Keep Hierarchy : No
|
2021-10-29 10:04:59 +00:00
|
|
|
Netlist Hierarchy : As_Optimized
|
|
|
|
|
RTL Output : Yes
|
|
|
|
|
Hierarchy Separator : /
|
|
|
|
|
Bus Delimiter : <>
|
|
|
|
|
Case Specifier : Maintain
|
|
|
|
|
Verilog 2001 : YES
|
|
|
|
|
|
|
|
|
|
---- Other Options
|
|
|
|
|
Clock Enable : YES
|
|
|
|
|
wysiwyg : NO
|
|
|
|
|
|
|
|
|
|
=========================================================================
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
=========================================================================
|
|
|
|
|
* HDL Compilation *
|
|
|
|
|
=========================================================================
|
|
|
|
|
Compiling verilog file "../RAM.v" in library work
|
2022-09-04 01:32:05 +00:00
|
|
|
ERROR:HDLCompilers:28 - "../RAM.v" line 63 'BACTr' has not been declared
|
|
|
|
|
ERROR:HDLCompilers:26 - "../RAM.v" line 69 unexpected token: ';'
|
|
|
|
|
ERROR:HDLCompilers:26 - "../RAM.v" line 75 unexpected token: 'begin'
|
|
|
|
|
ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting ';', found ')'
|
|
|
|
|
ERROR:HDLCompilers:26 - "../RAM.v" line 76 unexpected token: '<='
|
2021-10-29 10:04:59 +00:00
|
|
|
Module <RAM> compiled
|
2022-09-04 01:32:05 +00:00
|
|
|
ERROR:HDLCompilers:26 - "../RAM.v" line 76 expecting 'endmodule', found '0'
|
|
|
|
|
Compiling verilog file "../IOBS.v" in library work
|
2021-10-29 10:04:59 +00:00
|
|
|
Compiling verilog file "../IOBM.v" in library work
|
|
|
|
|
Module <IOBS> compiled
|
|
|
|
|
Compiling verilog file "../FSB.v" in library work
|
|
|
|
|
Module <IOBM> compiled
|
2022-09-04 01:32:05 +00:00
|
|
|
ERROR:HDLCompilers:28 - "../FSB.v" line 59 'BERR' has not been declared
|
2021-10-29 10:04:59 +00:00
|
|
|
Compiling verilog file "../CS.v" in library work
|
|
|
|
|
Module <FSB> compiled
|
|
|
|
|
Compiling verilog file "../CNT.v" in library work
|
|
|
|
|
Module <CS> compiled
|
2022-09-04 01:32:05 +00:00
|
|
|
ERROR:HDLCompilers:28 - "../CNT.v" line 29 'RefREQ' has not been declared
|
|
|
|
|
ERROR:HDLCompilers:28 - "../CNT.v" line 30 'RefREQ' has not been declared
|
|
|
|
|
ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting ';', found '='
|
2021-10-29 10:04:59 +00:00
|
|
|
Module <CNT> compiled
|
2022-09-04 01:32:05 +00:00
|
|
|
ERROR:HDLCompilers:26 - "../CNT.v" line 34 expecting 'endmodule', found '0'
|
|
|
|
|
Compiling verilog file "../WarpSE.v" in library work
|
2022-03-29 08:23:54 +00:00
|
|
|
Module <WarpSE> compiled
|
2022-09-04 01:32:05 +00:00
|
|
|
Analysis of file <"WarpSE.prj"> failed.
|
2021-10-29 10:04:59 +00:00
|
|
|
-->
|
|
|
|
|
|
2022-09-04 01:32:05 +00:00
|
|
|
Total memory usage is 190552 kilobytes
|
2021-10-29 10:04:59 +00:00
|
|
|
|
2022-09-04 01:32:05 +00:00
|
|
|
Number of errors : 11 ( 0 filtered)
|
|
|
|
|
Number of warnings : 0 ( 0 filtered)
|
2021-10-29 10:04:59 +00:00
|
|
|
Number of infos : 0 ( 0 filtered)
|
|
|
|
|
|
