Warp-SE/cpld/IOBS.v

141 lines
4.0 KiB
Coq
Raw Normal View History

2021-10-29 10:04:59 +00:00
module IOBS(
/* MC68HC000 interface */
input CLK, input nWE, input nAS, input nLDS, input nUDS,
/* AS cycle detection */
input BACT,
2023-03-30 15:50:05 +00:00
/* Select signals */
input IOCS, input IOPWCS, input ROMCS,
/* FSB cycle termination outputs */
output reg IONPReady, output IOPWReady, output reg nBERR_FSB,
2021-10-29 10:04:59 +00:00
/* Read data OE control */
output nDinOE,
/* IOB master controller interface */
output reg IORDREQ, output reg IOWRREQ,
input IOACT, input IODONEin, input IOBERR,
2021-10-29 10:04:59 +00:00
/* FIFO primary level control */
output reg ALE0, output reg IOL0, output reg IOU0,
2021-10-29 10:04:59 +00:00
/* FIFO secondary level control */
output reg ALE1);
/* IOACT input synchronization */
reg IOACTr = 0; always @(posedge CLK) IOACTr <= IOACT;
/* IODTACK input synchronization */
2023-04-07 06:33:04 +00:00
reg IODONEr; always @(posedge CLK) IODONEr <= IODONEin;
wire IODONE = IODONEr;
2021-10-29 10:04:59 +00:00
/* Read data OE control */
2023-03-30 15:50:05 +00:00
assign nDinOE = !(!nAS && IOCS && nWE && !ROMCS);
2021-10-29 10:04:59 +00:00
2023-03-30 15:50:05 +00:00
/* I/O transfer state
* TS0 - I/O bridge idle:
* asserts IOREQ
2023-04-01 08:46:47 +00:00
* transitions to TS3 when BACT && IOCS && !ALE1 && !Sent
2023-03-30 15:50:05 +00:00
* TS3 - starting I/O transfer:
latches LDS and UDS from FSB or FIFO secondary level
transitions immediately to TS2
* TS2 - waiting for IOBM to begin:
transitions to TS1 when IOACT true
* TS1 - waiting for IOBM to finish:
* transitions to TS1 when IOACT false */
reg [1:0] TS = 0;
2023-03-31 10:17:08 +00:00
reg Sent = 0;
2021-10-29 10:04:59 +00:00
/* FIFO secondary level control */
reg Load1; reg Clear1;
reg IORW1; reg IOL1; reg IOU1;
always @(posedge CLK) begin // ALE and R/W load control
2023-03-30 15:50:05 +00:00
// If write currently posting (TS!=0),
// I/O selected, and FIFO secondary level empty
if (BACT && IOCS && !ALE1 && !Sent && IOPWCS && TS!=0) begin
2023-03-30 15:50:05 +00:00
// Latch R/W now but latch address and LDS/UDS next cycle
2021-10-29 10:04:59 +00:00
IORW1 <= nWE;
Load1 <= 1;
2021-11-22 13:28:06 +00:00
end else Load1 <= 0;
end
always @(posedge CLK) begin // ALE clear control
2023-03-30 15:50:05 +00:00
// Make address latch transparent in cycle after TS3
// (i.e. first TS2 cycle that's not part of current write)
if (TS==3) Clear1 <= 1;
2021-11-22 13:28:06 +00:00
else Clear1 <= 0;
end
always @(posedge CLK) begin // LDS, UDS, ALE control
if (Load1) begin // Latch address, LDS, UDS when Load1 true
2023-04-01 08:46:47 +00:00
ALE1 <= 1;
IOL1 <= !nLDS;
IOU1 <= !nUDS;
2023-03-30 15:50:05 +00:00
end else if (Clear1) ALE1 <= 0;
2021-10-29 10:04:59 +00:00
end
/* FIFO primary level control */
2021-10-29 10:04:59 +00:00
always @(posedge CLK) begin
2023-03-30 15:50:05 +00:00
if (TS==0) begin
if (ALE1) begin // If FIFO secondary level occupied
// Request transfer from IOBM and latch R/W from FIFO
TS <= 3;
IORDREQ <= IORW1;
IOWRREQ <= !IORW1;
IOL0 <= IOL1;
IOU0 <= IOU1;
end else if (BACT && IOCS && !ALE1 && !Sent) begin // FSB request
2023-03-30 15:50:05 +00:00
// Request transfer from IOBM and latch R/W from FSB
TS <= 3;
IORDREQ <= nWE;
IOWRREQ <= !nWE;
IOL0 <= !nLDS;
IOU0 <= !nUDS;
2023-03-30 15:50:05 +00:00
end else begin // Otherwise stay in idle
TS <= 0;
IORDREQ <= 0;
IOWRREQ <= 0;
2021-10-29 10:04:59 +00:00
end
ALE0 <= 0;
2023-03-30 15:50:05 +00:00
end else if (TS==3) begin
TS <= 2; // Always go to TS2. Keep IORDREQ/IOWRREQ active
ALE0 <= 1; // Latch address (and data)
2023-03-30 15:50:05 +00:00
// Latch data strobes from FIFO or FSB as appropriate
2021-10-29 10:04:59 +00:00
if (ALE1) begin
IOL0 <= IOL1;
IOU0 <= IOU1;
end else begin
IOL0 <= !nLDS;
IOU0 <= !nUDS;
2021-10-29 10:04:59 +00:00
end
2023-03-30 15:50:05 +00:00
end else if (TS==2) begin
// Wait for IOACT then withdraw IOREQ and enter TS1
2021-10-29 10:04:59 +00:00
if (IOACTr) begin
2023-03-30 15:50:05 +00:00
TS <= 1;
IORDREQ <= 0;
IOWRREQ <= 0;
end else TS <= 2;
ALE0 <= 1; // Keep address latched
2023-03-30 15:50:05 +00:00
end else if (TS==1) begin
// Wait for IOACT low (transfer over) before going back to idle
if (!IOACTr) TS <= 0;
2023-03-31 10:14:53 +00:00
else TS <= 1;
IORDREQ <= 0;
IOWRREQ <= 0;
ALE0 <= 0; // Release addr latch since it's controlled by IOBM now
2021-10-29 10:04:59 +00:00
end
end
/* Sent control */
always @(posedge CLK) begin
if (!BACT) Sent <= 0;
else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1;
end
/* Nonposted and posted ready */
assign IOPWReady = !ALE1; // Posted write reaedy
always @(posedge CLK) begin // Nonposted read/write ready
if (!BACT) IONPReady <= 0;
else if (Sent && !IOPWCS && IODONE) IONPReady <= 1;
2021-10-29 10:04:59 +00:00
end
/* BERR control */
2021-10-29 10:04:59 +00:00
always @(posedge CLK) begin
if (!BACT) nBERR_FSB <= 1;
else if (Sent && IOBERR) nBERR_FSB <= 0;
2021-10-29 10:04:59 +00:00
end
endmodule