working on SDRAM

This commit is contained in:
Zane Kaminski 2022-04-05 18:00:27 -04:00
parent 80e8e3ebf6
commit 357eccab16
37 changed files with 7779 additions and 2801 deletions

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3747
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{ {
"board": { "board": {
"active_layer": 0, "active_layer": 31,
"active_layer_preset": "All Layers", "active_layer_preset": "All Layers",
"auto_track_width": true, "auto_track_width": true,
"hidden_nets": [], "hidden_nets": [],

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@ -487,7 +487,7 @@
], ],
[ [
"00000000-0000-0000-0000-000060941922", "00000000-0000-0000-0000-000060941922",
"Buf" "PDSBuf"
], ],
[ [
"00000000-0000-0000-0000-00005f72f108", "00000000-0000-0000-0000-00005f72f108",
@ -495,16 +495,12 @@
], ],
[ [
"00000000-0000-0000-0000-00005f723900", "00000000-0000-0000-0000-00005f723900",
"RAMROM" "RAM"
], ],
[ [
"00000000-0000-0000-0000-00005f723173", "00000000-0000-0000-0000-00005f723173",
"Control" "Control"
], ],
[
"00000000-0000-0000-0000-000061350d21",
"Clk.sch"
],
[ [
"00000000-0000-0000-0000-000061a87b62", "00000000-0000-0000-0000-000061a87b62",
"DIPSW" "DIPSW"
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[ [
"00000000-0000-0000-0000-000061aa52c4", "00000000-0000-0000-0000-000061aa52c4",
"Prog" "Prog"
],
[
"b5e3c22e-d373-459f-a3ce-4b8c26e51ce1",
"CPUBuf"
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], ],
"text_variables": {} "text_variables": {}

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13
cpld/CLK.v Normal file
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@ -0,0 +1,13 @@
module CLK(
input CLK, output reg [2:0] SS,
output reg MCLK, output RCLK);
always @(posedge CLK) begin
SS[1:0] <= SS[1:0]+1;
end
always @(posedge CLK) begin
MCLK <= SS[1:0]==2'b01 || SS[1:0]==2'b10;
end
endmodule

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@ -1,20 +1,13 @@
module CNT( module CNT(
/* FSB clock and AS detection */ /* FSB clock and AS detection */
input FCLK, input CACT, input FCLK, input CACT,
/* Refresh request */
output RefReq, output RefUrgent, input RefAck,
/* Timeout signals */ /* Timeout signals */
output reg TimeoutA, output reg TimeoutB); output reg TimeoutA, output reg TimeoutB);
/* Refresh counter */ /* Refresh counter */
reg [7:0] RefCnt = 0; reg [7:0] RefCnt = 0;
reg RefDone = 0;
assign RefReq = ~RefDone;
assign RefUrgent = RefCnt[7] && RefCnt[6] && RefCnt[5] && ~RefDone;
always @(posedge FCLK) begin always @(posedge FCLK) begin
RefCnt <= RefCnt+1; RefCnt <= RefCnt+1;
if (RefCnt==0) RefDone <= 0;
else if (RefAck) RefDone <= 1;
end end
/* Timeout signals */ /* Timeout signals */

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@ -39,7 +39,7 @@ module CS(
(A[15:12]==4'hC) || // 4096 bytes video (A[15:12]==4'hC) || // 4096 bytes video
(A[15:12]==4'hD) || // 4096 bytes video (A[15:12]==4'hD) || // 4096 bytes video
(A[15:12]==4'hE) || // 4096 bytes video (A[15:12]==4'hE) || // 4096 bytes video
(A[15:12]==4'hF)); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound (A[15:12]==4'hF)); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
assign SndRAMCSWR = VidRAMCSWR64k && ( assign SndRAMCSWR = VidRAMCSWR64k && (
(A[15:12]==4'hF && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) || (A[15:12]==4'hF && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
(A[15:12]==4'hA && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3))); (A[15:12]==4'hA && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
@ -49,18 +49,18 @@ module CS(
(A[23:20]==4'h0 && Overlay); (A[23:20]==4'h0 && Overlay);
/* Select signals - IOB domain */ /* Select signals - IOB domain */
assign IACS = A[23:08]==16'hFFFF; // IACK assign IACS = A[23:08]==16'hFFFF; // IACK
assign IOCS = (A[23:20]==4'h4 && MotherboardROMEN) || // Motherboard ROM assign IOCS = (A[23:20]==4'h4 && MotherboardROMEN) || // Motherboard ROM
A[23:20]==4'h5 || // SCSI A[23:20]==4'h5 || // SCSI
A[23:20]==4'h8 || // empty A[23:20]==4'h8 || // empty
A[23:20]==4'h9 || // SCC read/reset A[23:20]==4'h9 || // SCC read/reset
A[23:20]==4'hA || // empty A[23:20]==4'hA || // empty
A[23:20]==4'hB || // SCC write A[23:20]==4'hB || // SCC write
A[23:20]==4'hC || // empty A[23:20]==4'hC || // empty
A[23:20]==4'hD || // IWM A[23:20]==4'hD || // IWM
A[23:20]==4'hE || // VIA A[23:20]==4'hE || // VIA
A[23:20]==4'hF || // IACK A[23:20]==4'hF || // IACK
VidRAMCSWR; VidRAMCSWR;
assign SCSICS = A[23:20]==4'h5; // SCSI assign SCSICS = A[23:20]==4'h5; // SCSI
assign IOPWCS = RAMCS_OverlayOff && ~nWE; assign IOPWCS = RAMCS_OverlayOff && ~nWE;

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@ -1,39 +1,38 @@
module FSB( module FSB(
input CLK, input [1:0] SS,
/* MC68HC000 interface */ /* MC68HC000 interface */
input FCLK, input nAS, output reg nDTACK, output nVPA, output nBERR, input FCLK, input nAS, output reg nDTACK, output nVPA, output nBERR,
/* AS cycle detection */ /* AS cycle detection */
output BACT, output reg BACT,
/* Ready inputs */ /* Ready inputs */
input Ready0, input Ready1, input Ready2, input Disable, input Ready0, input Ready1, input Disable,
/* BERR inputs */ /* BERR inputs */
input BERR0, input BERR1, input BERR0, input BERR1,
/* Interrupt acknowledge select */ /* Interrupt acknowledge select */
input IACS); input IACS);
/* AS cycle detection */ /* AS cycle detection */
reg ASrf = 0; always @(posedge FCLK) begin
always @(negedge FCLK) begin ASrf <= ~nAS; end if (SS[1:0]==2'h1 && ~nAS) BACT <= 1;
assign BACT = ~nAS || ASrf; else if (SS[1:0]==2'h3 && nAS) BACT <= 0;
end
/* Ready and BERR "remember" */ /* Ready and BERR "remember" */
reg Ready0r, Ready1r, Ready2r; reg Ready0r, Ready1r;
reg BERR0r, BERR1r; reg BERR0r, BERR1r;
wire Ready = ~Disable && (Ready0 || Ready0r) && wire Ready = ~Disable && (Ready0 || Ready0r) &&
(Ready1 || Ready1r) && (Ready1 || Ready1r);
(Ready2 || Ready2r);
wire BERR = (BERR0 || BERR0r || BERR1 || BERR1r); wire BERR = (BERR0 || BERR0r || BERR1 || BERR1r);
assign nBERR = ~(~nAS && BERR); assign nBERR = ~(~nAS && BERR);
always @(posedge FCLK) begin always @(posedge FCLK) begin
if (~BACT) begin if (~BACT) begin
Ready0r <= 0; Ready0r <= 0;
Ready1r <= 0; Ready1r <= 0;
Ready2r <= 0;
BERR0r <= 0; BERR0r <= 0;
BERR1r <= 0; BERR1r <= 0;
end else begin end else begin
if (Ready0) Ready0r <= 1; if (Ready0) Ready0r <= 1;
if (Ready1) Ready1r <= 1; if (Ready1) Ready1r <= 1;
if (Ready2) Ready2r <= 1;
if (BERR0) BERR0r <= 1; if (BERR0) BERR0r <= 1;
if (BERR1) BERR1r <= 1; if (BERR1) BERR1r <= 1;
end end

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@ -1,150 +1,253 @@
module RAM( module RAM(
/* Fast clock and 25 MHz substate */
input CLK, input [1:0] SS,
/* MC68HC000 interface */ /* MC68HC000 interface */
input CLK, input [21:1] A, input nWE, input nAS, input nLDS, input nUDS, input [21:1] A, input nWE, input nAS, input nLDS, input nUDS,
/* AS cycle detection */
input BACT, input BACT,
/* Select and ready signals */ /* Select and ready signals */
input RAMCS, input ROMCS, output Ready, input RAMCS, input ROMCS,
/* Refresh Counter Interface */ /* SDRAM interface */
input RefReq, input RefUrgent, output RefAck, output reg CKE, output reg nCS,
/* DRAM and NOR flash interface */ output reg nRAS, output reg nCAS, output reg nRWE,
output [11:0] RA, output nRAS, output reg nCAS, output reg [1:0] BA, output reg [11:0] RA,
output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE); output reg DQMH, output reg DQML);
/* RAM control state */ /* RAM control state */
reg [2:0] RS = 0; reg [1:0] RS = 0;
reg Once = 0; reg Once1 = 0;
reg RAMReady = 0; reg Once3 = 0;
reg RASEL = 0; // RASEL controls /CAS signal
/* Refresh state */
reg RAMDIS1 = 0;
reg RAMDIS2 = 0;
wire RAMDIS = RAMDIS1 || RAMDIS2;
wire RAMEN = ~RAMDIS;
reg RefRAS = 0;
assign nROMCS = ~ROMCS;
assign nRAS = ~((~nAS && RAMCS && RAMEN && ~RefRAS /* does this add loading to these P-terms? */) || RefRAS);
assign nOE = ~(~nAS && nWE);
assign nLWE = ~(~nAS && ~nWE && ~nLDS && RAMEN);
assign nUWE = ~(~nAS && ~nWE && ~nUDS && RAMEN);
assign nROMWE = ~(~nAS && ~nWE);
assign RA[11] = A[19];
assign RA[10] = A[21];
assign RA[09] = RASEL ? A[20] : A[19];
assign RA[08] = (RASEL && RAMCS) ? A[09] : A[18];
assign RA[07] = RASEL ? A[08] : A[17];
assign RA[06] = RASEL ? A[07] : A[16];
assign RA[05] = RASEL ? A[06] : A[15];
assign RA[04] = RASEL ? A[05] : A[14];
assign RA[03] = RASEL ? A[04] : A[13];
assign RA[02] = RASEL ? A[03] : A[12];
assign RA[01] = RASEL ? A[02] : A[11];
assign RA[00] = RASEL ? A[01] : A[10];
always @(posedge CLK) begin always @(posedge CLK) begin
if (~BACT) Once <= 0; if (SS[1:0]==2'h3) case (RS[1:0])
else if (RS==0 && BACT && RAMCS) Once <= 1; 2'h0: RS <= 2'h1;
2'h1: RS <= ~nAS ? (Once3 ? 2'h3 : 2'h2) : 2'h1;
2'h2: RS <= 2'h3;
2'h3: RS <= 2'h0;
endcase
end end
always @(posedge CLK) begin always @(posedge CLK) begin
if (~BACT) RAMDIS2 <= 0; if (SS[1:0]==2'h1 && RS[1:0]==2'h1 && ~nAS && RAMCS) Once1 <= 1;
else if ((RS==0 && BACT && RefUrgent && Once && RAMCS) || else if (SS[1:0]==2'h3) begin
(RS==7 && BACT && RefUrgent && Once)) RAMDIS2 <= 1; if (nAS) begin
end Once1 <= 0;
reg BACTr; Once3 <= 0;
always @(posedge CLK) begin BACTr <= BACT; end end else Once3 <= Once1;
always @(posedge CLK) begin
if (RS==0) begin
if (( BACT && RefReq && ~RAMCS && ~BACTr) || // Non-urgent refresh can start during first clock of non-RAM cycle
(~BACT && RefUrgent) || // Urgent refresh can start during bus idle
( BACT && RefUrgent && ~RAMCS)) begin // Urgent refresh can start during non-ram cycle
RS <= 2;
RAMReady <= 0;
RASEL <= 1;
RAMDIS1 <= 1;
end else if (BACT && RAMCS && ~Once) begin
// RAM access cycle has priority over urgent refresh if RAM access already begun
RS <= 5;
RAMReady <= 0;
RASEL <= 1;
RAMDIS1 <= 0;
end else if (BACT && RAMCS && RefUrgent) begin
// Urgent refresh can start during prolonged RAM access cycle
// But we must insert one extra precharge state first.
RS <= 1;
RAMReady <= 0;
RASEL <= 0;
RAMDIS1 <= 1;
end else begin
// No RAM access/refresh requests pending
RS <= 0;
RAMReady <= 1;
RASEL <= 0;
RAMDIS1 <= 0;
end
RefRAS <= 0;
end else if (RS==1) begin
RS <= 2;
RAMReady <= 0;
RASEL <= 1;
RAMDIS1 <= 1;
RefRAS <= 0;
end else if (RS==2) begin
RS <= 3;
RAMReady <= 0;
RASEL <= 1;
RAMDIS1 <= 1;
RefRAS <= 1;
end else if (RS==3) begin
RS <= 4;
RAMReady <= 0;
RASEL <= 0;
RAMDIS1 <= 1;
RefRAS <= 1;
end else if (RS==4) begin
RS <= 7;
RAMReady <= 0;
RASEL <= 0;
RAMDIS1 <= 1;
RefRAS <= 0;
end else if (RS==5) begin
RS <= 6;
RAMReady <= 0;
RASEL <= 1;
RAMDIS1 <= 0;
RefRAS <= 0;
end else if (RS==6) begin
RS <= 7;
RAMReady <= 0;
RASEL <= 0;
RAMDIS1 <= 0;
RefRAS <= 0;
end else if (RS==7) begin
if (~BACT && RefUrgent) begin
RS <= 2;
RAMReady <= 0;
RAMDIS1 <= 1;
RASEL <= 1;
end else if (BACT && RefUrgent) begin
RS <= 1;
RAMReady <= 0;
RASEL <= 0;
RAMDIS1 <= 1;
end else begin
RS <= 0;
RAMReady <= 1;
RASEL <= 0;
RAMDIS1 <= 0;
end
RefRAS <= 0;
end end
end end
always @(negedge CLK) begin nCAS <= ~RASEL; end
assign RefAck = RefRAS; /* RAM control and address */
always @(posedge CLK) begin
assign Ready = ~RAMCS || RAMReady; case (RS[1:0])
2'h0: begin
// NOP CKD
CKE <= 1'b0;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end 2'h1: begin
case (SS[1:0])
2'h0: begin
if (RAMCS || ROMCS) begin
// NOP CKE
CKE <= 1'b1;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end else begin
// NOP CKD
CKE <= 1'b0;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end
RA[11:0] <= A[21:10];
end 2'h1: begin
if (~nAS && ~Once3 && (RAMCS || ROMCS)) begin
// ACT CKD
CKE <= 1'b0;
nCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end else begin
// NOP CKD
CKE <= 1'b0;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end
RA[11:0] <= A[21:10];
end 2'h2: begin
if (~nAS && ~Once3 && nWE && (RAMCS || ROMCS)) begin
// NOP CKE
CKE <= 1'b1;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end else begin
// NOP CKD
CKE <= 1'b0;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end
RA[10] <= 1'b1; // auto-precharge
RA[9] <= A[9]; // don't care
RA[8:0] <= A[9:1];
end 2'h3: begin
if (~nAS && ~Once3 && nWE && (RAMCS || ROMCS)) begin
// RD CKE
CKE <= 1'b1;
nCS <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b0;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end else begin
// NOP CKD
CKE <= 1'b0;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end
RA[10] <= 1'b1; // auto-precharge
RA[9] <= A[19]; // don't care
RA[8:0] <= A[9:1];
end
endcase
BA[1] <= 1'b0;
BA[0] <= RAMCS;
end 2'h2: begin
case (SS[1:0])
2'h0: begin
if (~nWE && RAMCS) begin
// NOP CKE
CKE <= 1'b1;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end else begin
// NOP CKD
CKE <= 1'b0;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end
end 2'h1: begin
if (~nWE && RAMCS) begin
// WR CKE
CKE <= 1'b1;
nCS <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b0;
nRWE <= 1'b0;
DQML <= nLDS;
DQMH <= nUDS;
end else begin
// NOP CKD
CKE <= 1'b0;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end
end 2'h2: begin
// NOP CKE
CKE <= 1'b1;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end 2'h3: begin
// PC CKD
CKE <= 1'b0;
nCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nRWE <= 1'b0;
DQML <= 1'b1;
DQMH <= 1'b1;
end
endcase
// BA[1:0] doesn't change
RA[10] <= 1'b1; // auto-precharge / "all"
RA[9] <= A[19]; // don't care
RA[8:0] <= A[9:1];
end 2'h3: begin
case (SS[1:0])
2'h0: begin
// NOP CKE
CKE <= 1'b1;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end 2'h1: begin
// AREF
CKE <= 1'b1;
nCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end 2'h2: begin
// NOP CKD
CKE <= 1'b0;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end 2'h3: begin
// NOP CKD
CKE <= 1'b0;
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
DQML <= 1'b1;
DQMH <= 1'b1;
end
endcase
end
endcase
end
endmodule endmodule

View File

@ -7,7 +7,9 @@ module WarpSE(
output nDTACK_FSB, output nDTACK_FSB,
output nVPA_FSB, output nVPA_FSB,
output nBERR_FSB, output nBERR_FSB,
input CLK_FSB, input CLK,
output MCLK,
output RCLK,
input CLK2X_IOB, input CLK2X_IOB,
input CLK_IOB, input CLK_IOB,
input E_IOB, input E_IOB,
@ -22,14 +24,15 @@ module WarpSE(
input nBERR_IOB, input nBERR_IOB,
input nRES, input nRES,
input nIPL2, input nIPL2,
output nROMCS, output CKE,
output nRAMLWE, output nCS,
output nRAMUWE,
output nROMWE,
output nRAS, output nRAS,
output nCAS, output nCAS,
output nRWE,
output [1:0] BA,
output [11:0] RA, output [11:0] RA,
output nOE, output DQMH,
output DQML,
output nADoutLE0, output nADoutLE0,
output nADoutLE1, output nADoutLE1,
output nAoutOE, output nAoutOE,
@ -48,8 +51,9 @@ module WarpSE(
/* AS cycle detection */ /* AS cycle detection */
wire BACT; wire BACT;
/* Refresh request/ack signals */ wire [1:0] SS;
wire RefReq, RefUrgent, RefAck; wire CLK_FSB = (~CLK && SS[1:0]==2'b01);
CLK clk(CLK, SS, MCLK, RCLK);
wire IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR; wire IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR;
CS cs( CS cs(
@ -62,19 +66,17 @@ module WarpSE(
/* Device select outputs */ /* Device select outputs */
IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR); IOCS, SCSICS, IOPWCS, IACS, ROMCS, RAMCS, SndRAMCSWR);
wire Ready_RAM;
RAM ram( RAM ram(
CLK, SS,
/* MC68HC000 interface */ /* MC68HC000 interface */
CLK_FSB, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB, A_FSB[21:1], nWE_FSB, nAS_FSB, nLDS_FSB, nUDS_FSB,
/* AS cycle detection */ /* AS cycle detection */
BACT, BACT,
/* Select and ready signals */ /* Select and ready signals */
RAMCS, ROMCS, Ready_RAM, RAMCS, ROMCS,
/* Refresh Counter Interface */ /* SDRAM interface */
RefReq, RefUrgent, RefAck, CKE, nCS, nRAS, nCAS, nRWE,
/* DRAM and NOR flash interface */ BA, RA, DQMH, DQML);
RA[11:0], nRAS, nCAS,
nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
wire Ready_IOBS, BERR_IOBS; wire Ready_IOBS, BERR_IOBS;
wire Park, IOREQ, IOACT, IOBERR; wire Park, IOREQ, IOACT, IOBERR;
@ -118,8 +120,6 @@ module WarpSE(
CNT cnt( CNT cnt(
/* FSB clock and AS detection */ /* FSB clock and AS detection */
CLK_FSB, BACT, CLK_FSB, BACT,
/* Refresh request */
RefReq, RefUrgent, RefAck,
/* Timeout signals */ /* Timeout signals */
TimeoutA, TimeoutB); TimeoutA, TimeoutB);
@ -140,12 +140,13 @@ module WarpSE(
end end
FSB fsb( FSB fsb(
CLK, SS,
/* MC68HC000 interface */ /* MC68HC000 interface */
CLK_FSB, nAS_FSB, nDTACK_FSB, nVPA_FSB, nBERR_FSB, CLK_FSB, nAS_FSB, nDTACK_FSB, nVPA_FSB, nBERR_FSB,
/* AS cycle detection */ /* AS cycle detection */
BACT, BACT,
/* Ready and IA inputs */ /* Ready and IA inputs */
Ready_RAM, Ready_IOBS, ~(SndRAMCSWR && ~TimeoutA), Disable, Ready_IOBS, ~(SndRAMCSWR && ~TimeoutA), Disable,
/* BERR inputs */ /* BERR inputs */
(~SCSICS && TimeoutB), BERR_IOBS, (~SCSICS && TimeoutB), BERR_IOBS,
/* Interrupt acknowledge select */ /* Interrupt acknowledge select */

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@ -22,3 +22,9 @@ cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt verilog -optimize speed -htmlr
XSLTProcess WarpSE_build.xml XSLTProcess WarpSE_build.xml
tsim -intstyle ise WarpSE WarpSE.nga tsim -intstyle ise WarpSE WarpSE.nga
taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"
xst -intstyle ise -ifn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "Z:/Warp-SE/cpld/XC95144XL/WarpSE.syr"

View File

@ -70,15 +70,15 @@
</files> </files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1648475056" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1648475056"> <transform xil_pn:end_ts="1648922635" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1648922635">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1648475056" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8819683973431472423" xil_pn:start_ts="1648475056"> <transform xil_pn:end_ts="1648922635" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8819683973431472423" xil_pn:start_ts="1648922635">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1648475110" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1233756204182495024" xil_pn:start_ts="1648475056"> <transform xil_pn:end_ts="1648923415" xil_pn:in_ck="-642168595227983762" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="1233756204182495024" xil_pn:start_ts="1648923377">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
@ -102,37 +102,30 @@
<transform xil_pn:end_ts="1648475141" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1648475110"> <transform xil_pn:end_ts="1648475141" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1648475110">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="WarpSE.bld"/> <status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="WarpSE.ngd"/>
<outfile xil_pn:name="WarpSE_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1648475214" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="6759205406869966736" xil_pn:start_ts="1648475141"> <transform xil_pn:end_ts="1648475214" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="6759205406869966736" xil_pn:start_ts="1648475141">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="WarpSE.gyd"/> <status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="WarpSE.mfd"/>
<outfile xil_pn:name="WarpSE.nga"/>
<outfile xil_pn:name="WarpSE.pad"/>
<outfile xil_pn:name="WarpSE.pnx"/>
<outfile xil_pn:name="WarpSE.rpt"/>
<outfile xil_pn:name="WarpSE.tim"/>
<outfile xil_pn:name="WarpSE.tspec"/>
<outfile xil_pn:name="WarpSE.vm6"/>
<outfile xil_pn:name="WarpSE.xml"/>
<outfile xil_pn:name="WarpSE_build.xml"/>
<outfile xil_pn:name="WarpSE_html"/>
<outfile xil_pn:name="WarpSE_pad.csv"/>
</transform> </transform>
<transform xil_pn:end_ts="1648475243" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="2785262643" xil_pn:start_ts="1648475214"> <transform xil_pn:end_ts="1648475243" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="2785262643" xil_pn:start_ts="1648475214">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputRemoved"/>
</transform> </transform>
</transforms> </transforms>

File diff suppressed because one or more lines are too long

File diff suppressed because one or more lines are too long

View File

@ -4,4 +4,5 @@ verilog work "../IOBM.v"
verilog work "../FSB.v" verilog work "../FSB.v"
verilog work "../CS.v" verilog work "../CS.v"
verilog work "../CNT.v" verilog work "../CNT.v"
verilog work "../CLK.v"
verilog work "../WarpSE.v" verilog work "../WarpSE.v"

View File

@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 1.00 secs Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.84 secs Total CPU time to Xst completion: 0.80 secs
--> Parameter xsthdpdir set to xst --> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.87 secs Total CPU time to Xst completion: 0.84 secs
--> Reading design: WarpSE.prj --> Reading design: WarpSE.prj
@ -86,8 +86,10 @@ Compiling verilog file "../CS.v" in library work
Module <FSB> compiled Module <FSB> compiled
Compiling verilog file "../CNT.v" in library work Compiling verilog file "../CNT.v" in library work
Module <CS> compiled Module <CS> compiled
Compiling verilog file "../WarpSE.v" in library work Compiling verilog file "../CLK.v" in library work
Module <CNT> compiled Module <CNT> compiled
Compiling verilog file "../WarpSE.v" in library work
Module <CLK> compiled
Module <WarpSE> compiled Module <WarpSE> compiled
No errors in compilation No errors in compilation
Analysis of file <"WarpSE.prj"> succeeded. Analysis of file <"WarpSE.prj"> succeeded.
@ -98,6 +100,8 @@ Analysis of file <"WarpSE.prj"> succeeded.
========================================================================= =========================================================================
Analyzing hierarchy for module <WarpSE> in library <work>. Analyzing hierarchy for module <WarpSE> in library <work>.
Analyzing hierarchy for module <CLK> in library <work>.
Analyzing hierarchy for module <CS> in library <work>. Analyzing hierarchy for module <CS> in library <work>.
Analyzing hierarchy for module <RAM> in library <work>. Analyzing hierarchy for module <RAM> in library <work>.
@ -117,6 +121,9 @@ Analyzing hierarchy for module <FSB> in library <work>.
Analyzing top module <WarpSE>. Analyzing top module <WarpSE>.
Module <WarpSE> is correct for synthesis. Module <WarpSE> is correct for synthesis.
Analyzing module <CLK> in library <work>.
Module <CLK> is correct for synthesis.
Analyzing module <CS> in library <work>. Analyzing module <CS> in library <work>.
Module <CS> is correct for synthesis. Module <CS> is correct for synthesis.
@ -141,6 +148,20 @@ Module <FSB> is correct for synthesis.
========================================================================= =========================================================================
Performing bidirectional port resolution... Performing bidirectional port resolution...
INFO:Xst:2679 - Register <BA<1>> in unit <RAM> has a constant value of 0 during circuit operation. The register is replaced by logic.
Synthesizing Unit <CLK>.
Related source file is "../CLK.v".
WARNING:Xst:1305 - Output <RCLK> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <SS<2>> is never assigned. Tied to value 0.
Found 2-bit register for signal <SS<1:0>>.
Found 1-bit register for signal <MCLK>.
Found 2-bit adder for signal <$add0000> created at line 6.
Summary:
inferred 3 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
Unit <CLK> synthesized.
Synthesizing Unit <CS>. Synthesizing Unit <CS>.
Related source file is "../CS.v". Related source file is "../CS.v".
@ -153,28 +174,33 @@ Unit <CS> synthesized.
Synthesizing Unit <RAM>. Synthesizing Unit <RAM>.
Related source file is "../RAM.v". Related source file is "../RAM.v".
WARNING:Xst:647 - Input <BACT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found finite state machine <FSM_0> for signal <RS>. Found finite state machine <FSM_0> for signal <RS>.
----------------------------------------------------------------------- -----------------------------------------------------------------------
| States | 8 | | States | 4 |
| Transitions | 18 | | Transitions | 6 |
| Inputs | 6 | | Inputs | 2 |
| Outputs | 9 | | Outputs | 4 |
| Clock | CLK (rising_edge) | | Clock | CLK (rising_edge) |
| Power Up State | 000 | | Clock enable | RS$cmp_eq0000 (positive) |
| Power Up State | 00 |
| Encoding | automatic | | Encoding | automatic |
| Implementation | automatic | | Implementation | automatic |
----------------------------------------------------------------------- -----------------------------------------------------------------------
Found 1-bit register for signal <BA<0>>.
Found 1-bit register for signal <nRAS>.
Found 1-bit register for signal <nCS>.
Found 1-bit register for signal <nCAS>. Found 1-bit register for signal <nCAS>.
Found 1-bit register for signal <BACTr>. Found 12-bit register for signal <RA>.
Found 1-bit register for signal <Once>. Found 1-bit register for signal <nRWE>.
Found 1-bit register for signal <RAMDIS1>. Found 1-bit register for signal <DQMH>.
Found 1-bit register for signal <RAMDIS2>. Found 1-bit register for signal <DQML>.
Found 1-bit register for signal <RAMReady>. Found 1-bit register for signal <CKE>.
Found 1-bit register for signal <RASEL>. Found 1-bit register for signal <Once1>.
Found 1-bit register for signal <RefRAS>. Found 1-bit register for signal <Once3>.
Summary: Summary:
inferred 1 Finite State Machine(s). inferred 1 Finite State Machine(s).
inferred 6 D-type flip-flop(s). inferred 21 D-type flip-flop(s).
Unit <RAM> synthesized. Unit <RAM> synthesized.
@ -262,7 +288,6 @@ Synthesizing Unit <CNT>.
Found 1-bit register for signal <TimeoutA>. Found 1-bit register for signal <TimeoutA>.
Found 1-bit register for signal <TimeoutB>. Found 1-bit register for signal <TimeoutB>.
Found 8-bit up counter for signal <RefCnt>. Found 8-bit up counter for signal <RefCnt>.
Found 1-bit register for signal <RefDone>.
Found 1-bit register for signal <TimeoutBPre>. Found 1-bit register for signal <TimeoutBPre>.
Summary: Summary:
inferred 1 Counter(s). inferred 1 Counter(s).
@ -271,13 +296,13 @@ Unit <CNT> synthesized.
Synthesizing Unit <FSB>. Synthesizing Unit <FSB>.
Related source file is "../FSB.v". Related source file is "../FSB.v".
WARNING:Xst:647 - Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <nDTACK>. Found 1-bit register for signal <nDTACK>.
Found 1-bit register for signal <ASrf>. Found 1-bit register for signal <BACT>.
Found 1-bit register for signal <BERR0r>. Found 1-bit register for signal <BERR0r>.
Found 1-bit register for signal <BERR1r>. Found 1-bit register for signal <BERR1r>.
Found 1-bit register for signal <Ready0r>. Found 1-bit register for signal <Ready0r>.
Found 1-bit register for signal <Ready1r>. Found 1-bit register for signal <Ready1r>.
Found 1-bit register for signal <Ready2r>.
Found 1-bit register for signal <VPA>. Found 1-bit register for signal <VPA>.
Summary: Summary:
inferred 1 D-type flip-flop(s). inferred 1 D-type flip-flop(s).
@ -308,11 +333,13 @@ Unit <WarpSE> synthesized.
HDL Synthesis Report HDL Synthesis Report
Macro Statistics Macro Statistics
# Adders/Subtractors : 1
2-bit adder : 1
# Counters : 2 # Counters : 2
5-bit up counter : 1 5-bit up counter : 1
8-bit up counter : 1 8-bit up counter : 1
# Registers : 68 # Registers : 83
1-bit register : 68 1-bit register : 83
# Tristates : 4 # Tristates : 4
1-bit tristate buffer : 4 1-bit tristate buffer : 4
@ -347,18 +374,14 @@ Optimizing FSM <iobs/PS/FSM> on signal <PS[1:2]> with johnson encoding.
01 | 10 01 | 10
------------------- -------------------
Analyzing FSM <FSM_0> for best encoding. Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <ram/RS/FSM> on signal <RS[1:3]> with compact encoding. Optimizing FSM <ram/RS/FSM> on signal <RS[1:2]> with compact encoding.
------------------- -------------------
State | Encoding State | Encoding
------------------- -------------------
000 | 000 00 | 10
010 | 010 01 | 00
101 | 001 11 | 11
001 | 101 10 | 01
011 | 011
100 | 111
111 | 100
110 | 110
------------------- -------------------
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone. WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block RESDone.
You should achieve better results by setting this init to 1. You should achieve better results by setting this init to 1.
@ -370,11 +393,13 @@ Advanced HDL Synthesis Report
Macro Statistics Macro Statistics
# FSMs : 3 # FSMs : 3
# Adders/Subtractors : 1
2-bit adder : 1
# Counters : 2 # Counters : 2
5-bit up counter : 1 5-bit up counter : 1
8-bit up counter : 1 8-bit up counter : 1
# Registers : 47 # Registers : 65
Flip-Flops : 47 Flip-Flops : 65
========================================================================= =========================================================================
@ -394,27 +419,23 @@ Optimizing unit <WarpSE> ...
implementation constraint: INIT=r : IPL2r1 implementation constraint: INIT=r : IPL2r1
implementation constraint: INIT=r : Disable implementation constraint: INIT=r : Disable
implementation constraint: INIT=r : RESDone implementation constraint: INIT=r : RESDone
implementation constraint: INIT=r : ram/RAMReady implementation constraint: INIT=r : ram/Once3
implementation constraint: INIT=r : ram/RASEL implementation constraint: INIT=r : ram/Once1
implementation constraint: INIT=r : ram/RAMDIS1 implementation constraint: INIT=r : iobs/PS_FSM_FFd1
implementation constraint: INIT=r : ram/RefRAS
implementation constraint: INIT=r : ram/RAMDIS2
implementation constraint: INIT=r : ram/Once
implementation constraint: INIT=r : iobs/IOACTr implementation constraint: INIT=r : iobs/IOACTr
implementation constraint: INIT=r : ram/RS_FSM_FFd1
implementation constraint: INIT=r : iobs/Once implementation constraint: INIT=r : iobs/Once
implementation constraint: INIT=r : cs/nOverlay0 implementation constraint: INIT=r : cs/nOverlay0
implementation constraint: INIT=r : cs/nOverlay1 implementation constraint: INIT=r : cs/nOverlay1
implementation constraint: INIT=r : iobs/PS_FSM_FFd1 implementation constraint: INIT=r : iobm/IOREQr
implementation constraint: INIT=r : iobs/PS_FSM_FFd2 implementation constraint: INIT=r : iobs/PS_FSM_FFd2
implementation constraint: INIT=r : iobm/IOS_FSM_FFd2
implementation constraint: INIT=r : iobm/IOS_FSM_FFd3
implementation constraint: INIT=r : iobm/ETACK implementation constraint: INIT=r : iobm/ETACK
implementation constraint: INIT=r : iobm/BGr0 implementation constraint: INIT=r : iobm/BGr0
implementation constraint: INIT=r : iobm/BGr1 implementation constraint: INIT=r : iobm/BGr1
implementation constraint: INIT=r : iobm/BG implementation constraint: INIT=r : iobm/BG
implementation constraint: INIT=r : iobm/IOREQr implementation constraint: INIT=s : ram/RS_FSM_FFd1
implementation constraint: INIT=r : fsb/ASrf
implementation constraint: INIT=r : ram/RS_FSM_FFd2 implementation constraint: INIT=r : ram/RS_FSM_FFd2
implementation constraint: INIT=r : cnt/RefDone
implementation constraint: INIT=r : cnt/RefCnt_0 implementation constraint: INIT=r : cnt/RefCnt_0
implementation constraint: INIT=r : cnt/RefCnt_1 implementation constraint: INIT=r : cnt/RefCnt_1
implementation constraint: INIT=r : cnt/RefCnt_2 implementation constraint: INIT=r : cnt/RefCnt_2
@ -423,10 +444,7 @@ Optimizing unit <WarpSE> ...
implementation constraint: INIT=r : cnt/RefCnt_5 implementation constraint: INIT=r : cnt/RefCnt_5
implementation constraint: INIT=r : cnt/RefCnt_6 implementation constraint: INIT=r : cnt/RefCnt_6
implementation constraint: INIT=r : cnt/RefCnt_7 implementation constraint: INIT=r : cnt/RefCnt_7
implementation constraint: INIT=r : ram/RS_FSM_FFd3
implementation constraint: INIT=r : iobm/IOS_FSM_FFd1 implementation constraint: INIT=r : iobm/IOS_FSM_FFd1
implementation constraint: INIT=r : iobm/IOS_FSM_FFd2
implementation constraint: INIT=r : iobm/IOS_FSM_FFd3
========================================================================= =========================================================================
* Partition Report * * Partition Report *
@ -455,44 +473,44 @@ Clock Enable : YES
wysiwyg : NO wysiwyg : NO
Design Statistics Design Statistics
# IOs : 75 # IOs : 79
Cell Usage : Cell Usage :
# BELS : 596 # BELS : 631
# AND2 : 165 # AND2 : 180
# AND3 : 25 # AND3 : 29
# AND4 : 15 # AND4 : 13
# AND5 : 3 # AND5 : 1
# AND6 : 1 # AND6 : 1
# AND7 : 1 # AND7 : 1
# AND8 : 3 # AND8 : 3
# GND : 1 # GND : 1
# INV : 265 # INV : 266
# OR2 : 98 # OR2 : 109
# OR3 : 5 # OR3 : 9
# OR4 : 1 # OR4 : 3
# VCC : 1 # VCC : 1
# XOR2 : 12 # XOR2 : 14
# FlipFlops/Latches : 89 # FlipFlops/Latches : 103
# FD : 60 # FD : 72
# FDCE : 29 # FDCE : 31
# Tri-States : 1 # Tri-States : 1
# BUFE : 1 # BUFE : 1
# IO Buffers : 74 # IO Buffers : 78
# IBUF : 39 # IBUF : 39
# OBUF : 31 # OBUF : 35
# OBUFE : 4 # OBUFE : 4
========================================================================= =========================================================================
Total REAL time to Xst completion: 39.00 secs Total REAL time to Xst completion: 23.00 secs
Total CPU time to Xst completion: 38.76 secs Total CPU time to Xst completion: 22.87 secs
--> -->
Total memory usage is 236884 kilobytes Total memory usage is 205652 kilobytes
Number of errors : 0 ( 0 filtered) Number of errors : 0 ( 0 filtered)
Number of warnings : 5 ( 0 filtered) Number of warnings : 10 ( 0 filtered)
Number of infos : 0 ( 0 filtered) Number of infos : 1 ( 0 filtered)

View File

@ -41,11 +41,15 @@
</file> </file>
<file xil_pn:name="../WarpSE.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../WarpSE.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file> </file>
<file xil_pn:name="../WarpSE-XC95144XL.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="../WarpSE-XC95144XL.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../CLK.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
</files> </files>
<properties> <properties>

View File

@ -2,12 +2,12 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status (03/28/2022 - 09:47:24)</B></TD></TR> <TD ALIGN=CENTER COLSPAN='4'><B>WarpSE Project Status</B></TD></TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>WarpSE.xise</TD> <TD>WarpSE.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD> <TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='Z:/Warp-SE/cpld/XC95144XL\_xmsgs/pn_parser.xmsgs?&DataKey=Error'>4 Errors</A></TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
@ -77,5 +77,5 @@ System Settings</A>
</TABLE> </TABLE>
<br><center><b>Date Generated:</b> 03/28/2022 - 09:47:24</center> <br><center><b>Date Generated:</b> 04/02/2022 - 12:52:13</center>
</BODY></HTML> </BODY></HTML>

View File

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Mon Mar 28 09:44:30 2022"> <application stringID="Xst" timeStamp="Sat Apr 02 14:16:30 2022">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
@ -79,9 +79,10 @@
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/> <item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
</section> </section>
<section stringID="XST_HDL_SYNTHESIS_REPORT"> <section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
<item dataType="int" stringID="XST_COUNTERS" value="2"></item> <item dataType="int" stringID="XST_COUNTERS" value="2"></item>
<item dataType="int" stringID="XST_REGISTERS" value="68"> <item dataType="int" stringID="XST_REGISTERS" value="83">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="68"/> <item dataType="int" stringID="XST_1BIT_REGISTER" value="83"/>
</item> </item>
<item dataType="int" stringID="XST_TRISTATES" value="4"> <item dataType="int" stringID="XST_TRISTATES" value="4">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="4"/> <item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="4"/>
@ -89,9 +90,10 @@
</section> </section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT"> <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_FSMS" value="3"/> <item dataType="int" stringID="XST_FSMS" value="3"/>
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
<item dataType="int" stringID="XST_COUNTERS" value="2"></item> <item dataType="int" stringID="XST_COUNTERS" value="2"></item>
<item dataType="int" stringID="XST_REGISTERS" value="47"> <item dataType="int" stringID="XST_REGISTERS" value="65">
<item dataType="int" stringID="XST_FLIPFLOPS" value="47"/> <item dataType="int" stringID="XST_FLIPFLOPS" value="65"/>
</item> </item>
</section> </section>
<section stringID="XST_PARTITION_REPORT"> <section stringID="XST_PARTITION_REPORT">
@ -108,34 +110,34 @@
<item stringID="XST_KEEP_HIERARCHY" value="No"/> <item stringID="XST_KEEP_HIERARCHY" value="No"/>
</section> </section>
<section stringID="XST_DESIGN_STATISTICS"> <section stringID="XST_DESIGN_STATISTICS">
<item stringID="XST_IOS" value="75"/> <item stringID="XST_IOS" value="79"/>
</section> </section>
<section stringID="XST_CELL_USAGE"> <section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="596"> <item dataType="int" stringID="XST_BELS" value="631">
<item dataType="int" stringID="XST_AND2" value="165"/> <item dataType="int" stringID="XST_AND2" value="180"/>
<item dataType="int" stringID="XST_AND3" value="25"/> <item dataType="int" stringID="XST_AND3" value="29"/>
<item dataType="int" stringID="XST_AND4" value="15"/> <item dataType="int" stringID="XST_AND4" value="13"/>
<item dataType="int" stringID="XST_GND" value="1"/> <item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="265"/> <item dataType="int" stringID="XST_INV" value="266"/>
<item dataType="int" stringID="XST_OR2" value="98"/> <item dataType="int" stringID="XST_OR2" value="109"/>
<item dataType="int" stringID="XST_VCC" value="1"/> <item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XOR2" value="12"/> <item dataType="int" stringID="XST_XOR2" value="14"/>
</item> </item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="89"> <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="103">
<item dataType="int" stringID="XST_FD" value="60"/> <item dataType="int" stringID="XST_FD" value="72"/>
<item dataType="int" stringID="XST_FDCE" value="29"/> <item dataType="int" stringID="XST_FDCE" value="31"/>
</item> </item>
<item dataType="int" stringID="XST_TRISTATES" value="1"></item> <item dataType="int" stringID="XST_TRISTATES" value="1"></item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="74"> <item dataType="int" stringID="XST_IO_BUFFERS" value="78">
<item dataType="int" stringID="XST_IBUF" value="39"/> <item dataType="int" stringID="XST_IBUF" value="39"/>
<item dataType="int" stringID="XST_OBUF" value="31"/> <item dataType="int" stringID="XST_OBUF" value="35"/>
</item> </item>
</section> </section>
</section> </section>
<section stringID="XST_ERRORS_STATISTICS"> <section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="5"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="10"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="1"/>
</section> </section>
</application> </application>

View File

@ -8,24 +8,6 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/CNT.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/CS.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/FSB.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/IOBM.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/IOBS.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/RAM.v&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/WarpSE.v&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Warp-SE/cpld/WarpSE.v&quot; into library work</arg>
</msg> </msg>

View File

@ -5,22 +5,40 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">SW&lt;2&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. <msg type="warning" file="HDLCompilers" num="261" delta="new" ><arg fmt="%s" index="1">&quot;../WarpSE.v&quot; line 56 </arg>Connection to output port &apos;<arg fmt="%s" index="2">SS</arg>&apos; does not match port size
</msg> </msg>
<msg type="warning" file="Xst" num="1426" delta="old" >The value init of the FF/Latch <arg fmt="%s" index="1">0</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">RESDone</arg>. <msg type="info" file="Xst" num="2679" delta="new" >Register &lt;<arg fmt="%s" index="1">BA&lt;1&gt;</arg>&gt; in unit &lt;<arg fmt="%s" index="2">RAM</arg>&gt; has a constant value of <arg fmt="%s" index="3">0</arg> during circuit operation. The register is replaced by logic.
</msg>
<msg type="warning" file="Xst" num="1305" delta="new" >Output &lt;<arg fmt="%s" index="1">RCLK</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
<msg type="warning" file="Xst" num="1305" delta="new" >Output &lt;<arg fmt="%s" index="1">SS&lt;2&gt;</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">BACT</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLK</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">SW&lt;2&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="1426" delta="new" >The value init of the FF/Latch <arg fmt="%s" index="1">0</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">RESDone</arg>.
You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>. You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.
</msg> </msg>
<msg type="warning" file="Xst" num="1426" delta="old" >The value init of the FF/Latch <arg fmt="%s" index="1">0</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">Disable</arg>. <msg type="warning" file="Xst" num="1426" delta="new" >The value init of the FF/Latch <arg fmt="%s" index="1">0</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">Disable</arg>.
You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>. You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.
</msg> </msg>
<msg type="warning" file="Xst" num="1426" delta="old" >The value init of the FF/Latch <arg fmt="%s" index="1">RESDone</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">WarpSE</arg>. <msg type="warning" file="Xst" num="1426" delta="new" >The value init of the FF/Latch <arg fmt="%s" index="1">RESDone</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">WarpSE</arg>.
You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>. You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.
</msg> </msg>
<msg type="warning" file="Xst" num="1426" delta="old" >The value init of the FF/Latch <arg fmt="%s" index="1">Disable</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">WarpSE</arg>. <msg type="warning" file="Xst" num="1426" delta="new" >The value init of the FF/Latch <arg fmt="%s" index="1">Disable</arg> hinder the constant cleaning in the block <arg fmt="%s" index="2">WarpSE</arg>.
You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>. You should achieve better results by setting this init to <arg fmt="%i" index="3">1</arg>.
</msg> </msg>

View File

@ -21,17 +21,16 @@
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes> <ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion> <ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Implement Design/Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode> <ClosedNode>User Constraints</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem>Generate Timing</SelectedItem> <SelectedItem>Synthesize - XST</SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >7</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >4</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000012b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012b0000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000012b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012b0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Timing</CurrentItem> <CurrentItem>Synthesize - XST</CurrentItem>
</ItemView> </ItemView>
<ItemView guiview="File" > <ItemView guiview="File" >
<ClosedNodes> <ClosedNodes>

View File

@ -1,7 +1,7 @@
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2022-03-28T09:36:17</DateModified> <DateModified>2022-04-02T12:52:13</DateModified>
<ModuleName>WarpSE</ModuleName> <ModuleName>WarpSE</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp> <SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>Z:/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath> <SavedFilePath>Z:/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>

View File

@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Mon Mar 28 09:44:18 2022"> <application name="pn" timeStamp="Sat Apr 02 14:16:19 2022">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="8B3C87EB1A1F4FD6BCA39339C89EC1EE" type="project"/> <property name="ProjectID" value="8B3C87EB1A1F4FD6BCA39339C89EC1EE" type="project"/>
<property name="ProjectIteration" value="0" type="project"/> <property name="ProjectIteration" value="0" type="project"/>
@ -41,7 +41,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_DevSpeed" value="-10" type="design"/> <property name="PROP_DevSpeed" value="-10" type="design"/>
<property name="PROP_PreferredLanguage" value="Verilog" type="design"/> <property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
<property name="FILE_UCF" value="1" type="source"/> <property name="FILE_UCF" value="1" type="source"/>
<property name="FILE_VERILOG" value="7" type="source"/> <property name="FILE_VERILOG" value="8" type="source"/>
</section> </section>
</application> </application>
</document> </document>

View File

@ -1,8 +1,9 @@
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1648475072 MO CLK NULL ../CLK.v vlg52/_c_l_k.bin 1648923392
MO CS NULL ../CS.v vlg22/_c_s.bin 1648475072 MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1648923392
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1648475072 MO CS NULL ../CS.v vlg22/_c_s.bin 1648923392
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1648475072 MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1648923391
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1648475072 MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1648923391
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1648475072 MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1648923392
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1648475071 MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1648923391
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1648923391
MO MXSE NULL ../MXSE.v vlg15/_m_x_s_e.bin 1648473402 MO MXSE NULL ../MXSE.v vlg15/_m_x_s_e.bin 1648473402

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