Fixed
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22c3dd55ac
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443a159063
70
cpld/RAM.v
70
cpld/RAM.v
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@ -10,17 +10,16 @@ module RAM(
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input RefReqIn, input RefUrgIn,
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input RefReqIn, input RefUrgIn,
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/* DRAM and NOR flash interface */
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/* DRAM and NOR flash interface */
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output [11:0] RA, output nRAS, output reg nCAS,
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output [11:0] RA, output nRAS, output reg nCAS,
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output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE);
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output nLWE, output nUWE, output reg nOE, output nROMCS, output nROMWE);
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/* BACT and /DTACK registration */
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/* BACT and /DTACK registration */
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reg BACTr; always @(posedge CLK) BACTr <= BACT;
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reg BACTr; always @(posedge CLK) BACTr <= BACT;
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reg DTACKr; always @(posedge CLK) DTACKr <= !nDTACK;
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reg DTACKr; always @(posedge CLK) DTACKr <= !nDTACK;
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/* RAM control state */
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/* RAM control state */
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reg [3:0] RS = 0;
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reg [2:0] RS = 0;
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reg RASEN = 0;
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reg RASEN = 0;
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reg RASEL = 0;
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reg RASEL = 0;
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reg CAS = 0;
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reg RASrr = 0;
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reg RASrr = 0;
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reg RASrf = 0;
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reg RASrf = 0;
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@ -28,21 +27,21 @@ module RAM(
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reg RefDone; // Refresh done "remember"
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reg RefDone; // Refresh done "remember"
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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if (!RefReqIn && !RefUrgIn) RefDone <= 0;
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if (!RefReqIn && !RefUrgIn) RefDone <= 0;
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else if (RS[3]) RefDone <= 1;
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else if (RS[2]) RefDone <= 1;
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end
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end
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wire RefReq = RefReqIn && !RefDone;
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wire RefReq = RefReqIn && !RefDone;
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wire RefUrg = RefUrgIn && !RefDone;
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wire RefUrg = RefUrgIn && !RefDone;
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/* RAM control signals */
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/* RAM control signals */
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assign nRAS = !((!nAS && RAMCS && RASEN) || RASrr || RASrf);
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assign nRAS = !((!nAS && RAMCS && RASEN) || RASrr || RASrf);
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assign nLWE = !(!nLDS && !nWE && RASEL);
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assign nLWE = !(!nLDS && !nWE && RASEL);
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assign nUWE = !(!nUDS && !nWE && RASEL);
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assign nUWE = !(!nUDS && !nWE && RASEL);
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/* ROM control signals */
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/* ROM control signals */
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assign nROMCS = !ROMCS;
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assign nROMCS = !ROMCS;
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assign nROMWE = !(!nAS && !nWE);
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assign nROMWE = !(!nAS && !nWE);
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/* Shared /OE control */
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/* Shared ROM and RAM /OE control */
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always @(posedge CLK) nOE <= !(BACT && !nWE && !(BACTr && DTACKr));
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always @(posedge CLK) nOE <= !(BACT && !nWE && !(BACTr && DTACKr));
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/* RAM address mux (and ROM address on RA8) */
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/* RAM address mux (and ROM address on RA8) */
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@ -61,15 +60,17 @@ module RAM(
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assign RA[04] = !RASEL ? A[11] : A[03];
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assign RA[04] = !RASEL ? A[11] : A[03];
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assign RA[01] = !RASEL ? A[10] : A[02];
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assign RA[01] = !RASEL ? A[10] : A[02];
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assign RA[00] = !RASEL ? A[09] : A[01];
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assign RA[00] = !RASEL ? A[09] : A[01];
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always @(posedge CLK) begin
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wire RS0toRef = (RefReq && BACT && !BACTr && !RAMCS0X) ||
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case (RS[3:0])
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0: begin // Idle/ready
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if ((RefReq && BACT && !BACTr && !RAMCS0X) ||
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(RefUrg && !RASEN) ||
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(RefUrg && !RASEN) ||
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(RefUrg && BACT && !RAMCS0X) ||
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(RefUrg && BACT && !RAMCS0X) ||
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(RefUrg && !BACT)) begin // Go to refresh
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(RefUrg && !BACT);
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RS <= 8;
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always @(posedge CLK) begin
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case (RS[2:0])
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0: begin // Idle/ready
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if (RS0toRef) begin // Go to refresh
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RS <= 4;
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RASEL <= 0;
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RASEL <= 0;
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RASrr <= 0;
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RASrr <= 0;
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RASEN <= 0;
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RASEN <= 0;
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@ -117,52 +118,49 @@ module RAM(
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end else begin // Cycle ended so go abck to idle/ready
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end else begin // Cycle ended so go abck to idle/ready
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RS <= 0;
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RS <= 0;
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RASEL <= 0;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASrr <= 0;
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RASEN <= 1;
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RASEN <= 1;
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RAMReady <= 1;
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RAMReady <= 1;
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end
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end
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end 4: begin // Refresh RAS I
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end 8: begin // Refresh CAS
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end 9: begin // Refresh RAS I
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RS <= 5;
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RS <= 5;
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RASEL <= 0;
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RASEL <= 0;
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RASrr <= 1;
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RASrr <= 1;
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RASEN <= 0;
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RASEN <= 0;
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RAMReady <= 0;
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RAMReady <= 0;
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end 10: begin // Refresh RAS II
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end 5: begin // Refresh RAS II
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RS <= 6;
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RS <= 6;
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RASEL <= 0;
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RASEL <= 0;
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RASrr <= 1;
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RASrr <= 1;
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RASEN <= 0;
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RASEN <= 0;
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RAMReady <= 0;
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RAMReady <= 0;
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end 11: begin // Refresh precharge I
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end 6: begin // Refresh precharge I / II
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RS <= 6;
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if (RASrr) begin
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RASEL <= 0;
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RS <= 6;
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RASrr <= 0;
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RASEL <= 0;
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RASEN <= 0;
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RASrr <= 0;
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RAMReady <= 0;
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RASEN <= 0;
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end 12: begin // Refresh precharge II
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RAMReady <= 0;
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RS <= 15;
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end else begin
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RASEL <= 0;
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RS <= 7;
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RASrr <= 0;
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RASEL <= 0;
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RASEN <= 0;
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RASrr <= 0;
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RAMReady <= 0;
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RASEN <= 0;
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end 15: begin // Reenable RAM and go to idle/ready
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RAMReady <= 0;
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end
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end 7: begin // Reenable RAM and go to idle/ready
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RS <= 0;
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RS <= 0;
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RASEL <= 0;
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RASEL <= 0;
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RASrr <= 0;
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RASrr <= 0;
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RASEN <= 1;
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RASEN <= 1;
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RAMReady <= 1;
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RAMReady <= 1;
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end default: begin
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end
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end
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endcase
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endcase
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end
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end
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always @(negedge CLK) begin
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always @(negedge CLK) begin
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RASrf <= RS==1;
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RASrf <= RS==1;
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case (RS[2:0])
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case (RS[2:0])
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0: nCAS <= 1;
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0: nCAS <= !RS0toRef;
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1: nCAS <= 0;
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1: nCAS <= 0;
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2: nCAS <= DTACKr;
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2: nCAS <= DTACKr;
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3: nCAS <= !RefUrg;
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3: nCAS <= !RefUrg;
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