parent
335232eae2
commit
83656e587a
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@ -120,6 +120,12 @@ module RAM(
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RAMReady <= 1;
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RAMReady <= 1;
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end
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end
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end 4: begin // Refresh RAS II
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end 4: begin // Refresh RAS II
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RS <= 5;
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RASEL <= 0;
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RASrr <= 1;
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RASEN <= 0;
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RAMReady <= 0;
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end 5: begin // Refresh precharge I
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RS <= 6;
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RS <= 6;
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RASEL <= 0;
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RASEL <= 0;
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RASrr <= 0;
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RASrr <= 0;
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@ -141,7 +147,7 @@ module RAM(
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endcase
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endcase
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end
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end
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always @(negedge CLK) begin
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always @(negedge CLK) begin
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RASrf <= RS==1 || RS==4;
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RASrf <= RS==1;
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case (RS[2:0])
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case (RS[2:0])
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0: nCAS <= !RS0toRef;
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0: nCAS <= !RS0toRef;
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1: nCAS <= 0;
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1: nCAS <= 0;
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