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Zane Kaminski
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@ -29,54 +29,26 @@
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</head>
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<body onload="WaveDrom.ProcessAll()">
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<h1>Garrett's Workshop Warp-SE 20/25 MHz 68HC000 Accelerator Documentation</h1>
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<h2>System Block Diagram</h2>
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<img src="CPLD.png" style="width:1000px;" />
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<h2>Relevant Timing Parameters</h2>
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<p>Some relevant timing parameters to which the bus timings were designed are as follows:</p>
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<table>
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<tr><th>Parameter</th><th>Value</th><th>Description</th></tr>
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<tr><td>tPD_CPLD</td> <td>10ns</td> <td>asynchronous propagation delay</td></tr>
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<tr><td>tCO_CPLD</td> <td>6ns</td> <td>clock-to-output delay</td></tr>
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<tr><td>tSU_CPLD</td> <td>6ns</td> <td>global clock setup time</td></tr>
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<tr><td>tRAS_DRAM</td> <td>60ns</td> <td>RAS pulse width / access time</td></tr>
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<tr><td>tASR_DRAM</td> <td>0ns</td> <td>row address setup time before RAS</td></tr>
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<tr><td>tRAH_DRAM</td> <td>10ns</td> <td>row address hold time after RAS</td></tr>
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<tr><td>tRCD_DRAM</td> <td>20ns</td> <td>minimum RAS-to-CAS delay</td></tr>
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<tr><td>tASC_DRAM</td> <td>0ns</td> <td>column address setup time before CAS</td></tr>
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<tr><td>tCAH_DRAM</td> <td>10ns</td> <td>column address hold time after CAS</td></tr>
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<tr><td>tCAS_DRAM</td> <td>20ns</td> <td>CAS pulse width / access time</td></tr>
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<tr><td>tRP_DRAM</td> <td>40ns</td> <td>RAS precharge time</td></tr>
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<tr><td>tCP_DRAM</td> <td>10ns</td> <td>CAS precharge time</td></tr>
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<tr><td>tRC_DRAM</td> <td>120ns</td> <td>minimum RAS cycle time</td></tr>
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<tr><td>tACC_ROM</td> <td>70ns</td> <td>ROM access time</td></tr>
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<tr><td>tOE_ROM</td> <td>40ns</td> <td>ROM OE access time</td></tr>
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<tr><td>tPD_573</td> <td>20ns</td> <td>74AHCT573 propagation delay after LE or D</td></tr>
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<tr><td>tSU_573</td> <td>5ns</td> <td>74AHCT573 setup time before LE</td></tr>
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<tr><td>tH_573</td> <td>2ns</td> <td>74AHCT573 hold time after LE</td></tr>
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</table>
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<h1>Garrett's Workshop WarpSE 25 MHz 68HC000 Accelerator Documentation</h1>
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<h2>Timing Diagrams</h2><p>
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Below I am presenting some timing diagrams showing the relevant signals for various interesting bus cycle cases. <br/>
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We are beginning with the timing of the accelerated processor bus, or the front-side bus (FSB), and proceeding on to the timing of the master port on the Mac SE bus, or the I/O Bus (IOB). <br/>
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The timing diagrams are scaled for a 25 MHz FSB clock frequency and the standard 7.8336 MHz Mac SE bus.
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</p>
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<h3 id="t0">0. Generic MC68000 bus cycle detection</h3>
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<script type="WaveDrom">{signal: [
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{name: 'FCLK', wave: 'p.....', phase: 0.00, period: 2},
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{name: 'A', wave: 'x2..x.', phase: 0.25, period: 2},
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{name: 'R/W', wave: 'x..1....x...', phase: 0.25, period: 1},
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{name: '/AS', wave: '1...x0........x1....x2.', phase:-0.25, period: 0.5},
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{name: '/DS (RD)', wave: '1...x0........x1....x..', phase:-0.25, period: 0.5},
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{name: '/DS (WR)', wave: '1.......x0....x1....x..', phase:-0.25, period: 0.5},
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{name: '/AS', wave: '1...x0........x1....x..', phase:-0.25, period: 0.5},
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{name: '/ASrf', wave: '1...x.....0.......1...x', phase:-0.25, period: 0.5},
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{name: 'BACT', wave: '0...x.1...........0.x.2', phase:-0.25, period: 0.5},
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{name: 'FCLK', wave: 'p.......................', phase: 0.00, period: 1},
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{name: 'CS', wave: '222222222222222222222222', phase: 0.00, period: 1,
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data:[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]},
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{name: 'MCLK', wave: 'p.....', phase: 0.00, period: 4},
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{name: 'A', wave: 'x2..x.', phase: 0.25, period: 4},
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{name: 'R/W', wave: 'x..1....x...', phase: 0.25, period: 2},
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{name: '/AS', wave: '1...x0........x1....x2.', phase:-0.25, period: 1},
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{name: '/DS (RD)', wave: '1...x0........x1....x..', phase:-0.25, period: 1},
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{name: '/DS (WR)', wave: '1.......x0....x1....x..', phase:-0.25, period: 1},
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{name: 'RCMD (RD)',wave: '222222222222222222222222', phase: 0.00, period: 1,
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data:['NOP','NOP','NOP','NOP','NOP','NOP','NOP','ACT','NOP','RD','NOP','NOP','NOP','PC','NOP','REF','NOP','NOP','NOP','NOP','NOP']},
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{name: 'RCMD (WR)',wave: '222222222222222222222222', phase: 0.00, period: 1,
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data:['NOP','NOP','NOP','NOP','NOP','NOP','NOP','ACT','NOP','NOP','NOP','WR','NOP','PC','NOP','REF','NOP','NOP','NOP','NOP','NOP']},
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]}
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</script><br/><p>
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For starters, it is instructive to look at a generic MC68000 bus cycle. <br/>
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@ -836,3 +808,50 @@ document.querySelectorAll('script[type=wavedrom]').forEach(function(dgm) {
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</body>
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</html>
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', period: 2, data:[0,3,2,2,2,2,1,1,0,3,2,2,2,1,1,0], phase:-0.3},
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{name: 'IOACT', wave: '0....|1.|0....|1.|0.', phase:-0.3, period: 2},
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{name: 'IOREQ', wave: '01...|..|.....|.0|..', phase:-0.3, period: 2},
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{name: 'ALE1', wave: '1...0|..|....1|..|..', phase:-0.3, period: 2},
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{name: 'IORW1', wave: '2..0.|..|.....|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU1', wave: '2...2|..|.....|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'ALE0', wave: '1.0..|.1|...0.|.1|..', phase:-0.3, period: 2},
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{name: 'IORW0', wave: '20...|..|..0..|..|..', phase:-0.3, period: 2, data:['R/W', 'R/W']},
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{name: 'IOLU0', wave: '2.2..|..|...2.|..|..', phase:-0.3, period: 2, data:['LDS, UDS', 'LDS, UDS']},
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{name: 'IOWRReady', wave: '1...0|..|....1|..|..', phase:-0.3, period: 2},
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]}
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</script><p>
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Similar to the previous case (again). This is the closest write timing allowed, even faster than MC68k can do.
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</p>
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<script type="text/javascript">
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document.querySelectorAll('script[type=wavedrom]').forEach(function(dgm) {
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var dj;
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eval('dj = ' + dgm.text + ';');
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var lines = {};
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var table = {};
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dj.signal.forEach(function(line) {
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lines[line.name] = '';
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for (var symbol = 0; symbol < line.wave.length; symbol++) {
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for (var reps = 0; reps < line.period / 0.5; reps++) {
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if (line.wave.charAt(symbol) === '.' ||
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line.wave.charAt(symbol) === '|') {
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var previndex = lines[line.name].charAt.length-1;
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if (previndex <= 0) {
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lines[line.name] += '1';
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} else {
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lines[line.name] += lines[line.name].charAt(previndex);
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}
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} else {
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lines[line.name] += line.wave.charAt(symbol);
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}
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}
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}
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//alert(lines[line.name]);
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});
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});
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</script>
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</body>
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</html>
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