This commit is contained in:
Zane Kaminski
2023-04-01 08:20:08 -04:00
2 changed files with 2 additions and 3 deletions

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@@ -19,7 +19,7 @@ module CS(
/* Select signals - FSB domain */ /* Select signals - FSB domain */
assign RAMCS = 0;//(A[23:22]==2'b00) && !Overlay; // 000000-3FFFFF when overlay disabled assign RAMCS = 0;//(A[23:22]==2'b00) && !Overlay; // 000000-3FFFFF when overlay disabled
wire VidRAMCSWR64k = RAMCS && (A[21:20]==2'h3) && (A[19:16]==4'hF) && ~nWE; // 3F0000-3FFFFF / 7F0000-7FFFFF wire VidRAMCSWR64k = RAMCS && !nWE && (A[21:20]==2'h3) && (A[19:16]==4'hF); // 3F0000-3FFFFF / 7F0000-7FFFFF
wire VidRAMCSWR = VidRAMCSWR64k && ( wire VidRAMCSWR = VidRAMCSWR64k && (
(A[15:12]==4'h2) || // 1792 bytes RAM, 2304 bytes video (A[15:12]==4'h2) || // 1792 bytes RAM, 2304 bytes video
(A[15:12]==4'h3) || // 4096 bytes video (A[15:12]==4'h3) || // 4096 bytes video

View File

@@ -57,8 +57,7 @@ module RAM(
else if (!BACT) RAMEN <= 1; else if (!BACT) RAMEN <= 1;
end else if (RS==7) begin end else if (RS==7) begin
if (RefFromRS7) RAMEN <= 0; if (RefFromRS7) RAMEN <= 0;
else if (BACT) RAMEN <= 0; else RAMEN <= 1;
else if (!BACT) RAMEN <= 1;
end end
end end