Works well again with speculative RAM refresh
This commit is contained in:
parent
f6ac67ba30
commit
d4e0008854
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@ -36,18 +36,19 @@ module CNT(
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* | 6 0110 | 1 | 0 |
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* | 6 0110 | 1 | 0 |
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* | 7 0111 | 1 | 0 |
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* | 7 0111 | 1 | 0 |
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* | 8 1000 | 1 | 0 |
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* | 8 1000 | 1 | 0 |
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* | 9 1001 | 1 | 0 |
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* | 9 1001 | 1 | 1 |
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* | 10 1010 | 1 | 1 |
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* | 10 1010 | 1 | 1 |
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* back to timer==0
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* back to timer==0
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*/
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*/
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reg [3:0] Timer = 0;
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reg [3:0] Timer = 0;
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wire TimerTC = RefUrg;
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reg TimerTC;
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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if (EFall) begin
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if (EFall) begin
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if (TimerTC) Timer <= 0;
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if (TimerTC) Timer <= 0;
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else Timer <= Timer+1;
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else Timer <= Timer+1;
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RefUrg <= Timer==9;
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RefUrg <= Timer==8 || Timer==9;
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RefReq <= !(Timer==10);
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RefReq <= Timer!=10;
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TimerTC <= Timer==9;
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end
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end
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end
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end
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137
cpld/RAM.v
137
cpld/RAM.v
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@ -4,20 +4,16 @@ module RAM(
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/* AS cycle detection */
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/* AS cycle detection */
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input BACT,
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input BACT,
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/* Select and ready signals */
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/* Select and ready signals */
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input RAMCS, input ROMCS, output reg RAMReady,
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input RAMCS, input RAMCS0X, input ROMCS, output reg RAMReady,
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/* Refresh Counter Interface */
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/* Refresh Counter Interface */
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input RefReqIn, input RefUrgIn,
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input RefReqIn, input RefUrgIn,
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/* DRAM and NOR flash interface */
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/* DRAM and NOR flash interface */
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output [11:0] RA, output nRAS, output reg nCAS,
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output [11:0] RA, output nRAS, output reg nCAS,
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output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE);
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output nLWE, output nUWE, output nOE, output nROMCS, output nROMWE);
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/* BACT saved from last cycle */
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reg BACTr; always @(posedge CLK) BACTr <= BACT;
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/* RAM control state */
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/* RAM control state */
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reg [2:0] RS = 0;
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reg [3:0] RS = 0;
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reg RAMEN = 0;
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reg RASEN = 0;
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reg Once = 0;
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reg RASEL = 0;
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reg RASEL = 0;
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reg CAS = 0;
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reg CAS = 0;
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reg RASrr = 0;
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reg RASrr = 0;
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@ -27,16 +23,16 @@ module RAM(
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reg RefDone; // Refresh done "remember"
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reg RefDone; // Refresh done "remember"
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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if (!RefReqIn && !RefUrgIn) RefDone <= 0;
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if (!RefReqIn && !RefUrgIn) RefDone <= 0;
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else if (RS==4 || RS==5) RefDone <= 1;
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else if (RS[3]) RefDone <= 1;
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end
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end
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wire RefReq = RefReqIn && !RefDone;
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wire RefReq = RefReqIn && !RefDone;
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wire RefUrg = RefUrgIn && !RefDone;
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wire RefUrg = RefUrgIn && !RefDone;
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/* RAM control signals */
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/* RAM control signals */
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assign nRAS = !((!nAS && RAMCS && RAMEN) || RASrr || RASrf);
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assign nRAS = !((!nAS && RAMCS && RASEN) || RASrr || RASrf);
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assign nOE = !((!nAS && nWE)); // Shared with ROM
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assign nOE = !(!nAS && nWE); // Shared with ROM
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assign nLWE = !((!nAS && !nWE && !nLDS && RAMEN));
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assign nLWE = !(!nLDS && !nWE && RASEL);
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assign nUWE = !((!nAS && !nWE && !nUDS && RAMEN));
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assign nUWE = !(!nUDS && !nWE && RASEL);
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/* ROM control signals */
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/* ROM control signals */
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assign nROMCS = !ROMCS;
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assign nROMCS = !ROMCS;
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@ -58,95 +54,120 @@ module RAM(
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assign RA[04] = !RASEL ? A[11] : A[03];
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assign RA[04] = !RASEL ? A[11] : A[03];
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assign RA[01] = !RASEL ? A[10] : A[02];
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assign RA[01] = !RASEL ? A[10] : A[02];
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assign RA[00] = !RASEL ? A[09] : A[01];
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assign RA[00] = !RASEL ? A[09] : A[01];
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wire RefFromRS0 = ((RefReq && !BACT) ||
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reg BACTr; always @(posedge CLK) BACTr <= BACT;
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(RefUrg && !BACT));
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wire RefFromRS2 = RefUrg;
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wire RAMStart = BACT && RAMCS && RAMEN;
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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case (RS[2:0])
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case (RS[3:0])
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0: begin
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0: begin
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if (RAMStart) begin
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if (( BACT && !BACTr && !RAMCS0X && RefReq) ||
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(!BACT && RefUrg) ||
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( BACT && RefUrg && !RAMCS0X) ||
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(!RASEN)) begin
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RS <= 8;
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RASEL <= 0;
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CAS <= 1;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 0;
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end else if (BACT && RAMCS && RASEN) begin
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RS <= 1;
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RS <= 1;
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RASEL <= 1;
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RASEL <= 1;
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CAS <= 1;
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CAS <= 1;
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RASrr <= 1;
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RASrr <= 1;
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end else if (RefFromRS0) begin
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RASEN <= 1;
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RS <= 3;
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RAMReady <= 1;
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RASEL <= 0;
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CAS <= 1;
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RASrr <= 0;
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end else begin
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end else begin
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RS <= 0;
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RS <= 0;
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RASEL <= 0;
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RASEL <= 0;
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CAS <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASrr <= 0;
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RASEN <= 1;
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RAMReady <= 1;
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end
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end
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end 1: begin
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end 1: begin
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RS <= 2;
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RS <= 2;
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RASEL <= 1;
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RASEL <= 1;
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CAS <= 1;
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CAS <= 1;
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RASrr <= 0;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 1;
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end 2: begin
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end 2: begin
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if (RefFromRS2) begin
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RS <= 3;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 1;
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end 3: begin
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if (BACT) begin
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RS <= 3;
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RS <= 3;
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RASEL <= 0;
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RASEL <= 0;
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CAS <= 1;
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RASrr <= 0;
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end else begin
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RS <= 7;
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RASEL <= 0;
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CAS <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 1;
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end else if (RefUrg) begin
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RS <= 8;
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RASEL <= 0;
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CAS <= 1;
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RASrr <= 0;
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RASEN <= 0;
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RAMReady <= 0;
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end else begin
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RS <= 0;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASEN <= 1;
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RAMReady <= 1;
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end
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end
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end 3: begin
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end 8: begin
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RS <= 4;
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RS <= 9;
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RASEL <= 0;
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RASEL <= 0;
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CAS <= 1;
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CAS <= 1;
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RASrr <= 1;
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RASrr <= 1;
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end 4: begin
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RASEN <= 0;
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RS <= 5;
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RAMReady <= 0;
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end 9: begin
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RS <= 10;
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RASEL <= 0;
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RASEL <= 0;
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CAS <= 0;
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CAS <= 0;
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RASrr <= 1;
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RASrr <= 1;
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end 5: begin
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RASEN <= 0;
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RS <= 6;
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RAMReady <= 0;
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end 10: begin
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RS <= 11;
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RASEL <= 0;
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RASEL <= 0;
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CAS <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASrr <= 0;
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end 6: begin
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RASEN <= 0;
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RS <= 7;
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RAMReady <= 0;
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end 11: begin
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RS <= 15;
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RASEL <= 0;
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RASEL <= 0;
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CAS <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASrr <= 0;
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end 7: begin
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RASEN <= 0;
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RAMReady <= 0;
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end 15: begin
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RS <= 0;
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RS <= 0;
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RASEL <= 0;
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RASEL <= 0;
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CAS <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASrr <= 0;
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RASEN <= 1;
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RAMReady <= 1;
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end default: begin
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RS <= 0;
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RASEL <= 0;
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CAS <= 0;
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RASrr <= 0;
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RASEN <= 1;
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RAMReady <= 1;
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end
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end
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endcase
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endcase
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end
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end
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always @(negedge CLK) RASrf <= RS==1;
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always @(negedge CLK) RASrf <= RS==1;
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always @(negedge CLK) nCAS <= !CAS;
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always @(negedge CLK) nCAS <= !CAS;
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/* RAM state control */
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always @(posedge CLK) begin
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if (RS==0 && RefFromRS0) RAMEN <= 0;
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else if (RS==1) RAMEN <= 0;
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else if (!BACT && RS==7) RAMEN <= 1;
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else if (!BACT && RS==0) RAMEN <= 1;
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else if (!Once && RS==7) RAMEN <= 1;
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else if (!Once && RS==0) RAMEN <= 1; // not needed?
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end
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always @(posedge CLK) begin
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if (!BACT) Once <= 0;
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else if (RS==0 && RAMStart) Once <= 1;
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end
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/* RAM ready signal */
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always @(posedge CLK) begin
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RAMReady <= (BACT && RAMReady) || (RS==7) || (RS==0 && !RefFromRS0);
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end
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endmodule
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endmodule
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@ -75,9 +75,9 @@ module WarpSE(
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/* AS cycle detection */
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/* AS cycle detection */
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BACT,
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BACT,
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/* Select and ready signals */
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/* Select and ready signals */
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RAMCS, ROMCS, RAMReady,
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RAMCS, RAMCS0X, ROMCS, RAMReady,
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/* Refresh Counter Interface */
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/* Refresh Counter Interface */
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RefReq, RefUrg,
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RefReq, RefUrg,
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/* DRAM and NOR flash interface */
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/* DRAM and NOR flash interface */
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RA[11:0], nRAS, nCAS,
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RA[11:0], nRAS, nCAS,
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nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
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nRAMLWE, nRAMUWE, nOE, nROMCS, nROMWE);
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@ -30,7 +30,7 @@ NGDBUILD Design Results Summary:
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Number of errors: 0
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Number of errors: 0
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Number of warnings: 0
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Number of warnings: 0
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Total memory usage is 154596 kilobytes
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Total memory usage is 155620 kilobytes
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Writing NGD file "WarpSE.ngd" ...
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Writing NGD file "WarpSE.ngd" ...
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Total REAL time to NGDBUILD completion: 3 sec
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Total REAL time to NGDBUILD completion: 3 sec
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@ -666,3 +666,244 @@ cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -
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tsim -intstyle ise WarpSE WarpSE.nga
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tsim -intstyle ise WarpSE WarpSE.nga
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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taengine -intstyle ise -f WarpSE -l WarpSE.tim -e {C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\taengine.err}
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taengine -intstyle ise -f WarpSE -l WarpSE.tim -e {C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\taengine.err}
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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tsim -intstyle ise WarpSE WarpSE.nga
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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tsim -intstyle ise WarpSE WarpSE.nga
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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tsim -intstyle ise WarpSE WarpSE.nga
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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||||||
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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tsim -intstyle ise WarpSE WarpSE.nga
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||||||
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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||||||
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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tsim -intstyle ise WarpSE WarpSE.nga
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||||||
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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||||||
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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tsim -intstyle ise WarpSE WarpSE.nga
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||||||
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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||||||
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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||||||
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
|
||||||
|
ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
|
||||||
|
cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
|
||||||
|
tsim -intstyle ise WarpSE WarpSE.nga
|
||||||
|
hprep6 -s IEEE1149 -n WarpSE -i WarpSE
|
||||||
|
taengine -intstyle ise -f WarpSE -l WarpSE.tim -e {C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\taengine.err}
|
||||||
|
|
|
@ -139,16 +139,6 @@ CELL_FALL(scalar) {
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
|
||||||
A_FSB<10>_RA<1>_delay:
|
|
||||||
CELL_RISE(scalar) {
|
|
||||||
VALUES("10");
|
|
||||||
}
|
|
||||||
CELL_FALL(scalar) {
|
|
||||||
VALUES("10");
|
|
||||||
}
|
|
||||||
ENDARCDATA
|
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<2>_RA<1>_delay:
|
A_FSB<2>_RA<1>_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
|
@ -160,7 +150,7 @@ CELL_FALL(scalar) {
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<16>_RA<2>_delay:
|
A_FSB<10>_RA<1>_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("10");
|
||||||
}
|
}
|
||||||
|
@ -180,7 +170,7 @@ CELL_FALL(scalar) {
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<19>_RA<3>_delay:
|
A_FSB<16>_RA<2>_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("10");
|
||||||
}
|
}
|
||||||
|
@ -199,6 +189,16 @@ CELL_FALL(scalar) {
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
|
ARCDATA
|
||||||
|
A_FSB<19>_RA<3>_delay:
|
||||||
|
CELL_RISE(scalar) {
|
||||||
|
VALUES("10");
|
||||||
|
}
|
||||||
|
CELL_FALL(scalar) {
|
||||||
|
VALUES("10");
|
||||||
|
}
|
||||||
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<11>_RA<4>_delay:
|
A_FSB<11>_RA<4>_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
|
@ -222,20 +222,20 @@ ENDARCDATA
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<12>_RA<5>_delay:
|
A_FSB<12>_RA<5>_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
CELL_FALL(scalar) {
|
CELL_FALL(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<4>_RA<5>_delay:
|
A_FSB<4>_RA<5>_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
CELL_FALL(scalar) {
|
CELL_FALL(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
|
@ -260,7 +260,7 @@ CELL_FALL(scalar) {
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<6>_RA<7>_delay:
|
A_FSB<14>_RA<7>_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("10");
|
||||||
}
|
}
|
||||||
|
@ -270,7 +270,7 @@ CELL_FALL(scalar) {
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<14>_RA<7>_delay:
|
A_FSB<6>_RA<7>_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("10");
|
||||||
}
|
}
|
||||||
|
@ -319,16 +319,6 @@ CELL_FALL(scalar) {
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
|
||||||
A_FSB<23>_nDinOE_delay:
|
|
||||||
CELL_RISE(scalar) {
|
|
||||||
VALUES("10");
|
|
||||||
}
|
|
||||||
CELL_FALL(scalar) {
|
|
||||||
VALUES("10");
|
|
||||||
}
|
|
||||||
ENDARCDATA
|
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nAS_FSB_nDinOE_delay:
|
nAS_FSB_nDinOE_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
|
@ -339,26 +329,6 @@ CELL_FALL(scalar) {
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
|
||||||
A_FSB<20>_nDinOE_delay:
|
|
||||||
CELL_RISE(scalar) {
|
|
||||||
VALUES("10");
|
|
||||||
}
|
|
||||||
CELL_FALL(scalar) {
|
|
||||||
VALUES("10");
|
|
||||||
}
|
|
||||||
ENDARCDATA
|
|
||||||
|
|
||||||
ARCDATA
|
|
||||||
A_FSB<22>_nDinOE_delay:
|
|
||||||
CELL_RISE(scalar) {
|
|
||||||
VALUES("10");
|
|
||||||
}
|
|
||||||
CELL_FALL(scalar) {
|
|
||||||
VALUES("10");
|
|
||||||
}
|
|
||||||
ENDARCDATA
|
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nWE_FSB_nDinOE_delay:
|
nWE_FSB_nDinOE_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
|
@ -369,6 +339,16 @@ CELL_FALL(scalar) {
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
|
ARCDATA
|
||||||
|
A_FSB<20>_nDinOE_delay:
|
||||||
|
CELL_RISE(scalar) {
|
||||||
|
VALUES("10");
|
||||||
|
}
|
||||||
|
CELL_FALL(scalar) {
|
||||||
|
VALUES("10");
|
||||||
|
}
|
||||||
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<21>_nDinOE_delay:
|
A_FSB<21>_nDinOE_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
|
@ -380,7 +360,17 @@ CELL_FALL(scalar) {
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nWE_FSB_nOE_delay:
|
A_FSB<22>_nDinOE_delay:
|
||||||
|
CELL_RISE(scalar) {
|
||||||
|
VALUES("10");
|
||||||
|
}
|
||||||
|
CELL_FALL(scalar) {
|
||||||
|
VALUES("10");
|
||||||
|
}
|
||||||
|
ENDARCDATA
|
||||||
|
|
||||||
|
ARCDATA
|
||||||
|
A_FSB<23>_nDinOE_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("10");
|
||||||
}
|
}
|
||||||
|
@ -400,7 +390,7 @@ CELL_FALL(scalar) {
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nLDS_FSB_nRAMLWE_delay:
|
nWE_FSB_nOE_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("10");
|
||||||
}
|
}
|
||||||
|
@ -410,7 +400,7 @@ CELL_FALL(scalar) {
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nAS_FSB_nRAMLWE_delay:
|
nLDS_FSB_nRAMLWE_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("10");
|
||||||
}
|
}
|
||||||
|
@ -429,26 +419,6 @@ CELL_FALL(scalar) {
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
|
||||||
nWE_FSB_nRAMUWE_delay:
|
|
||||||
CELL_RISE(scalar) {
|
|
||||||
VALUES("11");
|
|
||||||
}
|
|
||||||
CELL_FALL(scalar) {
|
|
||||||
VALUES("11");
|
|
||||||
}
|
|
||||||
ENDARCDATA
|
|
||||||
|
|
||||||
ARCDATA
|
|
||||||
nAS_FSB_nRAMUWE_delay:
|
|
||||||
CELL_RISE(scalar) {
|
|
||||||
VALUES("11");
|
|
||||||
}
|
|
||||||
CELL_FALL(scalar) {
|
|
||||||
VALUES("11");
|
|
||||||
}
|
|
||||||
ENDARCDATA
|
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nUDS_FSB_nRAMUWE_delay:
|
nUDS_FSB_nRAMUWE_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
|
@ -460,7 +430,7 @@ CELL_FALL(scalar) {
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nAS_FSB_nRAS_delay:
|
nWE_FSB_nRAMUWE_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("11");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
|
@ -479,6 +449,16 @@ CELL_FALL(scalar) {
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
|
ARCDATA
|
||||||
|
nAS_FSB_nRAS_delay:
|
||||||
|
CELL_RISE(scalar) {
|
||||||
|
VALUES("11");
|
||||||
|
}
|
||||||
|
CELL_FALL(scalar) {
|
||||||
|
VALUES("11");
|
||||||
|
}
|
||||||
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<23>_nRAS_delay:
|
A_FSB<23>_nRAS_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
|
@ -492,60 +472,60 @@ ENDARCDATA
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<22>_nROMCS_delay:
|
A_FSB<22>_nROMCS_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
CELL_FALL(scalar) {
|
CELL_FALL(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<20>_nROMCS_delay:
|
A_FSB<20>_nROMCS_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
CELL_FALL(scalar) {
|
CELL_FALL(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<23>_nROMCS_delay:
|
A_FSB<23>_nROMCS_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
CELL_FALL(scalar) {
|
CELL_FALL(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<21>_nROMCS_delay:
|
A_FSB<21>_nROMCS_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
CELL_FALL(scalar) {
|
CELL_FALL(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nWE_FSB_nROMWE_delay:
|
nWE_FSB_nROMWE_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
CELL_FALL(scalar) {
|
CELL_FALL(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nAS_FSB_nROMWE_delay:
|
nAS_FSB_nROMWE_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
CELL_FALL(scalar) {
|
CELL_FALL(scalar) {
|
||||||
VALUES("10");
|
VALUES("11");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
|
@ -702,10 +682,10 @@ ENDARCDATA
|
||||||
ARCDATA
|
ARCDATA
|
||||||
FCLK_RA<5>_delay:
|
FCLK_RA<5>_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("13.5");
|
VALUES("14.5");
|
||||||
}
|
}
|
||||||
CELL_FALL(scalar) {
|
CELL_FALL(scalar) {
|
||||||
VALUES("13.5");
|
VALUES("14.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
|
@ -842,10 +822,10 @@ ENDARCDATA
|
||||||
ARCDATA
|
ARCDATA
|
||||||
FCLK_nROMCS_delay:
|
FCLK_nROMCS_delay:
|
||||||
CELL_RISE(scalar) {
|
CELL_RISE(scalar) {
|
||||||
VALUES("13.5");
|
VALUES("14.5");
|
||||||
}
|
}
|
||||||
CELL_FALL(scalar) {
|
CELL_FALL(scalar) {
|
||||||
VALUES("13.5");
|
VALUES("14.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
|
@ -922,112 +902,112 @@ ENDARCDATA
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<10>_FCLK_setup:
|
A_FSB<10>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<11>_FCLK_setup:
|
A_FSB<11>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<12>_FCLK_setup:
|
A_FSB<12>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<13>_FCLK_setup:
|
A_FSB<13>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<14>_FCLK_setup:
|
A_FSB<14>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<15>_FCLK_setup:
|
A_FSB<15>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<16>_FCLK_setup:
|
A_FSB<16>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<17>_FCLK_setup:
|
A_FSB<17>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<18>_FCLK_setup:
|
A_FSB<18>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<19>_FCLK_setup:
|
A_FSB<19>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<20>_FCLK_setup:
|
A_FSB<20>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<21>_FCLK_setup:
|
A_FSB<21>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<22>_FCLK_setup:
|
A_FSB<22>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<23>_FCLK_setup:
|
A_FSB<23>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<8>_FCLK_setup:
|
A_FSB<8>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<9>_FCLK_setup:
|
A_FSB<9>_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
|
@ -1076,119 +1056,119 @@ ENDARCDATA
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nWE_FSB_FCLK_setup:
|
nWE_FSB_FCLK_setup:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("19.6");
|
VALUES("20");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<10>_FCLK_hold:
|
A_FSB<10>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<11>_FCLK_hold:
|
A_FSB<11>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<12>_FCLK_hold:
|
A_FSB<12>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<13>_FCLK_hold:
|
A_FSB<13>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<14>_FCLK_hold:
|
A_FSB<14>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<15>_FCLK_hold:
|
A_FSB<15>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<16>_FCLK_hold:
|
A_FSB<16>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<17>_FCLK_hold:
|
A_FSB<17>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<18>_FCLK_hold:
|
A_FSB<18>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<19>_FCLK_hold:
|
A_FSB<19>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<20>_FCLK_hold:
|
A_FSB<20>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<21>_FCLK_hold:
|
A_FSB<21>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<22>_FCLK_hold:
|
A_FSB<22>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<23>_FCLK_hold:
|
A_FSB<23>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<8>_FCLK_hold:
|
A_FSB<8>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
ARCDATA
|
ARCDATA
|
||||||
A_FSB<9>_FCLK_hold:
|
A_FSB<9>_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
|
@ -1237,7 +1217,7 @@ ENDARCDATA
|
||||||
ARCDATA
|
ARCDATA
|
||||||
nWE_FSB_FCLK_hold:
|
nWE_FSB_FCLK_hold:
|
||||||
CONSTRAINT(scalar) {
|
CONSTRAINT(scalar) {
|
||||||
VALUES("-13.1");
|
VALUES("-13.5");
|
||||||
}
|
}
|
||||||
ENDARCDATA
|
ENDARCDATA
|
||||||
|
|
||||||
|
|
|
@ -59,15 +59,15 @@
|
||||||
</files>
|
</files>
|
||||||
|
|
||||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||||
<transform xil_pn:end_ts="1681097464" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1681097464">
|
<transform xil_pn:end_ts="1681100469" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1681100469">
|
||||||
<status xil_pn:value="SuccessfullyRun"/>
|
<status xil_pn:value="SuccessfullyRun"/>
|
||||||
<status xil_pn:value="ReadyToRun"/>
|
<status xil_pn:value="ReadyToRun"/>
|
||||||
</transform>
|
</transform>
|
||||||
<transform xil_pn:end_ts="1681097464" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8819683973431472423" xil_pn:start_ts="1681097464">
|
<transform xil_pn:end_ts="1681100469" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8819683973431472423" xil_pn:start_ts="1681100469">
|
||||||
<status xil_pn:value="SuccessfullyRun"/>
|
<status xil_pn:value="SuccessfullyRun"/>
|
||||||
<status xil_pn:value="ReadyToRun"/>
|
<status xil_pn:value="ReadyToRun"/>
|
||||||
</transform>
|
</transform>
|
||||||
<transform xil_pn:end_ts="1681097472" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1681097464">
|
<transform xil_pn:end_ts="1681113893" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1681113885">
|
||||||
<status xil_pn:value="SuccessfullyRun"/>
|
<status xil_pn:value="SuccessfullyRun"/>
|
||||||
<status xil_pn:value="WarningsGenerated"/>
|
<status xil_pn:value="WarningsGenerated"/>
|
||||||
<status xil_pn:value="ReadyToRun"/>
|
<status xil_pn:value="ReadyToRun"/>
|
||||||
|
@ -83,11 +83,11 @@
|
||||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||||
<outfile xil_pn:name="xst"/>
|
<outfile xil_pn:name="xst"/>
|
||||||
</transform>
|
</transform>
|
||||||
<transform xil_pn:end_ts="1681097472" xil_pn:in_ck="-6638154780101949348" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704756" xil_pn:start_ts="1681097472">
|
<transform xil_pn:end_ts="1681100477" xil_pn:in_ck="-6638154780101949348" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704756" xil_pn:start_ts="1681100477">
|
||||||
<status xil_pn:value="SuccessfullyRun"/>
|
<status xil_pn:value="SuccessfullyRun"/>
|
||||||
<status xil_pn:value="ReadyToRun"/>
|
<status xil_pn:value="ReadyToRun"/>
|
||||||
</transform>
|
</transform>
|
||||||
<transform xil_pn:end_ts="1681097477" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1681097472">
|
<transform xil_pn:end_ts="1681113899" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1681113893">
|
||||||
<status xil_pn:value="SuccessfullyRun"/>
|
<status xil_pn:value="SuccessfullyRun"/>
|
||||||
<status xil_pn:value="ReadyToRun"/>
|
<status xil_pn:value="ReadyToRun"/>
|
||||||
<outfile xil_pn:name="WarpSE.bld"/>
|
<outfile xil_pn:name="WarpSE.bld"/>
|
||||||
|
@ -96,10 +96,12 @@
|
||||||
<outfile xil_pn:name="_ngo"/>
|
<outfile xil_pn:name="_ngo"/>
|
||||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||||
</transform>
|
</transform>
|
||||||
<transform xil_pn:end_ts="1681097494" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1681097477">
|
<transform xil_pn:end_ts="1681113915" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1681113899">
|
||||||
<status xil_pn:value="SuccessfullyRun"/>
|
<status xil_pn:value="SuccessfullyRun"/>
|
||||||
<status xil_pn:value="WarningsGenerated"/>
|
<status xil_pn:value="WarningsGenerated"/>
|
||||||
<status xil_pn:value="ReadyToRun"/>
|
<status xil_pn:value="ReadyToRun"/>
|
||||||
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||||
|
<status xil_pn:value="OutputChanged"/>
|
||||||
<outfile xil_pn:name="WarpSE.gyd"/>
|
<outfile xil_pn:name="WarpSE.gyd"/>
|
||||||
<outfile xil_pn:name="WarpSE.mfd"/>
|
<outfile xil_pn:name="WarpSE.mfd"/>
|
||||||
<outfile xil_pn:name="WarpSE.nga"/>
|
<outfile xil_pn:name="WarpSE.nga"/>
|
||||||
|
@ -114,12 +116,12 @@
|
||||||
<outfile xil_pn:name="WarpSE_html"/>
|
<outfile xil_pn:name="WarpSE_html"/>
|
||||||
<outfile xil_pn:name="WarpSE_pad.csv"/>
|
<outfile xil_pn:name="WarpSE_pad.csv"/>
|
||||||
</transform>
|
</transform>
|
||||||
<transform xil_pn:end_ts="1681097496" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1681097494">
|
<transform xil_pn:end_ts="1681113917" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1681113915">
|
||||||
<status xil_pn:value="SuccessfullyRun"/>
|
<status xil_pn:value="SuccessfullyRun"/>
|
||||||
<status xil_pn:value="ReadyToRun"/>
|
<status xil_pn:value="ReadyToRun"/>
|
||||||
<outfile xil_pn:name="WarpSE.jed"/>
|
<outfile xil_pn:name="WarpSE.jed"/>
|
||||||
</transform>
|
</transform>
|
||||||
<transform xil_pn:end_ts="1681097561" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1681097559">
|
<transform xil_pn:end_ts="1681114088" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1681114086">
|
||||||
<status xil_pn:value="SuccessfullyRun"/>
|
<status xil_pn:value="SuccessfullyRun"/>
|
||||||
<status xil_pn:value="ReadyToRun"/>
|
<status xil_pn:value="ReadyToRun"/>
|
||||||
</transform>
|
</transform>
|
||||||
|
|
|
@ -76,44 +76,44 @@ nVPA_FSB S:PIN93
|
||||||
;The remaining section of the .gyd file is for documentation purposes only.
|
;The remaining section of the .gyd file is for documentation purposes only.
|
||||||
;It shows where your internal equations were placed in the last successful fit.
|
;It shows where your internal equations were placed in the last successful fit.
|
||||||
|
|
||||||
PARTITION FB1_1 ram/RS_FSM_FFd2 ram/RS_FSM_FFd1 iobm/Er cnt/Er<1>
|
PARTITION FB1_1 ram/BACTr nRESout iobs/Clear1 iobm/Er
|
||||||
cnt/Er<0> ram/RefDone ram/RS_FSM_FFd4 iobs/TS_FSM_FFd1
|
fsb/ASrf cnt/nIPL2r cnt/Er<1> cnt/Er<0>
|
||||||
iobs/IOU1 iobs/IOL1 cnt/Timer<0> cnt/IS_FSM_FFd2
|
ALE0S $OpTx$$OpTx$FX_DC$348_INV$535 iobs/TS_FSM_FFd1 iobs/IOU1
|
||||||
RefUrg RefReq iobm/ES<2> cnt/Timer<1>
|
iobs/IOL1 cnt/Timer<0> RefUrg IOBERR
|
||||||
cnt/Timer<3> cnt/Timer<2>
|
iobm/ES<2> cnt/Timer<1>
|
||||||
PARTITION FB2_4 ram/RS_FSM_FFd5 ram/RS_FSM_FFd3 ram/RASrf iobs/IODONEr
|
PARTITION FB2_3 ram/RS_FSM_FFd6 ram/RS_FSM_FFd4 ram/RS_FSM_FFd3 ram/RS_FSM_FFd2
|
||||||
iobs/IOACTr iobm/VPAr iobm/IOWRREQr iobm/IOS_FSM_FFd5
|
ram/RS_FSM_FFd1 ram/RASrf iobs/IODONEr iobs/IOACTr
|
||||||
iobm/IOS_FSM_FFd4 iobm/IOS_FSM_FFd1 iobm/IORDREQr iobm/C8Mr
|
iobm/VPAr iobm/IOWRREQr iobm/IOS_FSM_FFd5 iobm/IOS_FSM_FFd4
|
||||||
cnt/nIPL2r iobm/IOS_FSM_FFd2 IOBERR
|
iobm/IOS_FSM_FFd1 iobm/IORDREQr iobm/C8Mr iobm/IOS_FSM_FFd2
|
||||||
PARTITION FB3_1 iobs/Sent iobs/Clear1 ram/RS_FSM_FFd7 ram/RS_FSM_FFd6
|
|
||||||
ram/RASEL ram/RASrr ram/Once cs/nOverlay
|
PARTITION FB3_1 EXP10_ cnt/WS<0> ram/RefDone ram/RS_FSM_FFd7
|
||||||
nDTACK_FSB_OBUF RAMReady ram/RS_FSM_FFd8 ram/RAMEN
|
ram/RS_FSM_FFd5 cnt/WS<2> cnt/WS<1> EXP11_
|
||||||
EXP10_ ram/CAS iobs/Load1 IORDREQ
|
nDTACK_FSB_OBUF ram/RS_FSM_FFd8 EXP12_ ram/RASEN
|
||||||
nROMWE_OBUF EXP11_
|
EXP13_ ram/CAS ram/RS_FSM_FFd9 EXP14_
|
||||||
PARTITION FB4_1 QoSReady nAoutOE_OBUF nRESout fsb/ASrf
|
nROMWE_OBUF RAMReady
|
||||||
nDoutOE_OBUF nDinOE_OBUF cnt/WS<0> N0
|
PARTITION FB4_1 EXP15_ nAoutOE_OBUF cnt/LTimer<9> cnt/LTimer<8>
|
||||||
ALE0S $OpTx$$OpTx$FX_DC$354_INV$541 nVPA_FSB_OBUF cnt/WS<3>
|
nDoutOE_OBUF nDinOE_OBUF cnt/LTimer<7> N0
|
||||||
cnt/WS<2> cnt/WS<1> IONPReady EXP12_
|
cnt/LTimer<11> cnt/LTimer<10> nVPA_FSB_OBUF IONPReady
|
||||||
cnt/LTimer<1> EXP13_
|
EXP16_ cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2 EXP17_ cnt/LTimer<1>
|
||||||
PARTITION FB5_1 EXP14_ nROMCS_OBUF
|
EXP18_ cnt/LTimer<0>
|
||||||
PARTITION FB5_5 nCAS_OBUF nOE_OBUF
|
PARTITION FB5_1 QoSReady nROMCS_OBUF ram/RASEL cs/nOverlay
|
||||||
PARTITION FB5_9 RA_4_OBUF
|
nCAS_OBUF nOE_OBUF cnt/WS<3> ram/RASrr
|
||||||
PARTITION FB5_11 RA_11_OBUF RA_5_OBUF
|
RA_4_OBUF iobs/Load1 RA_11_OBUF RA_5_OBUF
|
||||||
PARTITION FB5_14 RA_2_OBUF RA_6_OBUF cnt/LTimerTC EXP15_
|
iobs/Sent RA_2_OBUF RA_6_OBUF EXP19_
|
||||||
cnt/LTimer<0>
|
IORDREQ EXP20_
|
||||||
PARTITION FB6_1 iobm/IOS_FSM_FFd6 nVMA_IOBout iobm/IOS_FSM_FFd7 iobm/IOS_FSM_FFd3
|
PARTITION FB6_1 iobm/IOS_FSM_FFd6 nVMA_IOBout iobm/IOS_FSM_FFd7 iobm/IOS_FSM_FFd3
|
||||||
iobm/ES<0> iobm/ES<3> iobm/ES<1> iobm/DoutOE
|
iobm/ES<0> iobm/ES<3> iobm/ES<1> iobm/DoutOE
|
||||||
nLDS_IOBout IODONE nUDS_IOBout nAS_IOBout
|
nLDS_IOBout IODONE nUDS_IOBout nAS_IOBout
|
||||||
iobm/IOS0 nADoutLE1_OBUF nADoutLE0_OBUF ALE0M
|
iobm/IOS0 nADoutLE1_OBUF nADoutLE0_OBUF ALE0M
|
||||||
nDinLE_OBUF IOACT
|
nDinLE_OBUF IOACT
|
||||||
PARTITION FB7_1 cnt/LTimer<9> RA_1_OBUF cnt/LTimer<8> cnt/LTimer<7>
|
PARTITION FB7_1 cnt/LTimerTC RA_1_OBUF cnt/TimerTC cnt/IS_FSM_FFd2
|
||||||
RA_7_OBUF RA_0_OBUF cnt/LTimer<6> RA_8_OBUF
|
RA_7_OBUF RA_0_OBUF RefReq RA_8_OBUF
|
||||||
RA_10_OBUF cnt/LTimer<5> RA_9_OBUF C25MEN_OBUF
|
RA_10_OBUF cnt/LTimer<6> RA_9_OBUF C25MEN_OBUF
|
||||||
cnt/LTimer<4> cnt/LTimer<3> cnt/LTimer<2> cnt/LTimer<11>
|
cnt/LTimer<5> cnt/LTimer<4> cnt/LTimer<3> cnt/LTimer<2>
|
||||||
cnt/LTimer<10> cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2
|
cnt/Timer<3> cnt/Timer<2>
|
||||||
PARTITION FB8_1 IOL0 RA_11_OBUF$BUF0 iobs/TS_FSM_FFd2 EXP16_
|
PARTITION FB8_1 IOL0 RA_11_OBUF$BUF0 iobs/TS_FSM_FFd2 EXP21_
|
||||||
nRAS_OBUF nRAMLWE_OBUF EXP17_ nRAMUWE_OBUF
|
nRAS_OBUF nRAMLWE_OBUF EXP22_ nRAMUWE_OBUF
|
||||||
IOWRREQ EXP18_ EXP19_ nBERR_FSB_OBUF
|
IOWRREQ EXP23_ EXP24_ nBERR_FSB_OBUF
|
||||||
EXP20_ IOU0 nBR_IOB_OBUF cnt/IS_FSM_FFd1
|
EXP25_ IOU0 nBR_IOB_OBUF cnt/IS_FSM_FFd1
|
||||||
iobs/IORW1 EXP21_
|
iobs/IORW1 EXP26_
|
||||||
|
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -81,40 +81,38 @@ A_FSB<7>_RA<10>_delay: DELAY A_FSB<7> RA<10>;
|
||||||
A_FSB<17>_RA<10>_delay: DELAY A_FSB<17> RA<10>;
|
A_FSB<17>_RA<10>_delay: DELAY A_FSB<17> RA<10>;
|
||||||
A_FSB<20>_RA<11>_delay: DELAY A_FSB<20> RA<11>;
|
A_FSB<20>_RA<11>_delay: DELAY A_FSB<20> RA<11>;
|
||||||
A_FSB<19>_RA<11>_delay: DELAY A_FSB<19> RA<11>;
|
A_FSB<19>_RA<11>_delay: DELAY A_FSB<19> RA<11>;
|
||||||
A_FSB<10>_RA<1>_delay: DELAY A_FSB<10> RA<1>;
|
|
||||||
A_FSB<2>_RA<1>_delay: DELAY A_FSB<2> RA<1>;
|
A_FSB<2>_RA<1>_delay: DELAY A_FSB<2> RA<1>;
|
||||||
A_FSB<16>_RA<2>_delay: DELAY A_FSB<16> RA<2>;
|
A_FSB<10>_RA<1>_delay: DELAY A_FSB<10> RA<1>;
|
||||||
A_FSB<7>_RA<2>_delay: DELAY A_FSB<7> RA<2>;
|
A_FSB<7>_RA<2>_delay: DELAY A_FSB<7> RA<2>;
|
||||||
A_FSB<19>_RA<3>_delay: DELAY A_FSB<19> RA<3>;
|
A_FSB<16>_RA<2>_delay: DELAY A_FSB<16> RA<2>;
|
||||||
A_FSB<20>_RA<3>_delay: DELAY A_FSB<20> RA<3>;
|
A_FSB<20>_RA<3>_delay: DELAY A_FSB<20> RA<3>;
|
||||||
|
A_FSB<19>_RA<3>_delay: DELAY A_FSB<19> RA<3>;
|
||||||
A_FSB<11>_RA<4>_delay: DELAY A_FSB<11> RA<4>;
|
A_FSB<11>_RA<4>_delay: DELAY A_FSB<11> RA<4>;
|
||||||
A_FSB<3>_RA<4>_delay: DELAY A_FSB<3> RA<4>;
|
A_FSB<3>_RA<4>_delay: DELAY A_FSB<3> RA<4>;
|
||||||
A_FSB<12>_RA<5>_delay: DELAY A_FSB<12> RA<5>;
|
A_FSB<12>_RA<5>_delay: DELAY A_FSB<12> RA<5>;
|
||||||
A_FSB<4>_RA<5>_delay: DELAY A_FSB<4> RA<5>;
|
A_FSB<4>_RA<5>_delay: DELAY A_FSB<4> RA<5>;
|
||||||
A_FSB<5>_RA<6>_delay: DELAY A_FSB<5> RA<6>;
|
A_FSB<5>_RA<6>_delay: DELAY A_FSB<5> RA<6>;
|
||||||
A_FSB<13>_RA<6>_delay: DELAY A_FSB<13> RA<6>;
|
A_FSB<13>_RA<6>_delay: DELAY A_FSB<13> RA<6>;
|
||||||
A_FSB<6>_RA<7>_delay: DELAY A_FSB<6> RA<7>;
|
|
||||||
A_FSB<14>_RA<7>_delay: DELAY A_FSB<14> RA<7>;
|
A_FSB<14>_RA<7>_delay: DELAY A_FSB<14> RA<7>;
|
||||||
|
A_FSB<6>_RA<7>_delay: DELAY A_FSB<6> RA<7>;
|
||||||
A_FSB<18>_RA<8>_delay: DELAY A_FSB<18> RA<8>;
|
A_FSB<18>_RA<8>_delay: DELAY A_FSB<18> RA<8>;
|
||||||
A_FSB<21>_RA<8>_delay: DELAY A_FSB<21> RA<8>;
|
A_FSB<21>_RA<8>_delay: DELAY A_FSB<21> RA<8>;
|
||||||
A_FSB<15>_RA<9>_delay: DELAY A_FSB<15> RA<9>;
|
A_FSB<15>_RA<9>_delay: DELAY A_FSB<15> RA<9>;
|
||||||
A_FSB<8>_RA<9>_delay: DELAY A_FSB<8> RA<9>;
|
A_FSB<8>_RA<9>_delay: DELAY A_FSB<8> RA<9>;
|
||||||
A_FSB<23>_nDinOE_delay: DELAY A_FSB<23> nDinOE;
|
|
||||||
nAS_FSB_nDinOE_delay: DELAY nAS_FSB nDinOE;
|
nAS_FSB_nDinOE_delay: DELAY nAS_FSB nDinOE;
|
||||||
A_FSB<20>_nDinOE_delay: DELAY A_FSB<20> nDinOE;
|
|
||||||
A_FSB<22>_nDinOE_delay: DELAY A_FSB<22> nDinOE;
|
|
||||||
nWE_FSB_nDinOE_delay: DELAY nWE_FSB nDinOE;
|
nWE_FSB_nDinOE_delay: DELAY nWE_FSB nDinOE;
|
||||||
|
A_FSB<20>_nDinOE_delay: DELAY A_FSB<20> nDinOE;
|
||||||
A_FSB<21>_nDinOE_delay: DELAY A_FSB<21> nDinOE;
|
A_FSB<21>_nDinOE_delay: DELAY A_FSB<21> nDinOE;
|
||||||
nWE_FSB_nOE_delay: DELAY nWE_FSB nOE;
|
A_FSB<22>_nDinOE_delay: DELAY A_FSB<22> nDinOE;
|
||||||
|
A_FSB<23>_nDinOE_delay: DELAY A_FSB<23> nDinOE;
|
||||||
nAS_FSB_nOE_delay: DELAY nAS_FSB nOE;
|
nAS_FSB_nOE_delay: DELAY nAS_FSB nOE;
|
||||||
|
nWE_FSB_nOE_delay: DELAY nWE_FSB nOE;
|
||||||
nLDS_FSB_nRAMLWE_delay: DELAY nLDS_FSB nRAMLWE;
|
nLDS_FSB_nRAMLWE_delay: DELAY nLDS_FSB nRAMLWE;
|
||||||
nAS_FSB_nRAMLWE_delay: DELAY nAS_FSB nRAMLWE;
|
|
||||||
nWE_FSB_nRAMLWE_delay: DELAY nWE_FSB nRAMLWE;
|
nWE_FSB_nRAMLWE_delay: DELAY nWE_FSB nRAMLWE;
|
||||||
nWE_FSB_nRAMUWE_delay: DELAY nWE_FSB nRAMUWE;
|
|
||||||
nAS_FSB_nRAMUWE_delay: DELAY nAS_FSB nRAMUWE;
|
|
||||||
nUDS_FSB_nRAMUWE_delay: DELAY nUDS_FSB nRAMUWE;
|
nUDS_FSB_nRAMUWE_delay: DELAY nUDS_FSB nRAMUWE;
|
||||||
nAS_FSB_nRAS_delay: DELAY nAS_FSB nRAS;
|
nWE_FSB_nRAMUWE_delay: DELAY nWE_FSB nRAMUWE;
|
||||||
A_FSB<22>_nRAS_delay: DELAY A_FSB<22> nRAS;
|
A_FSB<22>_nRAS_delay: DELAY A_FSB<22> nRAS;
|
||||||
|
nAS_FSB_nRAS_delay: DELAY nAS_FSB nRAS;
|
||||||
A_FSB<23>_nRAS_delay: DELAY A_FSB<23> nRAS;
|
A_FSB<23>_nRAS_delay: DELAY A_FSB<23> nRAS;
|
||||||
A_FSB<22>_nROMCS_delay: DELAY A_FSB<22> nROMCS;
|
A_FSB<22>_nROMCS_delay: DELAY A_FSB<22> nROMCS;
|
||||||
A_FSB<20>_nROMCS_delay: DELAY A_FSB<20> nROMCS;
|
A_FSB<20>_nROMCS_delay: DELAY A_FSB<20> nROMCS;
|
||||||
|
|
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
@ -1,7 +1,7 @@
|
||||||
Release 8.1i - Fit P.20131013
|
Release 8.1i - Fit P.20131013
|
||||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||||
|
|
||||||
4- 9-2023 11:31PM
|
4-10-2023 4:05AM
|
||||||
|
|
||||||
NOTE: This file is designed to be imported into a spreadsheet program
|
NOTE: This file is designed to be imported into a spreadsheet program
|
||||||
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
|
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||||
|
|
||||||
|
|
||||||
Total REAL time to Xst completion: 0.00 secs
|
Total REAL time to Xst completion: 0.00 secs
|
||||||
Total CPU time to Xst completion: 0.09 secs
|
Total CPU time to Xst completion: 0.10 secs
|
||||||
|
|
||||||
--> Parameter xsthdpdir set to xst
|
--> Parameter xsthdpdir set to xst
|
||||||
|
|
||||||
|
|
||||||
Total REAL time to Xst completion: 0.00 secs
|
Total REAL time to Xst completion: 0.00 secs
|
||||||
Total CPU time to Xst completion: 0.09 secs
|
Total CPU time to Xst completion: 0.10 secs
|
||||||
|
|
||||||
--> Reading design: WarpSE.prj
|
--> Reading design: WarpSE.prj
|
||||||
|
|
||||||
|
@ -150,30 +150,29 @@ Unit <CS> synthesized.
|
||||||
|
|
||||||
Synthesizing Unit <RAM>.
|
Synthesizing Unit <RAM>.
|
||||||
Related source file is "../RAM.v".
|
Related source file is "../RAM.v".
|
||||||
WARNING:Xst:646 - Signal <BACTr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
||||||
Found finite state machine <FSM_0> for signal <RS>.
|
Found finite state machine <FSM_0> for signal <RS>.
|
||||||
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
||||||
| States | 8 |
|
| States | 9 |
|
||||||
| Transitions | 11 |
|
| Transitions | 21 |
|
||||||
| Inputs | 3 |
|
| Inputs | 7 |
|
||||||
| Outputs | 8 |
|
| Outputs | 9 |
|
||||||
| Clock | CLK (rising_edge) |
|
| Clock | CLK (rising_edge) |
|
||||||
| Power Up State | 000 |
|
| Power Up State | 0000 |
|
||||||
| Encoding | automatic |
|
| Encoding | automatic |
|
||||||
| Implementation | automatic |
|
| Implementation | automatic |
|
||||||
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
||||||
Found 1-bit register for signal <nCAS>.
|
Found 1-bit register for signal <nCAS>.
|
||||||
Found 1-bit register for signal <RAMReady>.
|
Found 1-bit register for signal <RAMReady>.
|
||||||
|
Found 1-bit register for signal <BACTr>.
|
||||||
Found 1-bit register for signal <CAS>.
|
Found 1-bit register for signal <CAS>.
|
||||||
Found 1-bit register for signal <Once>.
|
|
||||||
Found 1-bit register for signal <RAMEN>.
|
|
||||||
Found 1-bit register for signal <RASEL>.
|
Found 1-bit register for signal <RASEL>.
|
||||||
|
Found 1-bit register for signal <RASEN>.
|
||||||
Found 1-bit register for signal <RASrf>.
|
Found 1-bit register for signal <RASrf>.
|
||||||
Found 1-bit register for signal <RASrr>.
|
Found 1-bit register for signal <RASrr>.
|
||||||
Found 1-bit register for signal <RefDone>.
|
Found 1-bit register for signal <RefDone>.
|
||||||
Summary:
|
Summary:
|
||||||
inferred 1 Finite State Machine(s).
|
inferred 1 Finite State Machine(s).
|
||||||
inferred 6 D-type flip-flop(s).
|
inferred 8 D-type flip-flop(s).
|
||||||
Unit <RAM> synthesized.
|
Unit <RAM> synthesized.
|
||||||
|
|
||||||
|
|
||||||
|
@ -268,18 +267,19 @@ Synthesizing Unit <CNT>.
|
||||||
Found 1-bit register for signal <nRESout>.
|
Found 1-bit register for signal <nRESout>.
|
||||||
Found 1-bit register for signal <AoutOE>.
|
Found 1-bit register for signal <AoutOE>.
|
||||||
Found 1-bit register for signal <QoSReady>.
|
Found 1-bit register for signal <QoSReady>.
|
||||||
Found 2-bit adder for signal <$add0000> created at line 66.
|
Found 2-bit adder for signal <$add0000> created at line 67.
|
||||||
Found 12-bit adder for signal <$add0001> created at line 67.
|
Found 12-bit adder for signal <$add0001> created at line 68.
|
||||||
Found 2-bit register for signal <Er>.
|
Found 2-bit register for signal <Er>.
|
||||||
Found 12-bit register for signal <LTimer>.
|
Found 12-bit register for signal <LTimer>.
|
||||||
Found 1-bit register for signal <LTimerTC>.
|
Found 1-bit register for signal <LTimerTC>.
|
||||||
Found 1-bit register for signal <nIPL2r>.
|
Found 1-bit register for signal <nIPL2r>.
|
||||||
Found 4-bit up counter for signal <Timer>.
|
Found 4-bit up counter for signal <Timer>.
|
||||||
|
Found 1-bit register for signal <TimerTC>.
|
||||||
Found 4-bit up counter for signal <WS>.
|
Found 4-bit up counter for signal <WS>.
|
||||||
Summary:
|
Summary:
|
||||||
inferred 1 Finite State Machine(s).
|
inferred 1 Finite State Machine(s).
|
||||||
inferred 2 Counter(s).
|
inferred 2 Counter(s).
|
||||||
inferred 10 D-type flip-flop(s).
|
inferred 11 D-type flip-flop(s).
|
||||||
inferred 2 Adder/Subtractor(s).
|
inferred 2 Adder/Subtractor(s).
|
||||||
Unit <CNT> synthesized.
|
Unit <CNT> synthesized.
|
||||||
|
|
||||||
|
@ -318,8 +318,8 @@ Macro Statistics
|
||||||
2-bit adder : 1
|
2-bit adder : 1
|
||||||
# Counters : 3
|
# Counters : 3
|
||||||
4-bit up counter : 3
|
4-bit up counter : 3
|
||||||
# Registers : 66
|
# Registers : 67
|
||||||
1-bit register : 65
|
1-bit register : 66
|
||||||
2-bit register : 1
|
2-bit register : 1
|
||||||
# Tristates : 5
|
# Tristates : 5
|
||||||
1-bit tristate buffer : 5
|
1-bit tristate buffer : 5
|
||||||
|
@ -364,19 +364,20 @@ Optimizing FSM <iobs/TS/FSM> on signal <TS[1:2]> with johnson encoding.
|
||||||
01 | 10
|
01 | 10
|
||||||
-------------------
|
-------------------
|
||||||
Analyzing FSM <FSM_0> for best encoding.
|
Analyzing FSM <FSM_0> for best encoding.
|
||||||
Optimizing FSM <ram/RS/FSM> on signal <RS[1:8]> with one-hot encoding.
|
Optimizing FSM <ram/RS/FSM> on signal <RS[1:9]> with one-hot encoding.
|
||||||
-------------------
|
--------------------
|
||||||
State | Encoding
|
State | Encoding
|
||||||
-------------------
|
--------------------
|
||||||
000 | 00000001
|
0000 | 000000001
|
||||||
001 | 00000010
|
1000 | 000000010
|
||||||
011 | 00000100
|
0001 | 000000100
|
||||||
010 | 00001000
|
0010 | 000001000
|
||||||
111 | 00010000
|
0011 | 000010000
|
||||||
100 | 00100000
|
1001 | 000100000
|
||||||
101 | 01000000
|
1010 | 001000000
|
||||||
110 | 10000000
|
1011 | 010000000
|
||||||
-------------------
|
1111 | 100000000
|
||||||
|
--------------------
|
||||||
|
|
||||||
=========================================================================
|
=========================================================================
|
||||||
Advanced HDL Synthesis Report
|
Advanced HDL Synthesis Report
|
||||||
|
@ -388,8 +389,8 @@ Macro Statistics
|
||||||
2-bit adder : 1
|
2-bit adder : 1
|
||||||
# Counters : 3
|
# Counters : 3
|
||||||
4-bit up counter : 3
|
4-bit up counter : 3
|
||||||
# Registers : 44
|
# Registers : 47
|
||||||
Flip-Flops : 44
|
Flip-Flops : 47
|
||||||
|
|
||||||
=========================================================================
|
=========================================================================
|
||||||
|
|
||||||
|
@ -403,20 +404,20 @@ Optimizing unit <CS> ...
|
||||||
implementation constraint: INIT=r : nOverlay
|
implementation constraint: INIT=r : nOverlay
|
||||||
|
|
||||||
Optimizing unit <RAM> ...
|
Optimizing unit <RAM> ...
|
||||||
implementation constraint: INIT=s : RS_FSM_FFd8
|
implementation constraint: INIT=s : RS_FSM_FFd9
|
||||||
implementation constraint: INIT=r : RASEL
|
implementation constraint: INIT=r : RASEL
|
||||||
implementation constraint: INIT=r : CAS
|
implementation constraint: INIT=r : CAS
|
||||||
implementation constraint: INIT=r : RASrr
|
implementation constraint: INIT=r : RASrr
|
||||||
implementation constraint: INIT=r : RS_FSM_FFd7
|
implementation constraint: INIT=r : RASEN
|
||||||
implementation constraint: INIT=r : Once
|
|
||||||
implementation constraint: INIT=r : RASrf
|
|
||||||
implementation constraint: INIT=r : RAMEN
|
|
||||||
implementation constraint: INIT=r : RS_FSM_FFd1
|
implementation constraint: INIT=r : RS_FSM_FFd1
|
||||||
implementation constraint: INIT=r : RS_FSM_FFd2
|
implementation constraint: INIT=r : RS_FSM_FFd2
|
||||||
implementation constraint: INIT=r : RS_FSM_FFd3
|
implementation constraint: INIT=r : RS_FSM_FFd3
|
||||||
implementation constraint: INIT=r : RS_FSM_FFd4
|
implementation constraint: INIT=r : RS_FSM_FFd4
|
||||||
implementation constraint: INIT=r : RS_FSM_FFd5
|
implementation constraint: INIT=r : RS_FSM_FFd5
|
||||||
implementation constraint: INIT=r : RS_FSM_FFd6
|
implementation constraint: INIT=r : RS_FSM_FFd6
|
||||||
|
implementation constraint: INIT=r : RS_FSM_FFd7
|
||||||
|
implementation constraint: INIT=r : RS_FSM_FFd8
|
||||||
|
implementation constraint: INIT=r : RASrf
|
||||||
|
|
||||||
Optimizing unit <IOBS> ...
|
Optimizing unit <IOBS> ...
|
||||||
implementation constraint: INIT=r : IOACTr
|
implementation constraint: INIT=r : IOACTr
|
||||||
|
@ -479,24 +480,24 @@ Design Statistics
|
||||||
# IOs : 75
|
# IOs : 75
|
||||||
|
|
||||||
Cell Usage :
|
Cell Usage :
|
||||||
# BELS : 653
|
# BELS : 710
|
||||||
# AND2 : 202
|
# AND2 : 222
|
||||||
# AND3 : 27
|
# AND3 : 30
|
||||||
# AND4 : 13
|
# AND4 : 12
|
||||||
# AND5 : 2
|
# AND5 : 2
|
||||||
# AND7 : 2
|
# AND7 : 2
|
||||||
# AND8 : 4
|
# AND8 : 5
|
||||||
# GND : 6
|
# GND : 6
|
||||||
# INV : 253
|
# INV : 277
|
||||||
# OR2 : 112
|
# OR2 : 119
|
||||||
# OR3 : 9
|
# OR3 : 10
|
||||||
# OR4 : 2
|
# OR4 : 4
|
||||||
# VCC : 1
|
# VCC : 1
|
||||||
# XOR2 : 20
|
# XOR2 : 20
|
||||||
# FlipFlops/Latches : 98
|
# FlipFlops/Latches : 100
|
||||||
# FD : 65
|
# FD : 68
|
||||||
# FDC : 2
|
# FDC : 2
|
||||||
# FDCE : 30
|
# FDCE : 29
|
||||||
# FDP : 1
|
# FDP : 1
|
||||||
# IO Buffers : 70
|
# IO Buffers : 70
|
||||||
# IBUF : 35
|
# IBUF : 35
|
||||||
|
@ -507,13 +508,13 @@ Cell Usage :
|
||||||
|
|
||||||
|
|
||||||
Total REAL time to Xst completion: 5.00 secs
|
Total REAL time to Xst completion: 5.00 secs
|
||||||
Total CPU time to Xst completion: 5.04 secs
|
Total CPU time to Xst completion: 5.14 secs
|
||||||
|
|
||||||
-->
|
-->
|
||||||
|
|
||||||
Total memory usage is 266756 kilobytes
|
Total memory usage is 267972 kilobytes
|
||||||
|
|
||||||
Number of errors : 0 ( 0 filtered)
|
Number of errors : 0 ( 0 filtered)
|
||||||
Number of warnings : 4 ( 0 filtered)
|
Number of warnings : 3 ( 0 filtered)
|
||||||
Number of infos : 0 ( 0 filtered)
|
Number of infos : 0 ( 0 filtered)
|
||||||
|
|
||||||
|
|
|
@ -5,7 +5,7 @@ Design: WarpSE
|
||||||
Device: XC95144XL-10-TQ100
|
Device: XC95144XL-10-TQ100
|
||||||
Speed File: Version 3.0
|
Speed File: Version 3.0
|
||||||
Program: Timing Report Generator: version P.20131013
|
Program: Timing Report Generator: version P.20131013
|
||||||
Date: Sun Apr 09 23:32:40 2023
|
Date: Mon Apr 10 04:08:07 2023
|
||||||
|
|
||||||
Performance Summary:
|
Performance Summary:
|
||||||
|
|
||||||
|
@ -17,16 +17,16 @@ Clock net 'FCLK' path delays:
|
||||||
Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)
|
Clock Pad to Output Pad (tCO) : 14.5ns (2 macrocell levels)
|
||||||
Clock Pad 'FCLK' to Output Pad 'nRES' (GCK)
|
Clock Pad 'FCLK' to Output Pad 'nRES' (GCK)
|
||||||
|
|
||||||
Clock to Setup (tCYC) : 20.1ns (2 macrocell levels)
|
Clock to Setup (tCYC) : 20.5ns (2 macrocell levels)
|
||||||
Clock to Q, net 'cnt/IS_FSM_FFd1.Q' to DFF Setup(D) at 'cnt/LTimer<0>.D' (GCK)
|
Clock to Q, net 'cnt/IS_FSM_FFd1.Q' to DFF Setup(D) at 'cnt/LTimer<0>.D' (GCK)
|
||||||
Target FF drives output net 'cnt/LTimer<0>'
|
Target FF drives output net 'cnt/LTimer<0>'
|
||||||
|
|
||||||
Setup to Clock at the Pad (tSU) : 16.6ns (1 macrocell levels)
|
Setup to Clock at the Pad (tSU) : 17.0ns (1 macrocell levels)
|
||||||
Data signal 'A_FSB<23>' to DFF D input Pin at 'cnt/LTimer<0>.D'
|
Data signal 'A_FSB<23>' to DFF D input Pin at 'cnt/LTimer<0>.D'
|
||||||
Clock pad 'FCLK' (GCK)
|
Clock pad 'FCLK' (GCK)
|
||||||
|
|
||||||
Minimum Clock Period: 20.1ns
|
Minimum Clock Period: 20.5ns
|
||||||
Maximum Internal Clock Speed: 49.7Mhz
|
Maximum Internal Clock Speed: 48.7Mhz
|
||||||
(Limited by Cycle Time)
|
(Limited by Cycle Time)
|
||||||
|
|
||||||
Clock net 'C16M' path delays:
|
Clock net 'C16M' path delays:
|
||||||
|
@ -84,7 +84,7 @@ RA<1> 10.0
|
||||||
RA<2> 10.0
|
RA<2> 10.0
|
||||||
RA<3> 10.0
|
RA<3> 10.0
|
||||||
RA<4> 10.0
|
RA<4> 10.0
|
||||||
RA<5> 10.0
|
RA<5> 11.0
|
||||||
RA<6> 10.0
|
RA<6> 10.0
|
||||||
RA<7> 10.0
|
RA<7> 10.0
|
||||||
RA<8> 10.0
|
RA<8> 10.0
|
||||||
|
@ -118,7 +118,7 @@ RA<1> 10.0
|
||||||
RA<2> 10.0
|
RA<2> 10.0
|
||||||
RA<3> 10.0
|
RA<3> 10.0
|
||||||
RA<4> 10.0
|
RA<4> 10.0
|
||||||
RA<5> 10.0
|
RA<5> 11.0
|
||||||
RA<6> 10.0
|
RA<6> 10.0
|
||||||
RA<7> 10.0
|
RA<7> 10.0
|
||||||
RA<8> 10.0
|
RA<8> 10.0
|
||||||
|
@ -128,7 +128,7 @@ nOE
|
||||||
nRAMLWE
|
nRAMLWE
|
||||||
nRAMUWE
|
nRAMUWE
|
||||||
nRAS 11.0 11.0
|
nRAS 11.0 11.0
|
||||||
nROMCS 10.0 10.0 10.0 10.0
|
nROMCS 11.0 11.0 11.0 11.0
|
||||||
nROMWE
|
nROMWE
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
|
@ -159,11 +159,11 @@ RA<8>
|
||||||
RA<9>
|
RA<9>
|
||||||
nDinOE 10.0 10.0
|
nDinOE 10.0 10.0
|
||||||
nOE 10.0 10.0
|
nOE 10.0 10.0
|
||||||
nRAMLWE 10.0 10.0 10.0
|
nRAMLWE 10.0 10.0
|
||||||
nRAMUWE 11.0 11.0 11.0
|
nRAMUWE 11.0 11.0
|
||||||
nRAS 11.0
|
nRAS 11.0
|
||||||
nROMCS
|
nROMCS
|
||||||
nROMWE 10.0 10.0
|
nROMWE 11.0 11.0
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
Clock Pad to Output Pad (tCO) (nsec)
|
Clock Pad to Output Pad (tCO) (nsec)
|
||||||
|
@ -187,7 +187,7 @@ RA<1> 13.5
|
||||||
RA<2> 13.5
|
RA<2> 13.5
|
||||||
RA<3> 13.5
|
RA<3> 13.5
|
||||||
RA<4> 13.5
|
RA<4> 13.5
|
||||||
RA<5> 13.5
|
RA<5> 14.5
|
||||||
RA<6> 13.5
|
RA<6> 13.5
|
||||||
RA<7> 13.5
|
RA<7> 13.5
|
||||||
RA<8> 13.5
|
RA<8> 13.5
|
||||||
|
@ -207,7 +207,7 @@ nRAMLWE 13.5
|
||||||
nRAMUWE 14.5
|
nRAMUWE 14.5
|
||||||
nRAS 14.5
|
nRAS 14.5
|
||||||
nRES 14.5
|
nRES 14.5
|
||||||
nROMCS 13.5
|
nROMCS 14.5
|
||||||
nUDS_IOB 5.8 14.5
|
nUDS_IOB 5.8 14.5
|
||||||
nVMA_IOB 5.8 14.5
|
nVMA_IOB 5.8 14.5
|
||||||
nVPA_FSB 5.8
|
nVPA_FSB 5.8
|
||||||
|
@ -227,22 +227,22 @@ nVPA_FSB 5.8
|
||||||
\
|
\
|
||||||
To \------------------
|
To \------------------
|
||||||
|
|
||||||
A_FSB<10> 16.6
|
A_FSB<10> 17.0
|
||||||
A_FSB<11> 16.6
|
A_FSB<11> 17.0
|
||||||
A_FSB<12> 16.6
|
A_FSB<12> 17.0
|
||||||
A_FSB<13> 16.6
|
A_FSB<13> 17.0
|
||||||
A_FSB<14> 16.6
|
A_FSB<14> 17.0
|
||||||
A_FSB<15> 16.6
|
A_FSB<15> 17.0
|
||||||
A_FSB<16> 16.6
|
A_FSB<16> 17.0
|
||||||
A_FSB<17> 16.6
|
A_FSB<17> 17.0
|
||||||
A_FSB<18> 16.6
|
A_FSB<18> 17.0
|
||||||
A_FSB<19> 16.6
|
A_FSB<19> 17.0
|
||||||
A_FSB<20> 16.6
|
A_FSB<20> 17.0
|
||||||
A_FSB<21> 16.6
|
A_FSB<21> 17.0
|
||||||
A_FSB<22> 16.6
|
A_FSB<22> 17.0
|
||||||
A_FSB<23> 16.6
|
A_FSB<23> 17.0
|
||||||
A_FSB<8> 16.6
|
A_FSB<8> 17.0
|
||||||
A_FSB<9> 16.6
|
A_FSB<9> 17.0
|
||||||
C8M 6.5
|
C8M 6.5
|
||||||
E 6.5 6.5
|
E 6.5 6.5
|
||||||
nAS_FSB 16.6
|
nAS_FSB 16.6
|
||||||
|
@ -253,7 +253,7 @@ nLDS_FSB 6.5
|
||||||
nRES 6.5 6.5
|
nRES 6.5 6.5
|
||||||
nUDS_FSB 6.5
|
nUDS_FSB 6.5
|
||||||
nVPA_IOB 6.5
|
nVPA_IOB 6.5
|
||||||
nWE_FSB 16.6
|
nWE_FSB 17.0
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
Clock to Setup (tCYC) (nsec)
|
Clock to Setup (tCYC) (nsec)
|
||||||
|
@ -282,39 +282,41 @@ nWE_FSB 16.6
|
||||||
ALE0S.D
|
ALE0S.D
|
||||||
IOL0.D 11.0
|
IOL0.D 11.0
|
||||||
IONPReady.D 11.0
|
IONPReady.D 11.0
|
||||||
IORDREQ.D 10.0
|
IORDREQ.D 11.0
|
||||||
IOU0.D 11.0
|
IOU0.D 11.0
|
||||||
IOWRREQ.D 10.0
|
IOWRREQ.D 10.0
|
||||||
QoSReady.D 10.0
|
QoSReady.D 10.0
|
||||||
RAMReady.D 10.0 10.0 10.0
|
RAMReady.D 11.4 11.0
|
||||||
RefReq.CE 10.0
|
RefReq.CE 10.0
|
||||||
RefReq.D
|
RefReq.D
|
||||||
RefUrg.CE 10.0
|
RefUrg.CE 10.0
|
||||||
RefUrg.D
|
RefUrg.D
|
||||||
cnt/Er<1>.D 10.0
|
cnt/Er<1>.D 10.0
|
||||||
cnt/IS_FSM_FFd1.D 10.0 10.0
|
cnt/IS_FSM_FFd1.D 10.0
|
||||||
cnt/IS_FSM_FFd2.D 10.0 10.0
|
cnt/IS_FSM_FFd2.D 10.0
|
||||||
cnt/LTimer<0>.D 19.1 19.1
|
cnt/LTimer<0>.D 19.1
|
||||||
cnt/LTimer<10>.D 10.0 10.0
|
cnt/LTimer<10>.D 10.0
|
||||||
cnt/LTimer<11>.D 10.0 10.0
|
cnt/LTimer<11>.D 10.0
|
||||||
cnt/LTimer<1>.D 19.1 19.1
|
cnt/LTimer<1>.D 19.1
|
||||||
cnt/LTimer<2>.D 10.0 10.0
|
cnt/LTimer<2>.D 10.0
|
||||||
cnt/LTimer<3>.D 10.0 10.0
|
cnt/LTimer<3>.D 10.0
|
||||||
cnt/LTimer<4>.D 10.0 10.0
|
cnt/LTimer<4>.D 10.0
|
||||||
cnt/LTimer<5>.D 10.0 10.0
|
cnt/LTimer<5>.D 10.0
|
||||||
cnt/LTimer<6>.D 10.0 10.0
|
cnt/LTimer<6>.D 10.0
|
||||||
cnt/LTimer<7>.D 10.0 10.0
|
cnt/LTimer<7>.D 10.0
|
||||||
cnt/LTimer<8>.D 10.0 10.0
|
cnt/LTimer<8>.D 10.0
|
||||||
cnt/LTimer<9>.D 11.0 11.0
|
cnt/LTimer<9>.D 10.0
|
||||||
cnt/LTimerTC.D
|
cnt/LTimerTC.D
|
||||||
cnt/Timer<0>.CE 10.0
|
cnt/Timer<0>.CE 10.0
|
||||||
cnt/Timer<0>.D 10.0 10.0
|
cnt/Timer<0>.D 10.0
|
||||||
cnt/Timer<1>.CE 10.0
|
cnt/Timer<1>.CE 10.0
|
||||||
cnt/Timer<1>.D 10.0 10.0
|
cnt/Timer<1>.D 10.0
|
||||||
cnt/Timer<2>.CE 10.0
|
cnt/Timer<2>.CE 10.0
|
||||||
cnt/Timer<2>.D 10.0 10.0
|
cnt/Timer<2>.D 10.0
|
||||||
cnt/Timer<3>.CE 10.0
|
cnt/Timer<3>.CE 10.0
|
||||||
cnt/Timer<3>.D 10.0 10.0
|
cnt/Timer<3>.D 10.0
|
||||||
|
cnt/TimerTC.CE 10.0
|
||||||
|
cnt/TimerTC.D
|
||||||
cnt/WS<0>.D
|
cnt/WS<0>.D
|
||||||
cnt/WS<1>.D
|
cnt/WS<1>.D
|
||||||
cnt/WS<2>.D
|
cnt/WS<2>.D
|
||||||
|
@ -333,23 +335,24 @@ nAoutOE.D
|
||||||
nBERR_FSB.D
|
nBERR_FSB.D
|
||||||
nBR_IOB.D
|
nBR_IOB.D
|
||||||
nCAS.D
|
nCAS.D
|
||||||
nDTACK_FSB.D 11.0 10.0 11.0
|
nDTACK_FSB.D 11.4 11.0 11.4
|
||||||
nRESout.D
|
nRESout.D
|
||||||
nVPA_FSB.D 10.0
|
nVPA_FSB.D 11.0
|
||||||
ram/CAS.D 11.0 11.0
|
ram/BACTr.D
|
||||||
ram/Once.D
|
ram/CAS.D 11.4 11.0
|
||||||
ram/RAMEN.D 10.0 11.0
|
|
||||||
ram/RASEL.D
|
ram/RASEL.D
|
||||||
|
ram/RASEN.D 11.0 11.0
|
||||||
ram/RASrf.D
|
ram/RASrf.D
|
||||||
ram/RASrr.D
|
ram/RASrr.D
|
||||||
ram/RS_FSM_FFd1.D
|
ram/RS_FSM_FFd1.D
|
||||||
ram/RS_FSM_FFd2.D
|
ram/RS_FSM_FFd2.D
|
||||||
ram/RS_FSM_FFd3.D
|
ram/RS_FSM_FFd3.D
|
||||||
ram/RS_FSM_FFd4.D 10.0
|
ram/RS_FSM_FFd4.D
|
||||||
ram/RS_FSM_FFd5.D
|
ram/RS_FSM_FFd5.D
|
||||||
ram/RS_FSM_FFd6.D 10.0 10.0
|
ram/RS_FSM_FFd6.D
|
||||||
ram/RS_FSM_FFd7.D
|
ram/RS_FSM_FFd7.D
|
||||||
ram/RS_FSM_FFd8.D 10.0 10.0
|
ram/RS_FSM_FFd8.D 11.0 11.0
|
||||||
|
ram/RS_FSM_FFd9.D 11.4 11.4
|
||||||
ram/RefDone.D 10.0 10.0
|
ram/RefDone.D 10.0 10.0
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
|
@ -391,10 +394,10 @@ RefUrg.D
|
||||||
cnt/Er<1>.D
|
cnt/Er<1>.D
|
||||||
cnt/IS_FSM_FFd1.D 10.0 10.0 10.0
|
cnt/IS_FSM_FFd1.D 10.0 10.0 10.0
|
||||||
cnt/IS_FSM_FFd2.D 10.0 10.0 10.0
|
cnt/IS_FSM_FFd2.D 10.0 10.0 10.0
|
||||||
cnt/LTimer<0>.D 19.1 20.1 20.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1
|
cnt/LTimer<0>.D 19.1 20.5 20.5 19.1 19.1 19.1 19.1 19.1 19.1 19.1
|
||||||
cnt/LTimer<10>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
cnt/LTimer<10>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimer<11>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
cnt/LTimer<11>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimer<1>.D 19.1 20.1 20.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1
|
cnt/LTimer<1>.D 19.1 20.5 20.5 19.1 19.1 19.1 19.1 19.1 19.1 19.1
|
||||||
cnt/LTimer<2>.D 10.0 10.0 10.0 10.0 10.0 10.0
|
cnt/LTimer<2>.D 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimer<3>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
cnt/LTimer<3>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimer<4>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
cnt/LTimer<4>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
|
@ -402,7 +405,7 @@ cnt/LTimer<5>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimer<6>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
cnt/LTimer<6>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimer<7>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
cnt/LTimer<7>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimer<8>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
cnt/LTimer<8>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimer<9>.D 11.0 10.0 11.0 11.0 11.0 11.0 11.0 11.0
|
cnt/LTimer<9>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimerTC.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
cnt/LTimerTC.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/Timer<0>.CE 10.0
|
cnt/Timer<0>.CE 10.0
|
||||||
cnt/Timer<0>.D 10.0
|
cnt/Timer<0>.D 10.0
|
||||||
|
@ -412,6 +415,8 @@ cnt/Timer<2>.CE 10.0
|
||||||
cnt/Timer<2>.D 10.0
|
cnt/Timer<2>.D 10.0
|
||||||
cnt/Timer<3>.CE 10.0
|
cnt/Timer<3>.CE 10.0
|
||||||
cnt/Timer<3>.D 10.0
|
cnt/Timer<3>.D 10.0
|
||||||
|
cnt/TimerTC.CE 10.0
|
||||||
|
cnt/TimerTC.D
|
||||||
cnt/WS<0>.D
|
cnt/WS<0>.D
|
||||||
cnt/WS<1>.D
|
cnt/WS<1>.D
|
||||||
cnt/WS<2>.D
|
cnt/WS<2>.D
|
||||||
|
@ -433,10 +438,10 @@ nCAS.D
|
||||||
nDTACK_FSB.D
|
nDTACK_FSB.D
|
||||||
nRESout.D 10.0 10.0
|
nRESout.D 10.0 10.0
|
||||||
nVPA_FSB.D
|
nVPA_FSB.D
|
||||||
|
ram/BACTr.D
|
||||||
ram/CAS.D
|
ram/CAS.D
|
||||||
ram/Once.D
|
|
||||||
ram/RAMEN.D
|
|
||||||
ram/RASEL.D
|
ram/RASEL.D
|
||||||
|
ram/RASEN.D
|
||||||
ram/RASrf.D
|
ram/RASrf.D
|
||||||
ram/RASrr.D
|
ram/RASrr.D
|
||||||
ram/RS_FSM_FFd1.D
|
ram/RS_FSM_FFd1.D
|
||||||
|
@ -447,6 +452,7 @@ ram/RS_FSM_FFd5.D
|
||||||
ram/RS_FSM_FFd6.D
|
ram/RS_FSM_FFd6.D
|
||||||
ram/RS_FSM_FFd7.D
|
ram/RS_FSM_FFd7.D
|
||||||
ram/RS_FSM_FFd8.D
|
ram/RS_FSM_FFd8.D
|
||||||
|
ram/RS_FSM_FFd9.D
|
||||||
ram/RefDone.D
|
ram/RefDone.D
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
|
@ -484,7 +490,7 @@ RAMReady.D
|
||||||
RefReq.CE
|
RefReq.CE
|
||||||
RefReq.D 10.0 10.0 10.0 10.0
|
RefReq.D 10.0 10.0 10.0 10.0
|
||||||
RefUrg.CE
|
RefUrg.CE
|
||||||
RefUrg.D 10.0 10.0 10.0 10.0
|
RefUrg.D 10.0 10.0 10.0
|
||||||
cnt/Er<1>.D
|
cnt/Er<1>.D
|
||||||
cnt/IS_FSM_FFd1.D 10.0
|
cnt/IS_FSM_FFd1.D 10.0
|
||||||
cnt/IS_FSM_FFd2.D 10.0
|
cnt/IS_FSM_FFd2.D 10.0
|
||||||
|
@ -499,7 +505,7 @@ cnt/LTimer<5>.D 10.0
|
||||||
cnt/LTimer<6>.D 10.0 10.0
|
cnt/LTimer<6>.D 10.0 10.0
|
||||||
cnt/LTimer<7>.D 10.0 10.0 10.0
|
cnt/LTimer<7>.D 10.0 10.0 10.0
|
||||||
cnt/LTimer<8>.D 10.0 10.0 10.0 10.0
|
cnt/LTimer<8>.D 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimer<9>.D 11.0 11.0 11.0 11.0 10.0
|
cnt/LTimer<9>.D 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/LTimerTC.D 10.0 10.0 10.0 10.0 10.0
|
cnt/LTimerTC.D 10.0 10.0 10.0 10.0 10.0
|
||||||
cnt/Timer<0>.CE
|
cnt/Timer<0>.CE
|
||||||
cnt/Timer<0>.D 10.0
|
cnt/Timer<0>.D 10.0
|
||||||
|
@ -509,6 +515,8 @@ cnt/Timer<2>.CE
|
||||||
cnt/Timer<2>.D 10.0 10.0 10.0
|
cnt/Timer<2>.D 10.0 10.0 10.0
|
||||||
cnt/Timer<3>.CE
|
cnt/Timer<3>.CE
|
||||||
cnt/Timer<3>.D 10.0 10.0 10.0 10.0
|
cnt/Timer<3>.D 10.0 10.0 10.0 10.0
|
||||||
|
cnt/TimerTC.CE
|
||||||
|
cnt/TimerTC.D 10.0 10.0 10.0 10.0
|
||||||
cnt/WS<0>.D
|
cnt/WS<0>.D
|
||||||
cnt/WS<1>.D
|
cnt/WS<1>.D
|
||||||
cnt/WS<2>.D
|
cnt/WS<2>.D
|
||||||
|
@ -530,10 +538,10 @@ nCAS.D
|
||||||
nDTACK_FSB.D
|
nDTACK_FSB.D
|
||||||
nRESout.D
|
nRESout.D
|
||||||
nVPA_FSB.D
|
nVPA_FSB.D
|
||||||
|
ram/BACTr.D
|
||||||
ram/CAS.D
|
ram/CAS.D
|
||||||
ram/Once.D
|
|
||||||
ram/RAMEN.D
|
|
||||||
ram/RASEL.D
|
ram/RASEL.D
|
||||||
|
ram/RASEN.D
|
||||||
ram/RASrf.D
|
ram/RASrf.D
|
||||||
ram/RASrr.D
|
ram/RASrr.D
|
||||||
ram/RS_FSM_FFd1.D
|
ram/RS_FSM_FFd1.D
|
||||||
|
@ -544,26 +552,27 @@ ram/RS_FSM_FFd5.D
|
||||||
ram/RS_FSM_FFd6.D
|
ram/RS_FSM_FFd6.D
|
||||||
ram/RS_FSM_FFd7.D
|
ram/RS_FSM_FFd7.D
|
||||||
ram/RS_FSM_FFd8.D
|
ram/RS_FSM_FFd8.D
|
||||||
|
ram/RS_FSM_FFd9.D
|
||||||
ram/RefDone.D
|
ram/RefDone.D
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
Clock to Setup (tCYC) (nsec)
|
Clock to Setup (tCYC) (nsec)
|
||||||
(Clock: FCLK)
|
(Clock: FCLK)
|
||||||
|
|
||||||
\ From c c c c c c f i i i
|
\ From c c c c c c c f i i
|
||||||
\ n n n n n s s o o o
|
\ n n n n n n s s o o
|
||||||
\ t t t t t / b b b b
|
\ t t t t t t / b b b
|
||||||
\ / / / / / n / s s s
|
\ / / / / / / n / s s
|
||||||
\ W W W W n O A / / /
|
\ T W W W W n O A / /
|
||||||
\ S S S S I v S C I I
|
\ i S S S S I v S C I
|
||||||
\ < < < < P e r l O O
|
\ m < < < < P e r l O
|
||||||
\ 0 1 2 3 L r f e A D
|
\ e 0 1 2 3 L r f e A
|
||||||
\ > > > > 2 l . a C O
|
\ r > > > > 2 l . a C
|
||||||
\ . . . . r a Q r T N
|
\ T . . . . r a Q r T
|
||||||
\ Q Q Q Q . y 1 r E
|
\ C Q Q Q Q . y 1 r
|
||||||
\ Q . . . r
|
\ . Q . . .
|
||||||
\ Q Q Q .
|
\ Q Q Q Q
|
||||||
\ Q
|
\
|
||||||
\
|
\
|
||||||
\
|
\
|
||||||
\
|
\
|
||||||
|
@ -571,108 +580,111 @@ ram/RefDone.D
|
||||||
To \------------------------------------------------------------
|
To \------------------------------------------------------------
|
||||||
|
|
||||||
ALE0S.D
|
ALE0S.D
|
||||||
IOL0.D 11.0 11.0
|
IOL0.D 11.0 11.0
|
||||||
IONPReady.D 11.0 11.0
|
IONPReady.D 11.0
|
||||||
IORDREQ.D 11.0 11.0 10.0
|
IORDREQ.D 11.4 11.4 10.0
|
||||||
IOU0.D 11.4 11.0
|
IOU0.D 11.4 11.0
|
||||||
IOWRREQ.D 11.0 11.0 10.0
|
IOWRREQ.D 11.0 11.0 10.0
|
||||||
QoSReady.D 11.4 11.4 11.4 11.4 19.1
|
QoSReady.D 11.4 11.4 11.4 11.4 19.1
|
||||||
RAMReady.D 10.0
|
RAMReady.D 11.4
|
||||||
RefReq.CE
|
RefReq.CE
|
||||||
RefReq.D
|
RefReq.D
|
||||||
RefUrg.CE
|
RefUrg.CE
|
||||||
RefUrg.D
|
RefUrg.D
|
||||||
cnt/Er<1>.D
|
cnt/Er<1>.D
|
||||||
cnt/IS_FSM_FFd1.D 10.0
|
cnt/IS_FSM_FFd1.D 10.0 10.0
|
||||||
cnt/IS_FSM_FFd2.D
|
cnt/IS_FSM_FFd2.D 10.0
|
||||||
cnt/LTimer<0>.D 20.1
|
cnt/LTimer<0>.D 19.1 20.5
|
||||||
cnt/LTimer<10>.D
|
cnt/LTimer<10>.D 10.0
|
||||||
cnt/LTimer<11>.D
|
cnt/LTimer<11>.D 10.0
|
||||||
cnt/LTimer<1>.D 20.1
|
cnt/LTimer<1>.D 19.1 20.5
|
||||||
cnt/LTimer<2>.D
|
cnt/LTimer<2>.D 10.0
|
||||||
cnt/LTimer<3>.D
|
cnt/LTimer<3>.D 10.0
|
||||||
cnt/LTimer<4>.D
|
cnt/LTimer<4>.D 10.0
|
||||||
cnt/LTimer<5>.D
|
cnt/LTimer<5>.D 10.0
|
||||||
cnt/LTimer<6>.D
|
cnt/LTimer<6>.D 10.0
|
||||||
cnt/LTimer<7>.D
|
cnt/LTimer<7>.D 10.0
|
||||||
cnt/LTimer<8>.D
|
cnt/LTimer<8>.D 10.0
|
||||||
cnt/LTimer<9>.D
|
cnt/LTimer<9>.D 10.0
|
||||||
cnt/LTimerTC.D
|
cnt/LTimerTC.D
|
||||||
cnt/Timer<0>.CE
|
cnt/Timer<0>.CE
|
||||||
cnt/Timer<0>.D
|
cnt/Timer<0>.D 10.0
|
||||||
cnt/Timer<1>.CE
|
cnt/Timer<1>.CE
|
||||||
cnt/Timer<1>.D
|
cnt/Timer<1>.D 10.0
|
||||||
cnt/Timer<2>.CE
|
cnt/Timer<2>.CE
|
||||||
cnt/Timer<2>.D
|
cnt/Timer<2>.D 10.0
|
||||||
cnt/Timer<3>.CE
|
cnt/Timer<3>.CE
|
||||||
cnt/Timer<3>.D
|
cnt/Timer<3>.D 10.0
|
||||||
cnt/WS<0>.D 10.0 10.0
|
cnt/TimerTC.CE
|
||||||
cnt/WS<1>.D 11.0 11.0 10.0
|
cnt/TimerTC.D
|
||||||
cnt/WS<2>.D 10.0 10.0 10.0 10.0
|
cnt/WS<0>.D 10.0 10.0
|
||||||
cnt/WS<3>.D 10.0 10.0 10.0 10.0 10.0
|
cnt/WS<1>.D 11.0 11.0 11.0
|
||||||
cs/nOverlay.D 11.0 11.0
|
cnt/WS<2>.D 10.0 10.0 10.0 10.0
|
||||||
|
cnt/WS<3>.D 10.0 10.0 10.0 10.0 10.0
|
||||||
|
cs/nOverlay.D 10.0 10.0
|
||||||
iobs/Clear1.D
|
iobs/Clear1.D
|
||||||
iobs/IOL1.CE
|
iobs/IOL1.CE
|
||||||
iobs/IORW1.D 11.0
|
iobs/IORW1.D 11.0
|
||||||
iobs/IOU1.CE
|
iobs/IOU1.CE
|
||||||
iobs/Load1.D 11.0
|
iobs/Load1.D 11.0
|
||||||
iobs/Sent.D 11.0 11.0
|
iobs/Sent.D 11.0 11.0
|
||||||
iobs/TS_FSM_FFd1.D 10.0
|
iobs/TS_FSM_FFd1.D 10.0
|
||||||
iobs/TS_FSM_FFd2.D 11.4 11.0 10.0
|
iobs/TS_FSM_FFd2.D 11.4 11.0 10.0
|
||||||
nADoutLE1.D 10.0
|
nADoutLE1.D 10.0
|
||||||
nAoutOE.D
|
nAoutOE.D
|
||||||
nBERR_FSB.D 10.0
|
nBERR_FSB.D 10.0
|
||||||
nBR_IOB.D 10.0
|
nBR_IOB.D 10.0
|
||||||
nCAS.D
|
nCAS.D
|
||||||
nDTACK_FSB.D 10.0
|
nDTACK_FSB.D 11.0
|
||||||
nRESout.D
|
nRESout.D
|
||||||
nVPA_FSB.D 10.0
|
nVPA_FSB.D 11.0
|
||||||
ram/CAS.D 11.0 11.0
|
ram/BACTr.D 10.0
|
||||||
ram/Once.D 10.0 10.0
|
ram/CAS.D 11.0 11.4
|
||||||
ram/RAMEN.D 11.0
|
ram/RASEL.D 10.0 10.0
|
||||||
ram/RASEL.D 10.0 10.0
|
ram/RASEN.D 11.4
|
||||||
ram/RASrf.D
|
ram/RASrf.D
|
||||||
ram/RASrr.D 10.0 10.0
|
ram/RASrr.D 10.0 10.0
|
||||||
ram/RS_FSM_FFd1.D
|
ram/RS_FSM_FFd1.D
|
||||||
ram/RS_FSM_FFd2.D
|
ram/RS_FSM_FFd2.D
|
||||||
ram/RS_FSM_FFd3.D
|
ram/RS_FSM_FFd3.D
|
||||||
ram/RS_FSM_FFd4.D
|
ram/RS_FSM_FFd4.D
|
||||||
ram/RS_FSM_FFd5.D
|
ram/RS_FSM_FFd5.D 10.0
|
||||||
ram/RS_FSM_FFd6.D 10.0
|
ram/RS_FSM_FFd6.D
|
||||||
ram/RS_FSM_FFd7.D 10.0 10.0
|
ram/RS_FSM_FFd7.D 10.0 10.0
|
||||||
ram/RS_FSM_FFd8.D 11.0 11.0
|
ram/RS_FSM_FFd8.D 11.0
|
||||||
|
ram/RS_FSM_FFd9.D 11.4 11.4
|
||||||
ram/RefDone.D
|
ram/RefDone.D
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
Clock to Setup (tCYC) (nsec)
|
Clock to Setup (tCYC) (nsec)
|
||||||
(Clock: FCLK)
|
(Clock: FCLK)
|
||||||
|
|
||||||
\ From i i i i i i i n n n
|
\ From i i i i i i i i n n
|
||||||
\ o o o o o o o A A B
|
\ o o o o o o o o A A
|
||||||
\ b b b b b b b D o E
|
\ b b b b b b b b D o
|
||||||
\ s s s s s s s o u R
|
\ s s s s s s s s o u
|
||||||
\ / / / / / / / u t R
|
\ / / / / / / / / u t
|
||||||
\ I I I L S T T t O _
|
\ I I I I L S T T t O
|
||||||
\ O O O o e S S L E F
|
\ O O O O o e S S L E
|
||||||
\ L R U a n _ _ E . S
|
\ D L R U a n _ _ E .
|
||||||
\ 1 W 1 d t F F 1 Q B
|
\ O 1 W 1 d t F F 1 Q
|
||||||
\ . 1 . 1 . S S . .
|
\ N . 1 . 1 . S S .
|
||||||
\ Q . Q . Q M M Q Q
|
\ E Q . Q . Q M M Q
|
||||||
\ Q Q _ _
|
\ r Q Q _ _
|
||||||
\ F F
|
\ . F F
|
||||||
\ F F
|
\ Q F F
|
||||||
\ d d
|
\ d d
|
||||||
\ 1 2
|
\ 1 2
|
||||||
\ . .
|
\ . .
|
||||||
\ Q Q
|
\ Q Q
|
||||||
To \------------------------------------------------------------
|
To \------------------------------------------------------------
|
||||||
|
|
||||||
ALE0S.D 10.0
|
ALE0S.D 10.0
|
||||||
IOL0.D 11.0 10.0 10.0 11.4 11.4
|
IOL0.D 11.0 10.0 10.0 11.4 11.4
|
||||||
IONPReady.D 11.0
|
IONPReady.D 11.0 11.0
|
||||||
IORDREQ.D 11.0 10.0 10.0 11.0 11.0
|
IORDREQ.D 11.0 11.0 10.0 11.4 11.4
|
||||||
IOU0.D 11.0 10.0 10.0 11.4 11.4
|
IOU0.D 11.0 10.0 10.0 11.4 11.4
|
||||||
IOWRREQ.D 10.0 11.0 11.0 11.0 11.0
|
IOWRREQ.D 10.0 11.0 11.0 11.0 11.0
|
||||||
QoSReady.D
|
QoSReady.D
|
||||||
RAMReady.D
|
RAMReady.D
|
||||||
RefReq.CE
|
RefReq.CE
|
||||||
|
@ -703,31 +715,33 @@ cnt/Timer<2>.CE
|
||||||
cnt/Timer<2>.D
|
cnt/Timer<2>.D
|
||||||
cnt/Timer<3>.CE
|
cnt/Timer<3>.CE
|
||||||
cnt/Timer<3>.D
|
cnt/Timer<3>.D
|
||||||
|
cnt/TimerTC.CE
|
||||||
|
cnt/TimerTC.D
|
||||||
cnt/WS<0>.D
|
cnt/WS<0>.D
|
||||||
cnt/WS<1>.D
|
cnt/WS<1>.D
|
||||||
cnt/WS<2>.D
|
cnt/WS<2>.D
|
||||||
cnt/WS<3>.D
|
cnt/WS<3>.D
|
||||||
cs/nOverlay.D
|
cs/nOverlay.D
|
||||||
iobs/Clear1.D 10.0 10.0
|
iobs/Clear1.D 10.0 10.0
|
||||||
iobs/IOL1.CE 10.0
|
iobs/IOL1.CE 10.0
|
||||||
iobs/IORW1.D 11.0 11.0 11.0 11.0 11.0
|
iobs/IORW1.D 11.0 11.0 11.0 11.0 11.0
|
||||||
iobs/IOU1.CE 10.0
|
iobs/IOU1.CE 10.0
|
||||||
iobs/Load1.D 11.0 11.0 11.0 11.0
|
iobs/Load1.D 11.0 11.0 11.0 11.0
|
||||||
iobs/Sent.D 11.0 11.0 11.0 11.0
|
iobs/Sent.D 11.0 11.0 11.0 11.0
|
||||||
iobs/TS_FSM_FFd1.D 10.0 10.0
|
iobs/TS_FSM_FFd1.D 10.0 10.0
|
||||||
iobs/TS_FSM_FFd2.D 10.0 10.0 11.4 11.4
|
iobs/TS_FSM_FFd2.D 10.0 10.0 11.4 11.4
|
||||||
nADoutLE1.D 10.0 10.0
|
nADoutLE1.D 10.0 10.0
|
||||||
nAoutOE.D 11.0
|
nAoutOE.D 11.0
|
||||||
nBERR_FSB.D 10.0 11.0
|
nBERR_FSB.D 10.0
|
||||||
nBR_IOB.D
|
nBR_IOB.D
|
||||||
nCAS.D
|
nCAS.D
|
||||||
nDTACK_FSB.D 11.0
|
nDTACK_FSB.D 11.4
|
||||||
nRESout.D
|
nRESout.D
|
||||||
nVPA_FSB.D
|
nVPA_FSB.D
|
||||||
|
ram/BACTr.D
|
||||||
ram/CAS.D
|
ram/CAS.D
|
||||||
ram/Once.D
|
|
||||||
ram/RAMEN.D
|
|
||||||
ram/RASEL.D
|
ram/RASEL.D
|
||||||
|
ram/RASEN.D
|
||||||
ram/RASrf.D
|
ram/RASrf.D
|
||||||
ram/RASrr.D
|
ram/RASrr.D
|
||||||
ram/RS_FSM_FFd1.D
|
ram/RS_FSM_FFd1.D
|
||||||
|
@ -738,29 +752,30 @@ ram/RS_FSM_FFd5.D
|
||||||
ram/RS_FSM_FFd6.D
|
ram/RS_FSM_FFd6.D
|
||||||
ram/RS_FSM_FFd7.D
|
ram/RS_FSM_FFd7.D
|
||||||
ram/RS_FSM_FFd8.D
|
ram/RS_FSM_FFd8.D
|
||||||
|
ram/RS_FSM_FFd9.D
|
||||||
ram/RefDone.D
|
ram/RefDone.D
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
Clock to Setup (tCYC) (nsec)
|
Clock to Setup (tCYC) (nsec)
|
||||||
(Clock: FCLK)
|
(Clock: FCLK)
|
||||||
|
|
||||||
\ From n r r r r r r r r r
|
\ From n n r r r r r r r r
|
||||||
\ B a a a a a a a a a
|
\ B B a a a a a a a a
|
||||||
\ R m m m m m m m m m
|
\ E R m m m m m m m m
|
||||||
\ _ / / / / / / / / /
|
\ R _ / / / / / / / /
|
||||||
\ I C O R R R R R R R
|
\ R I B C R R R R R R
|
||||||
\ O A n A S S S S S S
|
\ _ O A A A S S S S S
|
||||||
\ B S c M _ _ _ _ _ _
|
\ F B C S S _ _ _ _ _
|
||||||
\ . . e E F F F F F F
|
\ S . T . E F F F F F
|
||||||
\ Q Q . N S S S S S S
|
\ B Q r Q N S S S S S
|
||||||
\ Q . M M M M M M
|
\ . . . M M M M M
|
||||||
\ Q _ _ _ _ _ _
|
\ Q Q Q _ _ _ _ _
|
||||||
\ F F F F F F
|
\ F F F F F
|
||||||
\ F F F F F F
|
\ F F F F F
|
||||||
\ d d d d d d
|
\ d d d d d
|
||||||
\ 1 2 3 4 5 6
|
\ 1 2 3 4 5
|
||||||
\ . . . . . .
|
\ . . . . .
|
||||||
\ Q Q Q Q Q Q
|
\ Q Q Q Q Q
|
||||||
\
|
\
|
||||||
To \------------------------------------------------------------
|
To \------------------------------------------------------------
|
||||||
|
|
||||||
|
@ -771,7 +786,7 @@ IORDREQ.D
|
||||||
IOU0.D
|
IOU0.D
|
||||||
IOWRREQ.D
|
IOWRREQ.D
|
||||||
QoSReady.D
|
QoSReady.D
|
||||||
RAMReady.D 10.0
|
RAMReady.D 11.4 10.0 11.4 11.0 11.0 10.0 11.4
|
||||||
RefReq.CE
|
RefReq.CE
|
||||||
RefReq.D
|
RefReq.D
|
||||||
RefUrg.CE
|
RefUrg.CE
|
||||||
|
@ -800,6 +815,8 @@ cnt/Timer<2>.CE
|
||||||
cnt/Timer<2>.D
|
cnt/Timer<2>.D
|
||||||
cnt/Timer<3>.CE
|
cnt/Timer<3>.CE
|
||||||
cnt/Timer<3>.D
|
cnt/Timer<3>.D
|
||||||
|
cnt/TimerTC.CE
|
||||||
|
cnt/TimerTC.D
|
||||||
cnt/WS<0>.D
|
cnt/WS<0>.D
|
||||||
cnt/WS<1>.D
|
cnt/WS<1>.D
|
||||||
cnt/WS<2>.D
|
cnt/WS<2>.D
|
||||||
|
@ -814,125 +831,129 @@ iobs/Sent.D
|
||||||
iobs/TS_FSM_FFd1.D
|
iobs/TS_FSM_FFd1.D
|
||||||
iobs/TS_FSM_FFd2.D
|
iobs/TS_FSM_FFd2.D
|
||||||
nADoutLE1.D
|
nADoutLE1.D
|
||||||
nAoutOE.D 11.0
|
nAoutOE.D 11.0
|
||||||
nBERR_FSB.D
|
nBERR_FSB.D 11.0
|
||||||
nBR_IOB.D 10.0
|
nBR_IOB.D 10.0
|
||||||
nCAS.D 10.0
|
nCAS.D 10.0
|
||||||
nDTACK_FSB.D
|
nDTACK_FSB.D
|
||||||
nRESout.D
|
nRESout.D
|
||||||
nVPA_FSB.D
|
nVPA_FSB.D
|
||||||
ram/CAS.D 11.0 11.0 10.0
|
ram/BACTr.D
|
||||||
ram/Once.D 10.0 10.0
|
ram/CAS.D 11.4 10.0 11.0
|
||||||
ram/RAMEN.D 10.0 10.0 10.0
|
ram/RASEL.D 10.0
|
||||||
ram/RASEL.D 10.0
|
ram/RASEN.D 11.0 11.4 10.0 10.0 10.0 10.0 11.0
|
||||||
ram/RASrf.D
|
ram/RASrf.D
|
||||||
ram/RASrr.D 10.0 10.0 10.0
|
ram/RASrr.D 10.0 10.0
|
||||||
ram/RS_FSM_FFd1.D 10.0
|
ram/RS_FSM_FFd1.D 10.0
|
||||||
ram/RS_FSM_FFd2.D 10.0
|
ram/RS_FSM_FFd2.D 10.0
|
||||||
ram/RS_FSM_FFd3.D 10.0
|
ram/RS_FSM_FFd3.D 10.0
|
||||||
ram/RS_FSM_FFd4.D 10.0 10.0
|
ram/RS_FSM_FFd4.D
|
||||||
ram/RS_FSM_FFd5.D
|
ram/RS_FSM_FFd5.D 10.0
|
||||||
ram/RS_FSM_FFd6.D 10.0
|
ram/RS_FSM_FFd6.D
|
||||||
ram/RS_FSM_FFd7.D 10.0
|
ram/RS_FSM_FFd7.D 10.0
|
||||||
ram/RS_FSM_FFd8.D 11.0 11.0
|
ram/RS_FSM_FFd8.D 11.0 10.0 11.0
|
||||||
ram/RefDone.D 10.0 10.0
|
ram/RS_FSM_FFd9.D 11.4 11.4 10.0 11.0
|
||||||
|
ram/RefDone.D 10.0 10.0 10.0 10.0
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
Clock to Setup (tCYC) (nsec)
|
Clock to Setup (tCYC) (nsec)
|
||||||
(Clock: FCLK)
|
(Clock: FCLK)
|
||||||
|
|
||||||
\ From r r r
|
\ From r r r r r
|
||||||
\ a a a
|
\ a a a a a
|
||||||
\ m m m
|
\ m m m m m
|
||||||
\ / / /
|
\ / / / / /
|
||||||
\ R R R
|
\ R R R R R
|
||||||
\ S S e
|
\ S S S S e
|
||||||
\ _ _ f
|
\ _ _ _ _ f
|
||||||
\ F F D
|
\ F F F F D
|
||||||
\ S S o
|
\ S S S S o
|
||||||
\ M M n
|
\ M M M M n
|
||||||
\ _ _ e
|
\ _ _ _ _ e
|
||||||
\ F F .
|
\ F F F F .
|
||||||
\ F F Q
|
\ F F F F Q
|
||||||
\ d d
|
\ d d d d
|
||||||
\ 7 8
|
\ 6 7 8 9
|
||||||
\ . .
|
\ . . . .
|
||||||
\ Q Q
|
\ Q Q Q Q
|
||||||
\
|
\
|
||||||
To \------------------
|
To \------------------------------
|
||||||
|
|
||||||
ALE0S.D
|
ALE0S.D
|
||||||
IOL0.D
|
IOL0.D
|
||||||
IONPReady.D
|
IONPReady.D
|
||||||
IORDREQ.D
|
IORDREQ.D
|
||||||
IOU0.D
|
IOU0.D
|
||||||
IOWRREQ.D
|
IOWRREQ.D
|
||||||
QoSReady.D
|
QoSReady.D
|
||||||
RAMReady.D 10.0 10.0
|
RAMReady.D 11.4 11.4 10.0 11.4 11.4
|
||||||
RefReq.CE
|
RefReq.CE
|
||||||
RefReq.D
|
RefReq.D
|
||||||
RefUrg.CE
|
RefUrg.CE
|
||||||
RefUrg.D
|
RefUrg.D
|
||||||
cnt/Er<1>.D
|
cnt/Er<1>.D
|
||||||
cnt/IS_FSM_FFd1.D
|
cnt/IS_FSM_FFd1.D
|
||||||
cnt/IS_FSM_FFd2.D
|
cnt/IS_FSM_FFd2.D
|
||||||
cnt/LTimer<0>.D
|
cnt/LTimer<0>.D
|
||||||
cnt/LTimer<10>.D
|
cnt/LTimer<10>.D
|
||||||
cnt/LTimer<11>.D
|
cnt/LTimer<11>.D
|
||||||
cnt/LTimer<1>.D
|
cnt/LTimer<1>.D
|
||||||
cnt/LTimer<2>.D
|
cnt/LTimer<2>.D
|
||||||
cnt/LTimer<3>.D
|
cnt/LTimer<3>.D
|
||||||
cnt/LTimer<4>.D
|
cnt/LTimer<4>.D
|
||||||
cnt/LTimer<5>.D
|
cnt/LTimer<5>.D
|
||||||
cnt/LTimer<6>.D
|
cnt/LTimer<6>.D
|
||||||
cnt/LTimer<7>.D
|
cnt/LTimer<7>.D
|
||||||
cnt/LTimer<8>.D
|
cnt/LTimer<8>.D
|
||||||
cnt/LTimer<9>.D
|
cnt/LTimer<9>.D
|
||||||
cnt/LTimerTC.D
|
cnt/LTimerTC.D
|
||||||
cnt/Timer<0>.CE
|
cnt/Timer<0>.CE
|
||||||
cnt/Timer<0>.D
|
cnt/Timer<0>.D
|
||||||
cnt/Timer<1>.CE
|
cnt/Timer<1>.CE
|
||||||
cnt/Timer<1>.D
|
cnt/Timer<1>.D
|
||||||
cnt/Timer<2>.CE
|
cnt/Timer<2>.CE
|
||||||
cnt/Timer<2>.D
|
cnt/Timer<2>.D
|
||||||
cnt/Timer<3>.CE
|
cnt/Timer<3>.CE
|
||||||
cnt/Timer<3>.D
|
cnt/Timer<3>.D
|
||||||
cnt/WS<0>.D
|
cnt/TimerTC.CE
|
||||||
cnt/WS<1>.D
|
cnt/TimerTC.D
|
||||||
cnt/WS<2>.D
|
cnt/WS<0>.D
|
||||||
cnt/WS<3>.D
|
cnt/WS<1>.D
|
||||||
cs/nOverlay.D
|
cnt/WS<2>.D
|
||||||
iobs/Clear1.D
|
cnt/WS<3>.D
|
||||||
iobs/IOL1.CE
|
cs/nOverlay.D
|
||||||
iobs/IORW1.D
|
iobs/Clear1.D
|
||||||
iobs/IOU1.CE
|
iobs/IOL1.CE
|
||||||
iobs/Load1.D
|
iobs/IORW1.D
|
||||||
iobs/Sent.D
|
iobs/IOU1.CE
|
||||||
iobs/TS_FSM_FFd1.D
|
iobs/Load1.D
|
||||||
iobs/TS_FSM_FFd2.D
|
iobs/Sent.D
|
||||||
nADoutLE1.D
|
iobs/TS_FSM_FFd1.D
|
||||||
nAoutOE.D
|
iobs/TS_FSM_FFd2.D
|
||||||
nBERR_FSB.D
|
nADoutLE1.D
|
||||||
nBR_IOB.D
|
nAoutOE.D
|
||||||
nCAS.D
|
nBERR_FSB.D
|
||||||
nDTACK_FSB.D
|
nBR_IOB.D
|
||||||
nRESout.D
|
nCAS.D
|
||||||
nVPA_FSB.D
|
nDTACK_FSB.D
|
||||||
ram/CAS.D 10.0 11.0 11.0
|
nRESout.D
|
||||||
ram/Once.D 10.0
|
nVPA_FSB.D
|
||||||
ram/RAMEN.D 10.0 11.0 11.0
|
ram/BACTr.D
|
||||||
ram/RASEL.D 10.0 10.0
|
ram/CAS.D 10.0 10.0 11.4 11.4
|
||||||
ram/RASrf.D 10.0
|
ram/RASEL.D 10.0 10.0
|
||||||
ram/RASrr.D 10.0
|
ram/RASEN.D 10.0 10.0 10.0 11.4 11.0
|
||||||
ram/RS_FSM_FFd1.D
|
ram/RASrf.D 10.0
|
||||||
ram/RS_FSM_FFd2.D
|
ram/RASrr.D 10.0 10.0
|
||||||
ram/RS_FSM_FFd3.D
|
ram/RS_FSM_FFd1.D
|
||||||
ram/RS_FSM_FFd4.D 10.0
|
ram/RS_FSM_FFd2.D
|
||||||
ram/RS_FSM_FFd5.D 10.0
|
ram/RS_FSM_FFd3.D
|
||||||
ram/RS_FSM_FFd6.D 10.0 10.0
|
ram/RS_FSM_FFd4.D 10.0
|
||||||
ram/RS_FSM_FFd7.D 10.0
|
ram/RS_FSM_FFd5.D 10.0
|
||||||
ram/RS_FSM_FFd8.D 10.0 10.0
|
ram/RS_FSM_FFd6.D 10.0
|
||||||
ram/RefDone.D 10.0
|
ram/RS_FSM_FFd7.D 10.0
|
||||||
|
ram/RS_FSM_FFd8.D 11.0 11.0
|
||||||
|
ram/RS_FSM_FFd9.D 11.4 11.0
|
||||||
|
ram/RefDone.D 10.0 10.0
|
||||||
|
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
Clock to Setup (tCYC) (nsec)
|
Clock to Setup (tCYC) (nsec)
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
|
@ -5,7 +5,7 @@
|
||||||
The structure and the elements are likely to change over the next few releases.
|
The structure and the elements are likely to change over the next few releases.
|
||||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||||
|
|
||||||
<application stringID="NgdBuild" timeStamp="Sun Apr 09 23:31:16 2023">
|
<application stringID="NgdBuild" timeStamp="Mon Apr 10 04:04:57 2023">
|
||||||
<section stringID="User_Env">
|
<section stringID="User_Env">
|
||||||
<table stringID="User_EnvVar">
|
<table stringID="User_EnvVar">
|
||||||
<column stringID="variable"/>
|
<column stringID="variable"/>
|
||||||
|
@ -66,36 +66,36 @@
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||||
</section>
|
</section>
|
||||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="202"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="222"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="27"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="30"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="12"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="65"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="68"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="2"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="2"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="30"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="29"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="1"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="1"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="6"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="6"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="253"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="277"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="30"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="30"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="112"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="119"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="9"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="20"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="20"/>
|
||||||
</section>
|
</section>
|
||||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="202"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="222"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="27"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="30"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="12"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="74"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="77"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="41"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="41"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="253"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="277"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="30"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="30"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="112"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="119"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="9"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="2"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="20"/>
|
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="20"/>
|
||||||
</section>
|
</section>
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
Release 8.1i - Fit P.20131013
|
Release 8.1i - Fit P.20131013
|
||||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||||
|
|
||||||
4- 9-2023 11:31PM
|
4-10-2023 4:05AM
|
||||||
|
|
||||||
NOTE: This file is designed to be imported into a spreadsheet program
|
NOTE: This file is designed to be imported into a spreadsheet program
|
||||||
such as Microsoft Excel for viewing, printing and sorting. The comma ','
|
such as Microsoft Excel for viewing, printing and sorting. The comma ','
|
||||||
|
|
|
|
@ -5,7 +5,7 @@
|
||||||
The structure and the elements are likely to change over the next few releases.
|
The structure and the elements are likely to change over the next few releases.
|
||||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||||
|
|
||||||
<application stringID="Xst" timeStamp="Sun Apr 09 23:31:05 2023">
|
<application stringID="Xst" timeStamp="Mon Apr 10 04:04:47 2023">
|
||||||
<section stringID="User_Env">
|
<section stringID="User_Env">
|
||||||
<table stringID="User_EnvVar">
|
<table stringID="User_EnvVar">
|
||||||
<column stringID="variable"/>
|
<column stringID="variable"/>
|
||||||
|
@ -79,8 +79,8 @@
|
||||||
<item dataType="int" stringID="XST_COUNTERS" value="3">
|
<item dataType="int" stringID="XST_COUNTERS" value="3">
|
||||||
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="3"/>
|
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="3"/>
|
||||||
</item>
|
</item>
|
||||||
<item dataType="int" stringID="XST_REGISTERS" value="66">
|
<item dataType="int" stringID="XST_REGISTERS" value="67">
|
||||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="65"/>
|
<item dataType="int" stringID="XST_1BIT_REGISTER" value="66"/>
|
||||||
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
|
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
|
||||||
</item>
|
</item>
|
||||||
<item dataType="int" stringID="XST_TRISTATES" value="5">
|
<item dataType="int" stringID="XST_TRISTATES" value="5">
|
||||||
|
@ -93,8 +93,8 @@
|
||||||
<item dataType="int" stringID="XST_COUNTERS" value="3">
|
<item dataType="int" stringID="XST_COUNTERS" value="3">
|
||||||
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="3"/>
|
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="3"/>
|
||||||
</item>
|
</item>
|
||||||
<item dataType="int" stringID="XST_REGISTERS" value="44">
|
<item dataType="int" stringID="XST_REGISTERS" value="47">
|
||||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="44"/>
|
<item dataType="int" stringID="XST_FLIPFLOPS" value="47"/>
|
||||||
</item>
|
</item>
|
||||||
</section>
|
</section>
|
||||||
<section stringID="XST_PARTITION_REPORT">
|
<section stringID="XST_PARTITION_REPORT">
|
||||||
|
@ -114,20 +114,20 @@
|
||||||
<item stringID="XST_IOS" value="75"/>
|
<item stringID="XST_IOS" value="75"/>
|
||||||
</section>
|
</section>
|
||||||
<section stringID="XST_CELL_USAGE">
|
<section stringID="XST_CELL_USAGE">
|
||||||
<item dataType="int" stringID="XST_BELS" value="653">
|
<item dataType="int" stringID="XST_BELS" value="710">
|
||||||
<item dataType="int" stringID="XST_AND2" value="202"/>
|
<item dataType="int" stringID="XST_AND2" value="222"/>
|
||||||
<item dataType="int" stringID="XST_AND3" value="27"/>
|
<item dataType="int" stringID="XST_AND3" value="30"/>
|
||||||
<item dataType="int" stringID="XST_AND4" value="13"/>
|
<item dataType="int" stringID="XST_AND4" value="12"/>
|
||||||
<item dataType="int" stringID="XST_GND" value="6"/>
|
<item dataType="int" stringID="XST_GND" value="6"/>
|
||||||
<item dataType="int" stringID="XST_INV" value="253"/>
|
<item dataType="int" stringID="XST_INV" value="277"/>
|
||||||
<item dataType="int" stringID="XST_OR2" value="112"/>
|
<item dataType="int" stringID="XST_OR2" value="119"/>
|
||||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||||
<item dataType="int" stringID="XST_XOR2" value="20"/>
|
<item dataType="int" stringID="XST_XOR2" value="20"/>
|
||||||
</item>
|
</item>
|
||||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="98">
|
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="100">
|
||||||
<item dataType="int" stringID="XST_FD" value="65"/>
|
<item dataType="int" stringID="XST_FD" value="68"/>
|
||||||
<item dataType="int" stringID="XST_FDC" value="2"/>
|
<item dataType="int" stringID="XST_FDC" value="2"/>
|
||||||
<item dataType="int" stringID="XST_FDCE" value="30"/>
|
<item dataType="int" stringID="XST_FDCE" value="29"/>
|
||||||
<item dataType="int" stringID="XST_FDP" value="1"/>
|
<item dataType="int" stringID="XST_FDP" value="1"/>
|
||||||
</item>
|
</item>
|
||||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="70">
|
<item dataType="int" stringID="XST_IO_BUFFERS" value="70">
|
||||||
|
@ -138,7 +138,7 @@
|
||||||
</section>
|
</section>
|
||||||
<section stringID="XST_ERRORS_STATISTICS">
|
<section stringID="XST_ERRORS_STATISTICS">
|
||||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="4"/>
|
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="3"/>
|
||||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
|
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
|
||||||
</section>
|
</section>
|
||||||
</application>
|
</application>
|
||||||
|
|
|
@ -1,2 +1,2 @@
|
||||||
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1681097470
|
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1681113892
|
||||||
OK
|
OK
|
||||||
|
|
|
@ -8,26 +8,8 @@
|
||||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||||
|
|
||||||
<messages>
|
<messages>
|
||||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/CNT.v" into library work</arg>
|
|
||||||
</msg>
|
|
||||||
|
|
||||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/CS.v" into library work</arg>
|
|
||||||
</msg>
|
|
||||||
|
|
||||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/FSB.v" into library work</arg>
|
|
||||||
</msg>
|
|
||||||
|
|
||||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/IOBM.v" into library work</arg>
|
|
||||||
</msg>
|
|
||||||
|
|
||||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/IOBS.v" into library work</arg>
|
|
||||||
</msg>
|
|
||||||
|
|
||||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/RAM.v" into library work</arg>
|
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/RAM.v" into library work</arg>
|
||||||
</msg>
|
</msg>
|
||||||
|
|
||||||
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE.v" into library work</arg>
|
|
||||||
</msg>
|
|
||||||
|
|
||||||
</messages>
|
</messages>
|
||||||
|
|
||||||
|
|
|
@ -5,9 +5,6 @@
|
||||||
behavior or data corruption. It is strongly advised that
|
behavior or data corruption. It is strongly advised that
|
||||||
users do not edit the contents of this file. -->
|
users do not edit the contents of this file. -->
|
||||||
<messages>
|
<messages>
|
||||||
<msg type="warning" file="Xst" num="646" delta="old" >Signal <<arg fmt="%s" index="1">BACTr</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
||||||
</msg>
|
|
||||||
|
|
||||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">C20MEN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">C20MEN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||||
</msg>
|
</msg>
|
||||||
|
|
||||||
|
|
|
@ -23,13 +23,13 @@
|
||||||
<ClosedNode>Design Utilities</ClosedNode>
|
<ClosedNode>Design Utilities</ClosedNode>
|
||||||
</ClosedNodes>
|
</ClosedNodes>
|
||||||
<SelectedItems>
|
<SelectedItems>
|
||||||
<SelectedItem/>
|
<SelectedItem></SelectedItem>
|
||||||
</SelectedItems>
|
</SelectedItems>
|
||||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
|
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
|
||||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||||
<CurrentItem/>
|
<CurrentItem></CurrentItem>
|
||||||
</ItemView>
|
</ItemView>
|
||||||
<ItemView guiview="File" >
|
<ItemView guiview="File" >
|
||||||
<ClosedNodes>
|
<ClosedNodes>
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
<?xml version='1.0' encoding='UTF-8'?>
|
<?xml version='1.0' encoding='UTF-8'?>
|
||||||
<report-views version="2.0" >
|
<report-views version="2.0" >
|
||||||
<header>
|
<header>
|
||||||
<DateModified>2023-04-09T23:31:34</DateModified>
|
<DateModified>2023-04-10T03:54:15</DateModified>
|
||||||
<ModuleName>WarpSE</ModuleName>
|
<ModuleName>WarpSE</ModuleName>
|
||||||
<SummaryTimeStamp>2023-04-09T23:24:43</SummaryTimeStamp>
|
<SummaryTimeStamp>2023-04-09T23:24:43</SummaryTimeStamp>
|
||||||
<SavedFilePath>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
|
<SavedFilePath>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
|
||||||
|
|
|
@ -3,7 +3,7 @@
|
||||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||||
The structure and the elements are likely to change over the next few releases.
|
The structure and the elements are likely to change over the next few releases.
|
||||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||||
<application name="pn" timeStamp="Sun Apr 09 23:31:05 2023">
|
<application name="pn" timeStamp="Mon Apr 10 04:04:46 2023">
|
||||||
<section name="Project Information" visible="false">
|
<section name="Project Information" visible="false">
|
||||||
<property name="ProjectID" value="7132971001B64D51887D7F260ADC77C3" type="project"/>
|
<property name="ProjectID" value="7132971001B64D51887D7F260ADC77C3" type="project"/>
|
||||||
<property name="ProjectIteration" value="0" type="project"/>
|
<property name="ProjectIteration" value="0" type="project"/>
|
||||||
|
|
Binary file not shown.
|
@ -1,7 +1,7 @@
|
||||||
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1681097466
|
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1681113887
|
||||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1681097466
|
MO CS NULL ../CS.v vlg22/_c_s.bin 1681113887
|
||||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1681097466
|
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1681113887
|
||||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1681097466
|
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1681113887
|
||||||
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1681097466
|
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1681113887
|
||||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1681097466
|
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1681113887
|
||||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1681097466
|
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1681113887
|
||||||
|
|
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Loading…
Reference in New Issue