Works. IOPWReady eliminated
This commit is contained in:
Zane Kaminski
parent
8e273169a0
commit
f6ac67ba30
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@ -660,3 +660,9 @@ XSLTProcess WarpSE_build.xml
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tsim -intstyle ise WarpSE WarpSE.nga
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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taengine -intstyle ise -f WarpSE -w --format html1 -l WarpSE_html/tim/timing_report.htm
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xst -intstyle ise -ifn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.xst" -ofn "C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/WarpSE.syr"
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ngdbuild -intstyle ise -dd _ngo -uc C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/WarpSE-XC95144XL.ucf -p xc95144xl-TQ100-10 WarpSE.ngc WarpSE.ngd
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cpldfit -intstyle ise -p xc95144xl-10-TQ100 -ofmt vhdl -optimize speed -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper WarpSE.ngd
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tsim -intstyle ise WarpSE WarpSE.nga
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hprep6 -s IEEE1149 -n WarpSE -i WarpSE
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taengine -intstyle ise -f WarpSE -l WarpSE.tim -e {C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\taengine.err}
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File diff suppressed because it is too large
Load Diff
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@ -59,15 +59,15 @@
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema">
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<transform xil_pn:end_ts="1680947820" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1680947820">
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<transform xil_pn:end_ts="1681097464" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1681097464">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1680947820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8819683973431472423" xil_pn:start_ts="1680947820">
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<transform xil_pn:end_ts="1681097464" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8819683973431472423" xil_pn:start_ts="1681097464">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1681030881" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1681030873">
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<transform xil_pn:end_ts="1681097472" xil_pn:in_ck="5474524715461797957" xil_pn:name="TRANEXT_xstsynthesize_xc9500xl" xil_pn:prop_ck="-827049739915084467" xil_pn:start_ts="1681097464">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -83,11 +83,11 @@
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<outfile xil_pn:name="webtalk_pn.xml"/>
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<outfile xil_pn:name="xst"/>
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</transform>
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<transform xil_pn:end_ts="1680947827" xil_pn:in_ck="-6638154780101949348" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704756" xil_pn:start_ts="1680947827">
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<transform xil_pn:end_ts="1681097472" xil_pn:in_ck="-6638154780101949348" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704756" xil_pn:start_ts="1681097472">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1681030886" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1681030881">
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<transform xil_pn:end_ts="1681097477" xil_pn:in_ck="814020912342028692" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="1893441463969615248" xil_pn:start_ts="1681097472">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="WarpSE.bld"/>
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@ -96,7 +96,7 @@
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<outfile xil_pn:name="_ngo"/>
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<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1681030912" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1681030886">
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<transform xil_pn:end_ts="1681097494" xil_pn:in_ck="4179227257693753" xil_pn:name="TRANEXT_vm6File_xc9500xl" xil_pn:prop_ck="3294015560432670715" xil_pn:start_ts="1681097477">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -114,12 +114,12 @@
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<outfile xil_pn:name="WarpSE_html"/>
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<outfile xil_pn:name="WarpSE_pad.csv"/>
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</transform>
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<transform xil_pn:end_ts="1681030914" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1681030912">
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<transform xil_pn:end_ts="1681097496" xil_pn:in_ck="4179227257702617" xil_pn:name="TRANEXT_crtProg_xc9500" xil_pn:prop_ck="-6294026017969277533" xil_pn:start_ts="1681097494">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="WarpSE.jed"/>
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</transform>
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<transform xil_pn:end_ts="1681030918" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1681030915">
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<transform xil_pn:end_ts="1681097561" xil_pn:in_ck="4179227257702617" xil_pn:name="TRAN_timRpt" xil_pn:prop_ck="111903974446" xil_pn:start_ts="1681097559">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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@ -76,31 +76,31 @@ nVPA_FSB S:PIN93
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;The remaining section of the .gyd file is for documentation purposes only.
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;It shows where your internal equations were placed in the last successful fit.
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PARTITION FB1_1 iobs/Clear1 iobm/Er cnt/nIPL2r cnt/Er<1>
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cnt/Er<0> ram/RS_FSM_FFd4 iobs/TS_FSM_FFd1 iobs/IOU1
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cnt/Timer<0> cnt/IS_FSM_FFd2 RefUrg RefReq
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IOPWReady IOBERR iobm/ES<2> cnt/Timer<1>
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PARTITION FB1_1 ram/RS_FSM_FFd2 ram/RS_FSM_FFd1 iobm/Er cnt/Er<1>
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cnt/Er<0> ram/RefDone ram/RS_FSM_FFd4 iobs/TS_FSM_FFd1
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iobs/IOU1 iobs/IOL1 cnt/Timer<0> cnt/IS_FSM_FFd2
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RefUrg RefReq iobm/ES<2> cnt/Timer<1>
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cnt/Timer<3> cnt/Timer<2>
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PARTITION FB2_4 ram/RS_FSM_FFd5 ram/RS_FSM_FFd3 ram/RS_FSM_FFd2 ram/RS_FSM_FFd1
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ram/RASrf iobs/IODONEr iobs/IOACTr iobm/VPAr
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iobm/IOWRREQr iobm/IOS_FSM_FFd5 iobm/IOS_FSM_FFd4 iobm/IOS_FSM_FFd1
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iobm/IORDREQr iobm/C8Mr iobm/IOS_FSM_FFd2
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PARTITION FB3_1 iobs/Sent ram/RefDone ram/RS_FSM_FFd7 cs/nOverlay
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ram/RS_FSM_FFd6 ram/RASrr ram/RASEL ram/Once
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PARTITION FB2_4 ram/RS_FSM_FFd5 ram/RS_FSM_FFd3 ram/RASrf iobs/IODONEr
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iobs/IOACTr iobm/VPAr iobm/IOWRREQr iobm/IOS_FSM_FFd5
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iobm/IOS_FSM_FFd4 iobm/IOS_FSM_FFd1 iobm/IORDREQr iobm/C8Mr
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cnt/nIPL2r iobm/IOS_FSM_FFd2 IOBERR
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PARTITION FB3_1 iobs/Sent iobs/Clear1 ram/RS_FSM_FFd7 ram/RS_FSM_FFd6
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ram/RASEL ram/RASrr ram/Once cs/nOverlay
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nDTACK_FSB_OBUF RAMReady ram/RS_FSM_FFd8 ram/RAMEN
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EXP10_ ram/CAS iobs/Load1 IORDREQ
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nROMWE_OBUF EXP11_
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PARTITION FB4_1 QoSReady nAoutOE_OBUF fsb/ASrf cnt/WS<0>
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nDoutOE_OBUF nDinOE_OBUF $OpTx$$OpTx$FX_DC$354_INV$541 N0
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iobs/IOL1 cs/ODCSr nVPA_FSB_OBUF cnt/WS<2>
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cnt/WS<1> IONPReady cnt/LTimer<1> cnt/WS<3>
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nRESout EXP12_
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PARTITION FB5_1 EXP13_ nROMCS_OBUF
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PARTITION FB4_1 QoSReady nAoutOE_OBUF nRESout fsb/ASrf
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nDoutOE_OBUF nDinOE_OBUF cnt/WS<0> N0
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ALE0S $OpTx$$OpTx$FX_DC$354_INV$541 nVPA_FSB_OBUF cnt/WS<3>
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cnt/WS<2> cnt/WS<1> IONPReady EXP12_
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cnt/LTimer<1> EXP13_
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PARTITION FB5_1 EXP14_ nROMCS_OBUF
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PARTITION FB5_5 nCAS_OBUF nOE_OBUF
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PARTITION FB5_9 RA_4_OBUF
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PARTITION FB5_11 RA_11_OBUF RA_5_OBUF cnt/LTimerTC RA_2_OBUF
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RA_6_OBUF ALE0S EXP14_ cnt/LTimer<0>
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PARTITION FB5_11 RA_11_OBUF RA_5_OBUF
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PARTITION FB5_14 RA_2_OBUF RA_6_OBUF cnt/LTimerTC EXP15_
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cnt/LTimer<0>
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PARTITION FB6_1 iobm/IOS_FSM_FFd6 nVMA_IOBout iobm/IOS_FSM_FFd7 iobm/IOS_FSM_FFd3
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iobm/ES<0> iobm/ES<3> iobm/ES<1> iobm/DoutOE
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nLDS_IOBout IODONE nUDS_IOBout nAS_IOBout
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@ -111,9 +111,9 @@ PARTITION FB7_1 cnt/LTimer<9> RA_1_OBUF cnt/LTimer<8> cnt/LTimer<7>
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RA_10_OBUF cnt/LTimer<5> RA_9_OBUF C25MEN_OBUF
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cnt/LTimer<4> cnt/LTimer<3> cnt/LTimer<2> cnt/LTimer<11>
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cnt/LTimer<10> cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2
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PARTITION FB8_1 IOL0 RA_11_OBUF$BUF0 iobs/TS_FSM_FFd2 EXP15_
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nRAS_OBUF nRAMLWE_OBUF EXP16_ nRAMUWE_OBUF
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IOWRREQ EXP17_ EXP18_ nBERR_FSB_OBUF
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EXP19_ IOU0 nBR_IOB_OBUF cnt/IS_FSM_FFd1
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iobs/IORW1 EXP20_
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PARTITION FB8_1 IOL0 RA_11_OBUF$BUF0 iobs/TS_FSM_FFd2 EXP16_
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nRAS_OBUF nRAMLWE_OBUF EXP17_ nRAMUWE_OBUF
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IOWRREQ EXP18_ EXP19_ nBERR_FSB_OBUF
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EXP20_ IOU0 nBR_IOB_OBUF cnt/IS_FSM_FFd1
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iobs/IORW1 EXP21_
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,223 @@
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MODEL
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MODEL_VERSION "v1998.8";
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DESIGN "WarpSE";
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/* port names and type */
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INPUT S:PIN24 = A_FSB<23>;
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INPUT S:PIN20 = A_FSB<22>;
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INPUT S:PIN19 = A_FSB<21>;
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INPUT S:PIN18 = A_FSB<20>;
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INPUT S:PIN17 = A_FSB<19>;
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INPUT S:PIN16 = A_FSB<18>;
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INPUT S:PIN15 = A_FSB<17>;
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INPUT S:PIN14 = A_FSB<16>;
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INPUT S:PIN13 = A_FSB<15>;
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INPUT S:PIN11 = A_FSB<13>;
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INPUT S:PIN10 = A_FSB<12>;
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INPUT S:PIN23 = C8M;
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INPUT S:PIN22 = C16M;
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INPUT S:PIN12 = A_FSB<14>;
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INPUT S:PIN9 = A_FSB<11>;
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INPUT S:PIN8 = A_FSB<10>;
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INPUT S:PIN27 = FCLK;
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INPUT S:PIN29 = nWE_FSB;
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INPUT S:PIN32 = nAS_FSB;
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INPUT S:PIN6 = A_FSB<8>;
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INPUT S:PIN7 = A_FSB<9>;
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INPUT S:PIN76 = nBERR_IOB;
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INPUT S:PIN78 = nDTACK_IOB;
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INPUT S:PIN30 = nLDS_FSB;
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INPUT S:PIN33 = nUDS_FSB;
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INPUT S:PIN25 = E;
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INPUT S:PIN92 = nIPL2;
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INPUT S:PIN77 = nVPA_IOB;
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INPUT S:PIN94 = A_FSB<1>;
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INPUT S:PIN4 = A_FSB<7>;
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INPUT S:PIN95 = A_FSB<2>;
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INPUT S:PIN96 = A_FSB<3>;
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INPUT S:PIN97 = A_FSB<4>;
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INPUT S:PIN2 = A_FSB<5>;
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INPUT S:PIN3 = A_FSB<6>;
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TRIOUT S:PIN91 = nRES;
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TRIOUT S:PIN74 = nVMA_IOB;
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TRIOUT S:PIN81 = nAS_IOB;
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TRIOUT S:PIN79 = nLDS_IOB;
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TRIOUT S:PIN80 = nUDS_IOB;
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OUTPUT S:PIN70 = nBERR_FSB;
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OUTPUT S:PIN93 = nVPA_FSB;
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OUTPUT S:PIN64 = nRAS;
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OUTPUT S:PIN72 = nBR_IOB;
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OUTPUT S:PIN41 = RA<3>;
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OUTPUT S:PIN53 = RA<0>;
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OUTPUT S:PIN55 = RA<10>;
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OUTPUT S:PIN50 = RA<1>;
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OUTPUT S:PIN43 = RA<2>;
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OUTPUT S:PIN40 = RA<4>;
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OUTPUT S:PIN42 = RA<5>;
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OUTPUT S:PIN46 = RA<6>;
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OUTPUT S:PIN52 = RA<7>;
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OUTPUT S:PIN54 = RA<8>;
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OUTPUT S:PIN56 = RA<9>;
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OUTPUT S:PIN37 = nOE;
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OUTPUT S:PIN34 = nROMWE;
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OUTPUT S:PIN85 = nADoutLE0;
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OUTPUT S:PIN36 = nCAS;
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OUTPUT S:PIN28 = nDTACK_FSB;
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OUTPUT S:PIN86 = nDinLE;
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OUTPUT S:PIN63 = RA<11>;
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OUTPUT S:PIN82 = nADoutLE1;
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OUTPUT S:PIN87 = nAoutOE;
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OUTPUT S:PIN90 = nDinOE;
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OUTPUT S:PIN89 = nDoutOE;
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OUTPUT S:PIN65 = nRAMLWE;
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OUTPUT S:PIN66 = nRAMUWE;
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OUTPUT S:PIN35 = nROMCS;
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OUTPUT S:PIN58 = C25MEN;
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/* timing arc definitions */
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A_FSB<1>_RA<0>_delay: DELAY A_FSB<1> RA<0>;
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A_FSB<9>_RA<0>_delay: DELAY A_FSB<9> RA<0>;
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A_FSB<7>_RA<10>_delay: DELAY A_FSB<7> RA<10>;
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A_FSB<17>_RA<10>_delay: DELAY A_FSB<17> RA<10>;
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A_FSB<20>_RA<11>_delay: DELAY A_FSB<20> RA<11>;
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A_FSB<19>_RA<11>_delay: DELAY A_FSB<19> RA<11>;
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A_FSB<10>_RA<1>_delay: DELAY A_FSB<10> RA<1>;
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A_FSB<2>_RA<1>_delay: DELAY A_FSB<2> RA<1>;
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A_FSB<16>_RA<2>_delay: DELAY A_FSB<16> RA<2>;
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A_FSB<7>_RA<2>_delay: DELAY A_FSB<7> RA<2>;
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A_FSB<19>_RA<3>_delay: DELAY A_FSB<19> RA<3>;
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A_FSB<20>_RA<3>_delay: DELAY A_FSB<20> RA<3>;
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A_FSB<11>_RA<4>_delay: DELAY A_FSB<11> RA<4>;
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A_FSB<3>_RA<4>_delay: DELAY A_FSB<3> RA<4>;
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A_FSB<12>_RA<5>_delay: DELAY A_FSB<12> RA<5>;
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A_FSB<4>_RA<5>_delay: DELAY A_FSB<4> RA<5>;
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A_FSB<5>_RA<6>_delay: DELAY A_FSB<5> RA<6>;
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A_FSB<13>_RA<6>_delay: DELAY A_FSB<13> RA<6>;
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A_FSB<6>_RA<7>_delay: DELAY A_FSB<6> RA<7>;
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A_FSB<14>_RA<7>_delay: DELAY A_FSB<14> RA<7>;
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A_FSB<18>_RA<8>_delay: DELAY A_FSB<18> RA<8>;
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A_FSB<21>_RA<8>_delay: DELAY A_FSB<21> RA<8>;
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A_FSB<15>_RA<9>_delay: DELAY A_FSB<15> RA<9>;
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A_FSB<8>_RA<9>_delay: DELAY A_FSB<8> RA<9>;
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A_FSB<23>_nDinOE_delay: DELAY A_FSB<23> nDinOE;
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nAS_FSB_nDinOE_delay: DELAY nAS_FSB nDinOE;
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A_FSB<20>_nDinOE_delay: DELAY A_FSB<20> nDinOE;
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A_FSB<22>_nDinOE_delay: DELAY A_FSB<22> nDinOE;
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nWE_FSB_nDinOE_delay: DELAY nWE_FSB nDinOE;
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A_FSB<21>_nDinOE_delay: DELAY A_FSB<21> nDinOE;
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nWE_FSB_nOE_delay: DELAY nWE_FSB nOE;
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nAS_FSB_nOE_delay: DELAY nAS_FSB nOE;
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nLDS_FSB_nRAMLWE_delay: DELAY nLDS_FSB nRAMLWE;
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nAS_FSB_nRAMLWE_delay: DELAY nAS_FSB nRAMLWE;
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nWE_FSB_nRAMLWE_delay: DELAY nWE_FSB nRAMLWE;
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nWE_FSB_nRAMUWE_delay: DELAY nWE_FSB nRAMUWE;
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nAS_FSB_nRAMUWE_delay: DELAY nAS_FSB nRAMUWE;
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nUDS_FSB_nRAMUWE_delay: DELAY nUDS_FSB nRAMUWE;
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nAS_FSB_nRAS_delay: DELAY nAS_FSB nRAS;
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A_FSB<22>_nRAS_delay: DELAY A_FSB<22> nRAS;
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A_FSB<23>_nRAS_delay: DELAY A_FSB<23> nRAS;
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A_FSB<22>_nROMCS_delay: DELAY A_FSB<22> nROMCS;
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A_FSB<20>_nROMCS_delay: DELAY A_FSB<20> nROMCS;
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A_FSB<23>_nROMCS_delay: DELAY A_FSB<23> nROMCS;
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A_FSB<21>_nROMCS_delay: DELAY A_FSB<21> nROMCS;
|
||||
nWE_FSB_nROMWE_delay: DELAY nWE_FSB nROMWE;
|
||||
nAS_FSB_nROMWE_delay: DELAY nAS_FSB nROMWE;
|
||||
FCLK_nRES_delay: DELAY (ENABLE_HIGH) FCLK nRES;
|
||||
FCLK_nVMA_IOB_delay: DELAY (ENABLE_HIGH) FCLK nVMA_IOB;
|
||||
FCLK_nAS_IOB_delay: DELAY (ENABLE_HIGH) FCLK nAS_IOB;
|
||||
FCLK_nLDS_IOB_delay: DELAY (ENABLE_HIGH) FCLK nLDS_IOB;
|
||||
FCLK_nUDS_IOB_delay: DELAY (ENABLE_HIGH) FCLK nUDS_IOB;
|
||||
FCLK_nBERR_FSB_delay: DELAY FCLK nBERR_FSB;
|
||||
FCLK_nVPA_FSB_delay: DELAY FCLK nVPA_FSB;
|
||||
FCLK_nRAS_delay: DELAY FCLK nRAS;
|
||||
FCLK_nBR_IOB_delay: DELAY FCLK nBR_IOB;
|
||||
FCLK_RA<3>_delay: DELAY FCLK RA<3>;
|
||||
FCLK_RA<0>_delay: DELAY FCLK RA<0>;
|
||||
FCLK_RA<10>_delay: DELAY FCLK RA<10>;
|
||||
FCLK_RA<1>_delay: DELAY FCLK RA<1>;
|
||||
FCLK_RA<2>_delay: DELAY FCLK RA<2>;
|
||||
FCLK_RA<4>_delay: DELAY FCLK RA<4>;
|
||||
FCLK_RA<5>_delay: DELAY FCLK RA<5>;
|
||||
FCLK_RA<6>_delay: DELAY FCLK RA<6>;
|
||||
FCLK_RA<7>_delay: DELAY FCLK RA<7>;
|
||||
FCLK_RA<8>_delay: DELAY FCLK RA<8>;
|
||||
FCLK_RA<9>_delay: DELAY FCLK RA<9>;
|
||||
FCLK_nADoutLE0_delay: DELAY FCLK nADoutLE0;
|
||||
FCLK_nCAS_delay: DELAY FCLK nCAS;
|
||||
FCLK_nDTACK_FSB_delay: DELAY FCLK nDTACK_FSB;
|
||||
FCLK_RA<11>_delay: DELAY FCLK RA<11>;
|
||||
FCLK_nADoutLE1_delay: DELAY FCLK nADoutLE1;
|
||||
FCLK_nAoutOE_delay: DELAY FCLK nAoutOE;
|
||||
FCLK_nDoutOE_delay: DELAY FCLK nDoutOE;
|
||||
FCLK_nRAMLWE_delay: DELAY FCLK nRAMLWE;
|
||||
FCLK_nRAMUWE_delay: DELAY FCLK nRAMUWE;
|
||||
FCLK_nROMCS_delay: DELAY FCLK nROMCS;
|
||||
C16M_nAS_IOB_delay: DELAY (ENABLE_HIGH) C16M nAS_IOB;
|
||||
C16M_nLDS_IOB_delay: DELAY (ENABLE_HIGH) C16M nLDS_IOB;
|
||||
C16M_nUDS_IOB_delay: DELAY (ENABLE_HIGH) C16M nUDS_IOB;
|
||||
C16M_nADoutLE0_delay: DELAY C16M nADoutLE0;
|
||||
C16M_nDinLE_delay: DELAY C16M nDinLE;
|
||||
C16M_nDoutOE_delay: DELAY C16M nDoutOE;
|
||||
C8M_nVMA_IOB_delay: DELAY (ENABLE_HIGH) C8M nVMA_IOB;
|
||||
|
||||
/* timing check arc definitions */
|
||||
A_FSB<10>_FCLK_setup: SETUP(POSEDGE) A_FSB<10> FCLK;
|
||||
A_FSB<11>_FCLK_setup: SETUP(POSEDGE) A_FSB<11> FCLK;
|
||||
A_FSB<12>_FCLK_setup: SETUP(POSEDGE) A_FSB<12> FCLK;
|
||||
A_FSB<13>_FCLK_setup: SETUP(POSEDGE) A_FSB<13> FCLK;
|
||||
A_FSB<14>_FCLK_setup: SETUP(POSEDGE) A_FSB<14> FCLK;
|
||||
A_FSB<15>_FCLK_setup: SETUP(POSEDGE) A_FSB<15> FCLK;
|
||||
A_FSB<16>_FCLK_setup: SETUP(POSEDGE) A_FSB<16> FCLK;
|
||||
A_FSB<17>_FCLK_setup: SETUP(POSEDGE) A_FSB<17> FCLK;
|
||||
A_FSB<18>_FCLK_setup: SETUP(POSEDGE) A_FSB<18> FCLK;
|
||||
A_FSB<19>_FCLK_setup: SETUP(POSEDGE) A_FSB<19> FCLK;
|
||||
A_FSB<20>_FCLK_setup: SETUP(POSEDGE) A_FSB<20> FCLK;
|
||||
A_FSB<21>_FCLK_setup: SETUP(POSEDGE) A_FSB<21> FCLK;
|
||||
A_FSB<22>_FCLK_setup: SETUP(POSEDGE) A_FSB<22> FCLK;
|
||||
A_FSB<23>_FCLK_setup: SETUP(POSEDGE) A_FSB<23> FCLK;
|
||||
A_FSB<8>_FCLK_setup: SETUP(POSEDGE) A_FSB<8> FCLK;
|
||||
A_FSB<9>_FCLK_setup: SETUP(POSEDGE) A_FSB<9> FCLK;
|
||||
E_FCLK_setup: SETUP(POSEDGE) E FCLK;
|
||||
nAS_FSB_FCLK_setup: SETUP(POSEDGE) nAS_FSB FCLK;
|
||||
nIPL2_FCLK_setup: SETUP(POSEDGE) nIPL2 FCLK;
|
||||
nLDS_FSB_FCLK_setup: SETUP(POSEDGE) nLDS_FSB FCLK;
|
||||
nRES_FCLK_setup: SETUP(POSEDGE) nRES FCLK;
|
||||
nUDS_FSB_FCLK_setup: SETUP(POSEDGE) nUDS_FSB FCLK;
|
||||
nWE_FSB_FCLK_setup: SETUP(POSEDGE) nWE_FSB FCLK;
|
||||
A_FSB<10>_FCLK_hold: HOLD(POSEDGE) A_FSB<10> FCLK;
|
||||
A_FSB<11>_FCLK_hold: HOLD(POSEDGE) A_FSB<11> FCLK;
|
||||
A_FSB<12>_FCLK_hold: HOLD(POSEDGE) A_FSB<12> FCLK;
|
||||
A_FSB<13>_FCLK_hold: HOLD(POSEDGE) A_FSB<13> FCLK;
|
||||
A_FSB<14>_FCLK_hold: HOLD(POSEDGE) A_FSB<14> FCLK;
|
||||
A_FSB<15>_FCLK_hold: HOLD(POSEDGE) A_FSB<15> FCLK;
|
||||
A_FSB<16>_FCLK_hold: HOLD(POSEDGE) A_FSB<16> FCLK;
|
||||
A_FSB<17>_FCLK_hold: HOLD(POSEDGE) A_FSB<17> FCLK;
|
||||
A_FSB<18>_FCLK_hold: HOLD(POSEDGE) A_FSB<18> FCLK;
|
||||
A_FSB<19>_FCLK_hold: HOLD(POSEDGE) A_FSB<19> FCLK;
|
||||
A_FSB<20>_FCLK_hold: HOLD(POSEDGE) A_FSB<20> FCLK;
|
||||
A_FSB<21>_FCLK_hold: HOLD(POSEDGE) A_FSB<21> FCLK;
|
||||
A_FSB<22>_FCLK_hold: HOLD(POSEDGE) A_FSB<22> FCLK;
|
||||
A_FSB<23>_FCLK_hold: HOLD(POSEDGE) A_FSB<23> FCLK;
|
||||
A_FSB<8>_FCLK_hold: HOLD(POSEDGE) A_FSB<8> FCLK;
|
||||
A_FSB<9>_FCLK_hold: HOLD(POSEDGE) A_FSB<9> FCLK;
|
||||
E_FCLK_hold: HOLD(POSEDGE) E FCLK;
|
||||
nAS_FSB_FCLK_hold: HOLD(POSEDGE) nAS_FSB FCLK;
|
||||
nIPL2_FCLK_hold: HOLD(POSEDGE) nIPL2 FCLK;
|
||||
nLDS_FSB_FCLK_hold: HOLD(POSEDGE) nLDS_FSB FCLK;
|
||||
nRES_FCLK_hold: HOLD(POSEDGE) nRES FCLK;
|
||||
nUDS_FSB_FCLK_hold: HOLD(POSEDGE) nUDS_FSB FCLK;
|
||||
nWE_FSB_FCLK_hold: HOLD(POSEDGE) nWE_FSB FCLK;
|
||||
C8M_C16M_setup: SETUP(POSEDGE) C8M C16M;
|
||||
C8M_C16M_hold: HOLD(POSEDGE) C8M C16M;
|
||||
E_C8M_setup: SETUP(POSEDGE) E C8M;
|
||||
nBERR_IOB_C8M_setup: SETUP(POSEDGE) nBERR_IOB C8M;
|
||||
nDTACK_IOB_C8M_setup: SETUP(POSEDGE) nDTACK_IOB C8M;
|
||||
nRES_C8M_setup: SETUP(POSEDGE) nRES C8M;
|
||||
nVPA_IOB_C8M_setup: SETUP(POSEDGE) nVPA_IOB C8M;
|
||||
E_C8M_hold: HOLD(POSEDGE) E C8M;
|
||||
nBERR_IOB_C8M_hold: HOLD(POSEDGE) nBERR_IOB C8M;
|
||||
nDTACK_IOB_C8M_hold: HOLD(POSEDGE) nDTACK_IOB C8M;
|
||||
nRES_C8M_hold: HOLD(POSEDGE) nRES C8M;
|
||||
nVPA_IOB_C8M_hold: HOLD(POSEDGE) nVPA_IOB C8M;
|
||||
|
||||
ENDMODEL
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -1,7 +1,7 @@
|
|||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
4- 9-2023 5:01AM
|
||||
4- 9-2023 11:31PM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The pipe '|'
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
cpldfit: version P.20131013 Xilinx Inc.
|
||||
Fitter Report
|
||||
Design Name: WarpSE Date: 4- 9-2023, 5:01AM
|
||||
Design Name: WarpSE Date: 4- 9-2023, 11:31PM
|
||||
Device Used: XC95144XL-10-TQ100
|
||||
Fitting Status: Successful
|
||||
|
||||
|
|
@ -9,22 +9,22 @@ Fitting Status: Successful
|
|||
|
||||
Macrocells Product Terms Function Block Registers Pins
|
||||
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
|
||||
125/144 ( 87%) 438 /720 ( 61%) 285/432 ( 66%) 100/144 ( 69%) 70 /81 ( 86%)
|
||||
123/144 ( 85%) 435 /720 ( 60%) 280/432 ( 65%) 98 /144 ( 68%) 70 /81 ( 86%)
|
||||
|
||||
** Function Block Resources **
|
||||
|
||||
Function Mcells FB Inps Pterms IO
|
||||
Block Used/Tot Used/Tot Used/Tot Used/Tot
|
||||
FB1 18/18* 28/54 40/90 11/11*
|
||||
FB2 15/18 16/54 16/90 8/10
|
||||
FB3 16/18 39/54 81/90 10/10*
|
||||
FB4 17/18 42/54 62/90 10/10*
|
||||
FB5 11/18 42/54 38/90 8/10
|
||||
FB1 18/18* 27/54 40/90 11/11*
|
||||
FB2 15/18 17/54 17/90 8/10
|
||||
FB3 16/18 36/54 81/90 10/10*
|
||||
FB4 16/18 41/54 59/90 10/10*
|
||||
FB5 10/18 41/54 37/90 8/10
|
||||
FB6 18/18* 36/54 68/90 10/10*
|
||||
FB7 18/18* 41/54 52/90 7/10
|
||||
FB8 12/18 41/54 81/90 6/10
|
||||
----- ----- ----- -----
|
||||
125/144 285/432 438/720 70/81
|
||||
123/144 280/432 435/720 70/81
|
||||
|
||||
* - Resource is exhausted
|
||||
|
||||
|
|
@ -51,7 +51,7 @@ GSR : 0 0 |
|
|||
|
||||
** Power Data **
|
||||
|
||||
There are 125 macrocells in high performance mode (MCHP).
|
||||
There are 123 macrocells in high performance mode (MCHP).
|
||||
There are 0 macrocells in low power mode (MCLP).
|
||||
End of Mapped Resource Summary
|
||||
************************** Errors and Warnings ***************************
|
||||
|
|
@ -95,7 +95,7 @@ nAoutOE 2 4 FB4_2 87 I/O O
|
|||
nDoutOE 2 5 FB4_5 89 I/O O STD FAST
|
||||
nDinOE 3 6 FB4_6 90 I/O O STD FAST
|
||||
nRES 1 1 FB4_8 91 I/O I/O STD FAST
|
||||
nVPA_FSB 3 12 FB4_11 93 I/O O STD FAST RESET
|
||||
nVPA_FSB 3 11 FB4_11 93 I/O O STD FAST RESET
|
||||
nROMCS 2 5 FB5_2 35 I/O O STD FAST
|
||||
nCAS 1 1 FB5_5 36 I/O O STD FAST RESET
|
||||
nOE 1 2 FB5_6 37 I/O O STD FAST
|
||||
|
|
@ -125,54 +125,54 @@ nRAMUWE 1 4 FB8_8 66 I/O O
|
|||
nBERR_FSB 3 5 FB8_12 70 I/O O STD FAST RESET
|
||||
nBR_IOB 2 4 FB8_15 72 I/O O STD FAST RESET
|
||||
|
||||
** 90 Buried Nodes **
|
||||
** 88 Buried Nodes **
|
||||
|
||||
Signal Total Total Loc Pwr Reg Init
|
||||
Name Pts Inps Mode State
|
||||
iobs/Clear1 1 2 FB1_1 STD RESET
|
||||
iobm/Er 1 1 FB1_2 STD RESET
|
||||
cnt/nIPL2r 1 1 FB1_3 STD RESET
|
||||
ram/RS_FSM_FFd2 1 1 FB1_1 STD RESET
|
||||
ram/RS_FSM_FFd1 1 1 FB1_2 STD RESET
|
||||
iobm/Er 1 1 FB1_3 STD RESET
|
||||
cnt/Er<1> 1 1 FB1_4 STD RESET
|
||||
cnt/Er<0> 1 1 FB1_5 STD RESET
|
||||
ram/RS_FSM_FFd4 2 4 FB1_6 STD RESET
|
||||
iobs/TS_FSM_FFd1 2 3 FB1_7 STD RESET
|
||||
iobs/IOU1 2 2 FB1_8 STD RESET
|
||||
cnt/Timer<0> 2 4 FB1_9 STD RESET
|
||||
cnt/IS_FSM_FFd2 2 6 FB1_10 STD RESET
|
||||
RefUrg 2 6 FB1_11 STD RESET
|
||||
RefReq 2 6 FB1_12 STD RESET
|
||||
IOPWReady 2 3 FB1_13 STD RESET
|
||||
IOBERR 2 2 FB1_14 STD RESET
|
||||
ram/RefDone 2 5 FB1_6 STD RESET
|
||||
ram/RS_FSM_FFd4 2 4 FB1_7 STD RESET
|
||||
iobs/TS_FSM_FFd1 2 3 FB1_8 STD RESET
|
||||
iobs/IOU1 2 2 FB1_9 STD RESET
|
||||
iobs/IOL1 2 2 FB1_10 STD RESET
|
||||
cnt/Timer<0> 2 4 FB1_11 STD RESET
|
||||
cnt/IS_FSM_FFd2 2 6 FB1_12 STD RESET
|
||||
RefUrg 2 6 FB1_13 STD RESET
|
||||
RefReq 2 6 FB1_14 STD RESET
|
||||
iobm/ES<2> 3 5 FB1_15 STD RESET
|
||||
cnt/Timer<1> 4 5 FB1_16 STD RESET
|
||||
cnt/Timer<3> 5 7 FB1_17 STD RESET
|
||||
cnt/Timer<2> 5 6 FB1_18 STD RESET
|
||||
ram/RS_FSM_FFd5 1 1 FB2_4 STD RESET
|
||||
ram/RS_FSM_FFd3 1 1 FB2_5 STD RESET
|
||||
ram/RS_FSM_FFd2 1 1 FB2_6 STD RESET
|
||||
ram/RS_FSM_FFd1 1 1 FB2_7 STD RESET
|
||||
ram/RASrf 1 1 FB2_8 STD RESET
|
||||
iobs/IODONEr 1 1 FB2_9 STD RESET
|
||||
iobs/IOACTr 1 1 FB2_10 STD RESET
|
||||
iobm/VPAr 1 1 FB2_11 STD RESET
|
||||
iobm/IOWRREQr 1 1 FB2_12 STD RESET
|
||||
iobm/IOS_FSM_FFd5 1 1 FB2_13 STD RESET
|
||||
iobm/IOS_FSM_FFd4 1 1 FB2_14 STD RESET
|
||||
iobm/IOS_FSM_FFd1 1 1 FB2_15 STD RESET
|
||||
iobm/IORDREQr 1 1 FB2_16 STD RESET
|
||||
iobm/C8Mr 1 1 FB2_17 STD RESET
|
||||
iobm/IOS_FSM_FFd2 2 4 FB2_18 STD RESET
|
||||
ram/RASrf 1 1 FB2_6 STD RESET
|
||||
iobs/IODONEr 1 1 FB2_7 STD RESET
|
||||
iobs/IOACTr 1 1 FB2_8 STD RESET
|
||||
iobm/VPAr 1 1 FB2_9 STD RESET
|
||||
iobm/IOWRREQr 1 1 FB2_10 STD RESET
|
||||
iobm/IOS_FSM_FFd5 1 1 FB2_11 STD RESET
|
||||
iobm/IOS_FSM_FFd4 1 1 FB2_12 STD RESET
|
||||
iobm/IOS_FSM_FFd1 1 1 FB2_13 STD RESET
|
||||
iobm/IORDREQr 1 1 FB2_14 STD RESET
|
||||
iobm/C8Mr 1 1 FB2_15 STD RESET
|
||||
cnt/nIPL2r 1 1 FB2_16 STD RESET
|
||||
iobm/IOS_FSM_FFd2 2 4 FB2_17 STD RESET
|
||||
IOBERR 2 2 FB2_18 STD RESET
|
||||
iobs/Sent 13 18 FB3_1 STD RESET
|
||||
ram/RefDone 2 5 FB3_2 STD RESET
|
||||
iobs/Clear1 1 2 FB3_2 STD RESET
|
||||
ram/RS_FSM_FFd7 2 7 FB3_3 STD RESET
|
||||
cs/nOverlay 2 5 FB3_4 STD RESET
|
||||
ram/RS_FSM_FFd6 3 7 FB3_5 STD RESET
|
||||
ram/RS_FSM_FFd6 3 7 FB3_4 STD RESET
|
||||
ram/RASEL 3 8 FB3_5 STD RESET
|
||||
ram/RASrr 4 9 FB3_6 STD RESET
|
||||
ram/RASEL 3 8 FB3_7 STD RESET
|
||||
ram/Once 3 8 FB3_7 STD RESET
|
||||
|
||||
Signal Total Total Loc Pwr Reg Init
|
||||
Name Pts Inps Mode State
|
||||
ram/Once 3 8 FB3_8 STD RESET
|
||||
cs/nOverlay 3 8 FB3_8 STD RESET
|
||||
RAMReady 4 8 FB3_10 STD RESET
|
||||
ram/RS_FSM_FFd8 5 11 FB3_11 STD SET
|
||||
ram/RAMEN 6 10 FB3_12 STD RESET
|
||||
|
|
@ -180,19 +180,17 @@ ram/CAS 7 13 FB3_14 STD RESET
|
|||
iobs/Load1 8 17 FB3_15 STD RESET
|
||||
IORDREQ 9 15 FB3_16 STD RESET
|
||||
QoSReady 18 25 FB4_1 STD RESET
|
||||
fsb/ASrf 1 1 FB4_3 STD RESET
|
||||
cnt/WS<0> 1 3 FB4_4 STD RESET
|
||||
$OpTx$$OpTx$FX_DC$354_INV$541 1 2 FB4_7 STD
|
||||
iobs/IOL1 2 2 FB4_9 STD RESET
|
||||
cs/ODCSr 2 6 FB4_10 STD RESET
|
||||
cnt/WS<2> 3 5 FB4_12 STD RESET
|
||||
cnt/WS<1> 3 4 FB4_13 STD RESET
|
||||
IONPReady 5 16 FB4_14 STD RESET
|
||||
cnt/LTimer<1> 11 24 FB4_15 STD RESET
|
||||
cnt/WS<3> 3 6 FB4_16 STD RESET
|
||||
nRESout 1 2 FB4_17 STD RESET
|
||||
cnt/LTimerTC 1 12 FB5_13 STD RESET
|
||||
ALE0S 1 1 FB5_16 STD RESET
|
||||
nRESout 1 2 FB4_3 STD RESET
|
||||
fsb/ASrf 1 1 FB4_4 STD RESET
|
||||
cnt/WS<0> 1 3 FB4_7 STD RESET
|
||||
ALE0S 1 1 FB4_9 STD RESET
|
||||
$OpTx$$OpTx$FX_DC$354_INV$541 1 2 FB4_10 STD
|
||||
cnt/WS<3> 3 6 FB4_12 STD RESET
|
||||
cnt/WS<2> 3 5 FB4_13 STD RESET
|
||||
cnt/WS<1> 3 4 FB4_14 STD RESET
|
||||
IONPReady 5 16 FB4_15 STD RESET
|
||||
cnt/LTimer<1> 11 24 FB4_17 STD RESET
|
||||
cnt/LTimerTC 1 12 FB5_16 STD RESET
|
||||
cnt/LTimer<0> 22 34 FB5_18 STD RESET
|
||||
iobm/IOS_FSM_FFd6 2 5 FB6_1 STD RESET
|
||||
iobm/IOS_FSM_FFd7 3 6 FB6_3 STD SET
|
||||
|
|
@ -212,11 +210,11 @@ cnt/LTimer<6> 3 12 FB7_7 STD RESET
|
|||
cnt/LTimer<5> 3 11 FB7_10 STD RESET
|
||||
cnt/LTimer<4> 3 10 FB7_13 STD RESET
|
||||
cnt/LTimer<3> 3 9 FB7_14 STD RESET
|
||||
cnt/LTimer<2> 3 8 FB7_15 STD RESET
|
||||
cnt/LTimer<11> 3 17 FB7_16 STD RESET
|
||||
|
||||
Signal Total Total Loc Pwr Reg Init
|
||||
Name Pts Inps Mode State
|
||||
cnt/LTimer<2> 3 8 FB7_15 STD RESET
|
||||
cnt/LTimer<11> 3 17 FB7_16 STD RESET
|
||||
cnt/LTimer<10> 3 16 FB7_17 STD RESET
|
||||
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2 10 36 FB7_18 STD
|
||||
IOL0 16 21 FB8_1 STD RESET
|
||||
|
|
@ -282,66 +280,65 @@ Pin Type/Use - I - Input GCK - Global Clock
|
|||
X - Signal used as input to the macrocell logic.
|
||||
Pin No. - ~ - User Assigned
|
||||
*********************************** FB1 ***********************************
|
||||
Number of function block inputs used/remaining: 28/26
|
||||
Number of signals used by logic mapping into function block: 28
|
||||
Number of function block inputs used/remaining: 27/27
|
||||
Number of signals used by logic mapping into function block: 27
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
iobs/Clear1 1 0 0 4 FB1_1 (b) (b)
|
||||
iobm/Er 1 0 0 4 FB1_2 11 I/O I
|
||||
cnt/nIPL2r 1 0 0 4 FB1_3 12 I/O I
|
||||
ram/RS_FSM_FFd2 1 0 0 4 FB1_1 (b) (b)
|
||||
ram/RS_FSM_FFd1 1 0 0 4 FB1_2 11 I/O I
|
||||
iobm/Er 1 0 0 4 FB1_3 12 I/O I
|
||||
cnt/Er<1> 1 0 0 4 FB1_4 (b) (b)
|
||||
cnt/Er<0> 1 0 0 4 FB1_5 13 I/O I
|
||||
ram/RS_FSM_FFd4 2 0 0 3 FB1_6 14 I/O I
|
||||
iobs/TS_FSM_FFd1 2 0 0 3 FB1_7 (b) (b)
|
||||
iobs/IOU1 2 0 0 3 FB1_8 15 I/O I
|
||||
cnt/Timer<0> 2 0 0 3 FB1_9 16 I/O I
|
||||
cnt/IS_FSM_FFd2 2 0 0 3 FB1_10 (b) (b)
|
||||
RefUrg 2 0 0 3 FB1_11 17 I/O I
|
||||
RefReq 2 0 0 3 FB1_12 18 I/O I
|
||||
IOPWReady 2 0 0 3 FB1_13 (b) (b)
|
||||
IOBERR 2 0 0 3 FB1_14 19 I/O I
|
||||
ram/RefDone 2 0 0 3 FB1_6 14 I/O I
|
||||
ram/RS_FSM_FFd4 2 0 0 3 FB1_7 (b) (b)
|
||||
iobs/TS_FSM_FFd1 2 0 0 3 FB1_8 15 I/O I
|
||||
iobs/IOU1 2 0 0 3 FB1_9 16 I/O I
|
||||
iobs/IOL1 2 0 0 3 FB1_10 (b) (b)
|
||||
cnt/Timer<0> 2 0 0 3 FB1_11 17 I/O I
|
||||
cnt/IS_FSM_FFd2 2 0 0 3 FB1_12 18 I/O I
|
||||
RefUrg 2 0 0 3 FB1_13 (b) (b)
|
||||
RefReq 2 0 0 3 FB1_14 19 I/O I
|
||||
iobm/ES<2> 3 0 0 2 FB1_15 20 I/O I
|
||||
cnt/Timer<1> 4 0 0 1 FB1_16 (b) (b)
|
||||
cnt/Timer<3> 5 0 0 0 FB1_17 22 GCK/I/O GCK
|
||||
cnt/Timer<2> 5 0 0 0 FB1_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: E 11: cnt/Timer<3> 20: iobs/TS_FSM_FFd2
|
||||
2: RefUrg 12: iobm/ES<0> 21: nADoutLE1
|
||||
3: cnt/Er<0> 13: iobm/ES<1> 22: nAS_IOB
|
||||
4: cnt/Er<1> 14: iobm/ES<2> 23: nBERR_IOB
|
||||
5: cnt/IS_FSM_FFd1 15: iobm/Er 24: nIPL2
|
||||
6: cnt/IS_FSM_FFd2 16: iobs/Clear1 25: nUDS_FSB
|
||||
7: cnt/LTimerTC 17: iobs/IOACTr 26: ram/RS_FSM_FFd1
|
||||
8: cnt/Timer<0> 18: iobs/Load1 27: ram/RS_FSM_FFd5
|
||||
9: cnt/Timer<1> 19: iobs/TS_FSM_FFd1 28: ram/RefDone
|
||||
10: cnt/Timer<2>
|
||||
1: E 10: cnt/Timer<1> 19: iobs/TS_FSM_FFd1
|
||||
2: RefReq 11: cnt/Timer<2> 20: iobs/TS_FSM_FFd2
|
||||
3: RefUrg 12: cnt/Timer<3> 21: nLDS_FSB
|
||||
4: cnt/Er<0> 13: iobm/ES<0> 22: nUDS_FSB
|
||||
5: cnt/Er<1> 14: iobm/ES<1> 23: ram/RS_FSM_FFd1
|
||||
6: cnt/IS_FSM_FFd1 15: iobm/ES<2> 24: ram/RS_FSM_FFd2
|
||||
7: cnt/IS_FSM_FFd2 16: iobm/Er 25: ram/RS_FSM_FFd3
|
||||
8: cnt/LTimerTC 17: iobs/IOACTr 26: ram/RS_FSM_FFd5
|
||||
9: cnt/Timer<0> 18: iobs/Load1 27: ram/RefDone
|
||||
|
||||
Signal 1 2 3 4 FB
|
||||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||||
iobs/Clear1 ..................XX.................... 2
|
||||
ram/RS_FSM_FFd2 ........................X............... 1
|
||||
ram/RS_FSM_FFd1 .......................X................ 1
|
||||
iobm/Er X....................................... 1
|
||||
cnt/nIPL2r .......................X................ 1
|
||||
cnt/Er<1> ..X..................................... 1
|
||||
cnt/Er<1> ...X.................................... 1
|
||||
cnt/Er<0> X....................................... 1
|
||||
ram/RS_FSM_FFd4 .X.......................XXX............ 4
|
||||
ram/RefDone .XX....................XX.X............. 5
|
||||
ram/RS_FSM_FFd4 ..X...................X..XX............. 4
|
||||
iobs/TS_FSM_FFd1 ................X.XX.................... 3
|
||||
iobs/IOU1 .................X......X............... 2
|
||||
cnt/Timer<0> .XXX...X................................ 4
|
||||
cnt/IS_FSM_FFd2 .XXXXXX................................. 6
|
||||
RefUrg ..XX...XXXX............................. 6
|
||||
RefReq ..XX...XXXX............................. 6
|
||||
IOPWReady ...............X.X..X................... 3
|
||||
IOBERR .....................XX................. 2
|
||||
iobm/ES<2> X..........XXXX......................... 5
|
||||
cnt/Timer<1> .XXX...XX............................... 5
|
||||
cnt/Timer<3> .XXX...XXXX............................. 7
|
||||
cnt/Timer<2> .XXX...XXX.............................. 6
|
||||
iobs/IOU1 .................X...X.................. 2
|
||||
iobs/IOL1 .................X..X................... 2
|
||||
cnt/Timer<0> ..XXX...X............................... 4
|
||||
cnt/IS_FSM_FFd2 ..XXXXXX................................ 6
|
||||
RefUrg ...XX...XXXX............................ 6
|
||||
RefReq ...XX...XXXX............................ 6
|
||||
iobm/ES<2> X...........XXXX........................ 5
|
||||
cnt/Timer<1> ..XXX...XX.............................. 5
|
||||
cnt/Timer<3> ..XXX...XXXX............................ 7
|
||||
cnt/Timer<2> ..XXX...XXX............................. 6
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
*********************************** FB2 ***********************************
|
||||
Number of function block inputs used/remaining: 16/38
|
||||
Number of signals used by logic mapping into function block: 16
|
||||
Number of function block inputs used/remaining: 17/37
|
||||
Number of signals used by logic mapping into function block: 17
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
(unused) 0 0 0 5 FB2_1 (b)
|
||||
|
|
@ -349,60 +346,60 @@ Name Pt Pt Pt Pt # Type Use
|
|||
(unused) 0 0 0 5 FB2_3 (b)
|
||||
ram/RS_FSM_FFd5 1 0 0 4 FB2_4 (b) (b)
|
||||
ram/RS_FSM_FFd3 1 0 0 4 FB2_5 1 GTS/I/O (b)
|
||||
ram/RS_FSM_FFd2 1 0 0 4 FB2_6 2 GTS/I/O I
|
||||
ram/RS_FSM_FFd1 1 0 0 4 FB2_7 (b) (b)
|
||||
ram/RASrf 1 0 0 4 FB2_8 3 GTS/I/O I
|
||||
iobs/IODONEr 1 0 0 4 FB2_9 4 GTS/I/O I
|
||||
iobs/IOACTr 1 0 0 4 FB2_10 (b) (b)
|
||||
iobm/VPAr 1 0 0 4 FB2_11 6 I/O I
|
||||
iobm/IOWRREQr 1 0 0 4 FB2_12 7 I/O I
|
||||
iobm/IOS_FSM_FFd5 1 0 0 4 FB2_13 (b) (b)
|
||||
iobm/IOS_FSM_FFd4 1 0 0 4 FB2_14 8 I/O I
|
||||
iobm/IOS_FSM_FFd1 1 0 0 4 FB2_15 9 I/O I
|
||||
iobm/IORDREQr 1 0 0 4 FB2_16 (b) (b)
|
||||
iobm/C8Mr 1 0 0 4 FB2_17 10 I/O I
|
||||
iobm/IOS_FSM_FFd2 2 0 0 3 FB2_18 (b) (b)
|
||||
ram/RASrf 1 0 0 4 FB2_6 2 GTS/I/O I
|
||||
iobs/IODONEr 1 0 0 4 FB2_7 (b) (b)
|
||||
iobs/IOACTr 1 0 0 4 FB2_8 3 GTS/I/O I
|
||||
iobm/VPAr 1 0 0 4 FB2_9 4 GTS/I/O I
|
||||
iobm/IOWRREQr 1 0 0 4 FB2_10 (b) (b)
|
||||
iobm/IOS_FSM_FFd5 1 0 0 4 FB2_11 6 I/O I
|
||||
iobm/IOS_FSM_FFd4 1 0 0 4 FB2_12 7 I/O I
|
||||
iobm/IOS_FSM_FFd1 1 0 0 4 FB2_13 (b) (b)
|
||||
iobm/IORDREQr 1 0 0 4 FB2_14 8 I/O I
|
||||
iobm/C8Mr 1 0 0 4 FB2_15 9 I/O I
|
||||
cnt/nIPL2r 1 0 0 4 FB2_16 (b) (b)
|
||||
iobm/IOS_FSM_FFd2 2 0 0 3 FB2_17 10 I/O I
|
||||
IOBERR 2 0 0 3 FB2_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: C8M 7: iobm/C8Mr 12: nVPA_IOB
|
||||
2: IOACT 8: iobm/IOS_FSM_FFd2 13: ram/RS_FSM_FFd2
|
||||
3: IOBERR 9: iobm/IOS_FSM_FFd3 14: ram/RS_FSM_FFd3
|
||||
4: IODONE 10: iobm/IOS_FSM_FFd5 15: ram/RS_FSM_FFd6
|
||||
5: IORDREQ 11: iobm/IOS_FSM_FFd6 16: ram/RS_FSM_FFd7
|
||||
6: IOWRREQ
|
||||
1: C8M 7: iobm/C8Mr 13: nBERR_IOB
|
||||
2: IOACT 8: iobm/IOS_FSM_FFd2 14: nIPL2
|
||||
3: IOBERR 9: iobm/IOS_FSM_FFd3 15: nVPA_IOB
|
||||
4: IODONE 10: iobm/IOS_FSM_FFd5 16: ram/RS_FSM_FFd6
|
||||
5: IORDREQ 11: iobm/IOS_FSM_FFd6 17: ram/RS_FSM_FFd7
|
||||
6: IOWRREQ 12: nAS_IOB
|
||||
|
||||
Signal 1 2 3 4 FB
|
||||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||||
ram/RS_FSM_FFd5 ...............X........................ 1
|
||||
ram/RS_FSM_FFd3 ..............X......................... 1
|
||||
ram/RS_FSM_FFd2 .............X.......................... 1
|
||||
ram/RS_FSM_FFd1 ............X........................... 1
|
||||
ram/RASrf ...............X........................ 1
|
||||
ram/RS_FSM_FFd5 ................X....................... 1
|
||||
ram/RS_FSM_FFd3 ...............X........................ 1
|
||||
ram/RASrf ................X....................... 1
|
||||
iobs/IODONEr ...X.................................... 1
|
||||
iobs/IOACTr .X...................................... 1
|
||||
iobm/VPAr ...........X............................ 1
|
||||
iobm/VPAr ..............X......................... 1
|
||||
iobm/IOWRREQr .....X.................................. 1
|
||||
iobm/IOS_FSM_FFd5 ..........X............................. 1
|
||||
iobm/IOS_FSM_FFd4 .........X.............................. 1
|
||||
iobm/IOS_FSM_FFd1 .......X................................ 1
|
||||
iobm/IORDREQr ....X................................... 1
|
||||
iobm/C8Mr X....................................... 1
|
||||
cnt/nIPL2r .............X.......................... 1
|
||||
iobm/IOS_FSM_FFd2 ..XX..X.X............................... 4
|
||||
IOBERR ...........XX........................... 2
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
*********************************** FB3 ***********************************
|
||||
Number of function block inputs used/remaining: 39/15
|
||||
Number of signals used by logic mapping into function block: 39
|
||||
Number of function block inputs used/remaining: 36/18
|
||||
Number of signals used by logic mapping into function block: 36
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
iobs/Sent 13 8<- 0 0 FB3_1 (b) (b)
|
||||
ram/RefDone 2 0 /\3 0 FB3_2 23 GCK/I/O GCK/I
|
||||
iobs/Clear1 1 0 /\3 1 FB3_2 23 GCK/I/O GCK/I
|
||||
ram/RS_FSM_FFd7 2 0 0 3 FB3_3 (b) (b)
|
||||
cs/nOverlay 2 0 0 3 FB3_4 (b) (b)
|
||||
ram/RS_FSM_FFd6 3 0 0 2 FB3_5 24 I/O I
|
||||
ram/RS_FSM_FFd6 3 0 0 2 FB3_4 (b) (b)
|
||||
ram/RASEL 3 0 0 2 FB3_5 24 I/O I
|
||||
ram/RASrr 4 0 0 1 FB3_6 25 I/O I
|
||||
ram/RASEL 3 0 \/2 0 FB3_7 (b) (b)
|
||||
ram/Once 3 2<- \/4 0 FB3_8 27 GCK/I/O GCK
|
||||
ram/Once 3 0 \/2 0 FB3_7 (b) (b)
|
||||
cs/nOverlay 3 2<- \/4 0 FB3_8 27 GCK/I/O GCK
|
||||
nDTACK_FSB 9 4<- 0 0 FB3_9 28 I/O O
|
||||
RAMReady 4 0 \/1 0 FB3_10 (b) (b)
|
||||
ram/RS_FSM_FFd8 5 1<- \/1 0 FB3_11 29 I/O I
|
||||
|
|
@ -415,63 +412,62 @@ nROMWE 1 0 /\4 0 FB3_17 34 I/O O
|
|||
(unused) 0 0 \/5 0 FB3_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: A_FSB<13> 14: nRES.PIN 27: nADoutLE1
|
||||
2: A_FSB<14> 15: QoSReady 28: nAS_FSB
|
||||
3: A_FSB<16> 16: RAMReady 29: nWE_FSB
|
||||
4: A_FSB<17> 17: RefReq 30: ram/Once
|
||||
5: A_FSB<18> 18: RefUrg 31: ram/RAMEN
|
||||
6: A_FSB<19> 19: cs/ODCSr 32: ram/RS_FSM_FFd2
|
||||
7: A_FSB<20> 20: cs/nOverlay 33: ram/RS_FSM_FFd3
|
||||
8: A_FSB<21> 21: fsb/ASrf 34: ram/RS_FSM_FFd4
|
||||
9: A_FSB<22> 22: iobs/IOACTr 35: ram/RS_FSM_FFd5
|
||||
10: A_FSB<23> 23: iobs/IORW1 36: ram/RS_FSM_FFd6
|
||||
11: IONPReady 24: iobs/Sent 37: ram/RS_FSM_FFd7
|
||||
12: IOPWReady 25: iobs/TS_FSM_FFd1 38: ram/RS_FSM_FFd8
|
||||
13: IORDREQ 26: iobs/TS_FSM_FFd2 39: ram/RefDone
|
||||
1: A_FSB<13> 13: nRES.PIN 25: nADoutLE1
|
||||
2: A_FSB<14> 14: QoSReady 26: nAS_FSB
|
||||
3: A_FSB<16> 15: RAMReady 27: nWE_FSB
|
||||
4: A_FSB<17> 16: RefReq 28: ram/Once
|
||||
5: A_FSB<18> 17: RefUrg 29: ram/RAMEN
|
||||
6: A_FSB<19> 18: cs/nOverlay 30: ram/RS_FSM_FFd3
|
||||
7: A_FSB<20> 19: fsb/ASrf 31: ram/RS_FSM_FFd4
|
||||
8: A_FSB<21> 20: iobs/IOACTr 32: ram/RS_FSM_FFd5
|
||||
9: A_FSB<22> 21: iobs/IORW1 33: ram/RS_FSM_FFd6
|
||||
10: A_FSB<23> 22: iobs/Sent 34: ram/RS_FSM_FFd7
|
||||
11: IONPReady 23: iobs/TS_FSM_FFd1 35: ram/RS_FSM_FFd8
|
||||
12: IORDREQ 24: iobs/TS_FSM_FFd2 36: ram/RefDone
|
||||
|
||||
Signal 1 2 3 4 FB
|
||||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||||
iobs/Sent XXXXXXXXXX.........XX..XXXXXX........... 18
|
||||
ram/RefDone ................XX.............XX.....X. 5
|
||||
ram/RS_FSM_FFd7 ........XX.........XX......X..X......X.. 7
|
||||
cs/nOverlay .............X....XXX......X............ 5
|
||||
ram/RS_FSM_FFd6 ................XX..X......X......X..XX. 7
|
||||
ram/RASrr ........XX.........XX......X..X.X..X.X.. 9
|
||||
ram/RASEL ........XX.........XX......X..X.....XX.. 8
|
||||
ram/Once ........XX.........XX......X.XX......X.. 8
|
||||
nDTACK_FSB XXXXXXXXXXXX..XX....X......XX........... 17
|
||||
RAMReady ...............XXX..X......X.....X...XX. 8
|
||||
ram/RS_FSM_FFd8 ........XX......XX.XX......X..X..X...XX. 11
|
||||
ram/RAMEN ................XX..X......X.XX..X..XXX. 10
|
||||
ram/CAS ........XX......XX.XX......X..X...XXXXX. 13
|
||||
iobs/Load1 XXXXXXXXXX..........X..XXXXXX........... 17
|
||||
IORDREQ ......XXXX..X......XXXXXXXXXX........... 15
|
||||
nROMWE ...........................XX........... 2
|
||||
iobs/Sent XXXXXXXXXX.......XX..XXXXXX............. 18
|
||||
iobs/Clear1 ......................XX................ 2
|
||||
ram/RS_FSM_FFd7 ........XX.......XX......X..X.....X..... 7
|
||||
ram/RS_FSM_FFd6 ...............XX.X......X.....X..XX.... 7
|
||||
ram/RASEL ........XX.......XX......X..X....XX..... 8
|
||||
ram/RASrr ........XX.......XX......X..XX..X.X..... 9
|
||||
ram/Once ........XX.......XX......X.XX.....X..... 8
|
||||
cs/nOverlay ......XXXX..X....XX......X.............. 8
|
||||
nDTACK_FSB XXXXXXXXXXX..XX...X.....XXX............. 17
|
||||
RAMReady ..............XXX.X......X....X...XX.... 8
|
||||
ram/RS_FSM_FFd8 ........XX.....XXXX......X..X.X...XX.... 11
|
||||
ram/RAMEN ...............XX.X......X.XX.X..XXX.... 10
|
||||
ram/CAS ........XX.....XXXX......X..X..XXXXX.... 13
|
||||
iobs/Load1 XXXXXXXXXX........X..XXXXXX............. 17
|
||||
IORDREQ ......XXXX.X.....XXXXXXXXXX............. 15
|
||||
nROMWE .........................XX............. 2
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
*********************************** FB4 ***********************************
|
||||
Number of function block inputs used/remaining: 42/12
|
||||
Number of signals used by logic mapping into function block: 42
|
||||
Number of function block inputs used/remaining: 41/13
|
||||
Number of signals used by logic mapping into function block: 41
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
QoSReady 18 13<- 0 0 FB4_1 (b) (b)
|
||||
nAoutOE 2 2<- /\5 0 FB4_2 87 I/O O
|
||||
fsb/ASrf 1 0 /\2 2 FB4_3 (b) (b)
|
||||
cnt/WS<0> 1 0 0 4 FB4_4 (b) (b)
|
||||
nRESout 1 0 /\2 2 FB4_3 (b) (b)
|
||||
fsb/ASrf 1 0 0 4 FB4_4 (b) (b)
|
||||
nDoutOE 2 0 0 3 FB4_5 89 I/O O
|
||||
nDinOE 3 0 0 2 FB4_6 90 I/O O
|
||||
$OpTx$$OpTx$FX_DC$354_INV$541
|
||||
1 0 0 4 FB4_7 (b) (b)
|
||||
cnt/WS<0> 1 0 0 4 FB4_7 (b) (b)
|
||||
nRES 1 0 0 4 FB4_8 91 I/O I/O
|
||||
iobs/IOL1 2 0 0 3 FB4_9 92 I/O I
|
||||
cs/ODCSr 2 0 0 3 FB4_10 (b) (b)
|
||||
ALE0S 1 0 0 4 FB4_9 92 I/O I
|
||||
$OpTx$$OpTx$FX_DC$354_INV$541
|
||||
1 0 0 4 FB4_10 (b) (b)
|
||||
nVPA_FSB 3 0 0 2 FB4_11 93 I/O O
|
||||
cnt/WS<2> 3 0 \/2 0 FB4_12 94 I/O I
|
||||
cnt/WS<1> 3 2<- \/4 0 FB4_13 (b) (b)
|
||||
IONPReady 5 4<- \/4 0 FB4_14 95 I/O I
|
||||
cnt/LTimer<1> 11 6<- 0 0 FB4_15 96 I/O I
|
||||
cnt/WS<3> 3 0 /\2 0 FB4_16 (b) (b)
|
||||
nRESout 1 0 \/3 1 FB4_17 97 I/O I
|
||||
cnt/WS<3> 3 0 0 2 FB4_12 94 I/O I
|
||||
cnt/WS<2> 3 0 \/2 0 FB4_13 (b) (b)
|
||||
cnt/WS<1> 3 2<- \/4 0 FB4_14 95 I/O I
|
||||
IONPReady 5 4<- \/4 0 FB4_15 96 I/O I
|
||||
(unused) 0 0 \/5 0 FB4_16 (b) (b)
|
||||
cnt/LTimer<1> 11 9<- \/3 0 FB4_17 97 I/O I
|
||||
(unused) 0 0 \/5 0 FB4_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
|
|
@ -481,40 +477,39 @@ Signals Used by Logic in Function Block
|
|||
4: A_FSB<12> 18: IONPReady 32: iobm/IOS0
|
||||
5: A_FSB<13> 19: QoSReady 33: iobm/IOWRREQr
|
||||
6: A_FSB<14> 20: cnt/IS_FSM_FFd1 34: iobs/IODONEr
|
||||
7: A_FSB<15> 21: cnt/IS_FSM_FFd2 35: iobs/Load1
|
||||
8: A_FSB<16> 22: cnt/LTimer<0> 36: iobs/Sent
|
||||
7: A_FSB<15> 21: cnt/IS_FSM_FFd2 35: iobs/Sent
|
||||
8: A_FSB<16> 22: cnt/LTimer<0> 36: iobs/TS_FSM_FFd2
|
||||
9: A_FSB<17> 23: cnt/LTimer<1> 37: nAS_FSB
|
||||
10: A_FSB<18> 24: cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2 38: nAoutOE
|
||||
11: A_FSB<19> 25: cnt/WS<0> 39: nBR_IOB
|
||||
12: A_FSB<20> 26: cnt/WS<1> 40: nLDS_FSB
|
||||
13: A_FSB<21> 27: cnt/WS<2> 41: nRESout
|
||||
14: A_FSB<22> 28: cnt/WS<3> 42: nWE_FSB
|
||||
12: A_FSB<20> 26: cnt/WS<1> 40: nRESout
|
||||
13: A_FSB<21> 27: cnt/WS<2> 41: nWE_FSB
|
||||
14: A_FSB<22> 28: cnt/WS<3>
|
||||
|
||||
Signal 1 2 3 4 5 FB
|
||||
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
||||
QoSReady XXXXXXXXXXXXXXXXX.X..XX.XXXX.............X........ 25
|
||||
QoSReady XXXXXXXXXXXXXXXXX.X..XX.XXXX............X......... 25
|
||||
nAoutOE ...................XX................XX........... 4
|
||||
nRESout ...................XX............................. 2
|
||||
fsb/ASrf ....................................X............. 1
|
||||
cnt/WS<0> ........................X...X.......X............. 3
|
||||
nDoutOE .............................XXXX....X............ 5
|
||||
nDinOE ...........XXXX.....................X....X........ 6
|
||||
nDinOE ...........XXXX.....................X...X......... 6
|
||||
cnt/WS<0> ........................X...X.......X............. 3
|
||||
nRES .......................................X.......... 1
|
||||
ALE0S ...................................X.............. 1
|
||||
$OpTx$$OpTx$FX_DC$354_INV$541
|
||||
............................X.......X............. 2
|
||||
nRES ........................................X......... 1
|
||||
iobs/IOL1 ..................................X....X.......... 2
|
||||
cs/ODCSr ...........XXXX.............X.......X............. 6
|
||||
nVPA_FSB .......XXXXXXXX..XX.........X.......X............. 12
|
||||
nVPA_FSB .......XXXXXXXX..X..........X.......X............. 11
|
||||
cnt/WS<3> ........................XXXXX.......X............. 6
|
||||
cnt/WS<2> ........................XXX.X.......X............. 5
|
||||
cnt/WS<1> ........................XX..X.......X............. 4
|
||||
IONPReady ....XX.XXXXXXXX..X..........X....X.XX....X........ 16
|
||||
cnt/LTimer<1> .XXXXXXXXXXXXXXXX..XXXXX....X.......X....X........ 24
|
||||
cnt/WS<3> ........................XXXXX.......X............. 6
|
||||
nRESout ...................XX............................. 2
|
||||
IONPReady ....XX.XXXXXXXX..X..........X....XX.X...X......... 16
|
||||
cnt/LTimer<1> .XXXXXXXXXXXXXXXX..XXXXX....X.......X...X......... 24
|
||||
0----+----1----+----2----+----3----+----4----+----5
|
||||
0 0 0 0 0
|
||||
*********************************** FB5 ***********************************
|
||||
Number of function block inputs used/remaining: 42/12
|
||||
Number of signals used by logic mapping into function block: 42
|
||||
Number of function block inputs used/remaining: 41/13
|
||||
Number of signals used by logic mapping into function block: 41
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
(unused) 0 0 /\5 0 FB5_1 (b) (b)
|
||||
|
|
@ -529,10 +524,10 @@ RA<4> 2 0 0 3 FB5_9 40 I/O O
|
|||
(unused) 0 0 0 5 FB5_10 (b)
|
||||
RA<3> 2 0 0 3 FB5_11 41 I/O O
|
||||
RA<5> 2 0 0 3 FB5_12 42 I/O O
|
||||
cnt/LTimerTC 1 0 0 4 FB5_13 (b) (b)
|
||||
(unused) 0 0 0 5 FB5_13 (b)
|
||||
RA<2> 2 0 0 3 FB5_14 43 I/O O
|
||||
RA<6> 2 0 0 3 FB5_15 46 I/O O
|
||||
ALE0S 1 0 \/4 0 FB5_16 (b) (b)
|
||||
cnt/LTimerTC 1 0 \/4 0 FB5_16 (b) (b)
|
||||
(unused) 0 0 \/5 0 FB5_17 49 I/O (b)
|
||||
cnt/LTimer<0> 22 17<- 0 0 FB5_18 (b) (b)
|
||||
|
||||
|
|
@ -546,25 +541,24 @@ Signals Used by Logic in Function Block
|
|||
7: A_FSB<16> 21: cnt/IS_FSM_FFd1 35: cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2
|
||||
8: A_FSB<17> 22: cnt/IS_FSM_FFd2 36: cs/nOverlay
|
||||
9: A_FSB<18> 23: cnt/LTimer<0> 37: fsb/ASrf
|
||||
10: A_FSB<19> 24: cnt/LTimer<10> 38: iobs/TS_FSM_FFd2
|
||||
11: A_FSB<20> 25: cnt/LTimer<11> 39: nAS_FSB
|
||||
12: A_FSB<21> 26: cnt/LTimer<1> 40: nWE_FSB
|
||||
13: A_FSB<22> 27: cnt/LTimer<2> 41: ram/CAS
|
||||
14: A_FSB<23> 28: cnt/LTimer<3> 42: ram/RASEL
|
||||
10: A_FSB<19> 24: cnt/LTimer<10> 38: nAS_FSB
|
||||
11: A_FSB<20> 25: cnt/LTimer<11> 39: nWE_FSB
|
||||
12: A_FSB<21> 26: cnt/LTimer<1> 40: ram/CAS
|
||||
13: A_FSB<22> 27: cnt/LTimer<2> 41: ram/RASEL
|
||||
14: A_FSB<23> 28: cnt/LTimer<3>
|
||||
|
||||
Signal 1 2 3 4 5 FB
|
||||
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
||||
nROMCS ..........XXXX.....................X.............. 5
|
||||
nCAS ........................................X......... 1
|
||||
nOE ......................................XX.......... 2
|
||||
RA<4> .X............X..........................X........ 3
|
||||
RA<3> .........XX..............................X........ 3
|
||||
RA<5> ..X............X.........................X........ 3
|
||||
nCAS .......................................X.......... 1
|
||||
nOE .....................................XX........... 2
|
||||
RA<4> .X............X.........................X......... 3
|
||||
RA<3> .........XX.............................X......... 3
|
||||
RA<5> ..X............X........................X......... 3
|
||||
RA<2> ......X..........X......................X......... 3
|
||||
RA<6> ...X............X.......................X......... 3
|
||||
cnt/LTimerTC ......................XXXXXXXXXXXX................ 12
|
||||
RA<2> ......X..........X.......................X........ 3
|
||||
RA<6> ...X............X........................X........ 3
|
||||
ALE0S .....................................X............ 1
|
||||
cnt/LTimer<0> XXXXXXXXXXXXXX....XXXXXXXXXXXXXXXXX.X.XX.......... 34
|
||||
cnt/LTimer<0> XXXXXXXXXXXXXX....XXXXXXXXXXXXXXXXX.XXX........... 34
|
||||
0----+----1----+----2----+----3----+----4----+----5
|
||||
0 0 0 0 0
|
||||
*********************************** FB6 ***********************************
|
||||
|
|
@ -793,6 +787,8 @@ C25MEN <= '1';
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -853,10 +849,6 @@ IONPReady_D <= ((NOT iobs/Sent AND NOT IONPReady)
|
|||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND
|
||||
NOT nWE_FSB AND NOT IONPReady));
|
||||
|
||||
FDCPE_IOPWReady: FDCPE port map (IOPWReady,IOPWReady_D,FCLK,'0','0');
|
||||
IOPWReady_D <= ((iobs/Clear1)
|
||||
OR (NOT iobs/Load1 AND nADoutLE1));
|
||||
|
||||
FDCPE_IORDREQ: FDCPE port map (IORDREQ,IORDREQ_D,FCLK,'0','0');
|
||||
IORDREQ_D <= ((NOT iobs/IORW1 AND NOT iobs/TS_FSM_FFd2 AND NOT nADoutLE1)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/TS_FSM_FFd2 AND
|
||||
|
|
@ -939,7 +931,7 @@ QoSReady_D <= ((A_FSB(22) AND NOT A_FSB(17) AND
|
|||
NOT $OpTx$$OpTx$FX_DC$354_INV$541)
|
||||
OR (A_FSB(22) AND NOT A_FSB(10) AND
|
||||
NOT $OpTx$$OpTx$FX_DC$354_INV$541)
|
||||
OR (nRESout.EXP)
|
||||
OR (cnt/LTimer(1).EXP)
|
||||
OR (A_FSB(22) AND A_FSB(21) AND
|
||||
NOT $OpTx$$OpTx$FX_DC$354_INV$541)
|
||||
OR (A_FSB(22) AND A_FSB(19) AND
|
||||
|
|
@ -1053,7 +1045,7 @@ cnt/LTimer_D(0) <= ((nROMCS_OBUF.EXP)
|
|||
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
|
||||
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
|
||||
A_FSB(8) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (ALE0S.EXP)
|
||||
OR (cnt/LTimerTC.EXP)
|
||||
OR (NOT cnt/LTimer(0) AND cnt/LTimer(3) AND
|
||||
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT cnt/LTimer(0) AND cnt/LTimer(4) AND
|
||||
|
|
@ -1076,51 +1068,32 @@ cnt/LTimer_D(0) <= ((nROMCS_OBUF.EXP)
|
|||
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2));
|
||||
|
||||
FDCPE_cnt/LTimer1: FDCPE port map (cnt/LTimer(1),cnt/LTimer_D(1),FCLK,'0','0');
|
||||
cnt/LTimer_D(1) <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
|
||||
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
|
||||
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
|
||||
A_FSB(9) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
|
||||
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
|
||||
NOT nWE_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND A_FSB(8) AND
|
||||
fsb/ASrf AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
|
||||
A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
||||
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
|
||||
A_FSB(9) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
|
||||
A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
||||
NOT nWE_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND A_FSB(8) AND
|
||||
fsb/ASrf AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
|
||||
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
|
||||
NOT nWE_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND A_FSB(9) AND
|
||||
fsb/ASrf AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
|
||||
A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
||||
NOT nWE_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND A_FSB(9) AND
|
||||
fsb/ASrf AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT cnt/LTimer(0) AND NOT cnt/LTimer(1))
|
||||
OR (NOT cnt/LTimer(1) AND
|
||||
NOT cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
cnt/LTimer_D(1) <= ((IONPReady.EXP)
|
||||
OR (cnt/LTimer(0) AND cnt/LTimer(1) AND
|
||||
cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
|
||||
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
|
||||
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
|
||||
A_FSB(9) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
|
||||
A_FSB(13) AND A_FSB(12) AND A_FSB(14) AND A_FSB(11) AND A_FSB(10) AND
|
||||
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
|
||||
A_FSB(8) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
|
||||
A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
||||
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
|
||||
A_FSB(8) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2));
|
||||
A_FSB(9) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND
|
||||
A_FSB(13) AND NOT A_FSB(12) AND NOT A_FSB(14) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
||||
NOT nWE_FSB AND NOT nAS_FSB AND cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2 AND
|
||||
A_FSB(8) AND cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2)
|
||||
OR (NOT cnt/LTimer(0) AND NOT cnt/LTimer(1))
|
||||
OR (NOT cnt/LTimer(1) AND
|
||||
NOT cnt/LTimer_1_not0001/cnt/LTimer_1_not0001_D2));
|
||||
|
||||
FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0');
|
||||
cnt/LTimer_T(2) <= ((cnt/LTimer(2) AND cnt/IS_FSM_FFd1 AND
|
||||
|
|
@ -1310,9 +1283,9 @@ FTCPE_cnt/WS0: FTCPE port map (cnt/WS(0),cnt/WS_T(0),FCLK,'0','0');
|
|||
cnt/WS_T(0) <= (nAS_FSB AND NOT cnt/WS(0) AND NOT fsb/ASrf);
|
||||
|
||||
FDCPE_cnt/WS1: FDCPE port map (cnt/WS(1),cnt/WS_D(1),FCLK,'0','0');
|
||||
cnt/WS_D(1) <= ((nAS_FSB AND NOT fsb/ASrf)
|
||||
cnt/WS_D(1) <= ((cnt/WS(0) AND cnt/WS(1))
|
||||
OR (NOT cnt/WS(0) AND NOT cnt/WS(1))
|
||||
OR (cnt/WS(0) AND cnt/WS(1)));
|
||||
OR (nAS_FSB AND NOT fsb/ASrf));
|
||||
|
||||
FTCPE_cnt/WS2: FTCPE port map (cnt/WS(2),cnt/WS_T(2),FCLK,'0','0');
|
||||
cnt/WS_T(2) <= ((nAS_FSB AND cnt/WS(2) AND NOT fsb/ASrf)
|
||||
|
|
@ -1326,16 +1299,12 @@ cnt/WS_T(3) <= ((nAS_FSB AND cnt/WS(3) AND NOT fsb/ASrf)
|
|||
|
||||
FDCPE_cnt/nIPL2r: FDCPE port map (cnt/nIPL2r,nIPL2,FCLK,'0','0');
|
||||
|
||||
FDCPE_cs/ODCSr: FDCPE port map (cs/ODCSr,cs/ODCSr_D,FCLK,'0','0');
|
||||
cs/ODCSr_D <= ((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
|
||||
NOT nAS_FSB)
|
||||
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
|
||||
fsb/ASrf));
|
||||
|
||||
FTCPE_cs/nOverlay: FTCPE port map (cs/nOverlay,cs/nOverlay_T,FCLK,'0','0');
|
||||
cs/nOverlay_T <= ((NOT nRES.PIN AND cs/nOverlay AND nAS_FSB AND NOT fsb/ASrf)
|
||||
OR (nRES.PIN AND NOT cs/nOverlay AND nAS_FSB AND cs/ODCSr AND
|
||||
NOT fsb/ASrf));
|
||||
cs/nOverlay_T <= ((NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
|
||||
NOT cs/nOverlay AND NOT nAS_FSB)
|
||||
OR (NOT A_FSB(23) AND A_FSB(22) AND NOT A_FSB(21) AND NOT A_FSB(20) AND
|
||||
NOT cs/nOverlay AND fsb/ASrf)
|
||||
OR (NOT nRES.PIN AND cs/nOverlay AND nAS_FSB AND NOT fsb/ASrf));
|
||||
|
||||
FDCPE_fsb/ASrf: FDCPE port map (fsb/ASrf,NOT nAS_FSB,NOT FCLK,'0','0');
|
||||
|
||||
|
|
@ -1589,17 +1558,17 @@ nBR_IOB_T <= ((nBR_IOB AND NOT cnt/IS_FSM_FFd1 AND NOT cnt/IS_FSM_FFd2)
|
|||
FDCPE_nCAS: FDCPE port map (nCAS,NOT ram/CAS,NOT FCLK,'0','0');
|
||||
|
||||
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0','0');
|
||||
nDTACK_FSB_D <= ((NOT QoSReady)
|
||||
OR (NOT A_FSB(22) AND NOT IONPReady AND NOT RAMReady)
|
||||
nDTACK_FSB_D <= ((NOT A_FSB(22) AND NOT IONPReady AND NOT RAMReady)
|
||||
OR (A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16))
|
||||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
A_FSB(17) AND A_FSB(16) AND A_FSB(13) AND NOT nWE_FSB AND NOT IONPReady AND
|
||||
NOT IOPWReady)
|
||||
NOT nADoutLE1)
|
||||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||||
A_FSB(17) AND A_FSB(16) AND A_FSB(14) AND NOT nWE_FSB AND NOT IONPReady AND
|
||||
NOT IOPWReady)
|
||||
NOT nADoutLE1)
|
||||
OR (A_FSB(23) AND NOT IONPReady)
|
||||
OR (NOT IONPReady AND NOT QoSReady)
|
||||
OR (nAS_FSB AND NOT fsb/ASrf)
|
||||
OR (A_FSB(22) AND A_FSB(21) AND NOT IONPReady)
|
||||
OR (A_FSB(22) AND A_FSB(20) AND NOT IONPReady));
|
||||
|
|
@ -1678,10 +1647,10 @@ nVMA_IOB_OE <= NOT nAoutOE;
|
|||
FDCPE_nVPA_FSB: FDCPE port map (nVPA_FSB,nVPA_FSB_D,FCLK,'0',nAS_FSB);
|
||||
nVPA_FSB_D <= ((A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND IONPReady AND
|
||||
NOT nAS_FSB AND QoSReady)
|
||||
NOT nAS_FSB)
|
||||
OR (A_FSB(23) AND A_FSB(22) AND A_FSB(21) AND A_FSB(20) AND
|
||||
A_FSB(19) AND A_FSB(18) AND A_FSB(17) AND A_FSB(16) AND IONPReady AND
|
||||
QoSReady AND fsb/ASrf));
|
||||
fsb/ASrf));
|
||||
|
||||
FDCPE_ram/CAS: FDCPE port map (ram/CAS,ram/CAS_D,FCLK,'0','0');
|
||||
ram/CAS_D <= ((ram/RS_FSM_FFd7)
|
||||
|
|
@ -1697,11 +1666,11 @@ ram/CAS_D <= ((ram/RS_FSM_FFd7)
|
|||
ram/RS_FSM_FFd8 AND fsb/ASrf));
|
||||
|
||||
FTCPE_ram/Once: FTCPE port map (ram/Once,ram/Once_T,FCLK,'0','0');
|
||||
ram/Once_T <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND ram/RAMEN AND cs/nOverlay AND
|
||||
ram/Once_T <= ((ram/Once AND nAS_FSB AND NOT fsb/ASrf)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND ram/RAMEN AND cs/nOverlay AND
|
||||
NOT ram/Once AND NOT nAS_FSB AND ram/RS_FSM_FFd8)
|
||||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND ram/RAMEN AND cs/nOverlay AND
|
||||
NOT ram/Once AND ram/RS_FSM_FFd8 AND fsb/ASrf)
|
||||
OR (ram/Once AND nAS_FSB AND NOT fsb/ASrf));
|
||||
NOT ram/Once AND ram/RS_FSM_FFd8 AND fsb/ASrf));
|
||||
|
||||
FDCPE_ram/RAMEN: FDCPE port map (ram/RAMEN,ram/RAMEN_D,FCLK,'0','0');
|
||||
ram/RAMEN_D <= ((ram/RS_FSM_FFd7)
|
||||
|
|
|
|||
|
|
@ -3,13 +3,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
|||
--> Parameter TMPDIR set to xst/projnav.tmp
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 1.00 secs
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 1.00 secs
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
--> Reading design: WarpSE.prj
|
||||
|
|
@ -145,9 +145,6 @@ Performing bidirectional port resolution...
|
|||
Synthesizing Unit <CS>.
|
||||
Related source file is "../CS.v".
|
||||
Found 1-bit register for signal <nOverlay>.
|
||||
Found 1-bit register for signal <ODCSr>.
|
||||
Summary:
|
||||
inferred 2 D-type flip-flop(s).
|
||||
Unit <CS> synthesized.
|
||||
|
||||
|
||||
|
|
@ -193,7 +190,6 @@ Synthesizing Unit <IOBS>.
|
|||
| Encoding | automatic |
|
||||
| Implementation | automatic |
|
||||
-----------------------------------------------------------------------
|
||||
Found 1-bit register for signal <IOPWReady>.
|
||||
Found 1-bit register for signal <IORDREQ>.
|
||||
Found 1-bit register for signal <IOL0>.
|
||||
Found 1-bit register for signal <IOWRREQ>.
|
||||
|
|
@ -322,8 +318,8 @@ Macro Statistics
|
|||
2-bit adder : 1
|
||||
# Counters : 3
|
||||
4-bit up counter : 3
|
||||
# Registers : 68
|
||||
1-bit register : 67
|
||||
# Registers : 66
|
||||
1-bit register : 65
|
||||
2-bit register : 1
|
||||
# Tristates : 5
|
||||
1-bit tristate buffer : 5
|
||||
|
|
@ -392,8 +388,8 @@ Macro Statistics
|
|||
2-bit adder : 1
|
||||
# Counters : 3
|
||||
4-bit up counter : 3
|
||||
# Registers : 46
|
||||
Flip-Flops : 46
|
||||
# Registers : 44
|
||||
Flip-Flops : 44
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
|
@ -483,22 +479,22 @@ Design Statistics
|
|||
# IOs : 75
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 655
|
||||
# AND2 : 203
|
||||
# BELS : 653
|
||||
# AND2 : 202
|
||||
# AND3 : 27
|
||||
# AND4 : 13
|
||||
# AND5 : 2
|
||||
# AND7 : 2
|
||||
# AND8 : 4
|
||||
# GND : 6
|
||||
# INV : 254
|
||||
# INV : 253
|
||||
# OR2 : 112
|
||||
# OR3 : 9
|
||||
# OR4 : 2
|
||||
# VCC : 1
|
||||
# XOR2 : 20
|
||||
# FlipFlops/Latches : 100
|
||||
# FD : 67
|
||||
# FlipFlops/Latches : 98
|
||||
# FD : 65
|
||||
# FDC : 2
|
||||
# FDCE : 30
|
||||
# FDP : 1
|
||||
|
|
@ -510,12 +506,12 @@ Cell Usage :
|
|||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 6.00 secs
|
||||
Total CPU time to Xst completion: 5.09 secs
|
||||
Total REAL time to Xst completion: 5.00 secs
|
||||
Total CPU time to Xst completion: 5.04 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 267012 kilobytes
|
||||
Total memory usage is 266756 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 4 ( 0 filtered)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
|
|
@ -5,7 +5,7 @@
|
|||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Sun Apr 09 05:01:25 2023">
|
||||
<application stringID="NgdBuild" timeStamp="Sun Apr 09 23:31:16 2023">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
|
|
@ -66,17 +66,17 @@
|
|||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="203"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="202"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="27"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="67"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="65"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDCE" value="30"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDP" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="35"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="254"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="253"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="30"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="112"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="9"/>
|
||||
|
|
@ -85,13 +85,13 @@
|
|||
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="20"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="203"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="202"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="27"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND4" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="76"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="74"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="41"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="254"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="253"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="30"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="112"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="9"/>
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
Release 8.1i - Fit P.20131013
|
||||
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
|
||||
|
||||
4- 9-2023 5:01AM
|
||||
4- 9-2023 11:31PM
|
||||
|
||||
NOTE: This file is designed to be imported into a spreadsheet program
|
||||
such as Microsoft Excel for viewing, printing and sorting. The comma ','
|
||||
|
|
|
|||
|
|
|
@ -5,7 +5,7 @@
|
|||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Sun Apr 09 05:01:15 2023">
|
||||
<application stringID="Xst" timeStamp="Sun Apr 09 23:31:05 2023">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
|
|
@ -79,8 +79,8 @@
|
|||
<item dataType="int" stringID="XST_COUNTERS" value="3">
|
||||
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="3"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="68">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="67"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="66">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="65"/>
|
||||
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_TRISTATES" value="5">
|
||||
|
|
@ -93,8 +93,8 @@
|
|||
<item dataType="int" stringID="XST_COUNTERS" value="3">
|
||||
<item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="3"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="46">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="46"/>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="44">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="44"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
|
|
@ -114,18 +114,18 @@
|
|||
<item stringID="XST_IOS" value="75"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="655">
|
||||
<item dataType="int" stringID="XST_AND2" value="203"/>
|
||||
<item dataType="int" stringID="XST_BELS" value="653">
|
||||
<item dataType="int" stringID="XST_AND2" value="202"/>
|
||||
<item dataType="int" stringID="XST_AND3" value="27"/>
|
||||
<item dataType="int" stringID="XST_AND4" value="13"/>
|
||||
<item dataType="int" stringID="XST_GND" value="6"/>
|
||||
<item dataType="int" stringID="XST_INV" value="254"/>
|
||||
<item dataType="int" stringID="XST_INV" value="253"/>
|
||||
<item dataType="int" stringID="XST_OR2" value="112"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||
<item dataType="int" stringID="XST_XOR2" value="20"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="100">
|
||||
<item dataType="int" stringID="XST_FD" value="67"/>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="98">
|
||||
<item dataType="int" stringID="XST_FD" value="65"/>
|
||||
<item dataType="int" stringID="XST_FDC" value="2"/>
|
||||
<item dataType="int" stringID="XST_FDCE" value="30"/>
|
||||
<item dataType="int" stringID="XST_FDP" value="1"/>
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1681030880
|
||||
C:\Users\Wolf\Documents\GitHub\Warp-SE\cpld\XC95144XL\WarpSE.ngc 1681097470
|
||||
OK
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2023-04-09T04:28:14</DateModified>
|
||||
<DateModified>2023-04-09T23:31:34</DateModified>
|
||||
<ModuleName>WarpSE</ModuleName>
|
||||
<SummaryTimeStamp>2023-04-09T02:22:59</SummaryTimeStamp>
|
||||
<SummaryTimeStamp>2023-04-09T23:24:43</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL/iseconfig/WarpSE.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>C:/Users/Wolf/Documents/GitHub/Warp-SE/cpld/XC95144XL\</ImplementationReportsDirectory>
|
||||
<DateInitialized>2023-04-07T01:51:28</DateInitialized>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Sun Apr 09 05:01:14 2023">
|
||||
<application name="pn" timeStamp="Sun Apr 09 23:31:05 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="7132971001B64D51887D7F260ADC77C3" type="project"/>
|
||||
<property name="ProjectIteration" value="0" type="project"/>
|
||||
|
|
@ -12,7 +12,6 @@ This means code written to parse this file will need to be revisited each subseq
|
|||
</section>
|
||||
<section name="Project Statistics" visible="true">
|
||||
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
|
||||
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
|
||||
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
|
||||
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
|
||||
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
|
||||
|
|
@ -21,7 +20,6 @@ This means code written to parse this file will need to be revisited each subseq
|
|||
<property name="PROP_SynthTopFile" value="changed" type="process"/>
|
||||
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
|
||||
<property name="PROP_UseSmartGuide" value="false" type="design"/>
|
||||
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
|
||||
<property name="PROP_intProjectCreationTimestamp" value="2023-04-07T01:50:52" type="design"/>
|
||||
<property name="PROP_intWbtProjectID" value="7132971001B64D51887D7F260ADC77C3" type="design"/>
|
||||
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,7 +1,7 @@
|
|||
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1681030875
|
||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1681030875
|
||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1681030875
|
||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1681030875
|
||||
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1681030875
|
||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1681030875
|
||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1681030875
|
||||
MO CNT NULL ../CNT.v vlg65/_c_n_t.bin 1681097466
|
||||
MO CS NULL ../CS.v vlg22/_c_s.bin 1681097466
|
||||
MO FSB NULL ../FSB.v vlg37/_f_s_b.bin 1681097466
|
||||
MO IOBM NULL ../IOBM.v vlg73/_i_o_b_m.bin 1681097466
|
||||
MO WarpSE NULL ../WarpSE.v vlg52/_warp_s_e.bin 1681097466
|
||||
MO IOBS NULL ../IOBS.v vlg79/_i_o_b_s.bin 1681097466
|
||||
MO RAM NULL ../RAM.v vlg14/_r_a_m.bin 1681097466
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Loading…
Reference in New Issue