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Add slowdown settings

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This commit is contained in:
Zane Kaminski
2024-10-11 16:41:31 -04:00
parent cfe5cf936c
commit d92e235e25
5 changed files with 119 additions and 36 deletions
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38
cpld/CNT.v
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@@ -11,11 +11,23 @@ module CNT(
input nAS, input nAS,
input ASrf, input ASrf,
input BACT, input BACT,
input QoSCS, input IACKCS,
input SndQoSCS, input VIACS,
input IWMCS,
input SCCCS,
input SCSICS,
input SndCSWR,
/* QoS settings inputs */
input SlowIACK,
input SlowVIA,
input SlowIWM,
input SlowSCC,
input SlowSCSI,
input SlowSnd,
input SlowClockGate,
input [3:0] SlowTimeout,
/* QoS outputs */ /* QoS outputs */
output reg QoSEN, output reg QoSEN,
output SndQoSReady,
output reg MCKE); output reg MCKE);
/* E clock synchronization */ /* E clock synchronization */
@@ -57,9 +69,16 @@ module CNT(
always @(posedge CLK) TimerTick <= EFall && TimerTC; always @(posedge CLK) TimerTick <= EFall && TimerTC;
/* QoS select latches */ /* QoS select latches */
reg QoSCSr, SndQoSCSr; reg QoSCSr;
always @(posedge CLK) QoSCSr <= (BACT && QoSCS) || !nRESin; always @(posedge CLK) begin
always @(posedge CLK) SndQoSCSr <= BACT && SndQoSCS; QoSCSr <= !nRESin ||
(!nAS && SlowIACK && IACKCS) ||
(!nAS && SlowVIA && VIACS) ||
(!nAS && SlowIWM && IWMCS) ||
(!nAS && SlowSCC && SCCCS) ||
(!nAS && SlowSCSI && SCSICS) ||
(!nAS && SlowSnd && SndCSWR);
end
/* QoS timer /* QoS timer
* In the absence of a QoS trigger, QS==0. * In the absence of a QoS trigger, QS==0.
@@ -68,19 +87,18 @@ module CNT(
* QoS enable period is 196.588 us - 210.630 us */ * QoS enable period is 196.588 us - 210.630 us */
reg [3:0] QS; reg [3:0] QS;
always @(posedge CLK) begin always @(posedge CLK) begin
if (SndQoSCSr || QoSCSr) QS <= 15; if (QoSCSr) QS <= 15;
else if (QS==0) QS <= 0; else if (QS==0) QS <= 0;
else if (TimerTick) QS <= QS-1; else if (TimerTick) QS <= QS-1;
end end
/* QoS enable control */ /* QoS enable control */
always @(posedge CLK) if (!BACT) QoSEN <= QS!=0; always @(posedge CLK) if (!BACT) QoSEN <= QS!=0 || SlowTimeout==0;
assign SndQoSReady = 1;
/* MC68k clock gating during QoS */ /* MC68k clock gating during QoS */
always @(negedge CLK, negedge nAS) begin always @(negedge CLK, negedge nAS) begin
if (!nAS) MCKE <= 1; if (!nAS) MCKE <= 1;
else MCKE <= ASrf || !QoSEN || C8MFall; else MCKE <= ASrf || !QoSEN || C8MFall || !SlowClockGate;
end end
/* Long timer counts from 0 to 4095. /* Long timer counts from 0 to 4095.

20
cpld/CS.v
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@@ -9,7 +9,9 @@ module CS(
output IOCS, output IORealCS, output IOPWCS, output IACS, output IOCS, output IORealCS, output IOPWCS, output IACS,
output ROMCS, output ROMCS4X, output ROMCS, output ROMCS4X,
output RAMCS, output RAMCS0X, output RAMCS, output RAMCS0X,
output QoSCS, output SndQoSCS); output IACKCS, output VIACS, output IWMCS,
output SCCCS, output SCSICS, output SndCSWR,
output SetCSWR);
/* Overlay control */ /* Overlay control */
reg Overlay; reg Overlay;
@@ -19,11 +21,11 @@ module CS(
end end
/* I/O select signals */ /* I/O select signals */
wire IACKCS = A[23:20]==4'hF; assign IACKCS = A[23:20]==4'hF;
wire VIACS = A[23:20]==4'hE; assign VIACS = A[23:20]==4'hE;
wire IWMCS = A[23:20]==4'hD; assign IWMCS = A[23:20]==4'hD;
wire SCCCS = A[23:20]==4'hB || A[23:20]==4'h9; assign SCCCS = A[23:20]==4'hB || A[23:20]==4'h9;
wire SCSICS = A[23:20]==4'h5; assign SCSICS = A[23:20]==4'h5;
/* ROM select signals */ /* ROM select signals */
assign ROMCS4X = A[23:20]==4'h4; assign ROMCS4X = A[23:20]==4'h4;
@@ -46,11 +48,11 @@ module CS(
//A[15:12]==4'hD || // 4096 bytes video //A[15:12]==4'hD || // 4096 bytes video
//A[15:12]==4'hE || // 4096 bytes video //A[15:12]==4'hE || // 4096 bytes video
//A[15:12]==4'hF); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound //A[15:12]==4'hF); // 3200 bytes video, 128 bytes RAM (system error space), 768 bytes sound
wire SndRAMCSWR = VidRAMCSWR64k && ( assign SndCSWR = VidRAMCSWR64k && (
((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) || ((A[15:12]==4'hF) && (A[11:8]==4'hD || A[11:8]==4'hE || A[11:8]==4'hF)) ||
((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3))); ((A[15:12]==4'hA) && (A[11:8]==4'h1 || A[11:8]==4'h2 || A[11:8]==4'h3)));
assign QoSCS = IACKCS || VIACS || IWMCS || SCCCS || SCSICS;
assign SndQoSCS = SndRAMCSWR; assign SetCSWR = A[23:20]==4'hF && !A[19];
/* Select signals - IOB domain */ /* Select signals - IOB domain */
assign IACS = A[23:20]==4'hF; // IACK assign IACS = A[23:20]==4'hF; // IACK

11
cpld/FSB.v
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@@ -7,9 +7,9 @@ module FSB(
input ROMCS, input ROMCS,
input RAMCS, input RAMReady, input RAMCS, input RAMReady,
input IOPWCS, input IOPWReady, input IONPReady, input IOPWCS, input IOPWReady, input IONPReady,
input QoSEN, input SndQoSReady, input QoSEN,
/* Interrupt acknowledge select */ /* Interrupt acknowledge select */
input IACS); input IACKCS);
/* AS cycle detection */ /* AS cycle detection */
always @(negedge FCLK) begin ASrf <= !nAS; end always @(negedge FCLK) begin ASrf <= !nAS; end
@@ -19,15 +19,14 @@ module FSB(
/* DTACK/VPA control */ /* DTACK/VPA control */
wire Ready = (RAMCS && !QoSEN && RAMReady && !IOPWCS) || wire Ready = (RAMCS && !QoSEN && RAMReady && !IOPWCS) ||
(RAMCS && !QoSEN && RAMReady && IOPWCS && IOPWReady) || (RAMCS && !QoSEN && RAMReady && IOPWCS && IOPWReady) ||
(ROMCS && !QoSEN) || (ROMCS && !QoSEN) || (IONPReady);
(IONPReady && SndQoSReady);
always @(posedge FCLK, posedge nAS) begin always @(posedge FCLK, posedge nAS) begin
if (nAS) nDTACK <= 1; if (nAS) nDTACK <= 1;
else nDTACK <= !(Ready && !IACS); else nDTACK <= !(Ready && !IACKCS);
end end
always @(posedge FCLK, posedge nAS) begin always @(posedge FCLK, posedge nAS) begin
if (nAS) nVPA <= 1; if (nAS) nVPA <= 1;
else nVPA <= !(Ready && IACS); else nVPA <= !(Ready && IACKCS);
end end
endmodule endmodule

30
cpld/SET.v Normal file
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@@ -0,0 +1,30 @@
module SET(
input CLK,
input BACT,
input [11:1] A,
input SetCSWR,
output reg SlowIACK,
output reg SlowVIA,
output reg SlowIWM,
output reg SlowSCC,
output reg SlowSCSI,
output reg SlowSnd,
output reg SlowClockGate,
output reg [3:0] SlowTimeout);
reg SetWRr; always @(posedge CLK) SetWRr <= BACT && SetCSWR;
always @(posedge CLK) begin
if (SetWRr) begin
SlowTimeout[3:0] <= A[11:8];
SlowIACK <= A[7];
SlowVIA <= A[6];
SlowIWM <= A[5];
SlowSCC <= A[4];
SlowSCSI <= A[3];
SlowSnd <= A[2];
SlowClockGate <= A[1];
end
end
endmodule

56
cpld/WarpSE.v
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@@ -63,10 +63,12 @@ module WarpSE(
wire RefReq, RefUrg; wire RefReq, RefUrg;
/* FSB chip select signals */ /* FSB chip select signals */
wire IOCS, IORealCS, IOPWCS, IACS; wire IOCS, IORealCS, IOPWCS;
wire ROMCS, ROMCS4X; wire ROMCS, ROMCS4X;
wire RAMCS, RAMCS0X; wire RAMCS, RAMCS0X;
wire QoSCS, SndQoSCS, QoSEN; wire QoSEN;
wire IACKCS, VIACS, IWMCS, SCCCS, SCSICS, SndCSWR;
wire SetCSWR;
CS cs( CS cs(
/* MC68HC000 interface */ /* MC68HC000 interface */
.A(A_FSB[23:08]), .A(A_FSB[23:08]),
@@ -81,13 +83,19 @@ module WarpSE(
.IOCS(IOCS), .IOCS(IOCS),
.IORealCS(IORealCS), .IORealCS(IORealCS),
.IOPWCS(IOPWCS), .IOPWCS(IOPWCS),
.IACS(IACS),
.ROMCS(ROMCS), .ROMCS(ROMCS),
.ROMCS4X(ROMCS4X), .ROMCS4X(ROMCS4X),
.RAMCS(RAMCS), .RAMCS(RAMCS),
.RAMCS0X(RAMCS0X), .RAMCS0X(RAMCS0X),
.QoSCS(QoSCS), /* Motherboard I/O device select outputs */
.SndQoSCS(SndQoSCS)); .IACKCS(IACKCS),
.VIACS(VIACS),
.IWMCS(IWMCS),
.SCCCS(SCCCS),
.SCSICS(SCSICS),
.SndCSWR(SndCSWR),
/* Settings register select output */
.SetCSWR(SetCSWR));
wire RAMReady; wire RAMReady;
RAM ram( RAM ram(
@@ -196,7 +204,22 @@ module WarpSE(
.IOACT(IOACT), .IOACT(IOACT),
.IODONE(IODONE)); .IODONE(IODONE));
wire SndQoSReady; wire SlowIACK, SlowVIA, SlowIWM, SlowSCC, SlowSCSI, SlowSnd, SlowClockGate;
wire [3:0] SlowTimeout;
SET set(
.CLK(FCLK),
.BACT(BACT),
.A(A_FSB[11:1]),
.SetCSWR(SetCSWR),
.SlowIACK(SlowIACK),
.SlowVIA(SlowVIA),
.SlowIWM(SlowIWM),
.SlowSCC(SlowSCC),
.SlowSCSI(SlowSCSI),
.SlowSnd(SlowSnd),
.SlowClockGate(SlowClockGate),
.SlowTimeout(SlowTimeout));
wire nBR_IOBout; wire nBR_IOBout;
assign nBR_IOB = nBR_IOBout ? 1'bZ : 1'b0; assign nBR_IOB = nBR_IOBout ? 1'bZ : 1'b0;
CNT cnt( CNT cnt(
@@ -218,11 +241,23 @@ module WarpSE(
.nAS(nAS_FSB), .nAS(nAS_FSB),
.ASrf(ASrf), .ASrf(ASrf),
.BACT(BACT), .BACT(BACT),
.QoSCS(QoSCS), .IACKCS(IACKCS),
.SndQoSCS(SndQoSCS), .VIACS(VIACS),
.IWMCS(IWMCS),
.SCCCS(SCCCS),
.SCSICS(SCSICS),
.SndCSWR(SndCSWR),
/* QoS settings inputs */
.SlowIACK(SlowIACK),
.SlowVIA(SlowVIA),
.SlowIWM(SlowIWM),
.SlowSCC(SlowSCC),
.SlowSCSI(SlowSCSI),
.SlowSnd(SlowSnd),
.SlowClockGate(SlowClockGate),
.SlowTimeout(SlowTimeout),
/* QoS outputs */ /* QoS outputs */
.QoSEN(QoSEN), .QoSEN(QoSEN),
.SndQoSReady(SndQoSReady),
.MCKE(MCKE)); .MCKE(MCKE));
FSB fsb( FSB fsb(
@@ -243,9 +278,8 @@ module WarpSE(
.IOPWReady(IOPWReady), .IOPWReady(IOPWReady),
.IONPReady(IONPReady), .IONPReady(IONPReady),
.QoSEN(QoSEN), .QoSEN(QoSEN),
.SndQoSReady(SndQoSReady),
/* Interrupt acknowledge select */ /* Interrupt acknowledge select */
.IACS(IACS)); .IACKCS(IACKCS));
endmodule endmodule