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46
cpld/CNT.v
46
cpld/CNT.v
@ -6,7 +6,7 @@ module CNT(
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/* Refresh request */
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output reg RefReq, output RefUrgent,
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/* BERR and QoS speed limit output */
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output reg BERRTimeout, output reg QoSReady,
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output reg BERRTimeout, output reg QoSGate,
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/* Reset, switch, button */
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input [3:1] SW, input nRESin, output reg nRESout, input nIPL2,
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/* Configuration outputs */
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@ -60,45 +60,53 @@ module CNT(
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end
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/* Sound QoS */
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reg [3:0] SC; // Sound counter
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always @(posedge C16M) begin
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if (PORDone && TimerTC) SC <= SC+1; // SC increment
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if SC[]
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QoSGate <= Timer[7:6]==2'b11;
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end
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/* IPL2 and /RESET registration */
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reg nIPL2r, nRESr;
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/* Button/switch synchronization */
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reg RESr, IPL2r;
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wire DisableSw = SW[1];
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reg DisableBtn;
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wire FastROMSw = !SW[2];
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reg FastROMBtn;
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always @(posedge C16M) begin
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nIPL2r <= nIPL2;
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nRESr <= nRES;
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DisableBtn <= !nRES;
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FastROMBtn <= !nIPL2;
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end
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/* Startup sequence control */
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reg PORDone = 0;
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reg [3:0] SC; // Startup counter
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always @(posedge C16M) if (PORDone && TimerTC) SC <= SC+1; // SC increment
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always @(posedge C16M) begin
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if (!PORDone) begin
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if (!nRESr) nRESout <= 1;
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else begin
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if (!nRESr) begin // While Mac is asserting POR...
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nRESout <= 1; // Disable reset
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nBR_IOB <= 1; // Disable bus request
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end else begin // Once Mac disbles POR...
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nRESout <= 0; // Re-enable reset
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PORDone <= 1; // Mark POR done
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// Decode buttons
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if (nRESr) begin // Reset not pressed: enable WarpSE
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nBR_IOB <= 0; // Request Mac bus
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FastROMEN <= 1; // Fast ROM enabled
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end else if (!nRES && nIPL2r) begin // Reset only: disable card
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if ((DisableSw ^ DisableBtn) && !FastROMBtn) begin
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// Disable switch XOR disable button and no ROM button
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nBR_IOB <= 1; // Don't request Mac bus
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FastROMEN <= 0; // Fast ROM enable is don't care
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end else if (!nRES && !nIPL2r) begin // Reset+IPL2: MB ROM
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end else if (( (DisableSw ^ DisableBtn) && FastROMBtn) ||
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(!(DisableSw ^ DisableBtn))) begin
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// Disable switch XOR disable button and ROM button
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// Or neither pressed/enabled
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// Or both pressed/enabled
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nBR_IOB <= 0; // Request Mac bus
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FastROMEN <= 1; // Fast ROM disabled so as to use motherboard ROM
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FastROMEN <= FastROMSw ^ FastROMBtn;
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end
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end
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end else if (SC[4]) nRESout <= 1; // Release reset to run
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end else if (SC[3:2]==2'b11) nRESout <= 1; // Release reset to run after 12 refresh cycles
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end
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// Enable both oscillators... only mount one
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assign C20MEN = 1; // SW[0];
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assign C25MEN = 1; //!SW[0];
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assign C20MEN = 1;
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assign C25MEN = 1;
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endmodule
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