Macintosh-HW/Warp-SE
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This commit is contained in:
Zane Kaminski 2022-09-05 04:37:18 -04:00
parent a91c6c4ffb
commit ddec174eb1
1 changed files with 27 additions and 19 deletions
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46
cpld/CNT.v
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@ -6,7 +6,7 @@ module CNT(
/* Refresh request */ /* Refresh request */
output reg RefReq, output RefUrgent, output reg RefReq, output RefUrgent,
/* BERR and QoS speed limit output */ /* BERR and QoS speed limit output */
output reg BERRTimeout, output reg QoSReady, output reg BERRTimeout, output reg QoSGate,
/* Reset, switch, button */ /* Reset, switch, button */
input [3:1] SW, input nRESin, output reg nRESout, input nIPL2, input [3:1] SW, input nRESin, output reg nRESout, input nIPL2,
/* Configuration outputs */ /* Configuration outputs */
@ -60,45 +60,53 @@ module CNT(
end end
/* Sound QoS */ /* Sound QoS */
reg [3:0] SC; // Sound counter
always @(posedge C16M) begin always @(posedge C16M) begin
if (PORDone && TimerTC) SC <= SC+1; // SC increment QoSGate <= Timer[7:6]==2'b11;
if SC[]
end end
/* IPL2 and /RESET registration */ /* Button/switch synchronization */
reg nIPL2r, nRESr; reg RESr, IPL2r;
wire DisableSw = SW[1];
reg DisableBtn;
wire FastROMSw = !SW[2];
reg FastROMBtn;
always @(posedge C16M) begin always @(posedge C16M) begin
nIPL2r <= nIPL2; DisableBtn <= !nRES;
nRESr <= nRES; FastROMBtn <= !nIPL2;
end end
/* Startup sequence control */ /* Startup sequence control */
reg PORDone = 0; reg PORDone = 0;
reg [3:0] SC; // Startup counter
always @(posedge C16M) if (PORDone && TimerTC) SC <= SC+1; // SC increment
always @(posedge C16M) begin always @(posedge C16M) begin
if (!PORDone) begin if (!PORDone) begin
if (!nRESr) nRESout <= 1; if (!nRESr) begin // While Mac is asserting POR...
else begin nRESout <= 1; // Disable reset
nBR_IOB <= 1; // Disable bus request
end else begin // Once Mac disbles POR...
nRESout <= 0; // Re-enable reset nRESout <= 0; // Re-enable reset
PORDone <= 1; // Mark POR done PORDone <= 1; // Mark POR done
// Decode buttons // Decode buttons
if (nRESr) begin // Reset not pressed: enable WarpSE if ((DisableSw ^ DisableBtn) && !FastROMBtn) begin
nBR_IOB <= 0; // Request Mac bus // Disable switch XOR disable button and no ROM button
FastROMEN <= 1; // Fast ROM enabled
end else if (!nRES && nIPL2r) begin // Reset only: disable card
nBR_IOB <= 1; // Don't request Mac bus nBR_IOB <= 1; // Don't request Mac bus
FastROMEN <= 0; // Fast ROM enable is don't care FastROMEN <= 0; // Fast ROM enable is don't care
end else if (!nRES && !nIPL2r) begin // Reset+IPL2: MB ROM end else if (( (DisableSw ^ DisableBtn) && FastROMBtn) ||
(!(DisableSw ^ DisableBtn))) begin
// Disable switch XOR disable button and ROM button
// Or neither pressed/enabled
// Or both pressed/enabled
nBR_IOB <= 0; // Request Mac bus nBR_IOB <= 0; // Request Mac bus
FastROMEN <= 1; // Fast ROM disabled so as to use motherboard ROM FastROMEN <= FastROMSw ^ FastROMBtn;
end end
end end
end else if (SC[4]) nRESout <= 1; // Release reset to run end else if (SC[3:2]==2'b11) nRESout <= 1; // Release reset to run after 12 refresh cycles
end end
// Enable both oscillators... only mount one // Enable both oscillators... only mount one
assign C20MEN = 1; // SW[0]; assign C20MEN = 1;
assign C25MEN = 1; //!SW[0]; assign C25MEN = 1;
endmodule endmodule