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Improved a lot of stuff

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This commit is contained in:
Zane Kaminski 2023-03-20 00:53:10 -04:00
parent f68adf22ea
commit fb6b6debcc
4 changed files with 112 additions and 81 deletions
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146
cpld/CNT.v
View File

@ -1,107 +1,121 @@
module CNT( module CNT(
/* C16M clock */ /* C8M clock input */
input C16M, input C8M,
/* FSB clock and bus active signal */ /* FSB clock and bus active signal */
input FCLK, input BACT, input FCLK, input LBACT,
/* Refresh request */ /* Refresh request */
output reg RefReq, output RefUrgent, output reg RefReq, output RefUrgent,
/* BERR and QoS speed limit output */ /* BERR output */
output reg BERRTimeout, output reg QoSGate, output reg BERRTimeout,
/* Reset, switch, button */ /* Reset, switch, button */
input [3:1] SW, input nRESin, output reg nRESout, input nIPL2, input [3:1] SW, input nRESin, output reg nRESout, input nIPL2,
/* Mac PDS bus master control outputs */
output reg AoutOE, output nAoutOE, output nBR_IOB,
/* Configuration outputs */ /* Configuration outputs */
output reg nBR_IOB, output reg FastROMEN, output reg C20MEN, output reg C25MEN); output reg WarpEnable, output reg FastROMEN, output C20MEN, output C25MEN);
/* Timer counts from 0 to 11100000 (224) -- 225 states == 14.36 uS */ /* Timer counts from 0 to 1100000 (96) -- 97 states == 12.382 us */
reg [7:0] Timer = 0; reg [6:0] Timer = 0;
wire TimerTC = Timer[7:5]==3'b111; wire TimerTC = Timer[6:5]==2'b11;
always @(posedge C16M) Timer <= TimerTC ? 0 : Timer+1; always @(posedge C8M) Timer <= TimerTC ? 0 : Timer+1;
/* Refresh timer outputs /* Refresh timer sequence
* ___ ______________________________________ * | Timer | RefReq | RefUrgent |
* RefReq |___________| |__________ * |----------------------------|
* ___ ^ Timer==0 ^ Timer==17 _____________^ Timer==0 * | 0 | 0 | 0 |
* RefUrg |____________________________________| |__________ * | 1 | 0 | 0 |
* ^ Timer==0 ^ Timer==128 ^ Timer==0 * | 2 | 0 | 0 |
* | 3 | 0 | 0 |
* | 4 | 0 | 0 |
* | 5 | 0 | 0 |
* | 6 | 0 | 0 |
* | 7 | 0 | 0 |
* | 8 | 0 | 0 |
* | 9 | 1 | 0 |
* | 10 | 1 | 0 |
* | 11 | 1 | 0 |
* | ... | 1 | 0 |
* | 62 | 1 | 0 |
* | 63 | 1 | 0 |
* | 64 | 1 | 1 |
* | 65 | 1 | 1 |
* | 66 | 1 | 1 |
* | ... | 1 | 1 |
* | 93 | 1 | 1 |
* | 94 | 1 | 1 |
* | 95 | 1 | 1 |
* | 96 | 1 | 1 |
* back to timer==0
*/ */
assign RefUrgent = Timer[7]; assign RefUrgent = Timer[6];
always @(posedge C16M) begin always @(posedge C8M) begin
if (Timer[4]) RefREQ <= 1; if (Timer[3]) RefREQ <= 1;
else if (TimerTC) RefREQ <= 0; else if (TimerTC) RefREQ <= 0;
end end
/* NBACT - "Narrow BACT" in FCLK clock domain */ /* LBACTr - LBACT synchronized to C16M clock domain */
reg [1:0] BACTCnt = 0; reg LBACTr;
reg NBACT; always @(posedge C8M) LBACTr <= LBACT;
always @(posedge FCLK) begin
if (!BACT) begin
BACTCnt <= 0;
NBACT <= 0;
end else begin
BACTCnt <= BACTCnt+1;
if (BACTCnt==2'b11 && BACT) NBACT <= 1;
end
end
/* NBACTr - NBACT synchronized to C16M clock domain */ /* BERR generation in C8M clock domain */
reg NBACTr;
always @(posedge C16M) NBACTr <= NBACT;
/* BERR generation in C16M clock domain */
reg BERRArm = 0; reg BERRArm = 0;
reg BERRTimeout = 0; reg BERRTimeout = 0;
always @(posedge C16M) begin always @(posedge C8M) begin
if (NBACTr && TimerTC) begin if (LBACTr && TimerTC) begin
BERRArm <= 1; BERRArm <= 1;
if (BERRArm) BERRTimeout <= 1; if (BERRArm) BERRTimeout <= 1;
end else if (!NBACTr) begin end else if (!LBACTr) begin
BERRArm <= 0; BERRArm <= 0;
BERRTimeout <= 0; BERRTimeout <= 0;
end end
end end
/* Sound QoS counter */ /* Long timer counts from 0 to 16384 -- 16385 states == 202.888 ms */
reg [13:0] SC; // Sound counter reg [14:0] LTimer; // Long timer
always @(posedge C16M) begin wire LTimerTC <= LTimer[14];
if (TimerTC) SC <= SC+1; // SC increment always @(posedge C8M) begin
end if (LTimerTC) LTimer <= 0;
else LTimer <= LTimer+1;
/* IPL2 registration */
reg nIPL2r, nRESr;
always @(negedge C16M) begin
nIPL2r <= nIPL2;
nRESr <= nRES;
end end
/* Startup sequence control */ /* Startup sequence control */
reg [1:0] PORS = 0; reg [1:0] PORS = 0;
always @(posedge C16M) begin reg Disable = 0;
reg BR_IOB = 0; assign nBR_IOB <= !BR_IOB;
assign nAoutOE <= !AoutOE;
always @(posedge C8M) begin
case (PORS) case (PORS)
0: begin 0: begin
nRESout <= !nRESr; AoutOE <= 0; // Tristate PDS address and control
if (nRESr) PORS <= 1; nRESout <= 0; // Hold reset low
Disable <= 0;
if (LTimerTC) PORS <= 1;
end 1: begin end 1: begin
nRESout <= 0; AoutOE <= 0; // Tristate PDS address and control
if (TimerTC && SC[13:0]==14'h3FFF && nIPL2r) PORS <= 2; nRESout <= 0; // Hold reset low
Disable <= Disable | !nIPL2; // No need to synchronize /IPL2
if (!IPL2r && LTimerTC) begin
BR_IOB <= !Disable;
PORS <= 2;
end
end 2: begin end 2: begin
nRESout <= 0; AoutOE <= 0; // Tristate PDS address and control
if (TimerTC && SC[13:0]==14'h3FFF) PORS <= 3; nRESout <= 0; // Hold reset low
if (LTimerTC) PORS <= 3;
end 3: begin end 3: begin
nRESout <= 1; AoutOE <= BR_IOB;
// Wait until LTimerTC to release reset
if (LTimerTC) nRESout <= 1;
else nRESout = 0;
PORS <= 3;
end end
endcase endcase
end end
/* Accelerator enable/disable control */
always @(posedge CLK) begin
if (PORS==0) begin
if (nRESr) nBR_IOB <= nIPL2r;
else nBR_IOB <= 1;
end
end
// Enable both oscillators... only mount one // Enable both oscillators... only mount one
assign C20MEN = 1; assign C20MEN = 1;
assign C25MEN = 1; assign C25MEN = 1;
// Enable fast ROM
assign FastROMEN = 1;
endmodule endmodule

17
cpld/FSB.v
View File

@ -2,7 +2,7 @@ module FSB(
/* MC68HC000 interface */ /* MC68HC000 interface */
input FCLK, input nAS, output reg nDTACK, output nVPA, output nBERR, input FCLK, input nAS, output reg nDTACK, output nVPA, output nBERR,
/* AS cycle detection */ /* AS cycle detection */
output BACT, output BACT, output LBACT,
/* Ready inputs */ /* Ready inputs */
input Ready0, input Ready1, input Ready2, input Ready0, input Ready1, input Ready2,
/* BERR inputs */ /* BERR inputs */
@ -13,7 +13,20 @@ module FSB(
/* AS cycle detection */ /* AS cycle detection */
reg ASrf = 0; reg ASrf = 0;
always @(negedge FCLK) begin ASrf <= ~nAS; end always @(negedge FCLK) begin ASrf <= ~nAS; end
assign BACT = ~nAS || ASrf; assign BACT = ~nAS || ASrf; // BACT - bus active
/* LBACT - "Long BACT" */
reg [1:0] BACTCnt = 0;
reg LBACT;
always @(posedge FCLK) begin
if (!BACT) begin
BACTCnt <= 0;
LBACT <= 0;
end else begin
BACTCnt <= BACTCnt+1;
if (BACTCnt==2'b11 && BACT) LBACT <= 1;
end
end
/* Ready generation and bypass */ /* Ready generation and bypass */
reg Ready0r, Ready1r, Ready2r; reg Ready0r, Ready1r, Ready2r;

8
cpld/IOBM.v
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@ -4,7 +4,7 @@ module IOBM(
output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA, output reg nASout, output reg nLDS, output reg nUDS, output reg nVMA,
input nASin, input nBG, input nDTACK, input nVPA, input nBERR, input nRES, input nASin, input nBG, input nDTACK, input nVPA, input nBERR, input nRES,
/* PDS address and data latch control */ /* PDS address and data latch control */
output nAoutOE, output reg nDoutOE, output reg ALE0, output reg nDinLE, input AoutOE, output nDoutOE, output reg ALE0, output reg nDinLE,
/* IO bus slave port interface */ /* IO bus slave port interface */
output reg IOACT, output reg IOBERR, output reg IOACT, output reg IOBERR,
input IOREQ, input IOLDS, input IOUDS, input IOWE); input IOREQ, input IOLDS, input IOUDS, input IOWE);
@ -107,11 +107,11 @@ module IOBM(
end end
/* PDS address and data latch control */ /* PDS address and data latch control */
assign nAoutOE = !BG;
always @(negedge C16M) begin nDinLE <= IOS==4 || IOS==5; end always @(negedge C16M) begin nDinLE <= IOS==4 || IOS==5; end
reg DoutOE = 0; assign nDoutOE <= !(AoutOE && DoutOE);
always @(posedge C16M) begin always @(posedge C16M) begin
nDoutOE <= ~(IOWE && (IOS==1 || IOS==2 || IOS==3 || DoutOE <= IOWE && (IOS==1 || IOS==2 || IOS==3 ||
IOS==4 || IOS==5 || IOS==6)); IOS==4 || IOS==5 || IOS==6);
end end
/* AS, DS control */ /* AS, DS control */

22
cpld/WarpSE.v
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@ -47,6 +47,7 @@ module WarpSE(
/* AS cycle detection */ /* AS cycle detection */
wire BACT; wire BACT;
wire LBACT;
/* Refresh request/ack signals */ /* Refresh request/ack signals */
wire RefReq, RefUrgent; wire RefReq, RefUrgent;
@ -112,31 +113,34 @@ module WarpSE(
nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout, nAS_IOBout, nLDS_IOBout, nUDS_IOBout, nVMA_IOBout,
nAS_IOB, nBG_IOB, nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin, nAS_IOB, nBG_IOB, nDTACK_IOB, nVPA_IOB, nBERR_IOB, nRESin,
/* PDS address and data latch control */ /* PDS address and data latch control */
nAoutOE, nDoutOE, ALE0M, nDinLE, AoutOE, nDoutOE, ALE0M, nDinLE,
/* IO bus slave port interface */ /* IO bus slave port interface */
IOACT, IOBERR, IOACT, IOBERR,
IOREQ, IOL0, IOU0, IORW0); IOREQ, IOL0, IOU0, IORW0);
wire BERRTimeout, QoSReady; wire BERRTimeout;
wire AoutOE;
CNT cnt( CNT cnt(
/* C16M clock */ /* C8M clock */
C16M, C8M,
/* FSB clock and bus active signal */ /* FSB bus active signals */
FCLK, BACT, BACT, LBACT,
/* Refresh request */ /* Refresh request */
RefReq, RefUrgent, RefReq, RefUrgent,
/* BERR and QoS speed limit output */ /* BERR and QoS speed limit output */
BERRTimeout, QoSReady, BERRTimeout,
/* Reset, switch, button */ /* Reset, switch, button */
SW[3:1], nRESin, nRESout, nIPL2, SW[3:1], nRESin, nRESout, nIPL2,
/* Mac PDS bus master control outputs */
nAoutOE, AoutOE, nBR_IOB,
/* Configuration outputs */ /* Configuration outputs */
nBR_IOB, FastROMEN, C20MEN, C25MEN); FastROMEN, C20MEN, C25MEN);
FSB fsb( FSB fsb(
/* MC68HC000 interface */ /* MC68HC000 interface */
CLK_FSB, nAS_FSB, nDTACK_FSB, nVPA_FSB, nBERR_FSB, CLK_FSB, nAS_FSB, nDTACK_FSB, nVPA_FSB, nBERR_FSB,
/* AS cycle detection */ /* AS cycle detection */
BACT, BACT, LBACT,
/* Ready and IA inputs */ /* Ready and IA inputs */
Ready_RAM, Ready_IOBS, (!SndRAMCSWR || QoSReady), Ready_RAM, Ready_IOBS, (!SndRAMCSWR || QoSReady),
/* BERR inputs */ /* BERR inputs */