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a3b441fde9
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c003bd2581 |
10
cpld/RAM.v
10
cpld/RAM.v
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@ -61,10 +61,14 @@ module RAM(
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assign RA[01] = !RASEL ? A[10] : A[02];
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assign RA[01] = !RASEL ? A[10] : A[02];
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assign RA[00] = !RASEL ? A[09] : A[01];
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assign RA[00] = !RASEL ? A[09] : A[01];
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wire RS0toRef = (RefReq && BACT && !BACTr && !RAMCS0X) ||
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wire RS0toRef = // Refresh during first clock of non-RAM access
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(RefUrg && !RASEN) ||
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(RefReq && BACT && !BACTr && !RAMCS0X) ||
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// Urgent refresh while bus inactive
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(RefUrg && !BACT) ||
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// Urgent refresh during non-RAM access
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(RefUrg && BACT && !RAMCS0X) ||
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(RefUrg && BACT && !RAMCS0X) ||
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(RefUrg && !BACT);
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// Urgent refresh if RAM is disabled
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(RefUrg && !RASEN);
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always @(posedge CLK) begin
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always @(posedge CLK) begin
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case (RS[2:0])
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case (RS[2:0])
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