Macintosh-HW/Warp-SE
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dev-0.7a-fastiack-fastscc-35us-noclockgate
Warp-SE/cpld
History
Zane Kaminski e5319295b0 0.7a-fastiack-fastscc-35us-noclockgate compiled
2024-10-12 02:03:13 -04:00
..
XC95144XL 0.7a-fastiack-fastscc-35us-noclockgate compiled 2024-10-12 02:03:13 -04:00
CNT.v Add settings module power-on reset 2024-10-11 17:28:08 -04:00
CS.v Add slowdown settings 2024-10-11 16:41:31 -04:00
FSB.v Add slowdown settings 2024-10-11 16:41:31 -04:00
IOBM.v PDS R/W output in IOBM latches IORW after assertion 2024-10-08 07:21:29 -04:00
IOBS.v Undo I/O R/W gate for now. Will have to re-add this later for new revision with PDS R/W connected to CPLD. 2024-10-09 04:15:23 -04:00
RAM.v RAM RefDone reset by RefReqIn only. No longer depends on RefUrg too 2024-10-08 22:48:11 -04:00
SET.v 0.7a-fastiack-fastscc-35us-noclockgate compiled 2024-10-12 02:03:13 -04:00
WarpSE-XC95144XL.ucf Fix PDS R/W constraint 2024-10-08 07:30:28 -04:00
WarpSE.v Add settings module power-on reset 2024-10-11 17:28:08 -04:00