mirror of
https://github.com/garrettsworkshop/Warp-SE.git
synced 2024-11-21 17:31:47 +00:00
1716 lines
90 KiB
Plaintext
1716 lines
90 KiB
Plaintext
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cpldfit: version P.20131013 Xilinx Inc.
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Fitter Report
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Design Name: WarpSE Date: 10-12-2024, 2:02AM
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Device Used: XC95144XL-10-TQ100
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Fitting Status: Successful
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************************* Mapped Resource Summary **************************
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Macrocells Product Terms Function Block Registers Pins
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Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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137/144 ( 95%) 381 /720 ( 53%) 265/432 ( 61%) 113/144 ( 78%) 73 /81 ( 90%)
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** Function Block Resources **
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 31/54 32/90 11/11*
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FB2 13/18 11/54 13/90 8/10
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FB3 18/18* 38/54 47/90 10/10*
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FB4 18/18* 30/54 36/90 10/10*
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FB5 16/18 42/54 46/90 8/10
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FB6 18/18* 32/54 67/90 10/10*
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FB7 18/18* 41/54 68/90 10/10*
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FB8 18/18* 40/54 72/90 6/10
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----- ----- ----- -----
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137/144 265/432 381/720 73/81
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* - Resource is exhausted
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** Global Control Resources **
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Signal 'C16M' mapped onto global clock net GCK1.
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Signal 'C8M' mapped onto global clock net GCK2.
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Signal 'FCLK' mapped onto global clock net GCK3.
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Global output enable net(s) unused.
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Global set/reset net(s) unused.
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** Pin Resources **
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Signal Type Required Mapped | Pin Type Used Total
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------------------------------------|------------------------------------
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Input : 32 32 | I/O : 67 73
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Output : 37 37 | GCK/IO : 3 3
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Bidirectional : 1 1 | GTS/IO : 3 4
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GCK : 3 3 | GSR/IO : 0 1
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GTS : 0 0 |
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GSR : 0 0 |
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---- ----
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Total 73 73
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** Power Data **
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There are 137 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
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End of Mapped Resource Summary
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************************** Errors and Warnings ***************************
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WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
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use the default filename of 'WarpSE.ise'.
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INFO:Cpld - Inferring BUFG constraint for signal 'C16M' based upon the LOC
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constraint 'P22'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'C8M' based upon the LOC
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constraint 'P23'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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INFO:Cpld - Inferring BUFG constraint for signal 'FCLK' based upon the LOC
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constraint 'P27'. It is recommended that you declare this BUFG explicitedly
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in your design. Note that for certain device families the output of a BUFG
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constraint can not drive a gated clock, and the BUFG constraint will be
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ignored.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<0>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<1>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<2>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<3>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<4>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'DBG<5>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'nBG_IOB'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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************************* Summary of Mapped Logic ************************
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** 38 Outputs **
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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nDTACK_FSB 8 15 FB3_9 28 I/O O STD SLOW RESET
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nROMWE 1 6 FB3_17 34 I/O O STD SLOW
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nAoutOE 1 3 FB4_2 87 I/O O STD SLOW SET
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nDoutOE 1 2 FB4_5 89 I/O O STD FAST
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nDinOE 3 7 FB4_6 90 I/O O STD SLOW
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nRES 1 1 FB4_8 91 I/O I/O STD SLOW
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nVPA_FSB 2 6 FB4_11 93 I/O O STD SLOW RESET
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nROMOE 2 7 FB5_2 35 I/O O STD SLOW
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nCAS 5 6 FB5_5 36 I/O O STD FAST RESET
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nOE 2 5 FB5_6 37 I/O O STD SLOW RESET
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RA<4> 2 3 FB5_9 40 I/O O STD FAST
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RA<3> 2 3 FB5_11 41 I/O O STD FAST
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RA<5> 2 3 FB5_12 42 I/O O STD FAST
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RA<2> 2 3 FB5_14 43 I/O O STD FAST
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RA<6> 2 3 FB5_15 46 I/O O STD FAST
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nVMA_IOB 3 8 FB6_2 74 I/O O STD SLOW RESET
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nLDS_IOB 6 10 FB6_9 79 I/O O STD SLOW RESET
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nUDS_IOB 6 10 FB6_11 80 I/O O STD SLOW RESET
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nAS_IOB 4 8 FB6_12 81 I/O O STD SLOW RESET
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nADoutLE1 2 3 FB6_14 82 I/O O STD FAST SET
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nADoutLE0 1 2 FB6_15 85 I/O O STD SLOW
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nDinLE 1 2 FB6_17 86 I/O O STD FAST RESET
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RA<1> 2 3 FB7_2 50 I/O O STD FAST
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RA<7> 2 3 FB7_5 52 I/O O STD FAST
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RA<0> 2 3 FB7_6 53 I/O O STD FAST
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RA<8> 2 3 FB7_8 54 I/O O STD FAST
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RA<10> 2 3 FB7_9 55 I/O O STD FAST
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RA<9> 2 3 FB7_11 56 I/O O STD FAST
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MCKE 3 6 FB7_12 58 I/O O STD FAST RESET
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RnW_IOB 6 11 FB7_14 59 I/O O STD SLOW RESET
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GA<23> 1 1 FB7_15 60 I/O O STD FAST
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GA<22> 1 1 FB7_17 61 I/O O STD FAST
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RA<11> 2 3 FB8_2 63 I/O O STD FAST
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nRAS 2 6 FB8_5 64 I/O O STD FAST
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nRAMLWE 1 3 FB8_6 65 I/O O STD SLOW
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nRAMUWE 1 3 FB8_8 66 I/O O STD SLOW
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nBERR_FSB 3 7 FB8_12 70 I/O O STD SLOW RESET
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nBR_IOB 1 1 FB8_15 72 I/O O STD SLOW
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** 99 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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cnt/LTimer<0> 1 1 FB1_1 STD RESET
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cnt/Er<1> 1 1 FB1_2 STD RESET
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cnt/C8Mr<3> 1 1 FB1_3 STD RESET
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cnt/C8Mr<2> 1 1 FB1_4 STD RESET
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cnt/C8Mr<1> 1 1 FB1_5 STD RESET
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iobs/IOU1 2 2 FB1_6 STD RESET
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iobs/IOL1 2 2 FB1_7 STD RESET
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cnt/Timer<2> 2 4 FB1_8 STD RESET
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cnt/LTimer<1> 2 2 FB1_9 STD RESET
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SlowTimeout<1> 2 4 FB1_10 STD RESET
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SlowTimeout<0> 2 4 FB1_11 STD RESET
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SlowSnd 2 4 FB1_12 STD RESET
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SlowSCSI 2 4 FB1_13 STD RESET
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SlowSCC 2 4 FB1_14 STD RESET
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SlowIWM 2 4 FB1_15 STD RESET
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SlowIACK 2 4 FB1_16 STD RESET
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SlowClockGate 2 4 FB1_17 STD RESET
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nPOR 3 5 FB1_18 STD RESET
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iobs/IODONErf 1 1 FB2_6 STD RESET
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iobs/IODONEr<0> 1 1 FB2_7 STD RESET
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iobs/IOACTr 1 1 FB2_8 STD RESET
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iobm/VPAr 1 1 FB2_9 STD RESET
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iobm/IOS_FSM_FFd5 1 1 FB2_10 STD RESET
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iobm/IOS_FSM_FFd4 1 1 FB2_11 STD RESET
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iobm/IOS_FSM_FFd1 1 1 FB2_12 STD RESET
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iobm/IOREQr 1 1 FB2_13 STD RESET
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iobm/Er 1 1 FB2_14 STD RESET
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iobm/C8Mr 1 1 FB2_15 STD RESET
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cnt/Er<0> 1 1 FB2_16 STD RESET
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cnt/C8Mr<0> 1 1 FB2_17 STD RESET
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ALE0S 1 1 FB2_18 STD RESET
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cnt/LTimerTick 1 13 FB3_1 STD RESET
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cnt/QS<3> 2 6 FB3_2 STD RESET
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cnt/LTimer<9> 2 10 FB3_3 STD RESET
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cnt/LTimer<8> 2 9 FB3_4 STD RESET
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cnt/LTimer<7> 2 8 FB3_5 STD RESET
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cnt/LTimer<6> 2 7 FB3_6 STD RESET
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cnt/LTimer<5> 2 6 FB3_7 STD RESET
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cnt/LTimer<4> 2 5 FB3_8 STD RESET
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cnt/LTimer<3> 2 4 FB3_10 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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cnt/LTimer<2> 2 3 FB3_11 STD RESET
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cnt/LTimer<11> 2 12 FB3_12 STD RESET
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cnt/LTimer<10> 2 11 FB3_13 STD RESET
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cnt/QS<2> 3 6 FB3_14 STD RESET
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cnt/QS<0> 3 6 FB3_15 STD RESET
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cnt/QS<1> 4 6 FB3_16 STD RESET
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QoSEN 5 10 FB3_18 STD RESET
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cnt/TimerTick 1 6 FB4_1 STD RESET
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nRESout 2 4 FB4_3 STD RESET
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nBR_IOBout 2 4 FB4_4 STD RESET
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cnt/Timer<0> 2 6 FB4_7 STD RESET
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cnt/IS<1> 2 4 FB4_9 STD RESET
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SlowVIA 2 4 FB4_10 STD RESET
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SlowTimeout<3> 2 4 FB4_12 STD RESET
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SlowTimeout<2> 2 4 FB4_13 STD RESET
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RefUrg 2 5 FB4_14 STD RESET
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RefReq 2 6 FB4_15 STD RESET
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cnt/Timer<3> 3 6 FB4_16 STD RESET
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cnt/Timer<1> 3 6 FB4_17 STD RESET
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cnt/IS<0> 3 5 FB4_18 STD RESET
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cnt/QoSCSr 10 25 FB5_1 STD RESET
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iobs/IODONEr<1> 1 1 FB5_4 STD RESET
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ASrf 1 1 FB5_7 STD RESET
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ram/RASrf 2 3 FB5_8 STD RESET
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ram/CASEndEN 2 3 FB5_10 STD RESET
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ram/RASEL 3 8 FB5_13 STD RESET
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cs/Overlay 3 8 FB5_16 STD RESET
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IONPReady 5 16 FB5_17 STD RESET
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iobm/IOS_FSM_FFd2 1 3 FB6_1 STD RESET
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iobm/IOS_FSM_FFd7 2 5 FB6_3 STD SET
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iobm/IOS_FSM_FFd3 2 4 FB6_4 STD RESET
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iobm/ES<2> 3 5 FB6_5 STD RESET
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iobm/ES<0> 3 6 FB6_6 STD RESET
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iobm/ES<3> 4 6 FB6_7 STD RESET
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iobm/ES<1> 4 6 FB6_8 STD RESET
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ALE0M 4 9 FB6_10 STD RESET
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iobm/DoutOE 5 9 FB6_13 STD RESET
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IOACT 6 11 FB6_16 STD RESET
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IODONE 10 13 FB6_18 STD RESET
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IOREQ 12 17 FB7_1 STD RESET
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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BACTr 1 2 FB7_3 STD RESET
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set/SetWRr 2 7 FB7_4 STD RESET
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iobs/TS_FSM_FFd1 2 3 FB7_7 STD RESET
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iobs/Sent 11 16 FB7_10 STD RESET
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iobs/Load1 4 16 FB7_13 STD RESET
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iobs/TS_FSM_FFd2 12 17 FB7_16 STD RESET
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iobm/IOS_FSM_FFd6 1 4 FB7_18 STD RESET
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RAMReady 10 11 FB8_1 STD RESET
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ram/RefDone 2 3 FB8_3 STD RESET
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ram/RS<1> 3 6 FB8_4 STD RESET
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IOU0 3 5 FB8_7 STD RESET
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ram/RS<2> 9 11 FB8_9 STD RESET
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IOL0 3 5 FB8_10 STD RESET
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iobs/IORW1 4 17 FB8_11 STD RESET
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ram/RS<0> 6 10 FB8_13 STD RESET
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ram/RefCAS 8 11 FB8_14 STD RESET
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IORW 3 5 FB8_16 STD RESET
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ram/RASEN 10 12 FB8_17 STD RESET
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iobs/Clear1 1 2 FB8_18 STD RESET
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** 35 Inputs **
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Signal Loc Pin Pin Pin
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Name No. Type Use
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A_FSB<13> FB1_2 11 I/O I
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A_FSB<14> FB1_3 12 I/O I
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A_FSB<15> FB1_5 13 I/O I
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A_FSB<16> FB1_6 14 I/O I
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A_FSB<17> FB1_8 15 I/O I
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A_FSB<18> FB1_9 16 I/O I
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A_FSB<19> FB1_11 17 I/O I
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A_FSB<20> FB1_12 18 I/O I
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A_FSB<21> FB1_14 19 I/O I
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A_FSB<22> FB1_15 20 I/O I
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C16M FB1_17 22 GCK/I/O GCK
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A_FSB<5> FB2_6 2 GTS/I/O I
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A_FSB<6> FB2_8 3 GTS/I/O I
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A_FSB<7> FB2_9 4 GTS/I/O I
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A_FSB<8> FB2_11 6 I/O I
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A_FSB<9> FB2_12 7 I/O I
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A_FSB<10> FB2_14 8 I/O I
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A_FSB<11> FB2_15 9 I/O I
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A_FSB<12> FB2_17 10 I/O I
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C8M FB3_2 23 GCK/I/O GCK/I
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A_FSB<23> FB3_5 24 I/O I
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E FB3_6 25 I/O I
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FCLK FB3_8 27 GCK/I/O GCK
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nWE_FSB FB3_11 29 I/O I
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nLDS_FSB FB3_12 30 I/O I
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nAS_FSB FB3_14 32 I/O I
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nUDS_FSB FB3_15 33 I/O I
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nIPL2 FB4_9 92 I/O I
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A_FSB<1> FB4_12 94 I/O I
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A_FSB<2> FB4_14 95 I/O I
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A_FSB<3> FB4_15 96 I/O I
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A_FSB<4> FB4_17 97 I/O I
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nBERR_IOB FB6_5 76 I/O I
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nVPA_IOB FB6_6 77 I/O I
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nDTACK_IOB FB6_8 78 I/O I
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Legend:
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Pin No. - ~ - User Assigned
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************************** Function Block Details ************************
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Legend:
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Total Pt - Total product terms used by the macrocell signal
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Imp Pt - Product terms imported from other macrocells
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Exp Pt - Product terms exported to other macrocells
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in direction shown
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Unused Pt - Unused local product terms remaining in macrocell
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Loc - Location where logic was mapped in device
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Pin Type/Use - I - Input GCK - Global Clock
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O - Output GTS - Global Output Enable
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(b) - Buried macrocell GSR - Global Set/Reset
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X - Signal used as input to the macrocell logic.
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Pin No. - ~ - User Assigned
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*********************************** FB1 ***********************************
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Number of function block inputs used/remaining: 31/23
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Number of signals used by logic mapping into function block: 31
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
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cnt/LTimer<0> 1 0 0 4 FB1_1 (b) (b)
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cnt/Er<1> 1 0 0 4 FB1_2 11 I/O I
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cnt/C8Mr<3> 1 0 0 4 FB1_3 12 I/O I
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cnt/C8Mr<2> 1 0 0 4 FB1_4 (b) (b)
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cnt/C8Mr<1> 1 0 0 4 FB1_5 13 I/O I
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iobs/IOU1 2 0 0 3 FB1_6 14 I/O I
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iobs/IOL1 2 0 0 3 FB1_7 (b) (b)
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cnt/Timer<2> 2 0 0 3 FB1_8 15 I/O I
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cnt/LTimer<1> 2 0 0 3 FB1_9 16 I/O I
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SlowTimeout<1> 2 0 0 3 FB1_10 (b) (b)
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SlowTimeout<0> 2 0 0 3 FB1_11 17 I/O I
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SlowSnd 2 0 0 3 FB1_12 18 I/O I
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SlowSCSI 2 0 0 3 FB1_13 (b) (b)
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SlowSCC 2 0 0 3 FB1_14 19 I/O I
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SlowIWM 2 0 0 3 FB1_15 20 I/O I
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SlowIACK 2 0 0 3 FB1_16 (b) (b)
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SlowClockGate 2 0 0 3 FB1_17 22 GCK/I/O GCK
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nPOR 3 0 0 2 FB1_18 (b) (b)
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Signals Used by Logic in Function Block
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1: A_FSB<1> 12: SlowSCC 22: cnt/Er<1>
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2: A_FSB<2> 13: SlowSCSI 23: cnt/LTimer<0>
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3: A_FSB<3> 14: SlowSnd 24: cnt/Timer<0>
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4: A_FSB<4> 15: SlowTimeout<0> 25: cnt/Timer<1>
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5: A_FSB<5> 16: SlowTimeout<1> 26: cnt/TimerTick
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6: A_FSB<7> 17: cnt/C8Mr<0> 27: iobs/Load1
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7: A_FSB<8> 18: cnt/C8Mr<1> 28: nLDS_FSB
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8: A_FSB<9> 19: cnt/C8Mr<2> 29: nPOR
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9: SlowClockGate 20: cnt/C8Mr<3> 30: nUDS_FSB
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10: SlowIACK 21: cnt/Er<0> 31: set/SetWRr
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11: SlowIWM
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Signal 1 2 3 4 FB
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Name 0----+----0----+----0----+----0----+----0 Inputs
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cnt/LTimer<0> .........................X.............. 1
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cnt/Er<1> ....................X................... 1
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cnt/C8Mr<3> ..................X..................... 1
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cnt/C8Mr<2> .................X...................... 1
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cnt/C8Mr<1> ................X....................... 1
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iobs/IOU1 ..........................X..X.......... 2
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iobs/IOL1 ..........................XX............ 2
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cnt/Timer<2> ....................XX.XX............... 4
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cnt/LTimer<1> ......................X..X.............. 2
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SlowTimeout<1> .......X.......X............X.X......... 4
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SlowTimeout<0> ......X.......X.............X.X......... 4
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SlowSnd .X...........X..............X.X......... 4
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SlowSCSI ..X.........X...............X.X......... 4
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SlowSCC ...X.......X................X.X......... 4
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SlowIWM ....X.....X.................X.X......... 4
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SlowIACK .....X...X..................X.X......... 4
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SlowClockGate X.......X...................X.X......... 4
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nPOR ................XXXX........X........... 5
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0----+----1----+----2----+----3----+----4
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0 0 0 0
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*********************************** FB2 ***********************************
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Number of function block inputs used/remaining: 11/43
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Number of signals used by logic mapping into function block: 11
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Signal Total Imp Exp Unused Loc Pin Pin Pin
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Name Pt Pt Pt Pt # Type Use
|
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(unused) 0 0 0 5 FB2_1 (b)
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(unused) 0 0 0 5 FB2_2 99 GSR/I/O
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(unused) 0 0 0 5 FB2_3 (b)
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(unused) 0 0 0 5 FB2_4 (b)
|
||
(unused) 0 0 0 5 FB2_5 1 GTS/I/O
|
||
iobs/IODONErf 1 0 0 4 FB2_6 2 GTS/I/O I
|
||
iobs/IODONEr<0> 1 0 0 4 FB2_7 (b) (b)
|
||
iobs/IOACTr 1 0 0 4 FB2_8 3 GTS/I/O I
|
||
iobm/VPAr 1 0 0 4 FB2_9 4 GTS/I/O I
|
||
iobm/IOS_FSM_FFd5 1 0 0 4 FB2_10 (b) (b)
|
||
iobm/IOS_FSM_FFd4 1 0 0 4 FB2_11 6 I/O I
|
||
iobm/IOS_FSM_FFd1 1 0 0 4 FB2_12 7 I/O I
|
||
iobm/IOREQr 1 0 0 4 FB2_13 (b) (b)
|
||
iobm/Er 1 0 0 4 FB2_14 8 I/O I
|
||
iobm/C8Mr 1 0 0 4 FB2_15 9 I/O I
|
||
cnt/Er<0> 1 0 0 4 FB2_16 (b) (b)
|
||
cnt/C8Mr<0> 1 0 0 4 FB2_17 10 I/O I
|
||
ALE0S 1 0 0 4 FB2_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: C8M 5: IOREQ 9: iobs/IODONErf
|
||
2: E 6: iobm/IOS_FSM_FFd2 10: iobs/TS_FSM_FFd2
|
||
3: IOACT 7: iobm/IOS_FSM_FFd5 11: nVPA_IOB
|
||
4: IODONE 8: iobm/IOS_FSM_FFd6
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
iobs/IODONErf ...X.................................... 1
|
||
iobs/IODONEr<0> ........X............................... 1
|
||
iobs/IOACTr ..X..................................... 1
|
||
iobm/VPAr ..........X............................. 1
|
||
iobm/IOS_FSM_FFd5 .......X................................ 1
|
||
iobm/IOS_FSM_FFd4 ......X................................. 1
|
||
iobm/IOS_FSM_FFd1 .....X.................................. 1
|
||
iobm/IOREQr ....X................................... 1
|
||
iobm/Er .X...................................... 1
|
||
iobm/C8Mr X....................................... 1
|
||
cnt/Er<0> .X...................................... 1
|
||
cnt/C8Mr<0> X....................................... 1
|
||
ALE0S .........X.............................. 1
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB3 ***********************************
|
||
Number of function block inputs used/remaining: 38/16
|
||
Number of signals used by logic mapping into function block: 38
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
cnt/LTimerTick 1 0 0 4 FB3_1 (b) (b)
|
||
cnt/QS<3> 2 0 0 3 FB3_2 23 GCK/I/O GCK/I
|
||
cnt/LTimer<9> 2 0 0 3 FB3_3 (b) (b)
|
||
cnt/LTimer<8> 2 0 0 3 FB3_4 (b) (b)
|
||
cnt/LTimer<7> 2 0 0 3 FB3_5 24 I/O I
|
||
cnt/LTimer<6> 2 0 0 3 FB3_6 25 I/O I
|
||
cnt/LTimer<5> 2 0 0 3 FB3_7 (b) (b)
|
||
cnt/LTimer<4> 2 0 \/2 1 FB3_8 27 GCK/I/O GCK
|
||
nDTACK_FSB 8 3<- 0 0 FB3_9 28 I/O O
|
||
cnt/LTimer<3> 2 0 /\1 2 FB3_10 (b) (b)
|
||
cnt/LTimer<2> 2 0 0 3 FB3_11 29 I/O I
|
||
cnt/LTimer<11> 2 0 0 3 FB3_12 30 I/O I
|
||
cnt/LTimer<10> 2 0 0 3 FB3_13 (b) (b)
|
||
cnt/QS<2> 3 0 0 2 FB3_14 32 I/O I
|
||
cnt/QS<0> 3 0 0 2 FB3_15 33 I/O I
|
||
cnt/QS<1> 4 0 0 1 FB3_16 (b) (b)
|
||
nROMWE 1 0 0 4 FB3_17 34 I/O O
|
||
QoSEN 5 0 0 0 FB3_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: ASrf 14: SlowTimeout<1> 27: cnt/LTimer<8>
|
||
2: A_FSB<16> 15: SlowTimeout<2> 28: cnt/LTimer<9>
|
||
3: A_FSB<17> 16: SlowTimeout<3> 29: cnt/QS<0>
|
||
4: A_FSB<18> 17: cnt/LTimer<0> 30: cnt/QS<1>
|
||
5: A_FSB<19> 18: cnt/LTimer<10> 31: cnt/QS<2>
|
||
6: A_FSB<20> 19: cnt/LTimer<11> 32: cnt/QS<3>
|
||
7: A_FSB<21> 20: cnt/LTimer<1> 33: cnt/QoSCSr
|
||
8: A_FSB<22> 21: cnt/LTimer<2> 34: cnt/TimerTick
|
||
9: A_FSB<23> 22: cnt/LTimer<3> 35: iobs/Sent
|
||
10: IONPReady 23: cnt/LTimer<4> 36: nADoutLE1
|
||
11: QoSEN 24: cnt/LTimer<5> 37: nAS_FSB
|
||
12: RAMReady 25: cnt/LTimer<6> 38: nWE_FSB
|
||
13: SlowTimeout<0> 26: cnt/LTimer<7>
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
cnt/LTimerTick ................XXXXXXXXXXXX.....X...... 13
|
||
cnt/QS<3> ............................XXXXXX...... 6
|
||
cnt/LTimer<9> ................X..XXXXXXXX......X...... 10
|
||
cnt/LTimer<8> ................X..XXXXXXX.......X...... 9
|
||
cnt/LTimer<7> ................X..XXXXXX........X...... 8
|
||
cnt/LTimer<6> ................X..XXXXX.........X...... 7
|
||
cnt/LTimer<5> ................X..XXXX..........X...... 6
|
||
cnt/LTimer<4> ................X..XXX...........X...... 5
|
||
nDTACK_FSB .XXXXXXXXXXX......................XXXX.. 15
|
||
cnt/LTimer<3> ................X..XX............X...... 4
|
||
cnt/LTimer<2> ................X..X.............X...... 3
|
||
cnt/LTimer<11> ................XX.XXXXXXXXX.....X...... 12
|
||
cnt/LTimer<10> ................X..XXXXXXXXX.....X...... 11
|
||
cnt/QS<2> ............................XXXXXX...... 6
|
||
cnt/QS<0> ............................XXXXXX...... 6
|
||
cnt/QS<1> ............................XXXXXX...... 6
|
||
nROMWE .....XXXX...........................XX.. 6
|
||
QoSEN X...........XXXX............XXXX....X... 10
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB4 ***********************************
|
||
Number of function block inputs used/remaining: 30/24
|
||
Number of signals used by logic mapping into function block: 30
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
cnt/TimerTick 1 0 0 4 FB4_1 (b) (b)
|
||
nAoutOE 1 0 0 4 FB4_2 87 I/O O
|
||
nRESout 2 0 0 3 FB4_3 (b) (b)
|
||
nBR_IOBout 2 0 0 3 FB4_4 (b) (b)
|
||
nDoutOE 1 0 0 4 FB4_5 89 I/O O
|
||
nDinOE 3 0 0 2 FB4_6 90 I/O O
|
||
cnt/Timer<0> 2 0 0 3 FB4_7 (b) (b)
|
||
nRES 1 0 0 4 FB4_8 91 I/O I/O
|
||
cnt/IS<1> 2 0 0 3 FB4_9 92 I/O I
|
||
SlowVIA 2 0 0 3 FB4_10 (b) (b)
|
||
nVPA_FSB 2 0 0 3 FB4_11 93 I/O O
|
||
SlowTimeout<3> 2 0 0 3 FB4_12 94 I/O I
|
||
SlowTimeout<2> 2 0 0 3 FB4_13 (b) (b)
|
||
RefUrg 2 0 0 3 FB4_14 95 I/O I
|
||
RefReq 2 0 0 3 FB4_15 96 I/O I
|
||
cnt/Timer<3> 3 0 0 2 FB4_16 (b) (b)
|
||
cnt/Timer<1> 3 0 0 2 FB4_17 97 I/O I
|
||
cnt/IS<0> 3 0 0 2 FB4_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: A_FSB<10> 11: SlowTimeout<3> 21: cnt/Timer<3>
|
||
2: A_FSB<11> 12: SlowVIA 22: iobm/DoutOE
|
||
3: A_FSB<20> 13: cnt/Er<0> 23: nAS_FSB
|
||
4: A_FSB<21> 14: cnt/Er<1> 24: nAoutOE
|
||
5: A_FSB<6> 15: cnt/IS<0> 25: nBR_IOBout
|
||
6: BACTr 16: cnt/IS<1> 26: nIPL2
|
||
7: A_FSB<22> 17: cnt/LTimerTick 27: nPOR
|
||
8: A_FSB<23> 18: cnt/Timer<0> 28: nRESout
|
||
9: IONPReady 19: cnt/Timer<1> 29: nWE_FSB
|
||
10: SlowTimeout<2> 20: cnt/Timer<2> 30: set/SetWRr
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
cnt/TimerTick ............XX...XXXX................... 6
|
||
nAoutOE ..............XX........X............... 3
|
||
nRESout ..............XXX..........X............ 4
|
||
nBR_IOBout ..............XX........XX.............. 4
|
||
nDoutOE .....................X.X................ 2
|
||
nDinOE ..XX.XXX..............X.....X........... 7
|
||
cnt/Timer<0> ............XX...XXXX................... 6
|
||
nRES ...........................X............ 1
|
||
cnt/IS<1> ..............XXX.........X............. 4
|
||
SlowVIA ....X......X..............X..X.......... 4
|
||
nVPA_FSB ..XX..XXX.............X................. 6
|
||
SlowTimeout<3> .X........X...............X..X.......... 4
|
||
SlowTimeout<2> X........X................X..X.......... 4
|
||
RefUrg ............XX....XXX................... 5
|
||
RefReq ............XX...XXXX................... 6
|
||
cnt/Timer<3> ............XX...XXXX................... 6
|
||
cnt/Timer<1> ............XX...XXXX................... 6
|
||
cnt/IS<0> ..............XXX........XX............. 5
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB5 ***********************************
|
||
Number of function block inputs used/remaining: 42/12
|
||
Number of signals used by logic mapping into function block: 42
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
cnt/QoSCSr 10 5<- 0 0 FB5_1 (b) (b)
|
||
nROMOE 2 0 0 3 FB5_2 35 I/O O
|
||
(unused) 0 0 0 5 FB5_3 (b)
|
||
iobs/IODONEr<1> 1 0 0 4 FB5_4 (b) (b)
|
||
nCAS 5 0 0 0 FB5_5 36 I/O O
|
||
nOE 2 0 0 3 FB5_6 37 I/O O
|
||
ASrf 1 0 0 4 FB5_7 (b) (b)
|
||
ram/RASrf 2 0 0 3 FB5_8 39 I/O (b)
|
||
RA<4> 2 0 0 3 FB5_9 40 I/O O
|
||
ram/CASEndEN 2 0 0 3 FB5_10 (b) (b)
|
||
RA<3> 2 0 0 3 FB5_11 41 I/O O
|
||
RA<5> 2 0 0 3 FB5_12 42 I/O O
|
||
ram/RASEL 3 0 0 2 FB5_13 (b) (b)
|
||
RA<2> 2 0 0 3 FB5_14 43 I/O O
|
||
RA<6> 2 0 0 3 FB5_15 46 I/O O
|
||
cs/Overlay 3 0 0 2 FB5_16 (b) (b)
|
||
IONPReady 5 0 0 0 FB5_17 49 I/O (b)
|
||
(unused) 0 0 \/5 0 FB5_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: ASrf 15: A_FSB<4> 29: SlowSnd
|
||
2: A_FSB<10> 16: A_FSB<5> 30: SlowVIA
|
||
3: A_FSB<11> 17: A_FSB<7> 31: cs/Overlay
|
||
4: A_FSB<12> 18: A_FSB<8> 32: iobs/IODONEr<0>
|
||
5: A_FSB<13> 19: A_FSB<9> 33: iobs/IODONEr<1>
|
||
6: A_FSB<14> 20: A_FSB<22> 34: iobs/Sent
|
||
7: A_FSB<15> 21: A_FSB<23> 35: nAS_FSB
|
||
8: A_FSB<16> 22: IONPReady 36: nWE_FSB
|
||
9: A_FSB<17> 23: nRES.PIN 37: ram/CASEndEN
|
||
10: A_FSB<18> 24: QoSEN 38: ram/RASEL
|
||
11: A_FSB<19> 25: SlowIACK 39: ram/RS<0>
|
||
12: A_FSB<20> 26: SlowIWM 40: ram/RS<1>
|
||
13: A_FSB<21> 27: SlowSCC 41: ram/RS<2>
|
||
14: A_FSB<3> 28: SlowSCSI 42: ram/RefCAS
|
||
|
||
Signal 1 2 3 4 5 FB
|
||
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
||
cnt/QoSCSr .XXXXXXXXXXXX....XXXX.X.XXXXXX....XX.............. 25
|
||
nROMOE ...........XX......XX.........X...XX.............. 7
|
||
iobs/IODONEr<1> ...............................X.................. 1
|
||
nCAS ..................................X.X.XXXX........ 6
|
||
nOE ...................XX.........X...XX.............. 5
|
||
ASrf ..................................X............... 1
|
||
ram/RASrf ......................................XXX......... 3
|
||
RA<4> ..X..........X.......................X............ 3
|
||
ram/CASEndEN ......................................XXX......... 3
|
||
RA<3> ..........XX.........................X............ 3
|
||
RA<5> ...X..........X......................X............ 3
|
||
ram/RASEL X..................XX.........X...X...XXX......... 8
|
||
RA<2> .......X........X....................X............ 3
|
||
RA<6> ....X..........X.....................X............ 3
|
||
cs/Overlay X..........XX......XX.X.......X...X............... 8
|
||
IONPReady X......XXXXXX......XXX.X.......XXXXX.............. 16
|
||
0----+----1----+----2----+----3----+----4----+----5
|
||
0 0 0 0 0
|
||
*********************************** FB6 ***********************************
|
||
Number of function block inputs used/remaining: 32/22
|
||
Number of signals used by logic mapping into function block: 32
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
iobm/IOS_FSM_FFd2 1 0 /\1 3 FB6_1 (b) (b)
|
||
nVMA_IOB 3 0 0 2 FB6_2 74 I/O O
|
||
iobm/IOS_FSM_FFd7 2 0 0 3 FB6_3 (b) (b)
|
||
iobm/IOS_FSM_FFd3 2 0 0 3 FB6_4 (b) (b)
|
||
iobm/ES<2> 3 0 0 2 FB6_5 76 I/O I
|
||
iobm/ES<0> 3 0 0 2 FB6_6 77 I/O I
|
||
iobm/ES<3> 4 0 0 1 FB6_7 (b) (b)
|
||
iobm/ES<1> 4 0 \/1 0 FB6_8 78 I/O I
|
||
nLDS_IOB 6 1<- 0 0 FB6_9 79 I/O O
|
||
ALE0M 4 0 \/1 0 FB6_10 (b) (b)
|
||
nUDS_IOB 6 1<- 0 0 FB6_11 80 I/O O
|
||
nAS_IOB 4 0 0 1 FB6_12 81 I/O O
|
||
iobm/DoutOE 5 0 0 0 FB6_13 (b) (b)
|
||
nADoutLE1 2 0 0 3 FB6_14 82 I/O O
|
||
nADoutLE0 1 0 \/1 3 FB6_15 85 I/O O
|
||
IOACT 6 1<- 0 0 FB6_16 (b) (b)
|
||
nDinLE 1 0 \/4 0 FB6_17 86 I/O O
|
||
IODONE 10 5<- 0 0 FB6_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: ALE0M 12: iobm/ES<0> 23: iobm/IOS_FSM_FFd6
|
||
2: ALE0S 13: iobm/ES<1> 24: iobm/IOS_FSM_FFd7
|
||
3: E 14: iobm/ES<2> 25: iobm/VPAr
|
||
4: IOACT 15: iobm/ES<3> 26: iobs/Clear1
|
||
5: IODONE 16: iobm/Er 27: iobs/Load1
|
||
6: IOL0 17: iobm/IOREQr 28: nADoutLE1
|
||
7: IORW 18: iobm/IOS_FSM_FFd1 29: nAoutOE
|
||
8: IOU0 19: iobm/IOS_FSM_FFd2 30: nBERR_IOB
|
||
9: nRES.PIN 20: iobm/IOS_FSM_FFd3 31: nDTACK_IOB
|
||
10: iobm/C8Mr 21: iobm/IOS_FSM_FFd4 32: nVMA_IOB
|
||
11: iobm/DoutOE 22: iobm/IOS_FSM_FFd5
|
||
|
||
Signal 1 2 3 4 FB
|
||
Name 0----+----0----+----0----+----0----+----0 Inputs
|
||
iobm/IOS_FSM_FFd2 ....X....X.........X.................... 3
|
||
nVMA_IOB ...X.......XXXX.........X...X..X........ 8
|
||
iobm/IOS_FSM_FFd7 .........X......XX.....X....X........... 5
|
||
iobm/IOS_FSM_FFd3 ....X....X.........XX................... 4
|
||
iobm/ES<2> ..X........XXX.X........................ 5
|
||
iobm/ES<0> ..X........XXXXX........................ 6
|
||
iobm/ES<3> ..X........XXXXX........................ 6
|
||
iobm/ES<1> ..X........XXXXX........................ 6
|
||
nLDS_IOB .....XX..X......X..XXXXX....X........... 10
|
||
ALE0M X...............XXXXXXXX................ 9
|
||
nUDS_IOB ......XX.X......X..XXXXX....X........... 10
|
||
nAS_IOB .........X......X..XXXXX....X........... 8
|
||
iobm/DoutOE ......X..XX.....X..XXXXX................ 9
|
||
nADoutLE1 .........................XXX............ 3
|
||
nADoutLE0 XX...................................... 2
|
||
IOACT ...XX....X......XXXXXXXX................ 11
|
||
nDinLE ...................XX................... 2
|
||
IODONE ....X...XX.XXXX....X.X.X.....XXX........ 13
|
||
0----+----1----+----2----+----3----+----4
|
||
0 0 0 0
|
||
*********************************** FB7 ***********************************
|
||
Number of function block inputs used/remaining: 41/13
|
||
Number of signals used by logic mapping into function block: 41
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
IOREQ 12 7<- 0 0 FB7_1 (b) (b)
|
||
RA<1> 2 0 /\3 0 FB7_2 50 I/O O
|
||
BACTr 1 0 0 4 FB7_3 (b) (b)
|
||
set/SetWRr 2 0 0 3 FB7_4 (b) (b)
|
||
RA<7> 2 0 0 3 FB7_5 52 I/O O
|
||
RA<0> 2 0 0 3 FB7_6 53 I/O O
|
||
iobs/TS_FSM_FFd1 2 0 0 3 FB7_7 (b) (b)
|
||
RA<8> 2 0 0 3 FB7_8 54 I/O O
|
||
RA<10> 2 0 \/3 0 FB7_9 55 I/O O
|
||
iobs/Sent 11 6<- 0 0 FB7_10 (b) (b)
|
||
RA<9> 2 0 /\3 0 FB7_11 56 I/O O
|
||
MCKE 3 0 0 2 FB7_12 58 I/O O
|
||
iobs/Load1 4 0 \/1 0 FB7_13 (b) (b)
|
||
RnW_IOB 6 1<- 0 0 FB7_14 59 I/O O
|
||
GA<23> 1 0 \/4 0 FB7_15 60 I/O O
|
||
iobs/TS_FSM_FFd2 12 7<- 0 0 FB7_16 (b) (b)
|
||
GA<22> 1 0 /\3 1 FB7_17 61 I/O O
|
||
iobm/IOS_FSM_FFd6 1 0 \/4 0 FB7_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: ASrf 15: A_FSB<8> 29: iobm/IOS_FSM_FFd4
|
||
2: A_FSB<10> 16: A_FSB<9> 30: iobm/IOS_FSM_FFd5
|
||
3: A_FSB<14> 17: A_FSB<22> 31: iobm/IOS_FSM_FFd6
|
||
4: A_FSB<15> 18: A_FSB<23> 32: iobm/IOS_FSM_FFd7
|
||
5: A_FSB<16> 19: IORW 33: iobs/IOACTr
|
||
6: A_FSB<17> 20: QoSEN 34: iobs/Sent
|
||
7: A_FSB<18> 21: RnW_IOB 35: iobs/TS_FSM_FFd1
|
||
8: A_FSB<19> 22: SlowClockGate 36: iobs/TS_FSM_FFd2
|
||
9: A_FSB<1> 23: cnt/C8Mr<0> 37: nADoutLE1
|
||
10: A_FSB<20> 24: cnt/C8Mr<1> 38: nAS_FSB
|
||
11: A_FSB<21> 25: iobm/C8Mr 39: nAoutOE
|
||
12: A_FSB<2> 26: iobm/IOREQr 40: nWE_FSB
|
||
13: A_FSB<6> 27: iobm/IOS_FSM_FFd2 41: ram/RASEL
|
||
14: A_FSB<7> 28: iobm/IOS_FSM_FFd3
|
||
|
||
Signal 1 2 3 4 5 FB
|
||
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
||
IOREQ X...XXXX.XX.....XX.X............XXXXXX.X.......... 17
|
||
RA<1> .X.........X............................X......... 3
|
||
BACTr X....................................X............ 2
|
||
set/SetWRr X......X.XX.....XX...................X............ 7
|
||
RA<7> ..X.........X...........................X......... 3
|
||
RA<0> ........X......X........................X......... 3
|
||
iobs/TS_FSM_FFd1 ................................X.XX.............. 3
|
||
RA<8> ......X...X.............................X......... 3
|
||
RA<10> .....X.......X..........................X......... 3
|
||
iobs/Sent X...XXXX.XX.....XX.X.............XXXXX.X.......... 16
|
||
RA<9> ...X..........X.........................X......... 3
|
||
MCKE X..................X.XXX.............X............ 6
|
||
iobs/Load1 X...XXXX.XX.....XX.X.............XXXXX.X.......... 16
|
||
RnW_IOB ..................X.X...XXXXXXXX......X........... 11
|
||
GA<23> .................X................................ 1
|
||
iobs/TS_FSM_FFd2 X...XXXX.XX.....XX.X............XXXXXX.X.......... 17
|
||
GA<22> ................X................................. 1
|
||
iobm/IOS_FSM_FFd6 ........................XX.....X......X........... 4
|
||
0----+----1----+----2----+----3----+----4----+----5
|
||
0 0 0 0 0
|
||
*********************************** FB8 ***********************************
|
||
Number of function block inputs used/remaining: 40/14
|
||
Number of signals used by logic mapping into function block: 40
|
||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||
Name Pt Pt Pt Pt # Type Use
|
||
RAMReady 10 5<- 0 0 FB8_1 (b) (b)
|
||
RA<11> 2 2<- /\5 0 FB8_2 63 I/O O
|
||
ram/RefDone 2 0 /\2 1 FB8_3 (b) (b)
|
||
ram/RS<1> 3 0 0 2 FB8_4 (b) (b)
|
||
nRAS 2 0 0 3 FB8_5 64 I/O O
|
||
nRAMLWE 1 0 0 4 FB8_6 65 I/O O
|
||
IOU0 3 0 0 2 FB8_7 (b) (b)
|
||
nRAMUWE 1 0 \/4 0 FB8_8 66 I/O O
|
||
ram/RS<2> 9 4<- 0 0 FB8_9 67 I/O (b)
|
||
IOL0 3 0 0 2 FB8_10 (b) (b)
|
||
iobs/IORW1 4 0 0 1 FB8_11 68 I/O (b)
|
||
nBERR_FSB 3 0 \/1 1 FB8_12 70 I/O O
|
||
ram/RS<0> 6 1<- 0 0 FB8_13 (b) (b)
|
||
ram/RefCAS 8 3<- 0 0 FB8_14 71 I/O (b)
|
||
nBR_IOB 1 0 /\3 1 FB8_15 72 I/O O
|
||
IORW 3 0 \/1 1 FB8_16 (b) (b)
|
||
ram/RASEN 10 5<- 0 0 FB8_17 73 I/O (b)
|
||
iobs/Clear1 1 0 /\4 0 FB8_18 (b) (b)
|
||
|
||
Signals Used by Logic in Function Block
|
||
1: ASrf 15: RefUrg 28: nBERR_IOB
|
||
2: A_FSB<16> 16: cs/Overlay 29: nBR_IOBout
|
||
3: A_FSB<17> 17: iobs/IODONEr<0> 30: nDTACK_FSB
|
||
4: A_FSB<18> 18: iobs/IODONEr<1> 31: nLDS_FSB
|
||
5: A_FSB<19> 19: iobs/IOL1 32: nUDS_FSB
|
||
6: A_FSB<20> 20: iobs/IORW1 33: nWE_FSB
|
||
7: A_FSB<21> 21: iobs/IOU1 34: ram/RASEL
|
||
8: BACTr 22: iobs/Sent 35: ram/RASEN
|
||
9: A_FSB<22> 23: iobs/TS_FSM_FFd1 36: ram/RASrf
|
||
10: A_FSB<23> 24: iobs/TS_FSM_FFd2 37: ram/RS<0>
|
||
11: IOL0 25: nADoutLE1 38: ram/RS<1>
|
||
12: IOU0 26: nAS_FSB 39: ram/RS<2>
|
||
13: QoSEN 27: nBERR_FSB 40: ram/RefDone
|
||
14: RefReq
|
||
|
||
Signal 1 2 3 4 5 FB
|
||
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
||
RAMReady X......XXX...XX..........X..........XXXX.......... 11
|
||
RA<11> ....XX...........................X................ 3
|
||
ram/RefDone .............X........................XX.......... 3
|
||
ram/RS<1> X........................X...X......XXX........... 6
|
||
nRAS ........XX.....X.........X........XX.............. 6
|
||
nRAMLWE ..............................X.XX................ 3
|
||
IOU0 ...........X........X.X.X......X.................. 5
|
||
nRAMUWE ...............................XXX................ 3
|
||
ram/RS<2> X......XXX...XX..........X..........XXXX.......... 11
|
||
IOL0 ..........X.......X...X.X.....X................... 5
|
||
iobs/IORW1 XXXXXXX.XX..X......X.XXXXX......X................. 17
|
||
nBERR_FSB X...............XX...X...XXX...................... 7
|
||
ram/RS<0> X.......XX.....X.........X...X....X.XXX........... 10
|
||
ram/RefCAS X......XXX...XX..........X..........XXXX.......... 11
|
||
nBR_IOB ............................X..................... 1
|
||
IORW ...................X..XXX.......X................. 5
|
||
ram/RASEN X......XXX...XX..........X...X......XXXX.......... 12
|
||
iobs/Clear1 ......................XX.......................... 2
|
||
0----+----1----+----2----+----3----+----4----+----5
|
||
0 0 0 0 0
|
||
******************************* Equations ********************************
|
||
|
||
********** Mapped Logic **********
|
||
|
||
FDCPE_ALE0M: FDCPE port map (ALE0M,ALE0M_D,C16M,'0','0');
|
||
ALE0M_D <= ((NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
||
iobm/IOS_FSM_FFd2)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
||
iobm/IOS_FSM_FFd1)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT ALE0M));
|
||
|
||
FDCPE_ALE0S: FDCPE port map (ALE0S,iobs/TS_FSM_FFd2,FCLK,'0','0');
|
||
|
||
FDCPE_ASrf: FDCPE port map (ASrf,NOT nAS_FSB,NOT FCLK,'0','0');
|
||
|
||
FDCPE_BACTr: FDCPE port map (BACTr,BACTr_D,FCLK,'0','0');
|
||
BACTr_D <= (nAS_FSB AND NOT ASrf);
|
||
|
||
|
||
|
||
|
||
GA(22) <= A_FSB(22);
|
||
|
||
|
||
GA(23) <= A_FSB(23);
|
||
|
||
FDCPE_IOACT: FDCPE port map (IOACT,IOACT_D,C16M,'0','0');
|
||
IOACT_D <= ((IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr AND
|
||
NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOREQr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND NOT IOACT)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
||
iobm/IOS_FSM_FFd2)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
||
iobm/IOS_FSM_FFd1)
|
||
OR (IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND
|
||
NOT iobm/IOS_FSM_FFd6));
|
||
|
||
FDCPE_IODONE: FDCPE port map (IODONE,IODONE_D,C16M,'0','0');
|
||
IODONE_D <= ((NOT nVMA_IOB AND NOT iobm/C8Mr AND NOT iobm/ES(0) AND
|
||
iobm/IOS_FSM_FFd5 AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND iobm/ES(3))
|
||
OR (IODONE AND NOT iobm/IOS_FSM_FFd7 AND iobm/C8Mr)
|
||
OR (NOT nBERR_IOB AND NOT iobm/C8Mr AND iobm/IOS_FSM_FFd5)
|
||
OR (IODONE AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd5)
|
||
OR (NOT nVMA_IOB AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr AND
|
||
NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND iobm/ES(3))
|
||
OR (NOT nBERR_IOB AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr)
|
||
OR (iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr AND NOT nRES.PIN)
|
||
OR (iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr AND NOT nDTACK_IOB)
|
||
OR (NOT iobm/C8Mr AND iobm/IOS_FSM_FFd5 AND NOT nRES.PIN)
|
||
OR (NOT iobm/C8Mr AND iobm/IOS_FSM_FFd5 AND NOT nDTACK_IOB));
|
||
|
||
FDCPE_IOL0: FDCPE port map (IOL0,IOL0_D,FCLK,'0','0');
|
||
IOL0_D <= ((iobs/TS_FSM_FFd1 AND IOL0)
|
||
OR (NOT nLDS_FSB AND NOT iobs/TS_FSM_FFd1 AND nADoutLE1)
|
||
OR (iobs/IOL1 AND NOT iobs/TS_FSM_FFd1 AND NOT nADoutLE1));
|
||
|
||
FDCPE_IONPReady: FDCPE port map (IONPReady,IONPReady_D,FCLK,'0','0');
|
||
IONPReady_D <= ((nAS_FSB AND NOT ASrf)
|
||
OR (NOT iobs/Sent AND NOT IONPReady)
|
||
OR (NOT IONPReady AND NOT iobs/IODONEr(0))
|
||
OR (NOT IONPReady AND iobs/IODONEr(1))
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT IONPReady AND NOT nWE_FSB));
|
||
|
||
FDCPE_IOREQ: FDCPE port map (IOREQ,IOREQ_D,FCLK,'0','0');
|
||
IOREQ_D <= ((NOT A_FSB(21) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(20) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND nWE_FSB AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(19) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(18) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(17) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
|
||
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr)
|
||
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT ASrf AND nADoutLE1)
|
||
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
|
||
|
||
FDCPE_IORW: FDCPE port map (IORW,IORW_D,FCLK,'0','0',IORW_CE);
|
||
IORW_D <= ((nWE_FSB AND nADoutLE1)
|
||
OR (iobs/IORW1 AND NOT nADoutLE1));
|
||
IORW_CE <= (NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2);
|
||
|
||
FDCPE_IOU0: FDCPE port map (IOU0,IOU0_D,FCLK,'0','0');
|
||
IOU0_D <= ((iobs/TS_FSM_FFd1 AND IOU0)
|
||
OR (NOT nUDS_FSB AND NOT iobs/TS_FSM_FFd1 AND nADoutLE1)
|
||
OR (iobs/IOU1 AND NOT iobs/TS_FSM_FFd1 AND NOT nADoutLE1));
|
||
|
||
FDCPE_MCKE: FDCPE port map (MCKE,MCKE_D,NOT FCLK,'0',NOT nAS_FSB);
|
||
MCKE_D <= ((QoSEN AND SlowClockGate AND NOT cnt/C8Mr(1) AND NOT ASrf)
|
||
OR (QoSEN AND SlowClockGate AND cnt/C8Mr(0) AND NOT ASrf));
|
||
|
||
FDCPE_QoSEN: FDCPE port map (QoSEN,QoSEN_D,FCLK,'0','0',QoSEN_CE);
|
||
QoSEN_D <= ((NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
|
||
SlowTimeout(0))
|
||
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
|
||
SlowTimeout(1))
|
||
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
|
||
SlowTimeout(2))
|
||
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
|
||
SlowTimeout(3)));
|
||
QoSEN_CE <= (nAS_FSB AND NOT ASrf);
|
||
|
||
|
||
RA(0) <= ((ram/RASEL AND A_FSB(1))
|
||
OR (NOT ram/RASEL AND A_FSB(9)));
|
||
|
||
|
||
RA(1) <= ((A_FSB(10) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(2)));
|
||
|
||
|
||
RA(2) <= ((A_FSB(16) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(7)));
|
||
|
||
|
||
RA(3) <= ((A_FSB(20) AND ram/RASEL)
|
||
OR (A_FSB(19) AND NOT ram/RASEL));
|
||
|
||
|
||
RA(4) <= ((A_FSB(11) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(3)));
|
||
|
||
|
||
RA(5) <= ((A_FSB(12) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(4)));
|
||
|
||
|
||
RA(6) <= ((A_FSB(13) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(5)));
|
||
|
||
|
||
RA(7) <= ((A_FSB(14) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(6)));
|
||
|
||
|
||
RA(8) <= ((A_FSB(21) AND ram/RASEL)
|
||
OR (A_FSB(18) AND NOT ram/RASEL));
|
||
|
||
|
||
RA(9) <= ((A_FSB(15) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(8)));
|
||
|
||
|
||
RA(10) <= ((A_FSB(17) AND NOT ram/RASEL)
|
||
OR (ram/RASEL AND A_FSB(7)));
|
||
|
||
|
||
RA(11) <= ((A_FSB(20) AND ram/RASEL)
|
||
OR (A_FSB(19) AND NOT ram/RASEL));
|
||
|
||
FDCPE_RAMReady: FDCPE port map (RAMReady,RAMReady_D,FCLK,'0','0');
|
||
RAMReady_D <= ((ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2))
|
||
OR (NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2))
|
||
OR (nAS_FSB AND NOT RefUrg AND NOT ram/RS(2) AND NOT ASrf)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND NOT ram/RS(0) AND
|
||
NOT ram/RS(2))
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/RS(0) AND NOT ram/RS(2) AND
|
||
ASrf)
|
||
OR (ram/RefDone AND NOT ram/RS(2))
|
||
OR (NOT RefReq AND NOT RefUrg AND NOT ram/RS(2))
|
||
OR (NOT RefUrg AND ram/RS(0) AND NOT ram/RS(2))
|
||
OR (NOT RefUrg AND NOT ram/RS(2) AND BACTr)
|
||
OR (ram/RS(1) AND ram/RS(0) AND ram/RS(2)));
|
||
|
||
FDCPE_RefReq: FDCPE port map (RefReq,RefReq_D,FCLK,'0','0',RefReq_CE);
|
||
RefReq_D <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
|
||
cnt/Timer(3));
|
||
RefReq_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
|
||
|
||
FDCPE_RefUrg: FDCPE port map (RefUrg,RefUrg_D,FCLK,'0','0',RefUrg_CE);
|
||
RefUrg_D <= (NOT cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3));
|
||
RefUrg_CE <= (NOT cnt/Er(0) AND cnt/Er(1));
|
||
|
||
FTCPE_RnW_IOB: FTCPE port map (RnW_IOB_I,RnW_IOB_T,NOT C16M,'0','0');
|
||
RnW_IOB_T <= ((NOT RnW_IOB AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
||
NOT iobm/IOS_FSM_FFd2)
|
||
OR (RnW_IOB AND NOT IORW AND iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND
|
||
iobm/IOREQr)
|
||
OR (NOT RnW_IOB AND IORW AND NOT iobm/IOS_FSM_FFd3 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
||
NOT iobm/IOS_FSM_FFd2)
|
||
OR (NOT RnW_IOB AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
||
NOT iobm/IOS_FSM_FFd2)
|
||
OR (NOT RnW_IOB AND NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6 AND
|
||
NOT iobm/IOS_FSM_FFd2));
|
||
RnW_IOB <= RnW_IOB_I when RnW_IOB_OE = '1' else 'Z';
|
||
RnW_IOB_OE <= NOT nAoutOE;
|
||
|
||
FDCPE_SlowClockGate: FDCPE port map (SlowClockGate,SlowClockGate_D,FCLK,'0','0');
|
||
SlowClockGate_D <= ((nPOR AND SlowClockGate AND NOT set/SetWRr)
|
||
OR (nPOR AND A_FSB(1) AND set/SetWRr));
|
||
|
||
FDCPE_SlowIACK: FDCPE port map (SlowIACK,SlowIACK_D,FCLK,'0','0');
|
||
SlowIACK_D <= ((nPOR AND SlowIACK AND NOT set/SetWRr)
|
||
OR (nPOR AND A_FSB(7) AND set/SetWRr));
|
||
|
||
FDCPE_SlowIWM: FDCPE port map (SlowIWM,SlowIWM_D,FCLK,'0','0');
|
||
SlowIWM_D <= ((nPOR AND NOT SlowIWM AND NOT set/SetWRr)
|
||
OR (nPOR AND NOT A_FSB(5) AND set/SetWRr));
|
||
|
||
FDCPE_SlowSCC: FDCPE port map (SlowSCC,SlowSCC_D,FCLK,'0','0');
|
||
SlowSCC_D <= ((nPOR AND SlowSCC AND NOT set/SetWRr)
|
||
OR (nPOR AND A_FSB(4) AND set/SetWRr));
|
||
|
||
FDCPE_SlowSCSI: FDCPE port map (SlowSCSI,SlowSCSI_D,FCLK,'0','0');
|
||
SlowSCSI_D <= ((nPOR AND NOT SlowSCSI AND NOT set/SetWRr)
|
||
OR (nPOR AND NOT A_FSB(3) AND set/SetWRr));
|
||
|
||
FDCPE_SlowSnd: FDCPE port map (SlowSnd,SlowSnd_D,FCLK,'0','0');
|
||
SlowSnd_D <= ((nPOR AND NOT SlowSnd AND NOT set/SetWRr)
|
||
OR (nPOR AND NOT A_FSB(2) AND set/SetWRr));
|
||
|
||
FDCPE_SlowTimeout0: FDCPE port map (SlowTimeout(0),SlowTimeout_D(0),FCLK,'0','0');
|
||
SlowTimeout_D(0) <= ((nPOR AND NOT SlowTimeout(0) AND NOT set/SetWRr)
|
||
OR (nPOR AND NOT A_FSB(8) AND set/SetWRr));
|
||
|
||
FDCPE_SlowTimeout1: FDCPE port map (SlowTimeout(1),SlowTimeout_D(1),FCLK,'0','0');
|
||
SlowTimeout_D(1) <= ((nPOR AND NOT SlowTimeout(1) AND NOT set/SetWRr)
|
||
OR (nPOR AND NOT A_FSB(9) AND set/SetWRr));
|
||
|
||
FDCPE_SlowTimeout2: FDCPE port map (SlowTimeout(2),SlowTimeout_D(2),FCLK,'0','0');
|
||
SlowTimeout_D(2) <= ((A_FSB(10) AND nPOR AND set/SetWRr)
|
||
OR (nPOR AND SlowTimeout(2) AND NOT set/SetWRr));
|
||
|
||
FDCPE_SlowTimeout3: FDCPE port map (SlowTimeout(3),SlowTimeout_D(3),FCLK,'0','0');
|
||
SlowTimeout_D(3) <= ((A_FSB(11) AND nPOR AND set/SetWRr)
|
||
OR (nPOR AND SlowTimeout(3) AND NOT set/SetWRr));
|
||
|
||
FDCPE_SlowVIA: FDCPE port map (SlowVIA,SlowVIA_D,FCLK,'0','0');
|
||
SlowVIA_D <= ((nPOR AND NOT SlowVIA AND NOT set/SetWRr)
|
||
OR (nPOR AND NOT A_FSB(6) AND set/SetWRr));
|
||
|
||
FDCPE_cnt/C8Mr0: FDCPE port map (cnt/C8Mr(0),C8M,FCLK,'0','0');
|
||
|
||
FDCPE_cnt/C8Mr1: FDCPE port map (cnt/C8Mr(1),cnt/C8Mr(0),FCLK,'0','0');
|
||
|
||
FDCPE_cnt/C8Mr2: FDCPE port map (cnt/C8Mr(2),cnt/C8Mr(1),FCLK,'0','0');
|
||
|
||
FDCPE_cnt/C8Mr3: FDCPE port map (cnt/C8Mr(3),cnt/C8Mr(2),FCLK,'0','0');
|
||
|
||
FDCPE_cnt/Er0: FDCPE port map (cnt/Er(0),E,FCLK,'0','0');
|
||
|
||
FDCPE_cnt/Er1: FDCPE port map (cnt/Er(1),cnt/Er(0),FCLK,'0','0');
|
||
|
||
FTCPE_cnt/IS0: FTCPE port map (cnt/IS(0),cnt/IS_T(0),FCLK,'0','0');
|
||
cnt/IS_T(0) <= ((NOT nPOR AND cnt/IS(0))
|
||
OR (nPOR AND NOT cnt/IS(1) AND cnt/LTimerTick)
|
||
OR (nPOR AND NOT cnt/IS(0) AND cnt/LTimerTick AND nIPL2));
|
||
|
||
FDCPE_cnt/IS1: FDCPE port map (cnt/IS(1),cnt/IS_D(1),FCLK,'0','0');
|
||
cnt/IS_D(1) <= ((nPOR AND cnt/IS(1))
|
||
OR (nPOR AND cnt/IS(0) AND cnt/LTimerTick));
|
||
|
||
FTCPE_cnt/LTimer0: FTCPE port map (cnt/LTimer(0),'1',FCLK,'0','0',cnt/TimerTick);
|
||
|
||
FTCPE_cnt/LTimer1: FTCPE port map (cnt/LTimer(1),cnt/LTimer(0),FCLK,'0','0',cnt/TimerTick);
|
||
|
||
FTCPE_cnt/LTimer2: FTCPE port map (cnt/LTimer(2),cnt/LTimer_T(2),FCLK,'0','0',cnt/TimerTick);
|
||
cnt/LTimer_T(2) <= (cnt/LTimer(0) AND cnt/LTimer(1));
|
||
|
||
FTCPE_cnt/LTimer3: FTCPE port map (cnt/LTimer(3),cnt/LTimer_T(3),FCLK,'0','0',cnt/TimerTick);
|
||
cnt/LTimer_T(3) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2));
|
||
|
||
FTCPE_cnt/LTimer4: FTCPE port map (cnt/LTimer(4),cnt/LTimer_T(4),FCLK,'0','0',cnt/TimerTick);
|
||
cnt/LTimer_T(4) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
||
cnt/LTimer(3));
|
||
|
||
FTCPE_cnt/LTimer5: FTCPE port map (cnt/LTimer(5),cnt/LTimer_T(5),FCLK,'0','0',cnt/TimerTick);
|
||
cnt/LTimer_T(5) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
||
cnt/LTimer(3) AND cnt/LTimer(4));
|
||
|
||
FTCPE_cnt/LTimer6: FTCPE port map (cnt/LTimer(6),cnt/LTimer_T(6),FCLK,'0','0',cnt/TimerTick);
|
||
cnt/LTimer_T(6) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
||
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5));
|
||
|
||
FTCPE_cnt/LTimer7: FTCPE port map (cnt/LTimer(7),cnt/LTimer_T(7),FCLK,'0','0',cnt/TimerTick);
|
||
cnt/LTimer_T(7) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
||
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6));
|
||
|
||
FTCPE_cnt/LTimer8: FTCPE port map (cnt/LTimer(8),cnt/LTimer_T(8),FCLK,'0','0',cnt/TimerTick);
|
||
cnt/LTimer_T(8) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
||
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
||
cnt/LTimer(7));
|
||
|
||
FTCPE_cnt/LTimer9: FTCPE port map (cnt/LTimer(9),cnt/LTimer_T(9),FCLK,'0','0',cnt/TimerTick);
|
||
cnt/LTimer_T(9) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
||
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
||
cnt/LTimer(7) AND cnt/LTimer(8));
|
||
|
||
FTCPE_cnt/LTimer10: FTCPE port map (cnt/LTimer(10),cnt/LTimer_T(10),FCLK,'0','0',cnt/TimerTick);
|
||
cnt/LTimer_T(10) <= (cnt/LTimer(0) AND cnt/LTimer(1) AND cnt/LTimer(2) AND
|
||
cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND cnt/LTimer(6) AND
|
||
cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
|
||
|
||
FTCPE_cnt/LTimer11: FTCPE port map (cnt/LTimer(11),cnt/LTimer_T(11),FCLK,'0','0',cnt/TimerTick);
|
||
cnt/LTimer_T(11) <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND
|
||
cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
|
||
cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9));
|
||
|
||
FDCPE_cnt/LTimerTick: FDCPE port map (cnt/LTimerTick,cnt/LTimerTick_D,FCLK,'0','0');
|
||
cnt/LTimerTick_D <= (cnt/LTimer(0) AND cnt/LTimer(10) AND cnt/LTimer(1) AND
|
||
cnt/LTimer(2) AND cnt/LTimer(3) AND cnt/LTimer(4) AND cnt/LTimer(5) AND
|
||
cnt/LTimer(6) AND cnt/LTimer(7) AND cnt/LTimer(8) AND cnt/LTimer(9) AND
|
||
cnt/LTimer(11) AND cnt/TimerTick);
|
||
|
||
FDCPE_cnt/QS0: FDCPE port map (cnt/QS(0),cnt/QS_D(0),FCLK,'0','0');
|
||
cnt/QS_D(0) <= ((cnt/QS(0) AND cnt/TimerTick AND NOT cnt/QoSCSr)
|
||
OR (NOT cnt/QS(0) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr)
|
||
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND
|
||
NOT cnt/QoSCSr));
|
||
|
||
FDCPE_cnt/QS1: FDCPE port map (cnt/QS(1),cnt/QS_D(1),FCLK,'0','0');
|
||
cnt/QS_D(1) <= ((cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QoSCSr)
|
||
OR (NOT cnt/QS(1) AND NOT cnt/TimerTick AND NOT cnt/QoSCSr)
|
||
OR (NOT cnt/QS(0) AND cnt/QS(1) AND cnt/TimerTick AND
|
||
NOT cnt/QoSCSr)
|
||
OR (NOT cnt/QS(1) AND NOT cnt/QS(2) AND NOT cnt/QS(3) AND NOT cnt/QoSCSr));
|
||
|
||
FTCPE_cnt/QS2: FTCPE port map (cnt/QS(2),cnt/QS_T(2),FCLK,'0','0');
|
||
cnt/QS_T(2) <= ((NOT cnt/QS(2) AND cnt/QoSCSr)
|
||
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND cnt/QS(2) AND
|
||
cnt/TimerTick AND NOT cnt/QoSCSr)
|
||
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND cnt/QS(3) AND
|
||
cnt/TimerTick));
|
||
|
||
FDCPE_cnt/QS3: FDCPE port map (cnt/QS(3),cnt/QS_D(3),FCLK,'0','0');
|
||
cnt/QS_D(3) <= ((NOT cnt/QS(3) AND NOT cnt/QoSCSr)
|
||
OR (NOT cnt/QS(0) AND NOT cnt/QS(1) AND NOT cnt/QS(2) AND
|
||
cnt/TimerTick AND NOT cnt/QoSCSr));
|
||
|
||
FDCPE_cnt/QoSCSr: FDCPE port map (cnt/QoSCSr,cnt/QoSCSr_D,FCLK,'0','0');
|
||
cnt/QoSCSr_D <= ((NOT nRES.PIN)
|
||
OR (NOT A_FSB(21) AND A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND
|
||
NOT nAS_FSB AND SlowIWM)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
NOT A_FSB(22) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
|
||
NOT nAS_FSB AND SlowSnd AND NOT nWE_FSB AND A_FSB(9))
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
NOT A_FSB(22) AND A_FSB(14) AND A_FSB(12) AND A_FSB(11) AND A_FSB(10) AND
|
||
NOT nAS_FSB AND SlowSnd AND NOT nWE_FSB AND A_FSB(8))
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
NOT A_FSB(22) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
||
NOT nAS_FSB AND SlowSnd AND NOT nWE_FSB AND A_FSB(9))
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND A_FSB(15) AND A_FSB(13) AND NOT A_FSB(23) AND
|
||
NOT A_FSB(22) AND NOT A_FSB(14) AND NOT A_FSB(12) AND NOT A_FSB(11) AND NOT A_FSB(10) AND
|
||
NOT nAS_FSB AND SlowSnd AND NOT nWE_FSB AND A_FSB(8))
|
||
OR (A_FSB(20) AND A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
||
SlowSCC)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND
|
||
NOT nAS_FSB AND SlowIACK)
|
||
OR (A_FSB(21) AND NOT A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND
|
||
NOT nAS_FSB AND SlowVIA)
|
||
OR (NOT A_FSB(21) AND A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND
|
||
NOT nAS_FSB AND SlowSCSI));
|
||
|
||
FTCPE_cnt/Timer0: FTCPE port map (cnt/Timer(0),cnt/Timer_T(0),FCLK,'0','0',cnt/Timer_CE(0));
|
||
cnt/Timer_T(0) <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
|
||
cnt/Timer(3) AND NOT cnt/Er(0) AND cnt/Er(1));
|
||
cnt/Timer_CE(0) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
||
|
||
FTCPE_cnt/Timer1: FTCPE port map (cnt/Timer(1),cnt/Timer_T(1),FCLK,'0','0',cnt/Timer_CE(1));
|
||
cnt/Timer_T(1) <= ((cnt/Timer(0))
|
||
OR (cnt/Timer(1) AND NOT cnt/Timer(2) AND cnt/Timer(3) AND
|
||
NOT cnt/Er(0) AND cnt/Er(1)));
|
||
cnt/Timer_CE(1) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
||
|
||
FTCPE_cnt/Timer2: FTCPE port map (cnt/Timer(2),cnt/Timer_T(2),FCLK,'0','0',cnt/Timer_CE(2));
|
||
cnt/Timer_T(2) <= (cnt/Timer(0) AND cnt/Timer(1));
|
||
cnt/Timer_CE(2) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
||
|
||
FTCPE_cnt/Timer3: FTCPE port map (cnt/Timer(3),cnt/Timer_T(3),FCLK,'0','0',cnt/Timer_CE(3));
|
||
cnt/Timer_T(3) <= ((cnt/Timer(0) AND cnt/Timer(1) AND cnt/Timer(2))
|
||
OR (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
|
||
cnt/Timer(3) AND NOT cnt/Er(0) AND cnt/Er(1)));
|
||
cnt/Timer_CE(3) <= (NOT cnt/Er(0) AND cnt/Er(1));
|
||
|
||
FDCPE_cnt/TimerTick: FDCPE port map (cnt/TimerTick,cnt/TimerTick_D,FCLK,'0','0');
|
||
cnt/TimerTick_D <= (NOT cnt/Timer(0) AND cnt/Timer(1) AND NOT cnt/Timer(2) AND
|
||
cnt/Timer(3) AND NOT cnt/Er(0) AND cnt/Er(1));
|
||
|
||
FTCPE_cs/Overlay: FTCPE port map (cs/Overlay,cs/Overlay_T,FCLK,'0','0');
|
||
cs/Overlay_T <= ((nAS_FSB AND NOT cs/Overlay AND NOT nRES.PIN AND NOT ASrf)
|
||
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND
|
||
NOT nAS_FSB AND cs/Overlay)
|
||
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND
|
||
cs/Overlay AND ASrf));
|
||
|
||
FDCPE_iobm/C8Mr: FDCPE port map (iobm/C8Mr,C8M,C16M,'0','0');
|
||
|
||
FDCPE_iobm/DoutOE: FDCPE port map (iobm/DoutOE,iobm/DoutOE_D,C16M,'0','0');
|
||
iobm/DoutOE_D <= ((iobm/IOS_FSM_FFd3 AND iobm/DoutOE)
|
||
OR (iobm/IOS_FSM_FFd4 AND iobm/DoutOE)
|
||
OR (iobm/IOS_FSM_FFd5 AND iobm/DoutOE)
|
||
OR (iobm/IOS_FSM_FFd6 AND iobm/DoutOE)
|
||
OR (NOT IORW AND iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND
|
||
iobm/IOREQr));
|
||
|
||
FTCPE_iobm/ES0: FTCPE port map (iobm/ES(0),iobm/ES_T(0),NOT C8M,'0','0');
|
||
iobm/ES_T(0) <= ((iobm/ES(0) AND NOT E AND iobm/Er)
|
||
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND E)
|
||
OR (NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND NOT iobm/Er));
|
||
|
||
FDCPE_iobm/ES1: FDCPE port map (iobm/ES(1),iobm/ES_D(1),NOT C8M,'0','0');
|
||
iobm/ES_D(1) <= ((iobm/ES(0) AND iobm/ES(1))
|
||
OR (NOT iobm/ES(0) AND NOT iobm/ES(1))
|
||
OR (NOT E AND iobm/Er)
|
||
OR (iobm/ES(0) AND NOT iobm/ES(2) AND iobm/ES(3)));
|
||
|
||
FTCPE_iobm/ES2: FTCPE port map (iobm/ES(2),iobm/ES_T(2),NOT C8M,'0','0');
|
||
iobm/ES_T(2) <= ((iobm/ES(0) AND iobm/ES(1) AND E)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND NOT iobm/Er)
|
||
OR (iobm/ES(2) AND NOT E AND iobm/Er));
|
||
|
||
FTCPE_iobm/ES3: FTCPE port map (iobm/ES(3),iobm/ES_T(3),NOT C8M,'0','0');
|
||
iobm/ES_T(3) <= ((iobm/ES(3) AND NOT E AND iobm/Er)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND E)
|
||
OR (iobm/ES(0) AND iobm/ES(1) AND iobm/ES(2) AND NOT iobm/Er)
|
||
OR (iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
iobm/ES(3)));
|
||
|
||
FDCPE_iobm/Er: FDCPE port map (iobm/Er,E,NOT C8M,'0','0');
|
||
|
||
FDCPE_iobm/IOREQr: FDCPE port map (iobm/IOREQr,IOREQ,C16M,'0','0');
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd1: FDCPE port map (iobm/IOS_FSM_FFd1,iobm/IOS_FSM_FFd2,C16M,'0','0');
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd2: FDCPE port map (iobm/IOS_FSM_FFd2,iobm/IOS_FSM_FFd2_D,C16M,'0','0');
|
||
iobm/IOS_FSM_FFd2_D <= (IODONE AND iobm/IOS_FSM_FFd3 AND NOT iobm/C8Mr);
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd3: FDCPE port map (iobm/IOS_FSM_FFd3,iobm/IOS_FSM_FFd3_D,C16M,'0','0');
|
||
iobm/IOS_FSM_FFd3_D <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4)
|
||
OR (IODONE AND NOT iobm/C8Mr AND NOT iobm/IOS_FSM_FFd4));
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd4: FDCPE port map (iobm/IOS_FSM_FFd4,iobm/IOS_FSM_FFd5,C16M,'0','0');
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd5: FDCPE port map (iobm/IOS_FSM_FFd5,iobm/IOS_FSM_FFd6,C16M,'0','0');
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd6: FDCPE port map (iobm/IOS_FSM_FFd6,iobm/IOS_FSM_FFd6_D,C16M,'0','0');
|
||
iobm/IOS_FSM_FFd6_D <= (iobm/IOS_FSM_FFd7 AND NOT iobm/C8Mr AND iobm/IOREQr AND
|
||
NOT nAoutOE);
|
||
|
||
FDCPE_iobm/IOS_FSM_FFd7: FDCPE port map (iobm/IOS_FSM_FFd7,iobm/IOS_FSM_FFd7_D,C16M,'0','0');
|
||
iobm/IOS_FSM_FFd7_D <= ((NOT iobm/IOS_FSM_FFd7 AND NOT iobm/IOS_FSM_FFd1)
|
||
OR (NOT iobm/C8Mr AND iobm/IOREQr AND NOT iobm/IOS_FSM_FFd1 AND
|
||
NOT nAoutOE));
|
||
|
||
FDCPE_iobm/VPAr: FDCPE port map (iobm/VPAr,NOT nVPA_IOB,NOT C8M,'0','0');
|
||
|
||
FDCPE_iobs/Clear1: FDCPE port map (iobs/Clear1,iobs/Clear1_D,FCLK,'0','0');
|
||
iobs/Clear1_D <= (NOT iobs/TS_FSM_FFd1 AND iobs/TS_FSM_FFd2);
|
||
|
||
FDCPE_iobs/IOACTr: FDCPE port map (iobs/IOACTr,IOACT,FCLK,'0','0');
|
||
|
||
FDCPE_iobs/IODONEr0: FDCPE port map (iobs/IODONEr(0),iobs/IODONErf,FCLK,'0','0');
|
||
|
||
FDCPE_iobs/IODONEr1: FDCPE port map (iobs/IODONEr(1),iobs/IODONEr(0),FCLK,'0','0');
|
||
|
||
FDCPE_iobs/IODONErf: FDCPE port map (iobs/IODONErf,IODONE,NOT FCLK,'0','0');
|
||
|
||
FDCPE_iobs/IOL1: FDCPE port map (iobs/IOL1,NOT nLDS_FSB,FCLK,'0','0',iobs/Load1);
|
||
|
||
FTCPE_iobs/IORW1: FTCPE port map (iobs/IORW1,iobs/IORW1_T,FCLK,'0','0');
|
||
iobs/IORW1_T <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
||
NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND
|
||
nADoutLE1)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
||
NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND
|
||
nADoutLE1)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND
|
||
NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd1 AND ASrf AND
|
||
nADoutLE1)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND
|
||
NOT QoSEN AND NOT nWE_FSB AND iobs/IORW1 AND iobs/TS_FSM_FFd2 AND ASrf AND
|
||
nADoutLE1));
|
||
|
||
FDCPE_iobs/IOU1: FDCPE port map (iobs/IOU1,NOT nUDS_FSB,FCLK,'0','0',iobs/Load1);
|
||
|
||
FDCPE_iobs/Load1: FDCPE port map (iobs/Load1,iobs/Load1_D,FCLK,'0','0');
|
||
iobs/Load1_D <= ((A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
||
NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND nADoutLE1)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
||
NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND
|
||
NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd1 AND ASrf AND nADoutLE1)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND
|
||
NOT QoSEN AND NOT nWE_FSB AND iobs/TS_FSM_FFd2 AND ASrf AND nADoutLE1));
|
||
|
||
FTCPE_iobs/Sent: FTCPE port map (iobs/Sent,iobs/Sent_T,FCLK,'0','0');
|
||
iobs/Sent_T <= ((A_FSB(21) AND A_FSB(22) AND NOT nAS_FSB AND NOT iobs/Sent AND
|
||
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT nAS_FSB AND NOT iobs/Sent AND
|
||
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT iobs/Sent AND
|
||
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND ASrf AND nADoutLE1)
|
||
OR (A_FSB(21) AND A_FSB(22) AND NOT iobs/Sent AND
|
||
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND ASrf AND nADoutLE1)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND
|
||
NOT iobs/Sent AND NOT QoSEN AND NOT nWE_FSB AND nADoutLE1)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT iobs/Sent AND
|
||
NOT QoSEN AND NOT nWE_FSB AND ASrf AND nADoutLE1)
|
||
OR (nAS_FSB AND iobs/Sent AND NOT ASrf)
|
||
OR (A_FSB(23) AND NOT nAS_FSB AND NOT iobs/Sent AND
|
||
NOT iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (A_FSB(23) AND NOT iobs/Sent AND NOT iobs/TS_FSM_FFd1 AND
|
||
NOT iobs/TS_FSM_FFd2 AND ASrf AND nADoutLE1)
|
||
OR (NOT nAS_FSB AND NOT iobs/Sent AND QoSEN AND NOT iobs/TS_FSM_FFd1 AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT iobs/Sent AND QoSEN AND NOT iobs/TS_FSM_FFd1 AND
|
||
NOT iobs/TS_FSM_FFd2 AND ASrf AND nADoutLE1));
|
||
|
||
FDCPE_iobs/TS_FSM_FFd1: FDCPE port map (iobs/TS_FSM_FFd1,iobs/TS_FSM_FFd1_D,FCLK,'0','0');
|
||
iobs/TS_FSM_FFd1_D <= ((iobs/TS_FSM_FFd2)
|
||
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr));
|
||
|
||
FDCPE_iobs/TS_FSM_FFd2: FDCPE port map (iobs/TS_FSM_FFd2,iobs/TS_FSM_FFd2_D,FCLK,'0','0');
|
||
iobs/TS_FSM_FFd2_D <= ((NOT A_FSB(19) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(18) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(17) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(16) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(21) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(20) AND NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT QoSEN AND nWE_FSB AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (iobs/TS_FSM_FFd1 AND NOT iobs/TS_FSM_FFd2)
|
||
OR (iobs/TS_FSM_FFd1 AND iobs/IOACTr)
|
||
OR (iobs/Sent AND NOT iobs/TS_FSM_FFd2 AND nADoutLE1)
|
||
OR (nAS_FSB AND NOT iobs/TS_FSM_FFd2 AND NOT ASrf AND nADoutLE1)
|
||
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND NOT QoSEN AND
|
||
NOT iobs/TS_FSM_FFd2 AND nADoutLE1));
|
||
|
||
|
||
nADoutLE0 <= (NOT ALE0M AND NOT ALE0S);
|
||
|
||
FDCPE_nADoutLE1: FDCPE port map (nADoutLE1,nADoutLE1_D,FCLK,'0','0');
|
||
nADoutLE1_D <= ((iobs/Load1)
|
||
OR (NOT iobs/Clear1 AND NOT nADoutLE1));
|
||
|
||
FDCPE_nAS_IOB: FDCPE port map (nAS_IOB_I,nAS_IOB,NOT C16M,'0','0');
|
||
nAS_IOB <= ((NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6));
|
||
nAS_IOB <= nAS_IOB_I when nAS_IOB_OE = '1' else 'Z';
|
||
nAS_IOB_OE <= NOT nAoutOE;
|
||
|
||
FDCPE_nAoutOE: FDCPE port map (nAoutOE,nAoutOE_D,FCLK,'0','0');
|
||
nAoutOE_D <= (cnt/IS(1) AND cnt/IS(0) AND NOT nBR_IOBout);
|
||
|
||
FTCPE_nBERR_FSB: FTCPE port map (nBERR_FSB,nBERR_FSB_T,FCLK,'0','0');
|
||
nBERR_FSB_T <= ((nAS_FSB AND NOT nBERR_FSB AND NOT ASrf)
|
||
OR (NOT nAS_FSB AND iobs/Sent AND NOT nBERR_IOB AND nBERR_FSB AND
|
||
iobs/IODONEr(0) AND NOT iobs/IODONEr(1))
|
||
OR (iobs/Sent AND NOT nBERR_IOB AND nBERR_FSB AND
|
||
iobs/IODONEr(0) AND ASrf AND NOT iobs/IODONEr(1)));
|
||
|
||
|
||
nBR_IOB_I <= '0';
|
||
nBR_IOB <= nBR_IOB_I when nBR_IOB_OE = '1' else 'Z';
|
||
nBR_IOB_OE <= NOT nBR_IOBout;
|
||
|
||
FDCPE_nBR_IOBout: FDCPE port map (nBR_IOBout,nBR_IOBout_D,FCLK,'0','0');
|
||
nBR_IOBout_D <= ((cnt/IS(1) AND nBR_IOBout)
|
||
OR (cnt/IS(1) AND NOT cnt/IS(0) AND NOT nIPL2));
|
||
|
||
FDCPE_nCAS: FDCPE port map (nCAS,nCAS_D,NOT FCLK,ram/RefCAS,nCAS_PRE);
|
||
nCAS_D <= ((ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2))
|
||
OR (NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2))
|
||
OR (NOT ram/RS(1) AND NOT ram/RS(0) AND ram/RS(2)));
|
||
nCAS_PRE <= (nAS_FSB AND ram/CASEndEN);
|
||
|
||
FDCPE_nDTACK_FSB: FDCPE port map (nDTACK_FSB,nDTACK_FSB_D,FCLK,'0',nAS_FSB);
|
||
nDTACK_FSB_D <= ((NOT A_FSB(22) AND NOT IONPReady AND NOT RAMReady)
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(23) AND A_FSB(22))
|
||
OR (A_FSB(21) AND A_FSB(20) AND A_FSB(19) AND A_FSB(18) AND
|
||
A_FSB(17) AND A_FSB(16) AND NOT iobs/Sent AND NOT IONPReady AND NOT nWE_FSB AND
|
||
NOT nADoutLE1)
|
||
OR (A_FSB(23) AND NOT IONPReady)
|
||
OR (QoSEN AND NOT IONPReady)
|
||
OR (A_FSB(21) AND A_FSB(22) AND NOT IONPReady)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT IONPReady));
|
||
|
||
FDCPE_nDinLE: FDCPE port map (nDinLE,nDinLE_D,NOT C16M,'0','0');
|
||
nDinLE_D <= (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4);
|
||
|
||
|
||
nDinOE <= NOT (((A_FSB(23) AND NOT nAS_FSB AND nWE_FSB AND BACTr)
|
||
OR (A_FSB(21) AND A_FSB(22) AND NOT nAS_FSB AND nWE_FSB AND
|
||
BACTr)
|
||
OR (A_FSB(20) AND A_FSB(22) AND NOT nAS_FSB AND nWE_FSB AND
|
||
BACTr)));
|
||
|
||
|
||
nDoutOE <= NOT ((iobm/DoutOE AND NOT nAoutOE));
|
||
|
||
FDCPE_nLDS_IOB: FDCPE port map (nLDS_IOB_I,nLDS_IOB,NOT C16M,'0','0');
|
||
nLDS_IOB <= ((NOT IOL0)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT IORW AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6));
|
||
nLDS_IOB <= nLDS_IOB_I when nLDS_IOB_OE = '1' else 'Z';
|
||
nLDS_IOB_OE <= NOT nAoutOE;
|
||
|
||
FDCPE_nOE: FDCPE port map (nOE,nOE_D,FCLK,'0',nAS_FSB);
|
||
nOE_D <= (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/Overlay AND nWE_FSB);
|
||
|
||
FTCPE_nPOR: FTCPE port map (nPOR,nPOR_T,FCLK,'0','0');
|
||
nPOR_T <= ((NOT nPOR AND NOT cnt/C8Mr(1) AND cnt/C8Mr(0))
|
||
OR (nPOR AND cnt/C8Mr(1) AND cnt/C8Mr(0) AND cnt/C8Mr(2) AND
|
||
cnt/C8Mr(3))
|
||
OR (nPOR AND NOT cnt/C8Mr(1) AND NOT cnt/C8Mr(0) AND NOT cnt/C8Mr(2) AND
|
||
NOT cnt/C8Mr(3)));
|
||
|
||
|
||
nRAMLWE <= NOT ((NOT nLDS_FSB AND NOT nWE_FSB AND ram/RASEL));
|
||
|
||
|
||
nRAMUWE <= NOT ((NOT nWE_FSB AND NOT nUDS_FSB AND ram/RASEL));
|
||
|
||
|
||
nRAS <= NOT (((ram/RASrf)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND NOT cs/Overlay AND
|
||
ram/RASEN)));
|
||
|
||
|
||
nRES_I <= '0';
|
||
nRES <= nRES_I when nRES_OE = '1' else 'Z';
|
||
nRES_OE <= NOT nRESout;
|
||
|
||
FDCPE_nRESout: FDCPE port map (nRESout,nRESout_D,FCLK,'0','0');
|
||
nRESout_D <= ((cnt/IS(1) AND cnt/IS(0) AND cnt/LTimerTick)
|
||
OR (cnt/IS(1) AND cnt/IS(0) AND nRESout));
|
||
|
||
|
||
nROMOE <= NOT (((NOT nAS_FSB AND cs/Overlay AND nWE_FSB)
|
||
OR (NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND
|
||
NOT nAS_FSB AND nWE_FSB)));
|
||
|
||
|
||
nROMWE <= NOT ((NOT A_FSB(21) AND NOT A_FSB(20) AND NOT A_FSB(23) AND A_FSB(22) AND
|
||
NOT nAS_FSB AND NOT nWE_FSB));
|
||
|
||
FDCPE_nUDS_IOB: FDCPE port map (nUDS_IOB_I,nUDS_IOB,NOT C16M,'0','0');
|
||
nUDS_IOB <= ((NOT IOU0)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd7 AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT IORW AND NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOS_FSM_FFd4 AND
|
||
NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND iobm/C8Mr AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6)
|
||
OR (NOT iobm/IOS_FSM_FFd3 AND NOT iobm/IOREQr AND
|
||
NOT iobm/IOS_FSM_FFd4 AND NOT iobm/IOS_FSM_FFd5 AND NOT iobm/IOS_FSM_FFd6));
|
||
nUDS_IOB <= nUDS_IOB_I when nUDS_IOB_OE = '1' else 'Z';
|
||
nUDS_IOB_OE <= NOT nAoutOE;
|
||
|
||
FTCPE_nVMA_IOB: FTCPE port map (nVMA_IOB_I,nVMA_IOB_T,NOT C8M,'0','0');
|
||
nVMA_IOB_T <= ((NOT nVMA_IOB AND NOT iobm/ES(0) AND NOT iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3))
|
||
OR (nVMA_IOB AND iobm/ES(0) AND iobm/ES(1) AND NOT iobm/ES(2) AND
|
||
NOT iobm/ES(3) AND IOACT AND iobm/VPAr));
|
||
nVMA_IOB <= nVMA_IOB_I when nVMA_IOB_OE = '1' else 'Z';
|
||
nVMA_IOB_OE <= NOT nAoutOE;
|
||
|
||
FDCPE_nVPA_FSB: FDCPE port map (nVPA_FSB,nVPA_FSB_D,FCLK,'0',nAS_FSB);
|
||
nVPA_FSB_D <= (A_FSB(21) AND A_FSB(20) AND A_FSB(23) AND A_FSB(22) AND
|
||
IONPReady);
|
||
|
||
FDCPE_ram/CASEndEN: FDCPE port map (ram/CASEndEN,ram/CASEndEN_D,NOT FCLK,'0','0');
|
||
ram/CASEndEN_D <= ((ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2))
|
||
OR (NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2)));
|
||
|
||
FDCPE_ram/RASEL: FDCPE port map (ram/RASEL,ram/RASEL_D,FCLK,'0','0');
|
||
ram/RASEL_D <= ((NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2))
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND NOT cs/Overlay AND
|
||
NOT ram/RS(1) AND NOT ram/RS(2))
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/Overlay AND NOT ram/RS(1) AND
|
||
NOT ram/RS(2) AND ASrf));
|
||
|
||
FDCPE_ram/RASEN: FDCPE port map (ram/RASEN,ram/RASEN_D,FCLK,'0','0');
|
||
ram/RASEN_D <= ((NOT RefReq AND NOT RefUrg AND NOT ram/RS(1) AND NOT ram/RS(0) AND
|
||
NOT ram/RS(2))
|
||
OR (NOT RefUrg AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND
|
||
BACTr)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2))
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT ram/RS(1) AND NOT ram/RS(0) AND
|
||
NOT ram/RS(2) AND ASrf)
|
||
OR (nAS_FSB AND NOT RefUrg AND NOT ram/RS(1) AND NOT ram/RS(0) AND
|
||
NOT ram/RS(2) AND NOT ASrf)
|
||
OR (NOT RefUrg AND ram/RS(1) AND ram/RS(0))
|
||
OR (ram/RefDone AND ram/RS(1) AND ram/RS(0))
|
||
OR (ram/RS(1) AND ram/RS(0) AND ram/RS(2))
|
||
OR (nDTACK_FSB AND NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2))
|
||
OR (ram/RefDone AND NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2)));
|
||
|
||
FDCPE_ram/RASrf: FDCPE port map (ram/RASrf,ram/RASrf_D,NOT FCLK,'0','0');
|
||
ram/RASrf_D <= ((NOT ram/RS(1) AND ram/RS(0))
|
||
OR (NOT ram/RS(1) AND ram/RS(2)));
|
||
|
||
FDCPE_ram/RS0: FDCPE port map (ram/RS(0),ram/RS_D(0),FCLK,'0','0');
|
||
ram/RS_D(0) <= ((NOT A_FSB(23) AND NOT A_FSB(22) AND NOT cs/Overlay AND NOT ram/RS(0) AND
|
||
ram/RASEN AND ASrf)
|
||
OR (ram/RS(1) AND NOT ram/RS(0))
|
||
OR (NOT ram/RS(0) AND ram/RS(2))
|
||
OR (NOT nAS_FSB AND nDTACK_FSB AND NOT ram/RS(1) AND ram/RS(0) AND
|
||
NOT ram/RS(2))
|
||
OR (nDTACK_FSB AND NOT ram/RS(1) AND ram/RS(0) AND NOT ram/RS(2) AND
|
||
ASrf)
|
||
OR (NOT A_FSB(23) AND NOT A_FSB(22) AND NOT nAS_FSB AND NOT cs/Overlay AND
|
||
NOT ram/RS(0) AND ram/RASEN));
|
||
|
||
FTCPE_ram/RS1: FTCPE port map (ram/RS(1),ram/RS_T(1),FCLK,'0','0');
|
||
ram/RS_T(1) <= ((NOT ram/RS(0))
|
||
OR (NOT nAS_FSB AND nDTACK_FSB AND NOT ram/RS(1) AND NOT ram/RS(2))
|
||
OR (nDTACK_FSB AND NOT ram/RS(1) AND NOT ram/RS(2) AND ASrf));
|
||
|
||
FTCPE_ram/RS2: FTCPE port map (ram/RS(2),ram/RS_T(2),FCLK,'0','0');
|
||
ram/RS_T(2) <= ((ram/RS(1) AND ram/RS(0) AND ram/RS(2))
|
||
OR (RefUrg AND NOT ram/RefDone AND ram/RS(1) AND ram/RS(0))
|
||
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2) AND ASrf AND NOT BACTr)
|
||
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2) AND ASrf AND NOT BACTr)
|
||
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2))
|
||
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2))
|
||
OR (nAS_FSB AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2) AND NOT ASrf)
|
||
OR (A_FSB(23) AND NOT nAS_FSB AND RefReq AND NOT ram/RefDone AND
|
||
NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr)
|
||
OR (A_FSB(22) AND NOT nAS_FSB AND RefReq AND NOT ram/RefDone AND
|
||
NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr));
|
||
|
||
FDCPE_ram/RefCAS: FDCPE port map (ram/RefCAS,ram/RefCAS_D,FCLK,'0','0');
|
||
ram/RefCAS_D <= ((A_FSB(23) AND NOT nAS_FSB AND RefReq AND NOT ram/RefDone AND
|
||
NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr)
|
||
OR (A_FSB(23) AND RefReq AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2) AND ASrf AND NOT BACTr)
|
||
OR (A_FSB(22) AND RefReq AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2) AND ASrf AND NOT BACTr)
|
||
OR (RefUrg AND NOT ram/RefDone AND ram/RS(1) AND ram/RS(0) AND
|
||
NOT ram/RS(2))
|
||
OR (A_FSB(23) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2))
|
||
OR (A_FSB(22) AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2))
|
||
OR (nAS_FSB AND RefUrg AND NOT ram/RefDone AND NOT ram/RS(1) AND
|
||
NOT ram/RS(0) AND NOT ram/RS(2) AND NOT ASrf)
|
||
OR (A_FSB(22) AND NOT nAS_FSB AND RefReq AND NOT ram/RefDone AND
|
||
NOT ram/RS(1) AND NOT ram/RS(0) AND NOT ram/RS(2) AND NOT BACTr));
|
||
|
||
FDCPE_ram/RefDone: FDCPE port map (ram/RefDone,ram/RefDone_D,FCLK,'0','0');
|
||
ram/RefDone_D <= ((RefReq AND ram/RefDone)
|
||
OR (RefReq AND ram/RS(2)));
|
||
|
||
FDCPE_set/SetWRr: FDCPE port map (set/SetWRr,set/SetWRr_D,FCLK,'0','0');
|
||
set/SetWRr_D <= ((A_FSB(21) AND A_FSB(20) AND NOT A_FSB(19) AND A_FSB(23) AND
|
||
A_FSB(22) AND NOT nAS_FSB)
|
||
OR (A_FSB(21) AND A_FSB(20) AND NOT A_FSB(19) AND A_FSB(23) AND
|
||
A_FSB(22) AND ASrf));
|
||
|
||
Register Legend:
|
||
FDCPE (Q,D,C,CLR,PRE,CE);
|
||
FTCPE (Q,D,C,CLR,PRE,CE);
|
||
LDCP (Q,D,G,CLR,PRE);
|
||
|
||
****************************** Device Pin Out *****************************
|
||
|
||
Device : XC95144XL-10-TQ100
|
||
|
||
|
||
--------------------------------------------------
|
||
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
|
||
| 99 97 95 93 91 89 87 85 83 81 79 77 |
|
||
| 1 75 |
|
||
| 2 74 |
|
||
| 3 73 |
|
||
| 4 72 |
|
||
| 5 71 |
|
||
| 6 70 |
|
||
| 7 69 |
|
||
| 8 68 |
|
||
| 9 67 |
|
||
| 10 66 |
|
||
| 11 65 |
|
||
| 12 64 |
|
||
| 13 XC95144XL-10-TQ100 63 |
|
||
| 14 62 |
|
||
| 15 61 |
|
||
| 16 60 |
|
||
| 17 59 |
|
||
| 18 58 |
|
||
| 19 57 |
|
||
| 20 56 |
|
||
| 21 55 |
|
||
| 22 54 |
|
||
| 23 53 |
|
||
| 24 52 |
|
||
| 25 51 |
|
||
| 27 29 31 33 35 37 39 41 43 45 47 49 |
|
||
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
|
||
--------------------------------------------------
|
||
|
||
|
||
Pin Signal Pin Signal
|
||
No. Name No. Name
|
||
1 KPR 51 VCC
|
||
2 A_FSB<5> 52 RA<7>
|
||
3 A_FSB<6> 53 RA<0>
|
||
4 A_FSB<7> 54 RA<8>
|
||
5 VCC 55 RA<10>
|
||
6 A_FSB<8> 56 RA<9>
|
||
7 A_FSB<9> 57 VCC
|
||
8 A_FSB<10> 58 MCKE
|
||
9 A_FSB<11> 59 RnW_IOB
|
||
10 A_FSB<12> 60 GA<23>
|
||
11 A_FSB<13> 61 GA<22>
|
||
12 A_FSB<14> 62 GND
|
||
13 A_FSB<15> 63 RA<11>
|
||
14 A_FSB<16> 64 nRAS
|
||
15 A_FSB<17> 65 nRAMLWE
|
||
16 A_FSB<18> 66 nRAMUWE
|
||
17 A_FSB<19> 67 KPR
|
||
18 A_FSB<20> 68 KPR
|
||
19 A_FSB<21> 69 GND
|
||
20 A_FSB<22> 70 nBERR_FSB
|
||
21 GND 71 KPR
|
||
22 C16M 72 nBR_IOB
|
||
23 C8M 73 KPR
|
||
24 A_FSB<23> 74 nVMA_IOB
|
||
25 E 75 GND
|
||
26 VCC 76 nBERR_IOB
|
||
27 FCLK 77 nVPA_IOB
|
||
28 nDTACK_FSB 78 nDTACK_IOB
|
||
29 nWE_FSB 79 nLDS_IOB
|
||
30 nLDS_FSB 80 nUDS_IOB
|
||
31 GND 81 nAS_IOB
|
||
32 nAS_FSB 82 nADoutLE1
|
||
33 nUDS_FSB 83 TDO
|
||
34 nROMWE 84 GND
|
||
35 nROMOE 85 nADoutLE0
|
||
36 nCAS 86 nDinLE
|
||
37 nOE 87 nAoutOE
|
||
38 VCC 88 VCC
|
||
39 KPR 89 nDoutOE
|
||
40 RA<4> 90 nDinOE
|
||
41 RA<3> 91 nRES
|
||
42 RA<5> 92 nIPL2
|
||
43 RA<2> 93 nVPA_FSB
|
||
44 GND 94 A_FSB<1>
|
||
45 TDI 95 A_FSB<2>
|
||
46 RA<6> 96 A_FSB<3>
|
||
47 TMS 97 A_FSB<4>
|
||
48 TCK 98 VCC
|
||
49 KPR 99 KPR
|
||
50 RA<1> 100 GND
|
||
|
||
|
||
Legend : NC = Not Connected, unbonded pin
|
||
PGND = Unused I/O configured as additional Ground pin
|
||
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
||
KPR = Unused I/O with weak keeper (leave unconnected)
|
||
VCC = Dedicated Power Pin
|
||
GND = Dedicated Ground Pin
|
||
TDI = Test Data In, JTAG pin
|
||
TDO = Test Data Out, JTAG pin
|
||
TCK = Test Clock, JTAG pin
|
||
TMS = Test Mode Select, JTAG pin
|
||
PROHIBITED = User reserved pin
|
||
**************************** Compiler Options ****************************
|
||
|
||
Following is a list of all global compiler options used by the fitter run.
|
||
|
||
Device(s) Specified : xc95144xl-10-TQ100
|
||
Optimization Method : SPEED
|
||
Multi-Level Logic Optimization : ON
|
||
Ignore Timing Specifications : OFF
|
||
Default Register Power Up Value : LOW
|
||
Keep User Location Constraints : ON
|
||
What-You-See-Is-What-You-Get : OFF
|
||
Exhaustive Fitting : OFF
|
||
Keep Unused Inputs : OFF
|
||
Slew Rate : FAST
|
||
Power Mode : STD
|
||
Ground on Unused IOs : OFF
|
||
Set I/O Pin Termination : KEEPER
|
||
Global Clock Optimization : ON
|
||
Global Set/Reset Optimization : ON
|
||
Global Ouput Enable Optimization : ON
|
||
Input Limit : 54
|
||
Pterm Limit : 25
|