Macintosh-HW/Warp-SE
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dev-0.7a-fastiack-fastscsi
Warp-SE/cpld
History
Zane Kaminski 1ea0196721 0.7a-fastiack-fastscsi
2024-10-12 00:39:35 -04:00
..
XC95144XL 0.7a-fastiack-fastscsi 2024-10-12 00:39:35 -04:00
CNT.v Add settings module power-on reset 2024-10-11 17:28:08 -04:00
CS.v Add slowdown settings 2024-10-11 16:41:31 -04:00
FSB.v Add slowdown settings 2024-10-11 16:41:31 -04:00
IOBM.v
IOBS.v Undo I/O R/W gate for now. Will have to re-add this later for new revision with PDS R/W connected to CPLD. 2024-10-09 04:15:23 -04:00
RAM.v
SET.v 0.7a-fastiack-fastscsi 2024-10-12 00:39:35 -04:00
WarpSE-XC95144XL.ucf
WarpSE.v Add settings module power-on reset 2024-10-11 17:28:08 -04:00