Add CAS PAL.
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@ -353,8 +353,6 @@ module bmu0(simclk, n_res,
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input wire oe1;
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output wire g244, we;
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output reg ava14, l15, vid, ava13;
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// N.B. Although this is nominally an output we can treat it as an
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// input?
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input wire servid, dtack;
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`power wire vcc;
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@ -439,7 +437,6 @@ module tsg(simclk, n_res,
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end
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end
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endmodule
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// U11E-16R8: Analog Signal Generator
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// N.B.: ASG as a "sound generator" is largely a misnomer, it is
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@ -491,6 +488,110 @@ module asg(simclk, n_res,
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end
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endmodule
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// 20R4: Bus Management Unit 2
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// The Macintosh Plus's version of BMU0, almost exactly the same
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// except for the addition of `C2M`, `*DMA`, `*TSEN0` as an input, and
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// RA8.
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module bmu2(simclk, n_res,
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sysclk, ramen, romen, va10, va11, va12, va13, va14, rw,
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c2m, n_snddma, gnd, oe1, oe1_2, ra8, g244, ava14, ava13,
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l15, vid, we, servid, dtack, vcc);
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input `virtwire simclk, n_res;
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input wire sysclk;
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input wire ramen, romen, va10, va11, va12, va13, va14, rw,
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c2m, n_snddma;
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`power wire gnd;
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input wire oe1, oe1_2;
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output wire ra8, g244;
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output reg ava14, ava13, l15, vid;
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output wire we;
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input wire servid, dtack;
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`power wire vcc;
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// We must implement RESET for simulation or else this will never
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// stabilize.
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always @(negedge n_res) begin
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// g244 = 1; we = 1;
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ava14 <= 1; l15 <= 1; vid <= 1; ava13 <= 1;
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end
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// Simulate combinatorial logic.
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assign g244
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= ~(~ramen & rw
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| ~g244 & ~ramen);
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assign we
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= ~(~ramen & ~rw
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| ~we & ~dtack); // or `dtack` is shorter before the video cycle
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// TODO FIXME: Determine how we should drive RA8.
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assign ra8
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= ~(~n_snddma & c2m & va10);
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// Simulate registered logic.
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always @(posedge sysclk) begin
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if (n_res) begin
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ava14 <= ~(~va14 & ~va13); // + 1
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l15 <=
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~(~va14 & ~va13 & ~va12 & ~va11 & ~va10 // we haven't passed line 15
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| va14 & ~va13 & va12 & va11 & va10); // passed by 368
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vid <=
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~(servid); // here we invert: blanking is in `vshft`
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ava13 <= ~(va13); // + 1
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end
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end
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endmodule
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// 20L8: Column Access Strobe
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module cas(simclk, n_res,
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a9, a19, a20, a21, a22, a23, c2m, s1, n_casl, n_cash,
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rows, gnd, tsen2, ramsize, n_romen, ovlay, n_cas0l,
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n_cas0h, n_cas1l, n_cas1h, n_scsi, n_dack, n_as, vcc);
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input `virtwire simclk, n_res;
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input wire a9, a19, a20, a21, a22, a23, c2m, s1, n_casl, n_cash,
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rows;
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`power wire gnd;
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input wire tsen2;
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input wire ramsize;
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output wire n_romen;
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input wire ovlay;
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output wire n_cas0l, n_cas0h, n_cas1l, n_cas1h, n_scsi, n_dack;
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input wire n_as;
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`power wire vcc;
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// We must implement RESET for simulation or else this will never
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// stabilize.
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always @(negedge n_res) begin
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end
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// Simulate combinatorial logic.
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assign n_romen
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= ~(a23 | a21 | a20 | ~ovlay & ~a22);
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assign n_cas0l
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= ~(n_casl);
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assign n_cas0h
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= ~(n_cash);
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assign n_cas1l
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= ~(n_casl
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| ovlay & ~rows
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| ramsize & ~rows
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| ~rows & n_as
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| ~rows & n_cash
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| ramsize & ~s1 & ~c2m & ~a23 & ~a22 & ~a21
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| rows & ~s1 & ~c2m & ~a23 & ~a22 & ~a21 & ~a20 & ~a19);
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assign n_cas1h
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= ~(n_cash
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| ovlay & ~rows
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| ramsize & ~rows
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| ~rows & n_as
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| ramsize & ~n_casl & ~s1 & ~c2m & ~a23 & ~a22 & ~a21
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| rows & ~n_casl & ~s1 & ~c2m & ~a23 & ~a22 & ~a21 & ~a20 & ~a19);
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assign n_scsi
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= ~(n_as | a23 | ~a22 | a21 | ~a20 | ~a19 | a9);
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assign n_dack
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= ~(n_as | a23 | ~a22 | a21 | ~a20 | ~a19 | ~a9);
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endmodule
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/* Now in order to fully implement the Macintosh's custom board
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capabilities, we must as a baseline have an implementation of some
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standard logic chips that are found on the Macintosh Main Logic
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@ -501,8 +602,8 @@ endmodule
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// logic chips. Here, we try to better indicate active high and
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// active low because we also need to stick in a hex inverter chip.
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//
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// Important! This is actually a board-level description of a
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// Macintosh Plus.
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// Important! This is actually almost a board-level description of a
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// Macintosh Plus, but not quite.
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module palcl(simclk, vcc, gnd, n_res, n_sysclk,
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sysclk, pclk, p0q1, clkscc, p0q2, vclk, q3, q4,
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e, keyclk,
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